1 /* 2 * ARM RealView Baseboard System emulation. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "qemu-common.h" 13 #include "cpu.h" 14 #include "hw/sysbus.h" 15 #include "hw/arm/arm.h" 16 #include "hw/arm/primecell.h" 17 #include "hw/devices.h" 18 #include "hw/pci/pci.h" 19 #include "net/net.h" 20 #include "sysemu/sysemu.h" 21 #include "hw/boards.h" 22 #include "hw/i2c/i2c.h" 23 #include "sysemu/block-backend.h" 24 #include "exec/address-spaces.h" 25 #include "qemu/error-report.h" 26 #include "hw/char/pl011.h" 27 28 #define SMP_BOOT_ADDR 0xe0000000 29 #define SMP_BOOTREG_ADDR 0x10000030 30 31 /* Board init. */ 32 33 static struct arm_boot_info realview_binfo = { 34 .smp_loader_start = SMP_BOOT_ADDR, 35 .smp_bootreg_addr = SMP_BOOTREG_ADDR, 36 }; 37 38 /* The following two lists must be consistent. */ 39 enum realview_board_type { 40 BOARD_EB, 41 BOARD_EB_MPCORE, 42 BOARD_PB_A8, 43 BOARD_PBX_A9, 44 }; 45 46 static const int realview_board_id[] = { 47 0x33b, 48 0x33b, 49 0x769, 50 0x76d 51 }; 52 53 static void realview_init(MachineState *machine, 54 enum realview_board_type board_type) 55 { 56 ARMCPU *cpu = NULL; 57 CPUARMState *env; 58 ObjectClass *cpu_oc; 59 MemoryRegion *sysmem = get_system_memory(); 60 MemoryRegion *ram_lo; 61 MemoryRegion *ram_hi = g_new(MemoryRegion, 1); 62 MemoryRegion *ram_alias = g_new(MemoryRegion, 1); 63 MemoryRegion *ram_hack = g_new(MemoryRegion, 1); 64 DeviceState *dev, *sysctl, *gpio2, *pl041; 65 SysBusDevice *busdev; 66 qemu_irq pic[64]; 67 qemu_irq mmc_irq[2]; 68 PCIBus *pci_bus = NULL; 69 NICInfo *nd; 70 I2CBus *i2c; 71 int n; 72 int done_nic = 0; 73 qemu_irq cpu_irq[4]; 74 int is_mpcore = 0; 75 int is_pb = 0; 76 uint32_t proc_id = 0; 77 uint32_t sys_id; 78 ram_addr_t low_ram_size; 79 ram_addr_t ram_size = machine->ram_size; 80 hwaddr periphbase = 0; 81 82 switch (board_type) { 83 case BOARD_EB: 84 break; 85 case BOARD_EB_MPCORE: 86 is_mpcore = 1; 87 periphbase = 0x10100000; 88 break; 89 case BOARD_PB_A8: 90 is_pb = 1; 91 break; 92 case BOARD_PBX_A9: 93 is_mpcore = 1; 94 is_pb = 1; 95 periphbase = 0x1f000000; 96 break; 97 } 98 99 cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, machine->cpu_model); 100 if (!cpu_oc) { 101 fprintf(stderr, "Unable to find CPU definition\n"); 102 exit(1); 103 } 104 105 for (n = 0; n < smp_cpus; n++) { 106 Object *cpuobj = object_new(object_class_get_name(cpu_oc)); 107 108 /* By default A9,A15 and ARM1176 CPUs have EL3 enabled. This board 109 * does not currently support EL3 so the CPU EL3 property is disabled 110 * before realization. 111 */ 112 if (object_property_find(cpuobj, "has_el3", NULL)) { 113 object_property_set_bool(cpuobj, false, "has_el3", &error_fatal); 114 } 115 116 if (is_pb && is_mpcore) { 117 object_property_set_int(cpuobj, periphbase, "reset-cbar", 118 &error_fatal); 119 } 120 121 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 122 123 cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpuobj), ARM_CPU_IRQ); 124 } 125 cpu = ARM_CPU(first_cpu); 126 env = &cpu->env; 127 if (arm_feature(env, ARM_FEATURE_V7)) { 128 if (is_mpcore) { 129 proc_id = 0x0c000000; 130 } else { 131 proc_id = 0x0e000000; 132 } 133 } else if (arm_feature(env, ARM_FEATURE_V6K)) { 134 proc_id = 0x06000000; 135 } else if (arm_feature(env, ARM_FEATURE_V6)) { 136 proc_id = 0x04000000; 137 } else { 138 proc_id = 0x02000000; 139 } 140 141 if (is_pb && ram_size > 0x20000000) { 142 /* Core tile RAM. */ 143 ram_lo = g_new(MemoryRegion, 1); 144 low_ram_size = ram_size - 0x20000000; 145 ram_size = 0x20000000; 146 memory_region_init_ram(ram_lo, NULL, "realview.lowmem", low_ram_size, 147 &error_fatal); 148 vmstate_register_ram_global(ram_lo); 149 memory_region_add_subregion(sysmem, 0x20000000, ram_lo); 150 } 151 152 memory_region_init_ram(ram_hi, NULL, "realview.highmem", ram_size, 153 &error_fatal); 154 vmstate_register_ram_global(ram_hi); 155 low_ram_size = ram_size; 156 if (low_ram_size > 0x10000000) 157 low_ram_size = 0x10000000; 158 /* SDRAM at address zero. */ 159 memory_region_init_alias(ram_alias, NULL, "realview.alias", 160 ram_hi, 0, low_ram_size); 161 memory_region_add_subregion(sysmem, 0, ram_alias); 162 if (is_pb) { 163 /* And again at a high address. */ 164 memory_region_add_subregion(sysmem, 0x70000000, ram_hi); 165 } else { 166 ram_size = low_ram_size; 167 } 168 169 sys_id = is_pb ? 0x01780500 : 0xc1400400; 170 sysctl = qdev_create(NULL, "realview_sysctl"); 171 qdev_prop_set_uint32(sysctl, "sys_id", sys_id); 172 qdev_prop_set_uint32(sysctl, "proc_id", proc_id); 173 qdev_init_nofail(sysctl); 174 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000); 175 176 if (is_mpcore) { 177 dev = qdev_create(NULL, is_pb ? "a9mpcore_priv": "realview_mpcore"); 178 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 179 qdev_init_nofail(dev); 180 busdev = SYS_BUS_DEVICE(dev); 181 sysbus_mmio_map(busdev, 0, periphbase); 182 for (n = 0; n < smp_cpus; n++) { 183 sysbus_connect_irq(busdev, n, cpu_irq[n]); 184 } 185 sysbus_create_varargs("l2x0", periphbase + 0x2000, NULL); 186 /* Both A9 and 11MPCore put the GIC CPU i/f at base + 0x100 */ 187 realview_binfo.gic_cpu_if_addr = periphbase + 0x100; 188 } else { 189 uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000; 190 /* For now just create the nIRQ GIC, and ignore the others. */ 191 dev = sysbus_create_simple("realview_gic", gic_addr, cpu_irq[0]); 192 } 193 for (n = 0; n < 64; n++) { 194 pic[n] = qdev_get_gpio_in(dev, n); 195 } 196 197 pl041 = qdev_create(NULL, "pl041"); 198 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 199 qdev_init_nofail(pl041); 200 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000); 201 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[19]); 202 203 sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]); 204 sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]); 205 206 pl011_create(0x10009000, pic[12], serial_hds[0]); 207 pl011_create(0x1000a000, pic[13], serial_hds[1]); 208 pl011_create(0x1000b000, pic[14], serial_hds[2]); 209 pl011_create(0x1000c000, pic[15], serial_hds[3]); 210 211 /* DMA controller is optional, apparently. */ 212 sysbus_create_simple("pl081", 0x10030000, pic[24]); 213 214 sysbus_create_simple("sp804", 0x10011000, pic[4]); 215 sysbus_create_simple("sp804", 0x10012000, pic[5]); 216 217 sysbus_create_simple("pl061", 0x10013000, pic[6]); 218 sysbus_create_simple("pl061", 0x10014000, pic[7]); 219 gpio2 = sysbus_create_simple("pl061", 0x10015000, pic[8]); 220 221 sysbus_create_simple("pl111", 0x10020000, pic[23]); 222 223 dev = sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL); 224 /* Wire up MMC card detect and read-only signals. These have 225 * to go to both the PL061 GPIO and the sysctl register. 226 * Note that the PL181 orders these lines (readonly,inserted) 227 * and the PL061 has them the other way about. Also the card 228 * detect line is inverted. 229 */ 230 mmc_irq[0] = qemu_irq_split( 231 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT), 232 qdev_get_gpio_in(gpio2, 1)); 233 mmc_irq[1] = qemu_irq_split( 234 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN), 235 qemu_irq_invert(qdev_get_gpio_in(gpio2, 0))); 236 qdev_connect_gpio_out(dev, 0, mmc_irq[0]); 237 qdev_connect_gpio_out(dev, 1, mmc_irq[1]); 238 239 sysbus_create_simple("pl031", 0x10017000, pic[10]); 240 241 if (!is_pb) { 242 dev = qdev_create(NULL, "realview_pci"); 243 busdev = SYS_BUS_DEVICE(dev); 244 qdev_init_nofail(dev); 245 sysbus_mmio_map(busdev, 0, 0x10019000); /* PCI controller registers */ 246 sysbus_mmio_map(busdev, 1, 0x60000000); /* PCI self-config */ 247 sysbus_mmio_map(busdev, 2, 0x61000000); /* PCI config */ 248 sysbus_mmio_map(busdev, 3, 0x62000000); /* PCI I/O */ 249 sysbus_mmio_map(busdev, 4, 0x63000000); /* PCI memory window 1 */ 250 sysbus_mmio_map(busdev, 5, 0x64000000); /* PCI memory window 2 */ 251 sysbus_mmio_map(busdev, 6, 0x68000000); /* PCI memory window 3 */ 252 sysbus_connect_irq(busdev, 0, pic[48]); 253 sysbus_connect_irq(busdev, 1, pic[49]); 254 sysbus_connect_irq(busdev, 2, pic[50]); 255 sysbus_connect_irq(busdev, 3, pic[51]); 256 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci"); 257 if (machine_usb(machine)) { 258 pci_create_simple(pci_bus, -1, "pci-ohci"); 259 } 260 n = drive_get_max_bus(IF_SCSI); 261 while (n >= 0) { 262 pci_create_simple(pci_bus, -1, "lsi53c895a"); 263 n--; 264 } 265 } 266 for(n = 0; n < nb_nics; n++) { 267 nd = &nd_table[n]; 268 269 if (!done_nic && (!nd->model || 270 strcmp(nd->model, is_pb ? "lan9118" : "smc91c111") == 0)) { 271 if (is_pb) { 272 lan9118_init(nd, 0x4e000000, pic[28]); 273 } else { 274 smc91c111_init(nd, 0x4e000000, pic[28]); 275 } 276 done_nic = 1; 277 } else { 278 if (pci_bus) { 279 pci_nic_init_nofail(nd, pci_bus, "rtl8139", NULL); 280 } 281 } 282 } 283 284 dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL); 285 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 286 i2c_create_slave(i2c, "ds1338", 0x68); 287 288 /* Memory map for RealView Emulation Baseboard: */ 289 /* 0x10000000 System registers. */ 290 /* 0x10001000 System controller. */ 291 /* 0x10002000 Two-Wire Serial Bus. */ 292 /* 0x10003000 Reserved. */ 293 /* 0x10004000 AACI. */ 294 /* 0x10005000 MCI. */ 295 /* 0x10006000 KMI0. */ 296 /* 0x10007000 KMI1. */ 297 /* 0x10008000 Character LCD. (EB) */ 298 /* 0x10009000 UART0. */ 299 /* 0x1000a000 UART1. */ 300 /* 0x1000b000 UART2. */ 301 /* 0x1000c000 UART3. */ 302 /* 0x1000d000 SSPI. */ 303 /* 0x1000e000 SCI. */ 304 /* 0x1000f000 Reserved. */ 305 /* 0x10010000 Watchdog. */ 306 /* 0x10011000 Timer 0+1. */ 307 /* 0x10012000 Timer 2+3. */ 308 /* 0x10013000 GPIO 0. */ 309 /* 0x10014000 GPIO 1. */ 310 /* 0x10015000 GPIO 2. */ 311 /* 0x10002000 Two-Wire Serial Bus - DVI. (PB) */ 312 /* 0x10017000 RTC. */ 313 /* 0x10018000 DMC. */ 314 /* 0x10019000 PCI controller config. */ 315 /* 0x10020000 CLCD. */ 316 /* 0x10030000 DMA Controller. */ 317 /* 0x10040000 GIC1. (EB) */ 318 /* 0x10050000 GIC2. (EB) */ 319 /* 0x10060000 GIC3. (EB) */ 320 /* 0x10070000 GIC4. (EB) */ 321 /* 0x10080000 SMC. */ 322 /* 0x1e000000 GIC1. (PB) */ 323 /* 0x1e001000 GIC2. (PB) */ 324 /* 0x1e002000 GIC3. (PB) */ 325 /* 0x1e003000 GIC4. (PB) */ 326 /* 0x40000000 NOR flash. */ 327 /* 0x44000000 DoC flash. */ 328 /* 0x48000000 SRAM. */ 329 /* 0x4c000000 Configuration flash. */ 330 /* 0x4e000000 Ethernet. */ 331 /* 0x4f000000 USB. */ 332 /* 0x50000000 PISMO. */ 333 /* 0x54000000 PISMO. */ 334 /* 0x58000000 PISMO. */ 335 /* 0x5c000000 PISMO. */ 336 /* 0x60000000 PCI. */ 337 /* 0x60000000 PCI Self Config. */ 338 /* 0x61000000 PCI Config. */ 339 /* 0x62000000 PCI IO. */ 340 /* 0x63000000 PCI mem 0. */ 341 /* 0x64000000 PCI mem 1. */ 342 /* 0x68000000 PCI mem 2. */ 343 344 /* ??? Hack to map an additional page of ram for the secondary CPU 345 startup code. I guess this works on real hardware because the 346 BootROM happens to be in ROM/flash or in memory that isn't clobbered 347 until after Linux boots the secondary CPUs. */ 348 memory_region_init_ram(ram_hack, NULL, "realview.hack", 0x1000, 349 &error_fatal); 350 vmstate_register_ram_global(ram_hack); 351 memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, ram_hack); 352 353 realview_binfo.ram_size = ram_size; 354 realview_binfo.kernel_filename = machine->kernel_filename; 355 realview_binfo.kernel_cmdline = machine->kernel_cmdline; 356 realview_binfo.initrd_filename = machine->initrd_filename; 357 realview_binfo.nb_cpus = smp_cpus; 358 realview_binfo.board_id = realview_board_id[board_type]; 359 realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0); 360 arm_load_kernel(ARM_CPU(first_cpu), &realview_binfo); 361 } 362 363 static void realview_eb_init(MachineState *machine) 364 { 365 if (!machine->cpu_model) { 366 machine->cpu_model = "arm926"; 367 } 368 realview_init(machine, BOARD_EB); 369 } 370 371 static void realview_eb_mpcore_init(MachineState *machine) 372 { 373 if (!machine->cpu_model) { 374 machine->cpu_model = "arm11mpcore"; 375 } 376 realview_init(machine, BOARD_EB_MPCORE); 377 } 378 379 static void realview_pb_a8_init(MachineState *machine) 380 { 381 if (!machine->cpu_model) { 382 machine->cpu_model = "cortex-a8"; 383 } 384 realview_init(machine, BOARD_PB_A8); 385 } 386 387 static void realview_pbx_a9_init(MachineState *machine) 388 { 389 if (!machine->cpu_model) { 390 machine->cpu_model = "cortex-a9"; 391 } 392 realview_init(machine, BOARD_PBX_A9); 393 } 394 395 static void realview_eb_class_init(ObjectClass *oc, void *data) 396 { 397 MachineClass *mc = MACHINE_CLASS(oc); 398 399 mc->desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)"; 400 mc->init = realview_eb_init; 401 mc->block_default_type = IF_SCSI; 402 } 403 404 static const TypeInfo realview_eb_type = { 405 .name = MACHINE_TYPE_NAME("realview-eb"), 406 .parent = TYPE_MACHINE, 407 .class_init = realview_eb_class_init, 408 }; 409 410 static void realview_eb_mpcore_class_init(ObjectClass *oc, void *data) 411 { 412 MachineClass *mc = MACHINE_CLASS(oc); 413 414 mc->desc = "ARM RealView Emulation Baseboard (ARM11MPCore)"; 415 mc->init = realview_eb_mpcore_init; 416 mc->block_default_type = IF_SCSI; 417 mc->max_cpus = 4; 418 } 419 420 static const TypeInfo realview_eb_mpcore_type = { 421 .name = MACHINE_TYPE_NAME("realview-eb-mpcore"), 422 .parent = TYPE_MACHINE, 423 .class_init = realview_eb_mpcore_class_init, 424 }; 425 426 static void realview_pb_a8_class_init(ObjectClass *oc, void *data) 427 { 428 MachineClass *mc = MACHINE_CLASS(oc); 429 430 mc->desc = "ARM RealView Platform Baseboard for Cortex-A8"; 431 mc->init = realview_pb_a8_init; 432 } 433 434 static const TypeInfo realview_pb_a8_type = { 435 .name = MACHINE_TYPE_NAME("realview-pb-a8"), 436 .parent = TYPE_MACHINE, 437 .class_init = realview_pb_a8_class_init, 438 }; 439 440 static void realview_pbx_a9_class_init(ObjectClass *oc, void *data) 441 { 442 MachineClass *mc = MACHINE_CLASS(oc); 443 444 mc->desc = "ARM RealView Platform Baseboard Explore for Cortex-A9"; 445 mc->init = realview_pbx_a9_init; 446 mc->block_default_type = IF_SCSI; 447 mc->max_cpus = 4; 448 } 449 450 static const TypeInfo realview_pbx_a9_type = { 451 .name = MACHINE_TYPE_NAME("realview-pbx-a9"), 452 .parent = TYPE_MACHINE, 453 .class_init = realview_pbx_a9_class_init, 454 }; 455 456 static void realview_machine_init(void) 457 { 458 type_register_static(&realview_eb_type); 459 type_register_static(&realview_eb_mpcore_type); 460 type_register_static(&realview_pb_a8_type); 461 type_register_static(&realview_pbx_a9_type); 462 } 463 464 type_init(realview_machine_init) 465