1 /* 2 * ARM RealView Baseboard System emulation. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "cpu.h" 13 #include "hw/sysbus.h" 14 #include "hw/arm/boot.h" 15 #include "hw/arm/primecell.h" 16 #include "hw/net/lan9118.h" 17 #include "hw/net/smc91c111.h" 18 #include "hw/pci/pci.h" 19 #include "net/net.h" 20 #include "sysemu/sysemu.h" 21 #include "hw/boards.h" 22 #include "hw/i2c/i2c.h" 23 #include "exec/address-spaces.h" 24 #include "qemu/error-report.h" 25 #include "hw/char/pl011.h" 26 #include "hw/cpu/a9mpcore.h" 27 #include "hw/intc/realview_gic.h" 28 #include "hw/irq.h" 29 #include "hw/i2c/arm_sbcon_i2c.h" 30 #include "hw/sd/sd.h" 31 32 #define SMP_BOOT_ADDR 0xe0000000 33 #define SMP_BOOTREG_ADDR 0x10000030 34 35 /* Board init. */ 36 37 static struct arm_boot_info realview_binfo = { 38 .smp_loader_start = SMP_BOOT_ADDR, 39 .smp_bootreg_addr = SMP_BOOTREG_ADDR, 40 }; 41 42 /* The following two lists must be consistent. */ 43 enum realview_board_type { 44 BOARD_EB, 45 BOARD_EB_MPCORE, 46 BOARD_PB_A8, 47 BOARD_PBX_A9, 48 }; 49 50 static const int realview_board_id[] = { 51 0x33b, 52 0x33b, 53 0x769, 54 0x76d 55 }; 56 57 static void realview_init(MachineState *machine, 58 enum realview_board_type board_type) 59 { 60 ARMCPU *cpu = NULL; 61 CPUARMState *env; 62 MemoryRegion *sysmem = get_system_memory(); 63 MemoryRegion *ram_lo; 64 MemoryRegion *ram_hi = g_new(MemoryRegion, 1); 65 MemoryRegion *ram_alias = g_new(MemoryRegion, 1); 66 MemoryRegion *ram_hack = g_new(MemoryRegion, 1); 67 DeviceState *dev, *sysctl, *gpio2, *pl041; 68 SysBusDevice *busdev; 69 qemu_irq pic[64]; 70 qemu_irq mmc_irq[2]; 71 PCIBus *pci_bus = NULL; 72 NICInfo *nd; 73 DriveInfo *dinfo; 74 I2CBus *i2c; 75 int n; 76 unsigned int smp_cpus = machine->smp.cpus; 77 int done_nic = 0; 78 qemu_irq cpu_irq[4]; 79 int is_mpcore = 0; 80 int is_pb = 0; 81 uint32_t proc_id = 0; 82 uint32_t sys_id; 83 ram_addr_t low_ram_size; 84 ram_addr_t ram_size = machine->ram_size; 85 hwaddr periphbase = 0; 86 87 switch (board_type) { 88 case BOARD_EB: 89 break; 90 case BOARD_EB_MPCORE: 91 is_mpcore = 1; 92 periphbase = 0x10100000; 93 break; 94 case BOARD_PB_A8: 95 is_pb = 1; 96 break; 97 case BOARD_PBX_A9: 98 is_mpcore = 1; 99 is_pb = 1; 100 periphbase = 0x1f000000; 101 break; 102 } 103 104 for (n = 0; n < smp_cpus; n++) { 105 Object *cpuobj = object_new(machine->cpu_type); 106 107 /* By default A9,A15 and ARM1176 CPUs have EL3 enabled. This board 108 * does not currently support EL3 so the CPU EL3 property is disabled 109 * before realization. 110 */ 111 if (object_property_find(cpuobj, "has_el3")) { 112 object_property_set_bool(cpuobj, "has_el3", false, &error_fatal); 113 } 114 115 if (is_pb && is_mpcore) { 116 object_property_set_int(cpuobj, "reset-cbar", periphbase, 117 &error_fatal); 118 } 119 120 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 121 122 cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpuobj), ARM_CPU_IRQ); 123 } 124 cpu = ARM_CPU(first_cpu); 125 env = &cpu->env; 126 if (arm_feature(env, ARM_FEATURE_V7)) { 127 if (is_mpcore) { 128 proc_id = 0x0c000000; 129 } else { 130 proc_id = 0x0e000000; 131 } 132 } else if (arm_feature(env, ARM_FEATURE_V6K)) { 133 proc_id = 0x06000000; 134 } else if (arm_feature(env, ARM_FEATURE_V6)) { 135 proc_id = 0x04000000; 136 } else { 137 proc_id = 0x02000000; 138 } 139 140 if (is_pb && ram_size > 0x20000000) { 141 /* Core tile RAM. */ 142 ram_lo = g_new(MemoryRegion, 1); 143 low_ram_size = ram_size - 0x20000000; 144 ram_size = 0x20000000; 145 memory_region_init_ram(ram_lo, NULL, "realview.lowmem", low_ram_size, 146 &error_fatal); 147 memory_region_add_subregion(sysmem, 0x20000000, ram_lo); 148 } 149 150 memory_region_init_ram(ram_hi, NULL, "realview.highmem", ram_size, 151 &error_fatal); 152 low_ram_size = ram_size; 153 if (low_ram_size > 0x10000000) 154 low_ram_size = 0x10000000; 155 /* SDRAM at address zero. */ 156 memory_region_init_alias(ram_alias, NULL, "realview.alias", 157 ram_hi, 0, low_ram_size); 158 memory_region_add_subregion(sysmem, 0, ram_alias); 159 if (is_pb) { 160 /* And again at a high address. */ 161 memory_region_add_subregion(sysmem, 0x70000000, ram_hi); 162 } else { 163 ram_size = low_ram_size; 164 } 165 166 sys_id = is_pb ? 0x01780500 : 0xc1400400; 167 sysctl = qdev_new("realview_sysctl"); 168 qdev_prop_set_uint32(sysctl, "sys_id", sys_id); 169 qdev_prop_set_uint32(sysctl, "proc_id", proc_id); 170 sysbus_realize_and_unref(SYS_BUS_DEVICE(sysctl), &error_fatal); 171 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000); 172 173 if (is_mpcore) { 174 dev = qdev_new(is_pb ? TYPE_A9MPCORE_PRIV : "realview_mpcore"); 175 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 176 busdev = SYS_BUS_DEVICE(dev); 177 sysbus_realize_and_unref(busdev, &error_fatal); 178 sysbus_mmio_map(busdev, 0, periphbase); 179 for (n = 0; n < smp_cpus; n++) { 180 sysbus_connect_irq(busdev, n, cpu_irq[n]); 181 } 182 sysbus_create_varargs("l2x0", periphbase + 0x2000, NULL); 183 /* Both A9 and 11MPCore put the GIC CPU i/f at base + 0x100 */ 184 realview_binfo.gic_cpu_if_addr = periphbase + 0x100; 185 } else { 186 uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000; 187 /* For now just create the nIRQ GIC, and ignore the others. */ 188 dev = sysbus_create_simple(TYPE_REALVIEW_GIC, gic_addr, cpu_irq[0]); 189 } 190 for (n = 0; n < 64; n++) { 191 pic[n] = qdev_get_gpio_in(dev, n); 192 } 193 194 pl041 = qdev_new("pl041"); 195 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 196 sysbus_realize_and_unref(SYS_BUS_DEVICE(pl041), &error_fatal); 197 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000); 198 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[19]); 199 200 sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]); 201 sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]); 202 203 pl011_create(0x10009000, pic[12], serial_hd(0)); 204 pl011_create(0x1000a000, pic[13], serial_hd(1)); 205 pl011_create(0x1000b000, pic[14], serial_hd(2)); 206 pl011_create(0x1000c000, pic[15], serial_hd(3)); 207 208 /* DMA controller is optional, apparently. */ 209 dev = qdev_new("pl081"); 210 object_property_set_link(OBJECT(dev), "downstream", OBJECT(sysmem), 211 &error_fatal); 212 busdev = SYS_BUS_DEVICE(dev); 213 sysbus_realize_and_unref(busdev, &error_fatal); 214 sysbus_mmio_map(busdev, 0, 0x10030000); 215 sysbus_connect_irq(busdev, 0, pic[24]); 216 217 sysbus_create_simple("sp804", 0x10011000, pic[4]); 218 sysbus_create_simple("sp804", 0x10012000, pic[5]); 219 220 sysbus_create_simple("pl061", 0x10013000, pic[6]); 221 sysbus_create_simple("pl061", 0x10014000, pic[7]); 222 gpio2 = sysbus_create_simple("pl061", 0x10015000, pic[8]); 223 224 sysbus_create_simple("pl111", 0x10020000, pic[23]); 225 226 dev = sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL); 227 /* Wire up MMC card detect and read-only signals. These have 228 * to go to both the PL061 GPIO and the sysctl register. 229 * Note that the PL181 orders these lines (readonly,inserted) 230 * and the PL061 has them the other way about. Also the card 231 * detect line is inverted. 232 */ 233 mmc_irq[0] = qemu_irq_split( 234 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT), 235 qdev_get_gpio_in(gpio2, 1)); 236 mmc_irq[1] = qemu_irq_split( 237 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN), 238 qemu_irq_invert(qdev_get_gpio_in(gpio2, 0))); 239 qdev_connect_gpio_out_named(dev, "card-read-only", 0, mmc_irq[0]); 240 qdev_connect_gpio_out_named(dev, "card-inserted", 0, mmc_irq[1]); 241 dinfo = drive_get_next(IF_SD); 242 if (dinfo) { 243 DeviceState *card; 244 245 card = qdev_new(TYPE_SD_CARD); 246 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 247 &error_fatal); 248 qdev_realize_and_unref(card, qdev_get_child_bus(dev, "sd-bus"), 249 &error_fatal); 250 } 251 252 sysbus_create_simple("pl031", 0x10017000, pic[10]); 253 254 if (!is_pb) { 255 dev = qdev_new("realview_pci"); 256 busdev = SYS_BUS_DEVICE(dev); 257 sysbus_realize_and_unref(busdev, &error_fatal); 258 sysbus_mmio_map(busdev, 0, 0x10019000); /* PCI controller registers */ 259 sysbus_mmio_map(busdev, 1, 0x60000000); /* PCI self-config */ 260 sysbus_mmio_map(busdev, 2, 0x61000000); /* PCI config */ 261 sysbus_mmio_map(busdev, 3, 0x62000000); /* PCI I/O */ 262 sysbus_mmio_map(busdev, 4, 0x63000000); /* PCI memory window 1 */ 263 sysbus_mmio_map(busdev, 5, 0x64000000); /* PCI memory window 2 */ 264 sysbus_mmio_map(busdev, 6, 0x68000000); /* PCI memory window 3 */ 265 sysbus_connect_irq(busdev, 0, pic[48]); 266 sysbus_connect_irq(busdev, 1, pic[49]); 267 sysbus_connect_irq(busdev, 2, pic[50]); 268 sysbus_connect_irq(busdev, 3, pic[51]); 269 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci"); 270 if (machine_usb(machine)) { 271 pci_create_simple(pci_bus, -1, "pci-ohci"); 272 } 273 n = drive_get_max_bus(IF_SCSI); 274 while (n >= 0) { 275 dev = DEVICE(pci_create_simple(pci_bus, -1, "lsi53c895a")); 276 lsi53c8xx_handle_legacy_cmdline(dev); 277 n--; 278 } 279 } 280 for(n = 0; n < nb_nics; n++) { 281 nd = &nd_table[n]; 282 283 if (!done_nic && (!nd->model || 284 strcmp(nd->model, is_pb ? "lan9118" : "smc91c111") == 0)) { 285 if (is_pb) { 286 lan9118_init(nd, 0x4e000000, pic[28]); 287 } else { 288 smc91c111_init(nd, 0x4e000000, pic[28]); 289 } 290 done_nic = 1; 291 } else { 292 if (pci_bus) { 293 pci_nic_init_nofail(nd, pci_bus, "rtl8139", NULL); 294 } 295 } 296 } 297 298 dev = sysbus_create_simple(TYPE_VERSATILE_I2C, 0x10002000, NULL); 299 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 300 i2c_slave_create_simple(i2c, "ds1338", 0x68); 301 302 /* Memory map for RealView Emulation Baseboard: */ 303 /* 0x10000000 System registers. */ 304 /* 0x10001000 System controller. */ 305 /* 0x10002000 Two-Wire Serial Bus. */ 306 /* 0x10003000 Reserved. */ 307 /* 0x10004000 AACI. */ 308 /* 0x10005000 MCI. */ 309 /* 0x10006000 KMI0. */ 310 /* 0x10007000 KMI1. */ 311 /* 0x10008000 Character LCD. (EB) */ 312 /* 0x10009000 UART0. */ 313 /* 0x1000a000 UART1. */ 314 /* 0x1000b000 UART2. */ 315 /* 0x1000c000 UART3. */ 316 /* 0x1000d000 SSPI. */ 317 /* 0x1000e000 SCI. */ 318 /* 0x1000f000 Reserved. */ 319 /* 0x10010000 Watchdog. */ 320 /* 0x10011000 Timer 0+1. */ 321 /* 0x10012000 Timer 2+3. */ 322 /* 0x10013000 GPIO 0. */ 323 /* 0x10014000 GPIO 1. */ 324 /* 0x10015000 GPIO 2. */ 325 /* 0x10002000 Two-Wire Serial Bus - DVI. (PB) */ 326 /* 0x10017000 RTC. */ 327 /* 0x10018000 DMC. */ 328 /* 0x10019000 PCI controller config. */ 329 /* 0x10020000 CLCD. */ 330 /* 0x10030000 DMA Controller. */ 331 /* 0x10040000 GIC1. (EB) */ 332 /* 0x10050000 GIC2. (EB) */ 333 /* 0x10060000 GIC3. (EB) */ 334 /* 0x10070000 GIC4. (EB) */ 335 /* 0x10080000 SMC. */ 336 /* 0x1e000000 GIC1. (PB) */ 337 /* 0x1e001000 GIC2. (PB) */ 338 /* 0x1e002000 GIC3. (PB) */ 339 /* 0x1e003000 GIC4. (PB) */ 340 /* 0x40000000 NOR flash. */ 341 /* 0x44000000 DoC flash. */ 342 /* 0x48000000 SRAM. */ 343 /* 0x4c000000 Configuration flash. */ 344 /* 0x4e000000 Ethernet. */ 345 /* 0x4f000000 USB. */ 346 /* 0x50000000 PISMO. */ 347 /* 0x54000000 PISMO. */ 348 /* 0x58000000 PISMO. */ 349 /* 0x5c000000 PISMO. */ 350 /* 0x60000000 PCI. */ 351 /* 0x60000000 PCI Self Config. */ 352 /* 0x61000000 PCI Config. */ 353 /* 0x62000000 PCI IO. */ 354 /* 0x63000000 PCI mem 0. */ 355 /* 0x64000000 PCI mem 1. */ 356 /* 0x68000000 PCI mem 2. */ 357 358 /* ??? Hack to map an additional page of ram for the secondary CPU 359 startup code. I guess this works on real hardware because the 360 BootROM happens to be in ROM/flash or in memory that isn't clobbered 361 until after Linux boots the secondary CPUs. */ 362 memory_region_init_ram(ram_hack, NULL, "realview.hack", 0x1000, 363 &error_fatal); 364 memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, ram_hack); 365 366 realview_binfo.ram_size = ram_size; 367 realview_binfo.nb_cpus = smp_cpus; 368 realview_binfo.board_id = realview_board_id[board_type]; 369 realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0); 370 arm_load_kernel(ARM_CPU(first_cpu), machine, &realview_binfo); 371 } 372 373 static void realview_eb_init(MachineState *machine) 374 { 375 realview_init(machine, BOARD_EB); 376 } 377 378 static void realview_eb_mpcore_init(MachineState *machine) 379 { 380 realview_init(machine, BOARD_EB_MPCORE); 381 } 382 383 static void realview_pb_a8_init(MachineState *machine) 384 { 385 realview_init(machine, BOARD_PB_A8); 386 } 387 388 static void realview_pbx_a9_init(MachineState *machine) 389 { 390 realview_init(machine, BOARD_PBX_A9); 391 } 392 393 static void realview_eb_class_init(ObjectClass *oc, void *data) 394 { 395 MachineClass *mc = MACHINE_CLASS(oc); 396 397 mc->desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)"; 398 mc->init = realview_eb_init; 399 mc->block_default_type = IF_SCSI; 400 mc->ignore_memory_transaction_failures = true; 401 mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); 402 } 403 404 static const TypeInfo realview_eb_type = { 405 .name = MACHINE_TYPE_NAME("realview-eb"), 406 .parent = TYPE_MACHINE, 407 .class_init = realview_eb_class_init, 408 }; 409 410 static void realview_eb_mpcore_class_init(ObjectClass *oc, void *data) 411 { 412 MachineClass *mc = MACHINE_CLASS(oc); 413 414 mc->desc = "ARM RealView Emulation Baseboard (ARM11MPCore)"; 415 mc->init = realview_eb_mpcore_init; 416 mc->block_default_type = IF_SCSI; 417 mc->max_cpus = 4; 418 mc->ignore_memory_transaction_failures = true; 419 mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm11mpcore"); 420 } 421 422 static const TypeInfo realview_eb_mpcore_type = { 423 .name = MACHINE_TYPE_NAME("realview-eb-mpcore"), 424 .parent = TYPE_MACHINE, 425 .class_init = realview_eb_mpcore_class_init, 426 }; 427 428 static void realview_pb_a8_class_init(ObjectClass *oc, void *data) 429 { 430 MachineClass *mc = MACHINE_CLASS(oc); 431 432 mc->desc = "ARM RealView Platform Baseboard for Cortex-A8"; 433 mc->init = realview_pb_a8_init; 434 mc->ignore_memory_transaction_failures = true; 435 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a8"); 436 } 437 438 static const TypeInfo realview_pb_a8_type = { 439 .name = MACHINE_TYPE_NAME("realview-pb-a8"), 440 .parent = TYPE_MACHINE, 441 .class_init = realview_pb_a8_class_init, 442 }; 443 444 static void realview_pbx_a9_class_init(ObjectClass *oc, void *data) 445 { 446 MachineClass *mc = MACHINE_CLASS(oc); 447 448 mc->desc = "ARM RealView Platform Baseboard Explore for Cortex-A9"; 449 mc->init = realview_pbx_a9_init; 450 mc->max_cpus = 4; 451 mc->ignore_memory_transaction_failures = true; 452 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); 453 } 454 455 static const TypeInfo realview_pbx_a9_type = { 456 .name = MACHINE_TYPE_NAME("realview-pbx-a9"), 457 .parent = TYPE_MACHINE, 458 .class_init = realview_pbx_a9_class_init, 459 }; 460 461 static void realview_machine_init(void) 462 { 463 type_register_static(&realview_eb_type); 464 type_register_static(&realview_eb_mpcore_type); 465 type_register_static(&realview_pb_a8_type); 466 type_register_static(&realview_pbx_a9_type); 467 } 468 469 type_init(realview_machine_init) 470