1 /* 2 * ARM RealView Baseboard System emulation. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "cpu.h" 13 #include "hw/sysbus.h" 14 #include "hw/arm/boot.h" 15 #include "hw/arm/primecell.h" 16 #include "hw/net/lan9118.h" 17 #include "hw/net/smc91c111.h" 18 #include "hw/pci/pci.h" 19 #include "net/net.h" 20 #include "sysemu/sysemu.h" 21 #include "hw/boards.h" 22 #include "hw/i2c/i2c.h" 23 #include "exec/address-spaces.h" 24 #include "qemu/error-report.h" 25 #include "hw/char/pl011.h" 26 #include "hw/cpu/a9mpcore.h" 27 #include "hw/intc/realview_gic.h" 28 #include "hw/irq.h" 29 #include "hw/i2c/arm_sbcon_i2c.h" 30 31 #define SMP_BOOT_ADDR 0xe0000000 32 #define SMP_BOOTREG_ADDR 0x10000030 33 34 /* Board init. */ 35 36 static struct arm_boot_info realview_binfo = { 37 .smp_loader_start = SMP_BOOT_ADDR, 38 .smp_bootreg_addr = SMP_BOOTREG_ADDR, 39 }; 40 41 /* The following two lists must be consistent. */ 42 enum realview_board_type { 43 BOARD_EB, 44 BOARD_EB_MPCORE, 45 BOARD_PB_A8, 46 BOARD_PBX_A9, 47 }; 48 49 static const int realview_board_id[] = { 50 0x33b, 51 0x33b, 52 0x769, 53 0x76d 54 }; 55 56 static void realview_init(MachineState *machine, 57 enum realview_board_type board_type) 58 { 59 ARMCPU *cpu = NULL; 60 CPUARMState *env; 61 MemoryRegion *sysmem = get_system_memory(); 62 MemoryRegion *ram_lo; 63 MemoryRegion *ram_hi = g_new(MemoryRegion, 1); 64 MemoryRegion *ram_alias = g_new(MemoryRegion, 1); 65 MemoryRegion *ram_hack = g_new(MemoryRegion, 1); 66 DeviceState *dev, *sysctl, *gpio2, *pl041; 67 SysBusDevice *busdev; 68 qemu_irq pic[64]; 69 qemu_irq mmc_irq[2]; 70 PCIBus *pci_bus = NULL; 71 NICInfo *nd; 72 I2CBus *i2c; 73 int n; 74 unsigned int smp_cpus = machine->smp.cpus; 75 int done_nic = 0; 76 qemu_irq cpu_irq[4]; 77 int is_mpcore = 0; 78 int is_pb = 0; 79 uint32_t proc_id = 0; 80 uint32_t sys_id; 81 ram_addr_t low_ram_size; 82 ram_addr_t ram_size = machine->ram_size; 83 hwaddr periphbase = 0; 84 85 switch (board_type) { 86 case BOARD_EB: 87 break; 88 case BOARD_EB_MPCORE: 89 is_mpcore = 1; 90 periphbase = 0x10100000; 91 break; 92 case BOARD_PB_A8: 93 is_pb = 1; 94 break; 95 case BOARD_PBX_A9: 96 is_mpcore = 1; 97 is_pb = 1; 98 periphbase = 0x1f000000; 99 break; 100 } 101 102 for (n = 0; n < smp_cpus; n++) { 103 Object *cpuobj = object_new(machine->cpu_type); 104 105 /* By default A9,A15 and ARM1176 CPUs have EL3 enabled. This board 106 * does not currently support EL3 so the CPU EL3 property is disabled 107 * before realization. 108 */ 109 if (object_property_find(cpuobj, "has_el3", NULL)) { 110 object_property_set_bool(cpuobj, "has_el3", false, &error_fatal); 111 } 112 113 if (is_pb && is_mpcore) { 114 object_property_set_int(cpuobj, "reset-cbar", periphbase, 115 &error_fatal); 116 } 117 118 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 119 120 cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpuobj), ARM_CPU_IRQ); 121 } 122 cpu = ARM_CPU(first_cpu); 123 env = &cpu->env; 124 if (arm_feature(env, ARM_FEATURE_V7)) { 125 if (is_mpcore) { 126 proc_id = 0x0c000000; 127 } else { 128 proc_id = 0x0e000000; 129 } 130 } else if (arm_feature(env, ARM_FEATURE_V6K)) { 131 proc_id = 0x06000000; 132 } else if (arm_feature(env, ARM_FEATURE_V6)) { 133 proc_id = 0x04000000; 134 } else { 135 proc_id = 0x02000000; 136 } 137 138 if (is_pb && ram_size > 0x20000000) { 139 /* Core tile RAM. */ 140 ram_lo = g_new(MemoryRegion, 1); 141 low_ram_size = ram_size - 0x20000000; 142 ram_size = 0x20000000; 143 memory_region_init_ram(ram_lo, NULL, "realview.lowmem", low_ram_size, 144 &error_fatal); 145 memory_region_add_subregion(sysmem, 0x20000000, ram_lo); 146 } 147 148 memory_region_init_ram(ram_hi, NULL, "realview.highmem", ram_size, 149 &error_fatal); 150 low_ram_size = ram_size; 151 if (low_ram_size > 0x10000000) 152 low_ram_size = 0x10000000; 153 /* SDRAM at address zero. */ 154 memory_region_init_alias(ram_alias, NULL, "realview.alias", 155 ram_hi, 0, low_ram_size); 156 memory_region_add_subregion(sysmem, 0, ram_alias); 157 if (is_pb) { 158 /* And again at a high address. */ 159 memory_region_add_subregion(sysmem, 0x70000000, ram_hi); 160 } else { 161 ram_size = low_ram_size; 162 } 163 164 sys_id = is_pb ? 0x01780500 : 0xc1400400; 165 sysctl = qdev_new("realview_sysctl"); 166 qdev_prop_set_uint32(sysctl, "sys_id", sys_id); 167 qdev_prop_set_uint32(sysctl, "proc_id", proc_id); 168 sysbus_realize_and_unref(SYS_BUS_DEVICE(sysctl), &error_fatal); 169 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000); 170 171 if (is_mpcore) { 172 dev = qdev_new(is_pb ? TYPE_A9MPCORE_PRIV : "realview_mpcore"); 173 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 174 busdev = SYS_BUS_DEVICE(dev); 175 sysbus_realize_and_unref(busdev, &error_fatal); 176 sysbus_mmio_map(busdev, 0, periphbase); 177 for (n = 0; n < smp_cpus; n++) { 178 sysbus_connect_irq(busdev, n, cpu_irq[n]); 179 } 180 sysbus_create_varargs("l2x0", periphbase + 0x2000, NULL); 181 /* Both A9 and 11MPCore put the GIC CPU i/f at base + 0x100 */ 182 realview_binfo.gic_cpu_if_addr = periphbase + 0x100; 183 } else { 184 uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000; 185 /* For now just create the nIRQ GIC, and ignore the others. */ 186 dev = sysbus_create_simple(TYPE_REALVIEW_GIC, gic_addr, cpu_irq[0]); 187 } 188 for (n = 0; n < 64; n++) { 189 pic[n] = qdev_get_gpio_in(dev, n); 190 } 191 192 pl041 = qdev_new("pl041"); 193 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 194 sysbus_realize_and_unref(SYS_BUS_DEVICE(pl041), &error_fatal); 195 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000); 196 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[19]); 197 198 sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]); 199 sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]); 200 201 pl011_create(0x10009000, pic[12], serial_hd(0)); 202 pl011_create(0x1000a000, pic[13], serial_hd(1)); 203 pl011_create(0x1000b000, pic[14], serial_hd(2)); 204 pl011_create(0x1000c000, pic[15], serial_hd(3)); 205 206 /* DMA controller is optional, apparently. */ 207 dev = qdev_new("pl081"); 208 object_property_set_link(OBJECT(dev), "downstream", OBJECT(sysmem), 209 &error_fatal); 210 busdev = SYS_BUS_DEVICE(dev); 211 sysbus_realize_and_unref(busdev, &error_fatal); 212 sysbus_mmio_map(busdev, 0, 0x10030000); 213 sysbus_connect_irq(busdev, 0, pic[24]); 214 215 sysbus_create_simple("sp804", 0x10011000, pic[4]); 216 sysbus_create_simple("sp804", 0x10012000, pic[5]); 217 218 sysbus_create_simple("pl061", 0x10013000, pic[6]); 219 sysbus_create_simple("pl061", 0x10014000, pic[7]); 220 gpio2 = sysbus_create_simple("pl061", 0x10015000, pic[8]); 221 222 sysbus_create_simple("pl111", 0x10020000, pic[23]); 223 224 dev = sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL); 225 /* Wire up MMC card detect and read-only signals. These have 226 * to go to both the PL061 GPIO and the sysctl register. 227 * Note that the PL181 orders these lines (readonly,inserted) 228 * and the PL061 has them the other way about. Also the card 229 * detect line is inverted. 230 */ 231 mmc_irq[0] = qemu_irq_split( 232 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT), 233 qdev_get_gpio_in(gpio2, 1)); 234 mmc_irq[1] = qemu_irq_split( 235 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN), 236 qemu_irq_invert(qdev_get_gpio_in(gpio2, 0))); 237 qdev_connect_gpio_out(dev, 0, mmc_irq[0]); 238 qdev_connect_gpio_out(dev, 1, mmc_irq[1]); 239 240 sysbus_create_simple("pl031", 0x10017000, pic[10]); 241 242 if (!is_pb) { 243 dev = qdev_new("realview_pci"); 244 busdev = SYS_BUS_DEVICE(dev); 245 sysbus_realize_and_unref(busdev, &error_fatal); 246 sysbus_mmio_map(busdev, 0, 0x10019000); /* PCI controller registers */ 247 sysbus_mmio_map(busdev, 1, 0x60000000); /* PCI self-config */ 248 sysbus_mmio_map(busdev, 2, 0x61000000); /* PCI config */ 249 sysbus_mmio_map(busdev, 3, 0x62000000); /* PCI I/O */ 250 sysbus_mmio_map(busdev, 4, 0x63000000); /* PCI memory window 1 */ 251 sysbus_mmio_map(busdev, 5, 0x64000000); /* PCI memory window 2 */ 252 sysbus_mmio_map(busdev, 6, 0x68000000); /* PCI memory window 3 */ 253 sysbus_connect_irq(busdev, 0, pic[48]); 254 sysbus_connect_irq(busdev, 1, pic[49]); 255 sysbus_connect_irq(busdev, 2, pic[50]); 256 sysbus_connect_irq(busdev, 3, pic[51]); 257 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci"); 258 if (machine_usb(machine)) { 259 pci_create_simple(pci_bus, -1, "pci-ohci"); 260 } 261 n = drive_get_max_bus(IF_SCSI); 262 while (n >= 0) { 263 dev = DEVICE(pci_create_simple(pci_bus, -1, "lsi53c895a")); 264 lsi53c8xx_handle_legacy_cmdline(dev); 265 n--; 266 } 267 } 268 for(n = 0; n < nb_nics; n++) { 269 nd = &nd_table[n]; 270 271 if (!done_nic && (!nd->model || 272 strcmp(nd->model, is_pb ? "lan9118" : "smc91c111") == 0)) { 273 if (is_pb) { 274 lan9118_init(nd, 0x4e000000, pic[28]); 275 } else { 276 smc91c111_init(nd, 0x4e000000, pic[28]); 277 } 278 done_nic = 1; 279 } else { 280 if (pci_bus) { 281 pci_nic_init_nofail(nd, pci_bus, "rtl8139", NULL); 282 } 283 } 284 } 285 286 dev = sysbus_create_simple(TYPE_VERSATILE_I2C, 0x10002000, NULL); 287 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 288 i2c_slave_create_simple(i2c, "ds1338", 0x68); 289 290 /* Memory map for RealView Emulation Baseboard: */ 291 /* 0x10000000 System registers. */ 292 /* 0x10001000 System controller. */ 293 /* 0x10002000 Two-Wire Serial Bus. */ 294 /* 0x10003000 Reserved. */ 295 /* 0x10004000 AACI. */ 296 /* 0x10005000 MCI. */ 297 /* 0x10006000 KMI0. */ 298 /* 0x10007000 KMI1. */ 299 /* 0x10008000 Character LCD. (EB) */ 300 /* 0x10009000 UART0. */ 301 /* 0x1000a000 UART1. */ 302 /* 0x1000b000 UART2. */ 303 /* 0x1000c000 UART3. */ 304 /* 0x1000d000 SSPI. */ 305 /* 0x1000e000 SCI. */ 306 /* 0x1000f000 Reserved. */ 307 /* 0x10010000 Watchdog. */ 308 /* 0x10011000 Timer 0+1. */ 309 /* 0x10012000 Timer 2+3. */ 310 /* 0x10013000 GPIO 0. */ 311 /* 0x10014000 GPIO 1. */ 312 /* 0x10015000 GPIO 2. */ 313 /* 0x10002000 Two-Wire Serial Bus - DVI. (PB) */ 314 /* 0x10017000 RTC. */ 315 /* 0x10018000 DMC. */ 316 /* 0x10019000 PCI controller config. */ 317 /* 0x10020000 CLCD. */ 318 /* 0x10030000 DMA Controller. */ 319 /* 0x10040000 GIC1. (EB) */ 320 /* 0x10050000 GIC2. (EB) */ 321 /* 0x10060000 GIC3. (EB) */ 322 /* 0x10070000 GIC4. (EB) */ 323 /* 0x10080000 SMC. */ 324 /* 0x1e000000 GIC1. (PB) */ 325 /* 0x1e001000 GIC2. (PB) */ 326 /* 0x1e002000 GIC3. (PB) */ 327 /* 0x1e003000 GIC4. (PB) */ 328 /* 0x40000000 NOR flash. */ 329 /* 0x44000000 DoC flash. */ 330 /* 0x48000000 SRAM. */ 331 /* 0x4c000000 Configuration flash. */ 332 /* 0x4e000000 Ethernet. */ 333 /* 0x4f000000 USB. */ 334 /* 0x50000000 PISMO. */ 335 /* 0x54000000 PISMO. */ 336 /* 0x58000000 PISMO. */ 337 /* 0x5c000000 PISMO. */ 338 /* 0x60000000 PCI. */ 339 /* 0x60000000 PCI Self Config. */ 340 /* 0x61000000 PCI Config. */ 341 /* 0x62000000 PCI IO. */ 342 /* 0x63000000 PCI mem 0. */ 343 /* 0x64000000 PCI mem 1. */ 344 /* 0x68000000 PCI mem 2. */ 345 346 /* ??? Hack to map an additional page of ram for the secondary CPU 347 startup code. I guess this works on real hardware because the 348 BootROM happens to be in ROM/flash or in memory that isn't clobbered 349 until after Linux boots the secondary CPUs. */ 350 memory_region_init_ram(ram_hack, NULL, "realview.hack", 0x1000, 351 &error_fatal); 352 memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, ram_hack); 353 354 realview_binfo.ram_size = ram_size; 355 realview_binfo.nb_cpus = smp_cpus; 356 realview_binfo.board_id = realview_board_id[board_type]; 357 realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0); 358 arm_load_kernel(ARM_CPU(first_cpu), machine, &realview_binfo); 359 } 360 361 static void realview_eb_init(MachineState *machine) 362 { 363 realview_init(machine, BOARD_EB); 364 } 365 366 static void realview_eb_mpcore_init(MachineState *machine) 367 { 368 realview_init(machine, BOARD_EB_MPCORE); 369 } 370 371 static void realview_pb_a8_init(MachineState *machine) 372 { 373 realview_init(machine, BOARD_PB_A8); 374 } 375 376 static void realview_pbx_a9_init(MachineState *machine) 377 { 378 realview_init(machine, BOARD_PBX_A9); 379 } 380 381 static void realview_eb_class_init(ObjectClass *oc, void *data) 382 { 383 MachineClass *mc = MACHINE_CLASS(oc); 384 385 mc->desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)"; 386 mc->init = realview_eb_init; 387 mc->block_default_type = IF_SCSI; 388 mc->ignore_memory_transaction_failures = true; 389 mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); 390 } 391 392 static const TypeInfo realview_eb_type = { 393 .name = MACHINE_TYPE_NAME("realview-eb"), 394 .parent = TYPE_MACHINE, 395 .class_init = realview_eb_class_init, 396 }; 397 398 static void realview_eb_mpcore_class_init(ObjectClass *oc, void *data) 399 { 400 MachineClass *mc = MACHINE_CLASS(oc); 401 402 mc->desc = "ARM RealView Emulation Baseboard (ARM11MPCore)"; 403 mc->init = realview_eb_mpcore_init; 404 mc->block_default_type = IF_SCSI; 405 mc->max_cpus = 4; 406 mc->ignore_memory_transaction_failures = true; 407 mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm11mpcore"); 408 } 409 410 static const TypeInfo realview_eb_mpcore_type = { 411 .name = MACHINE_TYPE_NAME("realview-eb-mpcore"), 412 .parent = TYPE_MACHINE, 413 .class_init = realview_eb_mpcore_class_init, 414 }; 415 416 static void realview_pb_a8_class_init(ObjectClass *oc, void *data) 417 { 418 MachineClass *mc = MACHINE_CLASS(oc); 419 420 mc->desc = "ARM RealView Platform Baseboard for Cortex-A8"; 421 mc->init = realview_pb_a8_init; 422 mc->ignore_memory_transaction_failures = true; 423 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a8"); 424 } 425 426 static const TypeInfo realview_pb_a8_type = { 427 .name = MACHINE_TYPE_NAME("realview-pb-a8"), 428 .parent = TYPE_MACHINE, 429 .class_init = realview_pb_a8_class_init, 430 }; 431 432 static void realview_pbx_a9_class_init(ObjectClass *oc, void *data) 433 { 434 MachineClass *mc = MACHINE_CLASS(oc); 435 436 mc->desc = "ARM RealView Platform Baseboard Explore for Cortex-A9"; 437 mc->init = realview_pbx_a9_init; 438 mc->max_cpus = 4; 439 mc->ignore_memory_transaction_failures = true; 440 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); 441 } 442 443 static const TypeInfo realview_pbx_a9_type = { 444 .name = MACHINE_TYPE_NAME("realview-pbx-a9"), 445 .parent = TYPE_MACHINE, 446 .class_init = realview_pbx_a9_class_init, 447 }; 448 449 static void realview_machine_init(void) 450 { 451 type_register_static(&realview_eb_type); 452 type_register_static(&realview_eb_mpcore_type); 453 type_register_static(&realview_pb_a8_type); 454 type_register_static(&realview_pbx_a9_type); 455 } 456 457 type_init(realview_machine_init) 458