1 /* 2 * ARM RealView Baseboard System emulation. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "hw/sysbus.h" 12 #include "hw/arm/arm.h" 13 #include "hw/arm/primecell.h" 14 #include "hw/devices.h" 15 #include "hw/pci/pci.h" 16 #include "net/net.h" 17 #include "sysemu/sysemu.h" 18 #include "hw/boards.h" 19 #include "hw/i2c/i2c.h" 20 #include "sysemu/block-backend.h" 21 #include "exec/address-spaces.h" 22 #include "qemu/error-report.h" 23 24 #define SMP_BOOT_ADDR 0xe0000000 25 #define SMP_BOOTREG_ADDR 0x10000030 26 27 /* Board init. */ 28 29 static struct arm_boot_info realview_binfo = { 30 .smp_loader_start = SMP_BOOT_ADDR, 31 .smp_bootreg_addr = SMP_BOOTREG_ADDR, 32 }; 33 34 /* The following two lists must be consistent. */ 35 enum realview_board_type { 36 BOARD_EB, 37 BOARD_EB_MPCORE, 38 BOARD_PB_A8, 39 BOARD_PBX_A9, 40 }; 41 42 static const int realview_board_id[] = { 43 0x33b, 44 0x33b, 45 0x769, 46 0x76d 47 }; 48 49 static void realview_init(MachineState *machine, 50 enum realview_board_type board_type) 51 { 52 ARMCPU *cpu = NULL; 53 CPUARMState *env; 54 ObjectClass *cpu_oc; 55 MemoryRegion *sysmem = get_system_memory(); 56 MemoryRegion *ram_lo; 57 MemoryRegion *ram_hi = g_new(MemoryRegion, 1); 58 MemoryRegion *ram_alias = g_new(MemoryRegion, 1); 59 MemoryRegion *ram_hack = g_new(MemoryRegion, 1); 60 DeviceState *dev, *sysctl, *gpio2, *pl041; 61 SysBusDevice *busdev; 62 qemu_irq pic[64]; 63 qemu_irq mmc_irq[2]; 64 PCIBus *pci_bus = NULL; 65 NICInfo *nd; 66 I2CBus *i2c; 67 int n; 68 int done_nic = 0; 69 qemu_irq cpu_irq[4]; 70 int is_mpcore = 0; 71 int is_pb = 0; 72 uint32_t proc_id = 0; 73 uint32_t sys_id; 74 ram_addr_t low_ram_size; 75 ram_addr_t ram_size = machine->ram_size; 76 hwaddr periphbase = 0; 77 78 switch (board_type) { 79 case BOARD_EB: 80 break; 81 case BOARD_EB_MPCORE: 82 is_mpcore = 1; 83 periphbase = 0x10100000; 84 break; 85 case BOARD_PB_A8: 86 is_pb = 1; 87 break; 88 case BOARD_PBX_A9: 89 is_mpcore = 1; 90 is_pb = 1; 91 periphbase = 0x1f000000; 92 break; 93 } 94 95 cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, machine->cpu_model); 96 if (!cpu_oc) { 97 fprintf(stderr, "Unable to find CPU definition\n"); 98 exit(1); 99 } 100 101 for (n = 0; n < smp_cpus; n++) { 102 Object *cpuobj = object_new(object_class_get_name(cpu_oc)); 103 104 /* By default A9,A15 and ARM1176 CPUs have EL3 enabled. This board 105 * does not currently support EL3 so the CPU EL3 property is disabled 106 * before realization. 107 */ 108 if (object_property_find(cpuobj, "has_el3", NULL)) { 109 object_property_set_bool(cpuobj, false, "has_el3", &error_fatal); 110 } 111 112 if (is_pb && is_mpcore) { 113 object_property_set_int(cpuobj, periphbase, "reset-cbar", 114 &error_fatal); 115 } 116 117 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 118 119 cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpuobj), ARM_CPU_IRQ); 120 } 121 cpu = ARM_CPU(first_cpu); 122 env = &cpu->env; 123 if (arm_feature(env, ARM_FEATURE_V7)) { 124 if (is_mpcore) { 125 proc_id = 0x0c000000; 126 } else { 127 proc_id = 0x0e000000; 128 } 129 } else if (arm_feature(env, ARM_FEATURE_V6K)) { 130 proc_id = 0x06000000; 131 } else if (arm_feature(env, ARM_FEATURE_V6)) { 132 proc_id = 0x04000000; 133 } else { 134 proc_id = 0x02000000; 135 } 136 137 if (is_pb && ram_size > 0x20000000) { 138 /* Core tile RAM. */ 139 ram_lo = g_new(MemoryRegion, 1); 140 low_ram_size = ram_size - 0x20000000; 141 ram_size = 0x20000000; 142 memory_region_init_ram(ram_lo, NULL, "realview.lowmem", low_ram_size, 143 &error_fatal); 144 vmstate_register_ram_global(ram_lo); 145 memory_region_add_subregion(sysmem, 0x20000000, ram_lo); 146 } 147 148 memory_region_init_ram(ram_hi, NULL, "realview.highmem", ram_size, 149 &error_fatal); 150 vmstate_register_ram_global(ram_hi); 151 low_ram_size = ram_size; 152 if (low_ram_size > 0x10000000) 153 low_ram_size = 0x10000000; 154 /* SDRAM at address zero. */ 155 memory_region_init_alias(ram_alias, NULL, "realview.alias", 156 ram_hi, 0, low_ram_size); 157 memory_region_add_subregion(sysmem, 0, ram_alias); 158 if (is_pb) { 159 /* And again at a high address. */ 160 memory_region_add_subregion(sysmem, 0x70000000, ram_hi); 161 } else { 162 ram_size = low_ram_size; 163 } 164 165 sys_id = is_pb ? 0x01780500 : 0xc1400400; 166 sysctl = qdev_create(NULL, "realview_sysctl"); 167 qdev_prop_set_uint32(sysctl, "sys_id", sys_id); 168 qdev_prop_set_uint32(sysctl, "proc_id", proc_id); 169 qdev_init_nofail(sysctl); 170 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000); 171 172 if (is_mpcore) { 173 dev = qdev_create(NULL, is_pb ? "a9mpcore_priv": "realview_mpcore"); 174 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 175 qdev_init_nofail(dev); 176 busdev = SYS_BUS_DEVICE(dev); 177 sysbus_mmio_map(busdev, 0, periphbase); 178 for (n = 0; n < smp_cpus; n++) { 179 sysbus_connect_irq(busdev, n, cpu_irq[n]); 180 } 181 sysbus_create_varargs("l2x0", periphbase + 0x2000, NULL); 182 /* Both A9 and 11MPCore put the GIC CPU i/f at base + 0x100 */ 183 realview_binfo.gic_cpu_if_addr = periphbase + 0x100; 184 } else { 185 uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000; 186 /* For now just create the nIRQ GIC, and ignore the others. */ 187 dev = sysbus_create_simple("realview_gic", gic_addr, cpu_irq[0]); 188 } 189 for (n = 0; n < 64; n++) { 190 pic[n] = qdev_get_gpio_in(dev, n); 191 } 192 193 pl041 = qdev_create(NULL, "pl041"); 194 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 195 qdev_init_nofail(pl041); 196 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000); 197 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[19]); 198 199 sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]); 200 sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]); 201 202 sysbus_create_simple("pl011", 0x10009000, pic[12]); 203 sysbus_create_simple("pl011", 0x1000a000, pic[13]); 204 sysbus_create_simple("pl011", 0x1000b000, pic[14]); 205 sysbus_create_simple("pl011", 0x1000c000, pic[15]); 206 207 /* DMA controller is optional, apparently. */ 208 sysbus_create_simple("pl081", 0x10030000, pic[24]); 209 210 sysbus_create_simple("sp804", 0x10011000, pic[4]); 211 sysbus_create_simple("sp804", 0x10012000, pic[5]); 212 213 sysbus_create_simple("pl061", 0x10013000, pic[6]); 214 sysbus_create_simple("pl061", 0x10014000, pic[7]); 215 gpio2 = sysbus_create_simple("pl061", 0x10015000, pic[8]); 216 217 sysbus_create_simple("pl111", 0x10020000, pic[23]); 218 219 dev = sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL); 220 /* Wire up MMC card detect and read-only signals. These have 221 * to go to both the PL061 GPIO and the sysctl register. 222 * Note that the PL181 orders these lines (readonly,inserted) 223 * and the PL061 has them the other way about. Also the card 224 * detect line is inverted. 225 */ 226 mmc_irq[0] = qemu_irq_split( 227 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT), 228 qdev_get_gpio_in(gpio2, 1)); 229 mmc_irq[1] = qemu_irq_split( 230 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN), 231 qemu_irq_invert(qdev_get_gpio_in(gpio2, 0))); 232 qdev_connect_gpio_out(dev, 0, mmc_irq[0]); 233 qdev_connect_gpio_out(dev, 1, mmc_irq[1]); 234 235 sysbus_create_simple("pl031", 0x10017000, pic[10]); 236 237 if (!is_pb) { 238 dev = qdev_create(NULL, "realview_pci"); 239 busdev = SYS_BUS_DEVICE(dev); 240 qdev_init_nofail(dev); 241 sysbus_mmio_map(busdev, 0, 0x10019000); /* PCI controller registers */ 242 sysbus_mmio_map(busdev, 1, 0x60000000); /* PCI self-config */ 243 sysbus_mmio_map(busdev, 2, 0x61000000); /* PCI config */ 244 sysbus_mmio_map(busdev, 3, 0x62000000); /* PCI I/O */ 245 sysbus_mmio_map(busdev, 4, 0x63000000); /* PCI memory window 1 */ 246 sysbus_mmio_map(busdev, 5, 0x64000000); /* PCI memory window 2 */ 247 sysbus_mmio_map(busdev, 6, 0x68000000); /* PCI memory window 3 */ 248 sysbus_connect_irq(busdev, 0, pic[48]); 249 sysbus_connect_irq(busdev, 1, pic[49]); 250 sysbus_connect_irq(busdev, 2, pic[50]); 251 sysbus_connect_irq(busdev, 3, pic[51]); 252 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci"); 253 if (usb_enabled()) { 254 pci_create_simple(pci_bus, -1, "pci-ohci"); 255 } 256 n = drive_get_max_bus(IF_SCSI); 257 while (n >= 0) { 258 pci_create_simple(pci_bus, -1, "lsi53c895a"); 259 n--; 260 } 261 } 262 for(n = 0; n < nb_nics; n++) { 263 nd = &nd_table[n]; 264 265 if (!done_nic && (!nd->model || 266 strcmp(nd->model, is_pb ? "lan9118" : "smc91c111") == 0)) { 267 if (is_pb) { 268 lan9118_init(nd, 0x4e000000, pic[28]); 269 } else { 270 smc91c111_init(nd, 0x4e000000, pic[28]); 271 } 272 done_nic = 1; 273 } else { 274 if (pci_bus) { 275 pci_nic_init_nofail(nd, pci_bus, "rtl8139", NULL); 276 } 277 } 278 } 279 280 dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL); 281 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 282 i2c_create_slave(i2c, "ds1338", 0x68); 283 284 /* Memory map for RealView Emulation Baseboard: */ 285 /* 0x10000000 System registers. */ 286 /* 0x10001000 System controller. */ 287 /* 0x10002000 Two-Wire Serial Bus. */ 288 /* 0x10003000 Reserved. */ 289 /* 0x10004000 AACI. */ 290 /* 0x10005000 MCI. */ 291 /* 0x10006000 KMI0. */ 292 /* 0x10007000 KMI1. */ 293 /* 0x10008000 Character LCD. (EB) */ 294 /* 0x10009000 UART0. */ 295 /* 0x1000a000 UART1. */ 296 /* 0x1000b000 UART2. */ 297 /* 0x1000c000 UART3. */ 298 /* 0x1000d000 SSPI. */ 299 /* 0x1000e000 SCI. */ 300 /* 0x1000f000 Reserved. */ 301 /* 0x10010000 Watchdog. */ 302 /* 0x10011000 Timer 0+1. */ 303 /* 0x10012000 Timer 2+3. */ 304 /* 0x10013000 GPIO 0. */ 305 /* 0x10014000 GPIO 1. */ 306 /* 0x10015000 GPIO 2. */ 307 /* 0x10002000 Two-Wire Serial Bus - DVI. (PB) */ 308 /* 0x10017000 RTC. */ 309 /* 0x10018000 DMC. */ 310 /* 0x10019000 PCI controller config. */ 311 /* 0x10020000 CLCD. */ 312 /* 0x10030000 DMA Controller. */ 313 /* 0x10040000 GIC1. (EB) */ 314 /* 0x10050000 GIC2. (EB) */ 315 /* 0x10060000 GIC3. (EB) */ 316 /* 0x10070000 GIC4. (EB) */ 317 /* 0x10080000 SMC. */ 318 /* 0x1e000000 GIC1. (PB) */ 319 /* 0x1e001000 GIC2. (PB) */ 320 /* 0x1e002000 GIC3. (PB) */ 321 /* 0x1e003000 GIC4. (PB) */ 322 /* 0x40000000 NOR flash. */ 323 /* 0x44000000 DoC flash. */ 324 /* 0x48000000 SRAM. */ 325 /* 0x4c000000 Configuration flash. */ 326 /* 0x4e000000 Ethernet. */ 327 /* 0x4f000000 USB. */ 328 /* 0x50000000 PISMO. */ 329 /* 0x54000000 PISMO. */ 330 /* 0x58000000 PISMO. */ 331 /* 0x5c000000 PISMO. */ 332 /* 0x60000000 PCI. */ 333 /* 0x60000000 PCI Self Config. */ 334 /* 0x61000000 PCI Config. */ 335 /* 0x62000000 PCI IO. */ 336 /* 0x63000000 PCI mem 0. */ 337 /* 0x64000000 PCI mem 1. */ 338 /* 0x68000000 PCI mem 2. */ 339 340 /* ??? Hack to map an additional page of ram for the secondary CPU 341 startup code. I guess this works on real hardware because the 342 BootROM happens to be in ROM/flash or in memory that isn't clobbered 343 until after Linux boots the secondary CPUs. */ 344 memory_region_init_ram(ram_hack, NULL, "realview.hack", 0x1000, 345 &error_fatal); 346 vmstate_register_ram_global(ram_hack); 347 memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, ram_hack); 348 349 realview_binfo.ram_size = ram_size; 350 realview_binfo.kernel_filename = machine->kernel_filename; 351 realview_binfo.kernel_cmdline = machine->kernel_cmdline; 352 realview_binfo.initrd_filename = machine->initrd_filename; 353 realview_binfo.nb_cpus = smp_cpus; 354 realview_binfo.board_id = realview_board_id[board_type]; 355 realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0); 356 arm_load_kernel(ARM_CPU(first_cpu), &realview_binfo); 357 } 358 359 static void realview_eb_init(MachineState *machine) 360 { 361 if (!machine->cpu_model) { 362 machine->cpu_model = "arm926"; 363 } 364 realview_init(machine, BOARD_EB); 365 } 366 367 static void realview_eb_mpcore_init(MachineState *machine) 368 { 369 if (!machine->cpu_model) { 370 machine->cpu_model = "arm11mpcore"; 371 } 372 realview_init(machine, BOARD_EB_MPCORE); 373 } 374 375 static void realview_pb_a8_init(MachineState *machine) 376 { 377 if (!machine->cpu_model) { 378 machine->cpu_model = "cortex-a8"; 379 } 380 realview_init(machine, BOARD_PB_A8); 381 } 382 383 static void realview_pbx_a9_init(MachineState *machine) 384 { 385 if (!machine->cpu_model) { 386 machine->cpu_model = "cortex-a9"; 387 } 388 realview_init(machine, BOARD_PBX_A9); 389 } 390 391 static void realview_eb_class_init(ObjectClass *oc, void *data) 392 { 393 MachineClass *mc = MACHINE_CLASS(oc); 394 395 mc->desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)"; 396 mc->init = realview_eb_init; 397 mc->block_default_type = IF_SCSI; 398 } 399 400 static const TypeInfo realview_eb_type = { 401 .name = MACHINE_TYPE_NAME("realview-eb"), 402 .parent = TYPE_MACHINE, 403 .class_init = realview_eb_class_init, 404 }; 405 406 static void realview_eb_mpcore_class_init(ObjectClass *oc, void *data) 407 { 408 MachineClass *mc = MACHINE_CLASS(oc); 409 410 mc->desc = "ARM RealView Emulation Baseboard (ARM11MPCore)"; 411 mc->init = realview_eb_mpcore_init; 412 mc->block_default_type = IF_SCSI; 413 mc->max_cpus = 4; 414 } 415 416 static const TypeInfo realview_eb_mpcore_type = { 417 .name = MACHINE_TYPE_NAME("realview-eb-mpcore"), 418 .parent = TYPE_MACHINE, 419 .class_init = realview_eb_mpcore_class_init, 420 }; 421 422 static void realview_pb_a8_class_init(ObjectClass *oc, void *data) 423 { 424 MachineClass *mc = MACHINE_CLASS(oc); 425 426 mc->desc = "ARM RealView Platform Baseboard for Cortex-A8"; 427 mc->init = realview_pb_a8_init; 428 } 429 430 static const TypeInfo realview_pb_a8_type = { 431 .name = MACHINE_TYPE_NAME("realview-pb-a8"), 432 .parent = TYPE_MACHINE, 433 .class_init = realview_pb_a8_class_init, 434 }; 435 436 static void realview_pbx_a9_class_init(ObjectClass *oc, void *data) 437 { 438 MachineClass *mc = MACHINE_CLASS(oc); 439 440 mc->desc = "ARM RealView Platform Baseboard Explore for Cortex-A9"; 441 mc->init = realview_pbx_a9_init; 442 mc->block_default_type = IF_SCSI; 443 mc->max_cpus = 4; 444 } 445 446 static const TypeInfo realview_pbx_a9_type = { 447 .name = MACHINE_TYPE_NAME("realview-pbx-a9"), 448 .parent = TYPE_MACHINE, 449 .class_init = realview_pbx_a9_class_init, 450 }; 451 452 static void realview_machine_init(void) 453 { 454 type_register_static(&realview_eb_type); 455 type_register_static(&realview_eb_mpcore_type); 456 type_register_static(&realview_pb_a8_type); 457 type_register_static(&realview_pbx_a9_type); 458 } 459 460 machine_init(realview_machine_init) 461