1 /* 2 * ARM RealView Baseboard System emulation. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "hw/sysbus.h" 11 #include "hw/arm/arm.h" 12 #include "hw/arm/primecell.h" 13 #include "hw/devices.h" 14 #include "hw/pci/pci.h" 15 #include "net/net.h" 16 #include "sysemu/sysemu.h" 17 #include "hw/boards.h" 18 #include "hw/i2c/i2c.h" 19 #include "sysemu/blockdev.h" 20 #include "exec/address-spaces.h" 21 22 #define SMP_BOOT_ADDR 0xe0000000 23 #define SMP_BOOTREG_ADDR 0x10000030 24 25 /* Board init. */ 26 27 static struct arm_boot_info realview_binfo = { 28 .smp_loader_start = SMP_BOOT_ADDR, 29 .smp_bootreg_addr = SMP_BOOTREG_ADDR, 30 }; 31 32 /* The following two lists must be consistent. */ 33 enum realview_board_type { 34 BOARD_EB, 35 BOARD_EB_MPCORE, 36 BOARD_PB_A8, 37 BOARD_PBX_A9, 38 }; 39 40 static const int realview_board_id[] = { 41 0x33b, 42 0x33b, 43 0x769, 44 0x76d 45 }; 46 47 static void realview_init(QEMUMachineInitArgs *args, 48 enum realview_board_type board_type) 49 { 50 ARMCPU *cpu = NULL; 51 CPUARMState *env; 52 MemoryRegion *sysmem = get_system_memory(); 53 MemoryRegion *ram_lo = g_new(MemoryRegion, 1); 54 MemoryRegion *ram_hi = g_new(MemoryRegion, 1); 55 MemoryRegion *ram_alias = g_new(MemoryRegion, 1); 56 MemoryRegion *ram_hack = g_new(MemoryRegion, 1); 57 DeviceState *dev, *sysctl, *gpio2, *pl041; 58 SysBusDevice *busdev; 59 qemu_irq *irqp; 60 qemu_irq pic[64]; 61 qemu_irq mmc_irq[2]; 62 PCIBus *pci_bus = NULL; 63 NICInfo *nd; 64 i2c_bus *i2c; 65 int n; 66 int done_nic = 0; 67 qemu_irq cpu_irq[4]; 68 int is_mpcore = 0; 69 int is_pb = 0; 70 uint32_t proc_id = 0; 71 uint32_t sys_id; 72 ram_addr_t low_ram_size; 73 ram_addr_t ram_size = args->ram_size; 74 75 switch (board_type) { 76 case BOARD_EB: 77 break; 78 case BOARD_EB_MPCORE: 79 is_mpcore = 1; 80 break; 81 case BOARD_PB_A8: 82 is_pb = 1; 83 break; 84 case BOARD_PBX_A9: 85 is_mpcore = 1; 86 is_pb = 1; 87 break; 88 } 89 for (n = 0; n < smp_cpus; n++) { 90 cpu = cpu_arm_init(args->cpu_model); 91 if (!cpu) { 92 fprintf(stderr, "Unable to find CPU definition\n"); 93 exit(1); 94 } 95 irqp = arm_pic_init_cpu(cpu); 96 cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ]; 97 } 98 env = &cpu->env; 99 if (arm_feature(env, ARM_FEATURE_V7)) { 100 if (is_mpcore) { 101 proc_id = 0x0c000000; 102 } else { 103 proc_id = 0x0e000000; 104 } 105 } else if (arm_feature(env, ARM_FEATURE_V6K)) { 106 proc_id = 0x06000000; 107 } else if (arm_feature(env, ARM_FEATURE_V6)) { 108 proc_id = 0x04000000; 109 } else { 110 proc_id = 0x02000000; 111 } 112 113 if (is_pb && ram_size > 0x20000000) { 114 /* Core tile RAM. */ 115 low_ram_size = ram_size - 0x20000000; 116 ram_size = 0x20000000; 117 memory_region_init_ram(ram_lo, NULL, "realview.lowmem", low_ram_size); 118 vmstate_register_ram_global(ram_lo); 119 memory_region_add_subregion(sysmem, 0x20000000, ram_lo); 120 } 121 122 memory_region_init_ram(ram_hi, NULL, "realview.highmem", ram_size); 123 vmstate_register_ram_global(ram_hi); 124 low_ram_size = ram_size; 125 if (low_ram_size > 0x10000000) 126 low_ram_size = 0x10000000; 127 /* SDRAM at address zero. */ 128 memory_region_init_alias(ram_alias, NULL, "realview.alias", 129 ram_hi, 0, low_ram_size); 130 memory_region_add_subregion(sysmem, 0, ram_alias); 131 if (is_pb) { 132 /* And again at a high address. */ 133 memory_region_add_subregion(sysmem, 0x70000000, ram_hi); 134 } else { 135 ram_size = low_ram_size; 136 } 137 138 sys_id = is_pb ? 0x01780500 : 0xc1400400; 139 sysctl = qdev_create(NULL, "realview_sysctl"); 140 qdev_prop_set_uint32(sysctl, "sys_id", sys_id); 141 qdev_prop_set_uint32(sysctl, "proc_id", proc_id); 142 qdev_init_nofail(sysctl); 143 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000); 144 145 if (is_mpcore) { 146 hwaddr periphbase; 147 dev = qdev_create(NULL, is_pb ? "a9mpcore_priv": "realview_mpcore"); 148 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 149 qdev_init_nofail(dev); 150 busdev = SYS_BUS_DEVICE(dev); 151 if (is_pb) { 152 periphbase = 0x1f000000; 153 } else { 154 periphbase = 0x10100000; 155 } 156 sysbus_mmio_map(busdev, 0, periphbase); 157 for (n = 0; n < smp_cpus; n++) { 158 sysbus_connect_irq(busdev, n, cpu_irq[n]); 159 } 160 sysbus_create_varargs("l2x0", periphbase + 0x2000, NULL); 161 /* Both A9 and 11MPCore put the GIC CPU i/f at base + 0x100 */ 162 realview_binfo.gic_cpu_if_addr = periphbase + 0x100; 163 } else { 164 uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000; 165 /* For now just create the nIRQ GIC, and ignore the others. */ 166 dev = sysbus_create_simple("realview_gic", gic_addr, cpu_irq[0]); 167 } 168 for (n = 0; n < 64; n++) { 169 pic[n] = qdev_get_gpio_in(dev, n); 170 } 171 172 pl041 = qdev_create(NULL, "pl041"); 173 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 174 qdev_init_nofail(pl041); 175 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000); 176 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[19]); 177 178 sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]); 179 sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]); 180 181 sysbus_create_simple("pl011", 0x10009000, pic[12]); 182 sysbus_create_simple("pl011", 0x1000a000, pic[13]); 183 sysbus_create_simple("pl011", 0x1000b000, pic[14]); 184 sysbus_create_simple("pl011", 0x1000c000, pic[15]); 185 186 /* DMA controller is optional, apparently. */ 187 sysbus_create_simple("pl081", 0x10030000, pic[24]); 188 189 sysbus_create_simple("sp804", 0x10011000, pic[4]); 190 sysbus_create_simple("sp804", 0x10012000, pic[5]); 191 192 sysbus_create_simple("pl061", 0x10013000, pic[6]); 193 sysbus_create_simple("pl061", 0x10014000, pic[7]); 194 gpio2 = sysbus_create_simple("pl061", 0x10015000, pic[8]); 195 196 sysbus_create_simple("pl111", 0x10020000, pic[23]); 197 198 dev = sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL); 199 /* Wire up MMC card detect and read-only signals. These have 200 * to go to both the PL061 GPIO and the sysctl register. 201 * Note that the PL181 orders these lines (readonly,inserted) 202 * and the PL061 has them the other way about. Also the card 203 * detect line is inverted. 204 */ 205 mmc_irq[0] = qemu_irq_split( 206 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT), 207 qdev_get_gpio_in(gpio2, 1)); 208 mmc_irq[1] = qemu_irq_split( 209 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN), 210 qemu_irq_invert(qdev_get_gpio_in(gpio2, 0))); 211 qdev_connect_gpio_out(dev, 0, mmc_irq[0]); 212 qdev_connect_gpio_out(dev, 1, mmc_irq[1]); 213 214 sysbus_create_simple("pl031", 0x10017000, pic[10]); 215 216 if (!is_pb) { 217 dev = qdev_create(NULL, "realview_pci"); 218 busdev = SYS_BUS_DEVICE(dev); 219 qdev_init_nofail(dev); 220 sysbus_mmio_map(busdev, 0, 0x10019000); /* PCI controller registers */ 221 sysbus_mmio_map(busdev, 1, 0x60000000); /* PCI self-config */ 222 sysbus_mmio_map(busdev, 2, 0x61000000); /* PCI config */ 223 sysbus_mmio_map(busdev, 3, 0x62000000); /* PCI I/O */ 224 sysbus_mmio_map(busdev, 4, 0x63000000); /* PCI memory window 1 */ 225 sysbus_mmio_map(busdev, 5, 0x64000000); /* PCI memory window 2 */ 226 sysbus_mmio_map(busdev, 6, 0x68000000); /* PCI memory window 3 */ 227 sysbus_connect_irq(busdev, 0, pic[48]); 228 sysbus_connect_irq(busdev, 1, pic[49]); 229 sysbus_connect_irq(busdev, 2, pic[50]); 230 sysbus_connect_irq(busdev, 3, pic[51]); 231 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci"); 232 if (usb_enabled(false)) { 233 pci_create_simple(pci_bus, -1, "pci-ohci"); 234 } 235 n = drive_get_max_bus(IF_SCSI); 236 while (n >= 0) { 237 pci_create_simple(pci_bus, -1, "lsi53c895a"); 238 n--; 239 } 240 } 241 for(n = 0; n < nb_nics; n++) { 242 nd = &nd_table[n]; 243 244 if (!done_nic && (!nd->model || 245 strcmp(nd->model, is_pb ? "lan9118" : "smc91c111") == 0)) { 246 if (is_pb) { 247 lan9118_init(nd, 0x4e000000, pic[28]); 248 } else { 249 smc91c111_init(nd, 0x4e000000, pic[28]); 250 } 251 done_nic = 1; 252 } else { 253 if (pci_bus) { 254 pci_nic_init_nofail(nd, pci_bus, "rtl8139", NULL); 255 } 256 } 257 } 258 259 dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL); 260 i2c = (i2c_bus *)qdev_get_child_bus(dev, "i2c"); 261 i2c_create_slave(i2c, "ds1338", 0x68); 262 263 /* Memory map for RealView Emulation Baseboard: */ 264 /* 0x10000000 System registers. */ 265 /* 0x10001000 System controller. */ 266 /* 0x10002000 Two-Wire Serial Bus. */ 267 /* 0x10003000 Reserved. */ 268 /* 0x10004000 AACI. */ 269 /* 0x10005000 MCI. */ 270 /* 0x10006000 KMI0. */ 271 /* 0x10007000 KMI1. */ 272 /* 0x10008000 Character LCD. (EB) */ 273 /* 0x10009000 UART0. */ 274 /* 0x1000a000 UART1. */ 275 /* 0x1000b000 UART2. */ 276 /* 0x1000c000 UART3. */ 277 /* 0x1000d000 SSPI. */ 278 /* 0x1000e000 SCI. */ 279 /* 0x1000f000 Reserved. */ 280 /* 0x10010000 Watchdog. */ 281 /* 0x10011000 Timer 0+1. */ 282 /* 0x10012000 Timer 2+3. */ 283 /* 0x10013000 GPIO 0. */ 284 /* 0x10014000 GPIO 1. */ 285 /* 0x10015000 GPIO 2. */ 286 /* 0x10002000 Two-Wire Serial Bus - DVI. (PB) */ 287 /* 0x10017000 RTC. */ 288 /* 0x10018000 DMC. */ 289 /* 0x10019000 PCI controller config. */ 290 /* 0x10020000 CLCD. */ 291 /* 0x10030000 DMA Controller. */ 292 /* 0x10040000 GIC1. (EB) */ 293 /* 0x10050000 GIC2. (EB) */ 294 /* 0x10060000 GIC3. (EB) */ 295 /* 0x10070000 GIC4. (EB) */ 296 /* 0x10080000 SMC. */ 297 /* 0x1e000000 GIC1. (PB) */ 298 /* 0x1e001000 GIC2. (PB) */ 299 /* 0x1e002000 GIC3. (PB) */ 300 /* 0x1e003000 GIC4. (PB) */ 301 /* 0x40000000 NOR flash. */ 302 /* 0x44000000 DoC flash. */ 303 /* 0x48000000 SRAM. */ 304 /* 0x4c000000 Configuration flash. */ 305 /* 0x4e000000 Ethernet. */ 306 /* 0x4f000000 USB. */ 307 /* 0x50000000 PISMO. */ 308 /* 0x54000000 PISMO. */ 309 /* 0x58000000 PISMO. */ 310 /* 0x5c000000 PISMO. */ 311 /* 0x60000000 PCI. */ 312 /* 0x60000000 PCI Self Config. */ 313 /* 0x61000000 PCI Config. */ 314 /* 0x62000000 PCI IO. */ 315 /* 0x63000000 PCI mem 0. */ 316 /* 0x64000000 PCI mem 1. */ 317 /* 0x68000000 PCI mem 2. */ 318 319 /* ??? Hack to map an additional page of ram for the secondary CPU 320 startup code. I guess this works on real hardware because the 321 BootROM happens to be in ROM/flash or in memory that isn't clobbered 322 until after Linux boots the secondary CPUs. */ 323 memory_region_init_ram(ram_hack, NULL, "realview.hack", 0x1000); 324 vmstate_register_ram_global(ram_hack); 325 memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, ram_hack); 326 327 realview_binfo.ram_size = ram_size; 328 realview_binfo.kernel_filename = args->kernel_filename; 329 realview_binfo.kernel_cmdline = args->kernel_cmdline; 330 realview_binfo.initrd_filename = args->initrd_filename; 331 realview_binfo.nb_cpus = smp_cpus; 332 realview_binfo.board_id = realview_board_id[board_type]; 333 realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0); 334 arm_load_kernel(ARM_CPU(first_cpu), &realview_binfo); 335 } 336 337 static void realview_eb_init(QEMUMachineInitArgs *args) 338 { 339 if (!args->cpu_model) { 340 args->cpu_model = "arm926"; 341 } 342 realview_init(args, BOARD_EB); 343 } 344 345 static void realview_eb_mpcore_init(QEMUMachineInitArgs *args) 346 { 347 if (!args->cpu_model) { 348 args->cpu_model = "arm11mpcore"; 349 } 350 realview_init(args, BOARD_EB_MPCORE); 351 } 352 353 static void realview_pb_a8_init(QEMUMachineInitArgs *args) 354 { 355 if (!args->cpu_model) { 356 args->cpu_model = "cortex-a8"; 357 } 358 realview_init(args, BOARD_PB_A8); 359 } 360 361 static void realview_pbx_a9_init(QEMUMachineInitArgs *args) 362 { 363 if (!args->cpu_model) { 364 args->cpu_model = "cortex-a9"; 365 } 366 realview_init(args, BOARD_PBX_A9); 367 } 368 369 static QEMUMachine realview_eb_machine = { 370 .name = "realview-eb", 371 .desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)", 372 .init = realview_eb_init, 373 .block_default_type = IF_SCSI, 374 DEFAULT_MACHINE_OPTIONS, 375 }; 376 377 static QEMUMachine realview_eb_mpcore_machine = { 378 .name = "realview-eb-mpcore", 379 .desc = "ARM RealView Emulation Baseboard (ARM11MPCore)", 380 .init = realview_eb_mpcore_init, 381 .block_default_type = IF_SCSI, 382 .max_cpus = 4, 383 DEFAULT_MACHINE_OPTIONS, 384 }; 385 386 static QEMUMachine realview_pb_a8_machine = { 387 .name = "realview-pb-a8", 388 .desc = "ARM RealView Platform Baseboard for Cortex-A8", 389 .init = realview_pb_a8_init, 390 DEFAULT_MACHINE_OPTIONS, 391 }; 392 393 static QEMUMachine realview_pbx_a9_machine = { 394 .name = "realview-pbx-a9", 395 .desc = "ARM RealView Platform Baseboard Explore for Cortex-A9", 396 .init = realview_pbx_a9_init, 397 .block_default_type = IF_SCSI, 398 .max_cpus = 4, 399 DEFAULT_MACHINE_OPTIONS, 400 }; 401 402 static void realview_machine_init(void) 403 { 404 qemu_register_machine(&realview_eb_machine); 405 qemu_register_machine(&realview_eb_mpcore_machine); 406 qemu_register_machine(&realview_pb_a8_machine); 407 qemu_register_machine(&realview_pbx_a9_machine); 408 } 409 410 machine_init(realview_machine_init); 411