1 /* 2 * ARM RealView Baseboard System emulation. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "hw/sysbus.h" 11 #include "hw/arm/arm.h" 12 #include "hw/arm/primecell.h" 13 #include "hw/devices.h" 14 #include "hw/pci/pci.h" 15 #include "net/net.h" 16 #include "sysemu/sysemu.h" 17 #include "hw/boards.h" 18 #include "hw/i2c/i2c.h" 19 #include "sysemu/block-backend.h" 20 #include "exec/address-spaces.h" 21 #include "qemu/error-report.h" 22 23 #define SMP_BOOT_ADDR 0xe0000000 24 #define SMP_BOOTREG_ADDR 0x10000030 25 26 /* Board init. */ 27 28 static struct arm_boot_info realview_binfo = { 29 .smp_loader_start = SMP_BOOT_ADDR, 30 .smp_bootreg_addr = SMP_BOOTREG_ADDR, 31 }; 32 33 /* The following two lists must be consistent. */ 34 enum realview_board_type { 35 BOARD_EB, 36 BOARD_EB_MPCORE, 37 BOARD_PB_A8, 38 BOARD_PBX_A9, 39 }; 40 41 static const int realview_board_id[] = { 42 0x33b, 43 0x33b, 44 0x769, 45 0x76d 46 }; 47 48 static void realview_init(MachineState *machine, 49 enum realview_board_type board_type) 50 { 51 ARMCPU *cpu = NULL; 52 CPUARMState *env; 53 ObjectClass *cpu_oc; 54 MemoryRegion *sysmem = get_system_memory(); 55 MemoryRegion *ram_lo; 56 MemoryRegion *ram_hi = g_new(MemoryRegion, 1); 57 MemoryRegion *ram_alias = g_new(MemoryRegion, 1); 58 MemoryRegion *ram_hack = g_new(MemoryRegion, 1); 59 DeviceState *dev, *sysctl, *gpio2, *pl041; 60 SysBusDevice *busdev; 61 qemu_irq pic[64]; 62 qemu_irq mmc_irq[2]; 63 PCIBus *pci_bus = NULL; 64 NICInfo *nd; 65 I2CBus *i2c; 66 int n; 67 int done_nic = 0; 68 qemu_irq cpu_irq[4]; 69 int is_mpcore = 0; 70 int is_pb = 0; 71 uint32_t proc_id = 0; 72 uint32_t sys_id; 73 ram_addr_t low_ram_size; 74 ram_addr_t ram_size = machine->ram_size; 75 hwaddr periphbase = 0; 76 77 switch (board_type) { 78 case BOARD_EB: 79 break; 80 case BOARD_EB_MPCORE: 81 is_mpcore = 1; 82 periphbase = 0x10100000; 83 break; 84 case BOARD_PB_A8: 85 is_pb = 1; 86 break; 87 case BOARD_PBX_A9: 88 is_mpcore = 1; 89 is_pb = 1; 90 periphbase = 0x1f000000; 91 break; 92 } 93 94 cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, machine->cpu_model); 95 if (!cpu_oc) { 96 fprintf(stderr, "Unable to find CPU definition\n"); 97 exit(1); 98 } 99 100 for (n = 0; n < smp_cpus; n++) { 101 Object *cpuobj = object_new(object_class_get_name(cpu_oc)); 102 103 /* By default A9,A15 and ARM1176 CPUs have EL3 enabled. This board 104 * does not currently support EL3 so the CPU EL3 property is disabled 105 * before realization. 106 */ 107 if (object_property_find(cpuobj, "has_el3", NULL)) { 108 object_property_set_bool(cpuobj, false, "has_el3", &error_fatal); 109 } 110 111 if (is_pb && is_mpcore) { 112 object_property_set_int(cpuobj, periphbase, "reset-cbar", 113 &error_fatal); 114 } 115 116 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 117 118 cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpuobj), ARM_CPU_IRQ); 119 } 120 cpu = ARM_CPU(first_cpu); 121 env = &cpu->env; 122 if (arm_feature(env, ARM_FEATURE_V7)) { 123 if (is_mpcore) { 124 proc_id = 0x0c000000; 125 } else { 126 proc_id = 0x0e000000; 127 } 128 } else if (arm_feature(env, ARM_FEATURE_V6K)) { 129 proc_id = 0x06000000; 130 } else if (arm_feature(env, ARM_FEATURE_V6)) { 131 proc_id = 0x04000000; 132 } else { 133 proc_id = 0x02000000; 134 } 135 136 if (is_pb && ram_size > 0x20000000) { 137 /* Core tile RAM. */ 138 ram_lo = g_new(MemoryRegion, 1); 139 low_ram_size = ram_size - 0x20000000; 140 ram_size = 0x20000000; 141 memory_region_init_ram(ram_lo, NULL, "realview.lowmem", low_ram_size, 142 &error_fatal); 143 vmstate_register_ram_global(ram_lo); 144 memory_region_add_subregion(sysmem, 0x20000000, ram_lo); 145 } 146 147 memory_region_init_ram(ram_hi, NULL, "realview.highmem", ram_size, 148 &error_fatal); 149 vmstate_register_ram_global(ram_hi); 150 low_ram_size = ram_size; 151 if (low_ram_size > 0x10000000) 152 low_ram_size = 0x10000000; 153 /* SDRAM at address zero. */ 154 memory_region_init_alias(ram_alias, NULL, "realview.alias", 155 ram_hi, 0, low_ram_size); 156 memory_region_add_subregion(sysmem, 0, ram_alias); 157 if (is_pb) { 158 /* And again at a high address. */ 159 memory_region_add_subregion(sysmem, 0x70000000, ram_hi); 160 } else { 161 ram_size = low_ram_size; 162 } 163 164 sys_id = is_pb ? 0x01780500 : 0xc1400400; 165 sysctl = qdev_create(NULL, "realview_sysctl"); 166 qdev_prop_set_uint32(sysctl, "sys_id", sys_id); 167 qdev_prop_set_uint32(sysctl, "proc_id", proc_id); 168 qdev_init_nofail(sysctl); 169 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000); 170 171 if (is_mpcore) { 172 dev = qdev_create(NULL, is_pb ? "a9mpcore_priv": "realview_mpcore"); 173 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 174 qdev_init_nofail(dev); 175 busdev = SYS_BUS_DEVICE(dev); 176 sysbus_mmio_map(busdev, 0, periphbase); 177 for (n = 0; n < smp_cpus; n++) { 178 sysbus_connect_irq(busdev, n, cpu_irq[n]); 179 } 180 sysbus_create_varargs("l2x0", periphbase + 0x2000, NULL); 181 /* Both A9 and 11MPCore put the GIC CPU i/f at base + 0x100 */ 182 realview_binfo.gic_cpu_if_addr = periphbase + 0x100; 183 } else { 184 uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000; 185 /* For now just create the nIRQ GIC, and ignore the others. */ 186 dev = sysbus_create_simple("realview_gic", gic_addr, cpu_irq[0]); 187 } 188 for (n = 0; n < 64; n++) { 189 pic[n] = qdev_get_gpio_in(dev, n); 190 } 191 192 pl041 = qdev_create(NULL, "pl041"); 193 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 194 qdev_init_nofail(pl041); 195 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000); 196 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[19]); 197 198 sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]); 199 sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]); 200 201 sysbus_create_simple("pl011", 0x10009000, pic[12]); 202 sysbus_create_simple("pl011", 0x1000a000, pic[13]); 203 sysbus_create_simple("pl011", 0x1000b000, pic[14]); 204 sysbus_create_simple("pl011", 0x1000c000, pic[15]); 205 206 /* DMA controller is optional, apparently. */ 207 sysbus_create_simple("pl081", 0x10030000, pic[24]); 208 209 sysbus_create_simple("sp804", 0x10011000, pic[4]); 210 sysbus_create_simple("sp804", 0x10012000, pic[5]); 211 212 sysbus_create_simple("pl061", 0x10013000, pic[6]); 213 sysbus_create_simple("pl061", 0x10014000, pic[7]); 214 gpio2 = sysbus_create_simple("pl061", 0x10015000, pic[8]); 215 216 sysbus_create_simple("pl111", 0x10020000, pic[23]); 217 218 dev = sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL); 219 /* Wire up MMC card detect and read-only signals. These have 220 * to go to both the PL061 GPIO and the sysctl register. 221 * Note that the PL181 orders these lines (readonly,inserted) 222 * and the PL061 has them the other way about. Also the card 223 * detect line is inverted. 224 */ 225 mmc_irq[0] = qemu_irq_split( 226 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT), 227 qdev_get_gpio_in(gpio2, 1)); 228 mmc_irq[1] = qemu_irq_split( 229 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN), 230 qemu_irq_invert(qdev_get_gpio_in(gpio2, 0))); 231 qdev_connect_gpio_out(dev, 0, mmc_irq[0]); 232 qdev_connect_gpio_out(dev, 1, mmc_irq[1]); 233 234 sysbus_create_simple("pl031", 0x10017000, pic[10]); 235 236 if (!is_pb) { 237 dev = qdev_create(NULL, "realview_pci"); 238 busdev = SYS_BUS_DEVICE(dev); 239 qdev_init_nofail(dev); 240 sysbus_mmio_map(busdev, 0, 0x10019000); /* PCI controller registers */ 241 sysbus_mmio_map(busdev, 1, 0x60000000); /* PCI self-config */ 242 sysbus_mmio_map(busdev, 2, 0x61000000); /* PCI config */ 243 sysbus_mmio_map(busdev, 3, 0x62000000); /* PCI I/O */ 244 sysbus_mmio_map(busdev, 4, 0x63000000); /* PCI memory window 1 */ 245 sysbus_mmio_map(busdev, 5, 0x64000000); /* PCI memory window 2 */ 246 sysbus_mmio_map(busdev, 6, 0x68000000); /* PCI memory window 3 */ 247 sysbus_connect_irq(busdev, 0, pic[48]); 248 sysbus_connect_irq(busdev, 1, pic[49]); 249 sysbus_connect_irq(busdev, 2, pic[50]); 250 sysbus_connect_irq(busdev, 3, pic[51]); 251 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci"); 252 if (usb_enabled()) { 253 pci_create_simple(pci_bus, -1, "pci-ohci"); 254 } 255 n = drive_get_max_bus(IF_SCSI); 256 while (n >= 0) { 257 pci_create_simple(pci_bus, -1, "lsi53c895a"); 258 n--; 259 } 260 } 261 for(n = 0; n < nb_nics; n++) { 262 nd = &nd_table[n]; 263 264 if (!done_nic && (!nd->model || 265 strcmp(nd->model, is_pb ? "lan9118" : "smc91c111") == 0)) { 266 if (is_pb) { 267 lan9118_init(nd, 0x4e000000, pic[28]); 268 } else { 269 smc91c111_init(nd, 0x4e000000, pic[28]); 270 } 271 done_nic = 1; 272 } else { 273 if (pci_bus) { 274 pci_nic_init_nofail(nd, pci_bus, "rtl8139", NULL); 275 } 276 } 277 } 278 279 dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL); 280 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 281 i2c_create_slave(i2c, "ds1338", 0x68); 282 283 /* Memory map for RealView Emulation Baseboard: */ 284 /* 0x10000000 System registers. */ 285 /* 0x10001000 System controller. */ 286 /* 0x10002000 Two-Wire Serial Bus. */ 287 /* 0x10003000 Reserved. */ 288 /* 0x10004000 AACI. */ 289 /* 0x10005000 MCI. */ 290 /* 0x10006000 KMI0. */ 291 /* 0x10007000 KMI1. */ 292 /* 0x10008000 Character LCD. (EB) */ 293 /* 0x10009000 UART0. */ 294 /* 0x1000a000 UART1. */ 295 /* 0x1000b000 UART2. */ 296 /* 0x1000c000 UART3. */ 297 /* 0x1000d000 SSPI. */ 298 /* 0x1000e000 SCI. */ 299 /* 0x1000f000 Reserved. */ 300 /* 0x10010000 Watchdog. */ 301 /* 0x10011000 Timer 0+1. */ 302 /* 0x10012000 Timer 2+3. */ 303 /* 0x10013000 GPIO 0. */ 304 /* 0x10014000 GPIO 1. */ 305 /* 0x10015000 GPIO 2. */ 306 /* 0x10002000 Two-Wire Serial Bus - DVI. (PB) */ 307 /* 0x10017000 RTC. */ 308 /* 0x10018000 DMC. */ 309 /* 0x10019000 PCI controller config. */ 310 /* 0x10020000 CLCD. */ 311 /* 0x10030000 DMA Controller. */ 312 /* 0x10040000 GIC1. (EB) */ 313 /* 0x10050000 GIC2. (EB) */ 314 /* 0x10060000 GIC3. (EB) */ 315 /* 0x10070000 GIC4. (EB) */ 316 /* 0x10080000 SMC. */ 317 /* 0x1e000000 GIC1. (PB) */ 318 /* 0x1e001000 GIC2. (PB) */ 319 /* 0x1e002000 GIC3. (PB) */ 320 /* 0x1e003000 GIC4. (PB) */ 321 /* 0x40000000 NOR flash. */ 322 /* 0x44000000 DoC flash. */ 323 /* 0x48000000 SRAM. */ 324 /* 0x4c000000 Configuration flash. */ 325 /* 0x4e000000 Ethernet. */ 326 /* 0x4f000000 USB. */ 327 /* 0x50000000 PISMO. */ 328 /* 0x54000000 PISMO. */ 329 /* 0x58000000 PISMO. */ 330 /* 0x5c000000 PISMO. */ 331 /* 0x60000000 PCI. */ 332 /* 0x60000000 PCI Self Config. */ 333 /* 0x61000000 PCI Config. */ 334 /* 0x62000000 PCI IO. */ 335 /* 0x63000000 PCI mem 0. */ 336 /* 0x64000000 PCI mem 1. */ 337 /* 0x68000000 PCI mem 2. */ 338 339 /* ??? Hack to map an additional page of ram for the secondary CPU 340 startup code. I guess this works on real hardware because the 341 BootROM happens to be in ROM/flash or in memory that isn't clobbered 342 until after Linux boots the secondary CPUs. */ 343 memory_region_init_ram(ram_hack, NULL, "realview.hack", 0x1000, 344 &error_fatal); 345 vmstate_register_ram_global(ram_hack); 346 memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, ram_hack); 347 348 realview_binfo.ram_size = ram_size; 349 realview_binfo.kernel_filename = machine->kernel_filename; 350 realview_binfo.kernel_cmdline = machine->kernel_cmdline; 351 realview_binfo.initrd_filename = machine->initrd_filename; 352 realview_binfo.nb_cpus = smp_cpus; 353 realview_binfo.board_id = realview_board_id[board_type]; 354 realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0); 355 arm_load_kernel(ARM_CPU(first_cpu), &realview_binfo); 356 } 357 358 static void realview_eb_init(MachineState *machine) 359 { 360 if (!machine->cpu_model) { 361 machine->cpu_model = "arm926"; 362 } 363 realview_init(machine, BOARD_EB); 364 } 365 366 static void realview_eb_mpcore_init(MachineState *machine) 367 { 368 if (!machine->cpu_model) { 369 machine->cpu_model = "arm11mpcore"; 370 } 371 realview_init(machine, BOARD_EB_MPCORE); 372 } 373 374 static void realview_pb_a8_init(MachineState *machine) 375 { 376 if (!machine->cpu_model) { 377 machine->cpu_model = "cortex-a8"; 378 } 379 realview_init(machine, BOARD_PB_A8); 380 } 381 382 static void realview_pbx_a9_init(MachineState *machine) 383 { 384 if (!machine->cpu_model) { 385 machine->cpu_model = "cortex-a9"; 386 } 387 realview_init(machine, BOARD_PBX_A9); 388 } 389 390 static void realview_eb_class_init(ObjectClass *oc, void *data) 391 { 392 MachineClass *mc = MACHINE_CLASS(oc); 393 394 mc->desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)"; 395 mc->init = realview_eb_init; 396 mc->block_default_type = IF_SCSI; 397 } 398 399 static const TypeInfo realview_eb_type = { 400 .name = MACHINE_TYPE_NAME("realview-eb"), 401 .parent = TYPE_MACHINE, 402 .class_init = realview_eb_class_init, 403 }; 404 405 static void realview_eb_mpcore_class_init(ObjectClass *oc, void *data) 406 { 407 MachineClass *mc = MACHINE_CLASS(oc); 408 409 mc->desc = "ARM RealView Emulation Baseboard (ARM11MPCore)"; 410 mc->init = realview_eb_mpcore_init; 411 mc->block_default_type = IF_SCSI; 412 mc->max_cpus = 4; 413 } 414 415 static const TypeInfo realview_eb_mpcore_type = { 416 .name = MACHINE_TYPE_NAME("realview-eb-mpcore"), 417 .parent = TYPE_MACHINE, 418 .class_init = realview_eb_mpcore_class_init, 419 }; 420 421 static void realview_pb_a8_class_init(ObjectClass *oc, void *data) 422 { 423 MachineClass *mc = MACHINE_CLASS(oc); 424 425 mc->desc = "ARM RealView Platform Baseboard for Cortex-A8"; 426 mc->init = realview_pb_a8_init; 427 } 428 429 static const TypeInfo realview_pb_a8_type = { 430 .name = MACHINE_TYPE_NAME("realview-pb-a8"), 431 .parent = TYPE_MACHINE, 432 .class_init = realview_pb_a8_class_init, 433 }; 434 435 static void realview_pbx_a9_class_init(ObjectClass *oc, void *data) 436 { 437 MachineClass *mc = MACHINE_CLASS(oc); 438 439 mc->desc = "ARM RealView Platform Baseboard Explore for Cortex-A9"; 440 mc->init = realview_pbx_a9_init; 441 mc->block_default_type = IF_SCSI; 442 mc->max_cpus = 4; 443 } 444 445 static const TypeInfo realview_pbx_a9_type = { 446 .name = MACHINE_TYPE_NAME("realview-pbx-a9"), 447 .parent = TYPE_MACHINE, 448 .class_init = realview_pbx_a9_class_init, 449 }; 450 451 static void realview_machine_init(void) 452 { 453 type_register_static(&realview_eb_type); 454 type_register_static(&realview_eb_mpcore_type); 455 type_register_static(&realview_pb_a8_type); 456 type_register_static(&realview_pbx_a9_type); 457 } 458 459 machine_init(realview_machine_init) 460