1 /* 2 * ARM RealView Baseboard System emulation. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "qemu-common.h" 13 #include "cpu.h" 14 #include "hw/sysbus.h" 15 #include "hw/arm/boot.h" 16 #include "hw/arm/primecell.h" 17 #include "hw/net/lan9118.h" 18 #include "hw/net/smc91c111.h" 19 #include "hw/pci/pci.h" 20 #include "net/net.h" 21 #include "sysemu/sysemu.h" 22 #include "hw/boards.h" 23 #include "hw/i2c/i2c.h" 24 #include "exec/address-spaces.h" 25 #include "qemu/error-report.h" 26 #include "hw/char/pl011.h" 27 #include "hw/cpu/a9mpcore.h" 28 #include "hw/intc/realview_gic.h" 29 30 #define SMP_BOOT_ADDR 0xe0000000 31 #define SMP_BOOTREG_ADDR 0x10000030 32 33 /* Board init. */ 34 35 static struct arm_boot_info realview_binfo = { 36 .smp_loader_start = SMP_BOOT_ADDR, 37 .smp_bootreg_addr = SMP_BOOTREG_ADDR, 38 }; 39 40 /* The following two lists must be consistent. */ 41 enum realview_board_type { 42 BOARD_EB, 43 BOARD_EB_MPCORE, 44 BOARD_PB_A8, 45 BOARD_PBX_A9, 46 }; 47 48 static const int realview_board_id[] = { 49 0x33b, 50 0x33b, 51 0x769, 52 0x76d 53 }; 54 55 static void realview_init(MachineState *machine, 56 enum realview_board_type board_type) 57 { 58 ARMCPU *cpu = NULL; 59 CPUARMState *env; 60 MemoryRegion *sysmem = get_system_memory(); 61 MemoryRegion *ram_lo; 62 MemoryRegion *ram_hi = g_new(MemoryRegion, 1); 63 MemoryRegion *ram_alias = g_new(MemoryRegion, 1); 64 MemoryRegion *ram_hack = g_new(MemoryRegion, 1); 65 DeviceState *dev, *sysctl, *gpio2, *pl041; 66 SysBusDevice *busdev; 67 qemu_irq pic[64]; 68 qemu_irq mmc_irq[2]; 69 PCIBus *pci_bus = NULL; 70 NICInfo *nd; 71 I2CBus *i2c; 72 int n; 73 int done_nic = 0; 74 qemu_irq cpu_irq[4]; 75 int is_mpcore = 0; 76 int is_pb = 0; 77 uint32_t proc_id = 0; 78 uint32_t sys_id; 79 ram_addr_t low_ram_size; 80 ram_addr_t ram_size = machine->ram_size; 81 hwaddr periphbase = 0; 82 83 switch (board_type) { 84 case BOARD_EB: 85 break; 86 case BOARD_EB_MPCORE: 87 is_mpcore = 1; 88 periphbase = 0x10100000; 89 break; 90 case BOARD_PB_A8: 91 is_pb = 1; 92 break; 93 case BOARD_PBX_A9: 94 is_mpcore = 1; 95 is_pb = 1; 96 periphbase = 0x1f000000; 97 break; 98 } 99 100 for (n = 0; n < smp_cpus; n++) { 101 Object *cpuobj = object_new(machine->cpu_type); 102 103 /* By default A9,A15 and ARM1176 CPUs have EL3 enabled. This board 104 * does not currently support EL3 so the CPU EL3 property is disabled 105 * before realization. 106 */ 107 if (object_property_find(cpuobj, "has_el3", NULL)) { 108 object_property_set_bool(cpuobj, false, "has_el3", &error_fatal); 109 } 110 111 if (is_pb && is_mpcore) { 112 object_property_set_int(cpuobj, periphbase, "reset-cbar", 113 &error_fatal); 114 } 115 116 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 117 118 cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpuobj), ARM_CPU_IRQ); 119 } 120 cpu = ARM_CPU(first_cpu); 121 env = &cpu->env; 122 if (arm_feature(env, ARM_FEATURE_V7)) { 123 if (is_mpcore) { 124 proc_id = 0x0c000000; 125 } else { 126 proc_id = 0x0e000000; 127 } 128 } else if (arm_feature(env, ARM_FEATURE_V6K)) { 129 proc_id = 0x06000000; 130 } else if (arm_feature(env, ARM_FEATURE_V6)) { 131 proc_id = 0x04000000; 132 } else { 133 proc_id = 0x02000000; 134 } 135 136 if (is_pb && ram_size > 0x20000000) { 137 /* Core tile RAM. */ 138 ram_lo = g_new(MemoryRegion, 1); 139 low_ram_size = ram_size - 0x20000000; 140 ram_size = 0x20000000; 141 memory_region_init_ram(ram_lo, NULL, "realview.lowmem", low_ram_size, 142 &error_fatal); 143 memory_region_add_subregion(sysmem, 0x20000000, ram_lo); 144 } 145 146 memory_region_init_ram(ram_hi, NULL, "realview.highmem", ram_size, 147 &error_fatal); 148 low_ram_size = ram_size; 149 if (low_ram_size > 0x10000000) 150 low_ram_size = 0x10000000; 151 /* SDRAM at address zero. */ 152 memory_region_init_alias(ram_alias, NULL, "realview.alias", 153 ram_hi, 0, low_ram_size); 154 memory_region_add_subregion(sysmem, 0, ram_alias); 155 if (is_pb) { 156 /* And again at a high address. */ 157 memory_region_add_subregion(sysmem, 0x70000000, ram_hi); 158 } else { 159 ram_size = low_ram_size; 160 } 161 162 sys_id = is_pb ? 0x01780500 : 0xc1400400; 163 sysctl = qdev_create(NULL, "realview_sysctl"); 164 qdev_prop_set_uint32(sysctl, "sys_id", sys_id); 165 qdev_prop_set_uint32(sysctl, "proc_id", proc_id); 166 qdev_init_nofail(sysctl); 167 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000); 168 169 if (is_mpcore) { 170 dev = qdev_create(NULL, is_pb ? TYPE_A9MPCORE_PRIV : "realview_mpcore"); 171 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 172 qdev_init_nofail(dev); 173 busdev = SYS_BUS_DEVICE(dev); 174 sysbus_mmio_map(busdev, 0, periphbase); 175 for (n = 0; n < smp_cpus; n++) { 176 sysbus_connect_irq(busdev, n, cpu_irq[n]); 177 } 178 sysbus_create_varargs("l2x0", periphbase + 0x2000, NULL); 179 /* Both A9 and 11MPCore put the GIC CPU i/f at base + 0x100 */ 180 realview_binfo.gic_cpu_if_addr = periphbase + 0x100; 181 } else { 182 uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000; 183 /* For now just create the nIRQ GIC, and ignore the others. */ 184 dev = sysbus_create_simple(TYPE_REALVIEW_GIC, gic_addr, cpu_irq[0]); 185 } 186 for (n = 0; n < 64; n++) { 187 pic[n] = qdev_get_gpio_in(dev, n); 188 } 189 190 pl041 = qdev_create(NULL, "pl041"); 191 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 192 qdev_init_nofail(pl041); 193 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000); 194 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[19]); 195 196 sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]); 197 sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]); 198 199 pl011_create(0x10009000, pic[12], serial_hd(0)); 200 pl011_create(0x1000a000, pic[13], serial_hd(1)); 201 pl011_create(0x1000b000, pic[14], serial_hd(2)); 202 pl011_create(0x1000c000, pic[15], serial_hd(3)); 203 204 /* DMA controller is optional, apparently. */ 205 dev = qdev_create(NULL, "pl081"); 206 object_property_set_link(OBJECT(dev), OBJECT(sysmem), "downstream", 207 &error_fatal); 208 qdev_init_nofail(dev); 209 busdev = SYS_BUS_DEVICE(dev); 210 sysbus_mmio_map(busdev, 0, 0x10030000); 211 sysbus_connect_irq(busdev, 0, pic[24]); 212 213 sysbus_create_simple("sp804", 0x10011000, pic[4]); 214 sysbus_create_simple("sp804", 0x10012000, pic[5]); 215 216 sysbus_create_simple("pl061", 0x10013000, pic[6]); 217 sysbus_create_simple("pl061", 0x10014000, pic[7]); 218 gpio2 = sysbus_create_simple("pl061", 0x10015000, pic[8]); 219 220 sysbus_create_simple("pl111", 0x10020000, pic[23]); 221 222 dev = sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL); 223 /* Wire up MMC card detect and read-only signals. These have 224 * to go to both the PL061 GPIO and the sysctl register. 225 * Note that the PL181 orders these lines (readonly,inserted) 226 * and the PL061 has them the other way about. Also the card 227 * detect line is inverted. 228 */ 229 mmc_irq[0] = qemu_irq_split( 230 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT), 231 qdev_get_gpio_in(gpio2, 1)); 232 mmc_irq[1] = qemu_irq_split( 233 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN), 234 qemu_irq_invert(qdev_get_gpio_in(gpio2, 0))); 235 qdev_connect_gpio_out(dev, 0, mmc_irq[0]); 236 qdev_connect_gpio_out(dev, 1, mmc_irq[1]); 237 238 sysbus_create_simple("pl031", 0x10017000, pic[10]); 239 240 if (!is_pb) { 241 dev = qdev_create(NULL, "realview_pci"); 242 busdev = SYS_BUS_DEVICE(dev); 243 qdev_init_nofail(dev); 244 sysbus_mmio_map(busdev, 0, 0x10019000); /* PCI controller registers */ 245 sysbus_mmio_map(busdev, 1, 0x60000000); /* PCI self-config */ 246 sysbus_mmio_map(busdev, 2, 0x61000000); /* PCI config */ 247 sysbus_mmio_map(busdev, 3, 0x62000000); /* PCI I/O */ 248 sysbus_mmio_map(busdev, 4, 0x63000000); /* PCI memory window 1 */ 249 sysbus_mmio_map(busdev, 5, 0x64000000); /* PCI memory window 2 */ 250 sysbus_mmio_map(busdev, 6, 0x68000000); /* PCI memory window 3 */ 251 sysbus_connect_irq(busdev, 0, pic[48]); 252 sysbus_connect_irq(busdev, 1, pic[49]); 253 sysbus_connect_irq(busdev, 2, pic[50]); 254 sysbus_connect_irq(busdev, 3, pic[51]); 255 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci"); 256 if (machine_usb(machine)) { 257 pci_create_simple(pci_bus, -1, "pci-ohci"); 258 } 259 n = drive_get_max_bus(IF_SCSI); 260 while (n >= 0) { 261 dev = DEVICE(pci_create_simple(pci_bus, -1, "lsi53c895a")); 262 lsi53c8xx_handle_legacy_cmdline(dev); 263 n--; 264 } 265 } 266 for(n = 0; n < nb_nics; n++) { 267 nd = &nd_table[n]; 268 269 if (!done_nic && (!nd->model || 270 strcmp(nd->model, is_pb ? "lan9118" : "smc91c111") == 0)) { 271 if (is_pb) { 272 lan9118_init(nd, 0x4e000000, pic[28]); 273 } else { 274 smc91c111_init(nd, 0x4e000000, pic[28]); 275 } 276 done_nic = 1; 277 } else { 278 if (pci_bus) { 279 pci_nic_init_nofail(nd, pci_bus, "rtl8139", NULL); 280 } 281 } 282 } 283 284 dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL); 285 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 286 i2c_create_slave(i2c, "ds1338", 0x68); 287 288 /* Memory map for RealView Emulation Baseboard: */ 289 /* 0x10000000 System registers. */ 290 /* 0x10001000 System controller. */ 291 /* 0x10002000 Two-Wire Serial Bus. */ 292 /* 0x10003000 Reserved. */ 293 /* 0x10004000 AACI. */ 294 /* 0x10005000 MCI. */ 295 /* 0x10006000 KMI0. */ 296 /* 0x10007000 KMI1. */ 297 /* 0x10008000 Character LCD. (EB) */ 298 /* 0x10009000 UART0. */ 299 /* 0x1000a000 UART1. */ 300 /* 0x1000b000 UART2. */ 301 /* 0x1000c000 UART3. */ 302 /* 0x1000d000 SSPI. */ 303 /* 0x1000e000 SCI. */ 304 /* 0x1000f000 Reserved. */ 305 /* 0x10010000 Watchdog. */ 306 /* 0x10011000 Timer 0+1. */ 307 /* 0x10012000 Timer 2+3. */ 308 /* 0x10013000 GPIO 0. */ 309 /* 0x10014000 GPIO 1. */ 310 /* 0x10015000 GPIO 2. */ 311 /* 0x10002000 Two-Wire Serial Bus - DVI. (PB) */ 312 /* 0x10017000 RTC. */ 313 /* 0x10018000 DMC. */ 314 /* 0x10019000 PCI controller config. */ 315 /* 0x10020000 CLCD. */ 316 /* 0x10030000 DMA Controller. */ 317 /* 0x10040000 GIC1. (EB) */ 318 /* 0x10050000 GIC2. (EB) */ 319 /* 0x10060000 GIC3. (EB) */ 320 /* 0x10070000 GIC4. (EB) */ 321 /* 0x10080000 SMC. */ 322 /* 0x1e000000 GIC1. (PB) */ 323 /* 0x1e001000 GIC2. (PB) */ 324 /* 0x1e002000 GIC3. (PB) */ 325 /* 0x1e003000 GIC4. (PB) */ 326 /* 0x40000000 NOR flash. */ 327 /* 0x44000000 DoC flash. */ 328 /* 0x48000000 SRAM. */ 329 /* 0x4c000000 Configuration flash. */ 330 /* 0x4e000000 Ethernet. */ 331 /* 0x4f000000 USB. */ 332 /* 0x50000000 PISMO. */ 333 /* 0x54000000 PISMO. */ 334 /* 0x58000000 PISMO. */ 335 /* 0x5c000000 PISMO. */ 336 /* 0x60000000 PCI. */ 337 /* 0x60000000 PCI Self Config. */ 338 /* 0x61000000 PCI Config. */ 339 /* 0x62000000 PCI IO. */ 340 /* 0x63000000 PCI mem 0. */ 341 /* 0x64000000 PCI mem 1. */ 342 /* 0x68000000 PCI mem 2. */ 343 344 /* ??? Hack to map an additional page of ram for the secondary CPU 345 startup code. I guess this works on real hardware because the 346 BootROM happens to be in ROM/flash or in memory that isn't clobbered 347 until after Linux boots the secondary CPUs. */ 348 memory_region_init_ram(ram_hack, NULL, "realview.hack", 0x1000, 349 &error_fatal); 350 memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, ram_hack); 351 352 realview_binfo.ram_size = ram_size; 353 realview_binfo.kernel_filename = machine->kernel_filename; 354 realview_binfo.kernel_cmdline = machine->kernel_cmdline; 355 realview_binfo.initrd_filename = machine->initrd_filename; 356 realview_binfo.nb_cpus = smp_cpus; 357 realview_binfo.board_id = realview_board_id[board_type]; 358 realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0); 359 arm_load_kernel(ARM_CPU(first_cpu), &realview_binfo); 360 } 361 362 static void realview_eb_init(MachineState *machine) 363 { 364 realview_init(machine, BOARD_EB); 365 } 366 367 static void realview_eb_mpcore_init(MachineState *machine) 368 { 369 realview_init(machine, BOARD_EB_MPCORE); 370 } 371 372 static void realview_pb_a8_init(MachineState *machine) 373 { 374 realview_init(machine, BOARD_PB_A8); 375 } 376 377 static void realview_pbx_a9_init(MachineState *machine) 378 { 379 realview_init(machine, BOARD_PBX_A9); 380 } 381 382 static void realview_eb_class_init(ObjectClass *oc, void *data) 383 { 384 MachineClass *mc = MACHINE_CLASS(oc); 385 386 mc->desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)"; 387 mc->init = realview_eb_init; 388 mc->block_default_type = IF_SCSI; 389 mc->ignore_memory_transaction_failures = true; 390 mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); 391 } 392 393 static const TypeInfo realview_eb_type = { 394 .name = MACHINE_TYPE_NAME("realview-eb"), 395 .parent = TYPE_MACHINE, 396 .class_init = realview_eb_class_init, 397 }; 398 399 static void realview_eb_mpcore_class_init(ObjectClass *oc, void *data) 400 { 401 MachineClass *mc = MACHINE_CLASS(oc); 402 403 mc->desc = "ARM RealView Emulation Baseboard (ARM11MPCore)"; 404 mc->init = realview_eb_mpcore_init; 405 mc->block_default_type = IF_SCSI; 406 mc->max_cpus = 4; 407 mc->ignore_memory_transaction_failures = true; 408 mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm11mpcore"); 409 } 410 411 static const TypeInfo realview_eb_mpcore_type = { 412 .name = MACHINE_TYPE_NAME("realview-eb-mpcore"), 413 .parent = TYPE_MACHINE, 414 .class_init = realview_eb_mpcore_class_init, 415 }; 416 417 static void realview_pb_a8_class_init(ObjectClass *oc, void *data) 418 { 419 MachineClass *mc = MACHINE_CLASS(oc); 420 421 mc->desc = "ARM RealView Platform Baseboard for Cortex-A8"; 422 mc->init = realview_pb_a8_init; 423 mc->ignore_memory_transaction_failures = true; 424 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a8"); 425 } 426 427 static const TypeInfo realview_pb_a8_type = { 428 .name = MACHINE_TYPE_NAME("realview-pb-a8"), 429 .parent = TYPE_MACHINE, 430 .class_init = realview_pb_a8_class_init, 431 }; 432 433 static void realview_pbx_a9_class_init(ObjectClass *oc, void *data) 434 { 435 MachineClass *mc = MACHINE_CLASS(oc); 436 437 mc->desc = "ARM RealView Platform Baseboard Explore for Cortex-A9"; 438 mc->init = realview_pbx_a9_init; 439 mc->max_cpus = 4; 440 mc->ignore_memory_transaction_failures = true; 441 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); 442 } 443 444 static const TypeInfo realview_pbx_a9_type = { 445 .name = MACHINE_TYPE_NAME("realview-pbx-a9"), 446 .parent = TYPE_MACHINE, 447 .class_init = realview_pbx_a9_class_init, 448 }; 449 450 static void realview_machine_init(void) 451 { 452 type_register_static(&realview_eb_type); 453 type_register_static(&realview_eb_mpcore_type); 454 type_register_static(&realview_pb_a8_type); 455 type_register_static(&realview_pbx_a9_type); 456 } 457 458 type_init(realview_machine_init) 459