1 /* 2 * Raspberry Pi emulation (c) 2012 Gregory Estrade 3 * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous 4 * 5 * Rasperry Pi 2 emulation Copyright (c) 2015, Microsoft 6 * Written by Andrew Baumann 7 * 8 * Raspberry Pi 3 emulation Copyright (c) 2018 Zoltán Baldaszti 9 * Upstream code cleanup (c) 2018 Pekka Enberg 10 * 11 * This work is licensed under the terms of the GNU GPL, version 2 or later. 12 * See the COPYING file in the top-level directory. 13 */ 14 15 #include "qemu/osdep.h" 16 #include "qemu/units.h" 17 #include "qemu/cutils.h" 18 #include "qapi/error.h" 19 #include "cpu.h" 20 #include "hw/arm/bcm2836.h" 21 #include "hw/registerfields.h" 22 #include "qemu/error-report.h" 23 #include "hw/boards.h" 24 #include "hw/loader.h" 25 #include "hw/arm/boot.h" 26 #include "sysemu/sysemu.h" 27 #include "qom/object.h" 28 29 #define SMPBOOT_ADDR 0x300 /* this should leave enough space for ATAGS */ 30 #define MVBAR_ADDR 0x400 /* secure vectors */ 31 #define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */ 32 #define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */ 33 #define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */ 34 #define SPINTABLE_ADDR 0xd8 /* Pi 3 bootloader spintable */ 35 36 /* Registered machine type (matches RPi Foundation bootloader and U-Boot) */ 37 #define MACH_TYPE_BCM2708 3138 38 39 struct RaspiMachineState { 40 /*< private >*/ 41 MachineState parent_obj; 42 /*< public >*/ 43 BCM283XState soc; 44 struct arm_boot_info binfo; 45 }; 46 typedef struct RaspiMachineState RaspiMachineState; 47 48 struct RaspiMachineClass { 49 /*< private >*/ 50 MachineClass parent_obj; 51 /*< public >*/ 52 uint32_t board_rev; 53 }; 54 typedef struct RaspiMachineClass RaspiMachineClass; 55 56 #define TYPE_RASPI_MACHINE MACHINE_TYPE_NAME("raspi-common") 57 DECLARE_OBJ_CHECKERS(RaspiMachineState, RaspiMachineClass, 58 RASPI_MACHINE, TYPE_RASPI_MACHINE) 59 60 61 /* 62 * Board revision codes: 63 * www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/ 64 */ 65 FIELD(REV_CODE, REVISION, 0, 4); 66 FIELD(REV_CODE, TYPE, 4, 8); 67 FIELD(REV_CODE, PROCESSOR, 12, 4); 68 FIELD(REV_CODE, MANUFACTURER, 16, 4); 69 FIELD(REV_CODE, MEMORY_SIZE, 20, 3); 70 FIELD(REV_CODE, STYLE, 23, 1); 71 72 typedef enum RaspiProcessorId { 73 PROCESSOR_ID_BCM2835 = 0, 74 PROCESSOR_ID_BCM2836 = 1, 75 PROCESSOR_ID_BCM2837 = 2, 76 } RaspiProcessorId; 77 78 static const struct { 79 const char *type; 80 int cores_count; 81 } soc_property[] = { 82 [PROCESSOR_ID_BCM2835] = {TYPE_BCM2835, 1}, 83 [PROCESSOR_ID_BCM2836] = {TYPE_BCM2836, BCM283X_NCPUS}, 84 [PROCESSOR_ID_BCM2837] = {TYPE_BCM2837, BCM283X_NCPUS}, 85 }; 86 87 static uint64_t board_ram_size(uint32_t board_rev) 88 { 89 assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */ 90 return 256 * MiB << FIELD_EX32(board_rev, REV_CODE, MEMORY_SIZE); 91 } 92 93 static RaspiProcessorId board_processor_id(uint32_t board_rev) 94 { 95 int proc_id = FIELD_EX32(board_rev, REV_CODE, PROCESSOR); 96 97 assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */ 98 assert(proc_id < ARRAY_SIZE(soc_property) && soc_property[proc_id].type); 99 100 return proc_id; 101 } 102 103 static const char *board_soc_type(uint32_t board_rev) 104 { 105 return soc_property[board_processor_id(board_rev)].type; 106 } 107 108 static int cores_count(uint32_t board_rev) 109 { 110 return soc_property[board_processor_id(board_rev)].cores_count; 111 } 112 113 static const char *board_type(uint32_t board_rev) 114 { 115 static const char *types[] = { 116 "A", "B", "A+", "B+", "2B", "Alpha", "CM1", NULL, "3B", "Zero", 117 "CM3", NULL, "Zero W", "3B+", "3A+", NULL, "CM3+", "4B", 118 }; 119 assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */ 120 int bt = FIELD_EX32(board_rev, REV_CODE, TYPE); 121 if (bt >= ARRAY_SIZE(types) || !types[bt]) { 122 return "Unknown"; 123 } 124 return types[bt]; 125 } 126 127 static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info) 128 { 129 static const uint32_t smpboot[] = { 130 0xe1a0e00f, /* mov lr, pc */ 131 0xe3a0fe00 + (BOARDSETUP_ADDR >> 4), /* mov pc, BOARDSETUP_ADDR */ 132 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5;get core ID */ 133 0xe7e10050, /* ubfx r0, r0, #0, #2 ;extract LSB */ 134 0xe59f5014, /* ldr r5, =0x400000CC ;load mbox base */ 135 0xe320f001, /* 1: yield */ 136 0xe7953200, /* ldr r3, [r5, r0, lsl #4] ;read mbox for our core*/ 137 0xe3530000, /* cmp r3, #0 ;spin while zero */ 138 0x0afffffb, /* beq 1b */ 139 0xe7853200, /* str r3, [r5, r0, lsl #4] ;clear mbox */ 140 0xe12fff13, /* bx r3 ;jump to target */ 141 0x400000cc, /* (constant: mailbox 3 read/clear base) */ 142 }; 143 144 /* check that we don't overrun board setup vectors */ 145 QEMU_BUILD_BUG_ON(SMPBOOT_ADDR + sizeof(smpboot) > MVBAR_ADDR); 146 /* check that board setup address is correctly relocated */ 147 QEMU_BUILD_BUG_ON((BOARDSETUP_ADDR & 0xf) != 0 148 || (BOARDSETUP_ADDR >> 4) >= 0x100); 149 150 rom_add_blob_fixed_as("raspi_smpboot", smpboot, sizeof(smpboot), 151 info->smp_loader_start, 152 arm_boot_address_space(cpu, info)); 153 } 154 155 static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info) 156 { 157 AddressSpace *as = arm_boot_address_space(cpu, info); 158 /* Unlike the AArch32 version we don't need to call the board setup hook. 159 * The mechanism for doing the spin-table is also entirely different. 160 * We must have four 64-bit fields at absolute addresses 161 * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for 162 * our CPUs, and which we must ensure are zero initialized before 163 * the primary CPU goes into the kernel. We put these variables inside 164 * a rom blob, so that the reset for ROM contents zeroes them for us. 165 */ 166 static const uint32_t smpboot[] = { 167 0xd2801b05, /* mov x5, 0xd8 */ 168 0xd53800a6, /* mrs x6, mpidr_el1 */ 169 0x924004c6, /* and x6, x6, #0x3 */ 170 0xd503205f, /* spin: wfe */ 171 0xf86678a4, /* ldr x4, [x5,x6,lsl #3] */ 172 0xb4ffffc4, /* cbz x4, spin */ 173 0xd2800000, /* mov x0, #0x0 */ 174 0xd2800001, /* mov x1, #0x0 */ 175 0xd2800002, /* mov x2, #0x0 */ 176 0xd2800003, /* mov x3, #0x0 */ 177 0xd61f0080, /* br x4 */ 178 }; 179 180 static const uint64_t spintables[] = { 181 0, 0, 0, 0 182 }; 183 184 rom_add_blob_fixed_as("raspi_smpboot", smpboot, sizeof(smpboot), 185 info->smp_loader_start, as); 186 rom_add_blob_fixed_as("raspi_spintables", spintables, sizeof(spintables), 187 SPINTABLE_ADDR, as); 188 } 189 190 static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info) 191 { 192 arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR); 193 } 194 195 static void reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info) 196 { 197 CPUState *cs = CPU(cpu); 198 cpu_set_pc(cs, info->smp_loader_start); 199 } 200 201 static void setup_boot(MachineState *machine, RaspiProcessorId processor_id, 202 size_t ram_size) 203 { 204 RaspiMachineState *s = RASPI_MACHINE(machine); 205 int r; 206 207 s->binfo.board_id = MACH_TYPE_BCM2708; 208 s->binfo.ram_size = ram_size; 209 s->binfo.nb_cpus = machine->smp.cpus; 210 211 if (processor_id <= PROCESSOR_ID_BCM2836) { 212 /* 213 * The BCM2835 and BCM2836 require some custom setup code to run 214 * in Secure mode before booting a kernel (to set up the SMC vectors 215 * so that we get a no-op SMC; this is used by Linux to call the 216 * firmware for some cache maintenance operations. 217 * The BCM2837 doesn't need this. 218 */ 219 s->binfo.board_setup_addr = BOARDSETUP_ADDR; 220 s->binfo.write_board_setup = write_board_setup; 221 s->binfo.secure_board_setup = true; 222 s->binfo.secure_boot = true; 223 } 224 225 /* BCM2836 and BCM2837 requires SMP setup */ 226 if (processor_id >= PROCESSOR_ID_BCM2836) { 227 s->binfo.smp_loader_start = SMPBOOT_ADDR; 228 if (processor_id == PROCESSOR_ID_BCM2836) { 229 s->binfo.write_secondary_boot = write_smpboot; 230 } else { 231 s->binfo.write_secondary_boot = write_smpboot64; 232 } 233 s->binfo.secondary_cpu_reset_hook = reset_secondary; 234 } 235 236 /* If the user specified a "firmware" image (e.g. UEFI), we bypass 237 * the normal Linux boot process 238 */ 239 if (machine->firmware) { 240 hwaddr firmware_addr = processor_id <= PROCESSOR_ID_BCM2836 241 ? FIRMWARE_ADDR_2 : FIRMWARE_ADDR_3; 242 /* load the firmware image (typically kernel.img) */ 243 r = load_image_targphys(machine->firmware, firmware_addr, 244 ram_size - firmware_addr); 245 if (r < 0) { 246 error_report("Failed to load firmware from %s", machine->firmware); 247 exit(1); 248 } 249 250 s->binfo.entry = firmware_addr; 251 s->binfo.firmware_loaded = true; 252 } 253 254 arm_load_kernel(&s->soc.cpu[0].core, machine, &s->binfo); 255 } 256 257 static void raspi_machine_init(MachineState *machine) 258 { 259 RaspiMachineClass *mc = RASPI_MACHINE_GET_CLASS(machine); 260 RaspiMachineState *s = RASPI_MACHINE(machine); 261 uint32_t board_rev = mc->board_rev; 262 uint64_t ram_size = board_ram_size(board_rev); 263 uint32_t vcram_size; 264 DriveInfo *di; 265 BlockBackend *blk; 266 BusState *bus; 267 DeviceState *carddev; 268 269 if (machine->ram_size != ram_size) { 270 char *size_str = size_to_str(ram_size); 271 error_report("Invalid RAM size, should be %s", size_str); 272 g_free(size_str); 273 exit(1); 274 } 275 276 /* FIXME: Remove when we have custom CPU address space support */ 277 memory_region_add_subregion_overlap(get_system_memory(), 0, 278 machine->ram, 0); 279 280 /* Setup the SOC */ 281 object_initialize_child(OBJECT(machine), "soc", &s->soc, 282 board_soc_type(board_rev)); 283 object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(machine->ram)); 284 object_property_set_int(OBJECT(&s->soc), "board-rev", board_rev, 285 &error_abort); 286 qdev_realize(DEVICE(&s->soc), NULL, &error_abort); 287 288 /* Create and plug in the SD cards */ 289 di = drive_get_next(IF_SD); 290 blk = di ? blk_by_legacy_dinfo(di) : NULL; 291 bus = qdev_get_child_bus(DEVICE(&s->soc), "sd-bus"); 292 if (bus == NULL) { 293 error_report("No SD bus found in SOC object"); 294 exit(1); 295 } 296 carddev = qdev_new(TYPE_SD_CARD); 297 qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal); 298 qdev_realize_and_unref(carddev, bus, &error_fatal); 299 300 vcram_size = object_property_get_uint(OBJECT(&s->soc), "vcram-size", 301 &error_abort); 302 setup_boot(machine, board_processor_id(mc->board_rev), 303 machine->ram_size - vcram_size); 304 } 305 306 static void raspi_machine_class_common_init(MachineClass *mc, 307 uint32_t board_rev) 308 { 309 mc->desc = g_strdup_printf("Raspberry Pi %s (revision 1.%u)", 310 board_type(board_rev), 311 FIELD_EX32(board_rev, REV_CODE, REVISION)); 312 mc->init = raspi_machine_init; 313 mc->block_default_type = IF_SD; 314 mc->no_parallel = 1; 315 mc->no_floppy = 1; 316 mc->no_cdrom = 1; 317 mc->default_cpus = mc->min_cpus = mc->max_cpus = cores_count(board_rev); 318 mc->default_ram_size = board_ram_size(board_rev); 319 mc->default_ram_id = "ram"; 320 }; 321 322 static void raspi0_machine_class_init(ObjectClass *oc, void *data) 323 { 324 MachineClass *mc = MACHINE_CLASS(oc); 325 RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc); 326 327 rmc->board_rev = 0x920092; /* Revision 1.2 */ 328 raspi_machine_class_common_init(mc, rmc->board_rev); 329 }; 330 331 static void raspi1ap_machine_class_init(ObjectClass *oc, void *data) 332 { 333 MachineClass *mc = MACHINE_CLASS(oc); 334 RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc); 335 336 rmc->board_rev = 0x900021; /* Revision 1.1 */ 337 raspi_machine_class_common_init(mc, rmc->board_rev); 338 }; 339 340 static void raspi2b_machine_class_init(ObjectClass *oc, void *data) 341 { 342 MachineClass *mc = MACHINE_CLASS(oc); 343 RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc); 344 345 mc->alias = "raspi2"; 346 rmc->board_rev = 0xa21041; 347 raspi_machine_class_common_init(mc, rmc->board_rev); 348 }; 349 350 #ifdef TARGET_AARCH64 351 static void raspi3ap_machine_class_init(ObjectClass *oc, void *data) 352 { 353 MachineClass *mc = MACHINE_CLASS(oc); 354 RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc); 355 356 rmc->board_rev = 0x9020e0; /* Revision 1.0 */ 357 raspi_machine_class_common_init(mc, rmc->board_rev); 358 }; 359 360 static void raspi3b_machine_class_init(ObjectClass *oc, void *data) 361 { 362 MachineClass *mc = MACHINE_CLASS(oc); 363 RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc); 364 365 mc->alias = "raspi3"; 366 rmc->board_rev = 0xa02082; 367 raspi_machine_class_common_init(mc, rmc->board_rev); 368 }; 369 #endif /* TARGET_AARCH64 */ 370 371 static const TypeInfo raspi_machine_types[] = { 372 { 373 .name = MACHINE_TYPE_NAME("raspi0"), 374 .parent = TYPE_RASPI_MACHINE, 375 .class_init = raspi0_machine_class_init, 376 }, { 377 .name = MACHINE_TYPE_NAME("raspi1ap"), 378 .parent = TYPE_RASPI_MACHINE, 379 .class_init = raspi1ap_machine_class_init, 380 }, { 381 .name = MACHINE_TYPE_NAME("raspi2b"), 382 .parent = TYPE_RASPI_MACHINE, 383 .class_init = raspi2b_machine_class_init, 384 #ifdef TARGET_AARCH64 385 }, { 386 .name = MACHINE_TYPE_NAME("raspi3ap"), 387 .parent = TYPE_RASPI_MACHINE, 388 .class_init = raspi3ap_machine_class_init, 389 }, { 390 .name = MACHINE_TYPE_NAME("raspi3b"), 391 .parent = TYPE_RASPI_MACHINE, 392 .class_init = raspi3b_machine_class_init, 393 #endif 394 }, { 395 .name = TYPE_RASPI_MACHINE, 396 .parent = TYPE_MACHINE, 397 .instance_size = sizeof(RaspiMachineState), 398 .class_size = sizeof(RaspiMachineClass), 399 .abstract = true, 400 } 401 }; 402 403 DEFINE_TYPES(raspi_machine_types) 404