1 /* 2 * Raspberry Pi emulation (c) 2012 Gregory Estrade 3 * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous 4 * 5 * Rasperry Pi 2 emulation Copyright (c) 2015, Microsoft 6 * Written by Andrew Baumann 7 * 8 * Raspberry Pi 3 emulation Copyright (c) 2018 Zoltán Baldaszti 9 * Upstream code cleanup (c) 2018 Pekka Enberg 10 * 11 * This work is licensed under the terms of the GNU GPL, version 2 or later. 12 * See the COPYING file in the top-level directory. 13 */ 14 15 #include "qemu/osdep.h" 16 #include "qemu/units.h" 17 #include "qemu/cutils.h" 18 #include "qapi/error.h" 19 #include "cpu.h" 20 #include "hw/arm/bcm2836.h" 21 #include "hw/registerfields.h" 22 #include "qemu/error-report.h" 23 #include "hw/boards.h" 24 #include "hw/loader.h" 25 #include "hw/arm/boot.h" 26 #include "sysemu/sysemu.h" 27 #include "qom/object.h" 28 29 #define SMPBOOT_ADDR 0x300 /* this should leave enough space for ATAGS */ 30 #define MVBAR_ADDR 0x400 /* secure vectors */ 31 #define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */ 32 #define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */ 33 #define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */ 34 #define SPINTABLE_ADDR 0xd8 /* Pi 3 bootloader spintable */ 35 36 /* Registered machine type (matches RPi Foundation bootloader and U-Boot) */ 37 #define MACH_TYPE_BCM2708 3138 38 39 struct RaspiMachineState { 40 /*< private >*/ 41 MachineState parent_obj; 42 /*< public >*/ 43 BCM283XState soc; 44 }; 45 typedef struct RaspiMachineState RaspiMachineState; 46 47 struct RaspiMachineClass { 48 /*< private >*/ 49 MachineClass parent_obj; 50 /*< public >*/ 51 uint32_t board_rev; 52 }; 53 typedef struct RaspiMachineClass RaspiMachineClass; 54 55 #define TYPE_RASPI_MACHINE MACHINE_TYPE_NAME("raspi-common") 56 DECLARE_OBJ_CHECKERS(RaspiMachineState, RaspiMachineClass, 57 RASPI_MACHINE, TYPE_RASPI_MACHINE) 58 59 60 /* 61 * Board revision codes: 62 * www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/ 63 */ 64 FIELD(REV_CODE, REVISION, 0, 4); 65 FIELD(REV_CODE, TYPE, 4, 8); 66 FIELD(REV_CODE, PROCESSOR, 12, 4); 67 FIELD(REV_CODE, MANUFACTURER, 16, 4); 68 FIELD(REV_CODE, MEMORY_SIZE, 20, 3); 69 FIELD(REV_CODE, STYLE, 23, 1); 70 71 static uint64_t board_ram_size(uint32_t board_rev) 72 { 73 assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */ 74 return 256 * MiB << FIELD_EX32(board_rev, REV_CODE, MEMORY_SIZE); 75 } 76 77 static int board_processor_id(uint32_t board_rev) 78 { 79 assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */ 80 return FIELD_EX32(board_rev, REV_CODE, PROCESSOR); 81 } 82 83 static int board_version(uint32_t board_rev) 84 { 85 return board_processor_id(board_rev) + 1; 86 } 87 88 static const char *board_soc_type(uint32_t board_rev) 89 { 90 static const char *soc_types[] = { 91 NULL, TYPE_BCM2836, TYPE_BCM2837, 92 }; 93 int proc_id = board_processor_id(board_rev); 94 95 if (proc_id >= ARRAY_SIZE(soc_types) || !soc_types[proc_id]) { 96 error_report("Unsupported processor id '%d' (board revision: 0x%x)", 97 proc_id, board_rev); 98 exit(1); 99 } 100 return soc_types[proc_id]; 101 } 102 103 static int cores_count(uint32_t board_rev) 104 { 105 static const int soc_cores_count[] = { 106 0, BCM283X_NCPUS, BCM283X_NCPUS, 107 }; 108 int proc_id = board_processor_id(board_rev); 109 110 if (proc_id >= ARRAY_SIZE(soc_cores_count) || !soc_cores_count[proc_id]) { 111 error_report("Unsupported processor id '%d' (board revision: 0x%x)", 112 proc_id, board_rev); 113 exit(1); 114 } 115 return soc_cores_count[proc_id]; 116 } 117 118 static const char *board_type(uint32_t board_rev) 119 { 120 static const char *types[] = { 121 "A", "B", "A+", "B+", "2B", "Alpha", "CM1", NULL, "3B", "Zero", 122 "CM3", NULL, "Zero W", "3B+", "3A+", NULL, "CM3+", "4B", 123 }; 124 assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */ 125 int bt = FIELD_EX32(board_rev, REV_CODE, TYPE); 126 if (bt >= ARRAY_SIZE(types) || !types[bt]) { 127 return "Unknown"; 128 } 129 return types[bt]; 130 } 131 132 static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info) 133 { 134 static const uint32_t smpboot[] = { 135 0xe1a0e00f, /* mov lr, pc */ 136 0xe3a0fe00 + (BOARDSETUP_ADDR >> 4), /* mov pc, BOARDSETUP_ADDR */ 137 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5;get core ID */ 138 0xe7e10050, /* ubfx r0, r0, #0, #2 ;extract LSB */ 139 0xe59f5014, /* ldr r5, =0x400000CC ;load mbox base */ 140 0xe320f001, /* 1: yield */ 141 0xe7953200, /* ldr r3, [r5, r0, lsl #4] ;read mbox for our core*/ 142 0xe3530000, /* cmp r3, #0 ;spin while zero */ 143 0x0afffffb, /* beq 1b */ 144 0xe7853200, /* str r3, [r5, r0, lsl #4] ;clear mbox */ 145 0xe12fff13, /* bx r3 ;jump to target */ 146 0x400000cc, /* (constant: mailbox 3 read/clear base) */ 147 }; 148 149 /* check that we don't overrun board setup vectors */ 150 QEMU_BUILD_BUG_ON(SMPBOOT_ADDR + sizeof(smpboot) > MVBAR_ADDR); 151 /* check that board setup address is correctly relocated */ 152 QEMU_BUILD_BUG_ON((BOARDSETUP_ADDR & 0xf) != 0 153 || (BOARDSETUP_ADDR >> 4) >= 0x100); 154 155 rom_add_blob_fixed_as("raspi_smpboot", smpboot, sizeof(smpboot), 156 info->smp_loader_start, 157 arm_boot_address_space(cpu, info)); 158 } 159 160 static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info) 161 { 162 AddressSpace *as = arm_boot_address_space(cpu, info); 163 /* Unlike the AArch32 version we don't need to call the board setup hook. 164 * The mechanism for doing the spin-table is also entirely different. 165 * We must have four 64-bit fields at absolute addresses 166 * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for 167 * our CPUs, and which we must ensure are zero initialized before 168 * the primary CPU goes into the kernel. We put these variables inside 169 * a rom blob, so that the reset for ROM contents zeroes them for us. 170 */ 171 static const uint32_t smpboot[] = { 172 0xd2801b05, /* mov x5, 0xd8 */ 173 0xd53800a6, /* mrs x6, mpidr_el1 */ 174 0x924004c6, /* and x6, x6, #0x3 */ 175 0xd503205f, /* spin: wfe */ 176 0xf86678a4, /* ldr x4, [x5,x6,lsl #3] */ 177 0xb4ffffc4, /* cbz x4, spin */ 178 0xd2800000, /* mov x0, #0x0 */ 179 0xd2800001, /* mov x1, #0x0 */ 180 0xd2800002, /* mov x2, #0x0 */ 181 0xd2800003, /* mov x3, #0x0 */ 182 0xd61f0080, /* br x4 */ 183 }; 184 185 static const uint64_t spintables[] = { 186 0, 0, 0, 0 187 }; 188 189 rom_add_blob_fixed_as("raspi_smpboot", smpboot, sizeof(smpboot), 190 info->smp_loader_start, as); 191 rom_add_blob_fixed_as("raspi_spintables", spintables, sizeof(spintables), 192 SPINTABLE_ADDR, as); 193 } 194 195 static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info) 196 { 197 arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR); 198 } 199 200 static void reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info) 201 { 202 CPUState *cs = CPU(cpu); 203 cpu_set_pc(cs, info->smp_loader_start); 204 } 205 206 static void setup_boot(MachineState *machine, int version, size_t ram_size) 207 { 208 static struct arm_boot_info binfo; 209 int r; 210 211 binfo.board_id = MACH_TYPE_BCM2708; 212 binfo.ram_size = ram_size; 213 binfo.nb_cpus = machine->smp.cpus; 214 215 if (version <= 2) { 216 /* The rpi1 and 2 require some custom setup code to run in Secure 217 * mode before booting a kernel (to set up the SMC vectors so 218 * that we get a no-op SMC; this is used by Linux to call the 219 * firmware for some cache maintenance operations. 220 * The rpi3 doesn't need this. 221 */ 222 binfo.board_setup_addr = BOARDSETUP_ADDR; 223 binfo.write_board_setup = write_board_setup; 224 binfo.secure_board_setup = true; 225 binfo.secure_boot = true; 226 } 227 228 /* Pi2 and Pi3 requires SMP setup */ 229 if (version >= 2) { 230 binfo.smp_loader_start = SMPBOOT_ADDR; 231 if (version == 2) { 232 binfo.write_secondary_boot = write_smpboot; 233 } else { 234 binfo.write_secondary_boot = write_smpboot64; 235 } 236 binfo.secondary_cpu_reset_hook = reset_secondary; 237 } 238 239 /* If the user specified a "firmware" image (e.g. UEFI), we bypass 240 * the normal Linux boot process 241 */ 242 if (machine->firmware) { 243 hwaddr firmware_addr = version == 3 ? FIRMWARE_ADDR_3 : FIRMWARE_ADDR_2; 244 /* load the firmware image (typically kernel.img) */ 245 r = load_image_targphys(machine->firmware, firmware_addr, 246 ram_size - firmware_addr); 247 if (r < 0) { 248 error_report("Failed to load firmware from %s", machine->firmware); 249 exit(1); 250 } 251 252 binfo.entry = firmware_addr; 253 binfo.firmware_loaded = true; 254 } 255 256 arm_load_kernel(ARM_CPU(first_cpu), machine, &binfo); 257 } 258 259 static void raspi_machine_init(MachineState *machine) 260 { 261 RaspiMachineClass *mc = RASPI_MACHINE_GET_CLASS(machine); 262 RaspiMachineState *s = RASPI_MACHINE(machine); 263 uint32_t board_rev = mc->board_rev; 264 int version = board_version(board_rev); 265 uint64_t ram_size = board_ram_size(board_rev); 266 uint32_t vcram_size; 267 DriveInfo *di; 268 BlockBackend *blk; 269 BusState *bus; 270 DeviceState *carddev; 271 272 if (machine->ram_size != ram_size) { 273 char *size_str = size_to_str(ram_size); 274 error_report("Invalid RAM size, should be %s", size_str); 275 g_free(size_str); 276 exit(1); 277 } 278 279 /* FIXME: Remove when we have custom CPU address space support */ 280 memory_region_add_subregion_overlap(get_system_memory(), 0, 281 machine->ram, 0); 282 283 /* Setup the SOC */ 284 object_initialize_child(OBJECT(machine), "soc", &s->soc, 285 board_soc_type(board_rev)); 286 object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(machine->ram)); 287 object_property_set_int(OBJECT(&s->soc), "board-rev", board_rev, 288 &error_abort); 289 qdev_realize(DEVICE(&s->soc), NULL, &error_abort); 290 291 /* Create and plug in the SD cards */ 292 di = drive_get_next(IF_SD); 293 blk = di ? blk_by_legacy_dinfo(di) : NULL; 294 bus = qdev_get_child_bus(DEVICE(&s->soc), "sd-bus"); 295 if (bus == NULL) { 296 error_report("No SD bus found in SOC object"); 297 exit(1); 298 } 299 carddev = qdev_new(TYPE_SD_CARD); 300 qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal); 301 qdev_realize_and_unref(carddev, bus, &error_fatal); 302 303 vcram_size = object_property_get_uint(OBJECT(&s->soc), "vcram-size", 304 &error_abort); 305 setup_boot(machine, version, machine->ram_size - vcram_size); 306 } 307 308 static void raspi_machine_class_init(ObjectClass *oc, void *data) 309 { 310 MachineClass *mc = MACHINE_CLASS(oc); 311 RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc); 312 uint32_t board_rev = (uint32_t)(uintptr_t)data; 313 314 rmc->board_rev = board_rev; 315 mc->desc = g_strdup_printf("Raspberry Pi %s", board_type(board_rev)); 316 mc->init = raspi_machine_init; 317 mc->block_default_type = IF_SD; 318 mc->no_parallel = 1; 319 mc->no_floppy = 1; 320 mc->no_cdrom = 1; 321 mc->default_cpus = mc->min_cpus = mc->max_cpus = cores_count(board_rev); 322 mc->default_ram_size = board_ram_size(board_rev); 323 mc->default_ram_id = "ram"; 324 if (board_version(board_rev) == 2) { 325 mc->ignore_memory_transaction_failures = true; 326 } 327 }; 328 329 static const TypeInfo raspi_machine_types[] = { 330 { 331 .name = MACHINE_TYPE_NAME("raspi2"), 332 .parent = TYPE_RASPI_MACHINE, 333 .class_init = raspi_machine_class_init, 334 .class_data = (void *)0xa21041, 335 #ifdef TARGET_AARCH64 336 }, { 337 .name = MACHINE_TYPE_NAME("raspi3"), 338 .parent = TYPE_RASPI_MACHINE, 339 .class_init = raspi_machine_class_init, 340 .class_data = (void *)0xa02082, 341 #endif 342 }, { 343 .name = TYPE_RASPI_MACHINE, 344 .parent = TYPE_MACHINE, 345 .instance_size = sizeof(RaspiMachineState), 346 .class_size = sizeof(RaspiMachineClass), 347 .abstract = true, 348 } 349 }; 350 351 DEFINE_TYPES(raspi_machine_types) 352