1 /* 2 * Raspberry Pi emulation (c) 2012 Gregory Estrade 3 * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous 4 * 5 * Rasperry Pi 2 emulation Copyright (c) 2015, Microsoft 6 * Written by Andrew Baumann 7 * 8 * Raspberry Pi 3 emulation Copyright (c) 2018 Zoltán Baldaszti 9 * Upstream code cleanup (c) 2018 Pekka Enberg 10 * 11 * This work is licensed under the terms of the GNU GPL, version 2 or later. 12 * See the COPYING file in the top-level directory. 13 */ 14 15 #include "qemu/osdep.h" 16 #include "qemu/units.h" 17 #include "qemu/cutils.h" 18 #include "qapi/error.h" 19 #include "hw/arm/boot.h" 20 #include "hw/arm/bcm2836.h" 21 #include "hw/registerfields.h" 22 #include "qemu/error-report.h" 23 #include "hw/boards.h" 24 #include "hw/loader.h" 25 #include "hw/arm/boot.h" 26 #include "qom/object.h" 27 28 #define SMPBOOT_ADDR 0x300 /* this should leave enough space for ATAGS */ 29 #define MVBAR_ADDR 0x400 /* secure vectors */ 30 #define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */ 31 #define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */ 32 #define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */ 33 #define SPINTABLE_ADDR 0xd8 /* Pi 3 bootloader spintable */ 34 35 /* Registered machine type (matches RPi Foundation bootloader and U-Boot) */ 36 #define MACH_TYPE_BCM2708 3138 37 38 struct RaspiMachineState { 39 /*< private >*/ 40 MachineState parent_obj; 41 /*< public >*/ 42 BCM283XState soc; 43 struct arm_boot_info binfo; 44 }; 45 typedef struct RaspiMachineState RaspiMachineState; 46 47 struct RaspiMachineClass { 48 /*< private >*/ 49 MachineClass parent_obj; 50 /*< public >*/ 51 uint32_t board_rev; 52 }; 53 typedef struct RaspiMachineClass RaspiMachineClass; 54 55 #define TYPE_RASPI_MACHINE MACHINE_TYPE_NAME("raspi-common") 56 DECLARE_OBJ_CHECKERS(RaspiMachineState, RaspiMachineClass, 57 RASPI_MACHINE, TYPE_RASPI_MACHINE) 58 59 60 /* 61 * Board revision codes: 62 * www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/ 63 */ 64 FIELD(REV_CODE, REVISION, 0, 4); 65 FIELD(REV_CODE, TYPE, 4, 8); 66 FIELD(REV_CODE, PROCESSOR, 12, 4); 67 FIELD(REV_CODE, MANUFACTURER, 16, 4); 68 FIELD(REV_CODE, MEMORY_SIZE, 20, 3); 69 FIELD(REV_CODE, STYLE, 23, 1); 70 71 typedef enum RaspiProcessorId { 72 PROCESSOR_ID_BCM2835 = 0, 73 PROCESSOR_ID_BCM2836 = 1, 74 PROCESSOR_ID_BCM2837 = 2, 75 } RaspiProcessorId; 76 77 static const struct { 78 const char *type; 79 int cores_count; 80 } soc_property[] = { 81 [PROCESSOR_ID_BCM2835] = {TYPE_BCM2835, 1}, 82 [PROCESSOR_ID_BCM2836] = {TYPE_BCM2836, BCM283X_NCPUS}, 83 [PROCESSOR_ID_BCM2837] = {TYPE_BCM2837, BCM283X_NCPUS}, 84 }; 85 86 static uint64_t board_ram_size(uint32_t board_rev) 87 { 88 assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */ 89 return 256 * MiB << FIELD_EX32(board_rev, REV_CODE, MEMORY_SIZE); 90 } 91 92 static RaspiProcessorId board_processor_id(uint32_t board_rev) 93 { 94 int proc_id = FIELD_EX32(board_rev, REV_CODE, PROCESSOR); 95 96 assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */ 97 assert(proc_id < ARRAY_SIZE(soc_property) && soc_property[proc_id].type); 98 99 return proc_id; 100 } 101 102 static const char *board_soc_type(uint32_t board_rev) 103 { 104 return soc_property[board_processor_id(board_rev)].type; 105 } 106 107 static int cores_count(uint32_t board_rev) 108 { 109 return soc_property[board_processor_id(board_rev)].cores_count; 110 } 111 112 static const char *board_type(uint32_t board_rev) 113 { 114 static const char *types[] = { 115 "A", "B", "A+", "B+", "2B", "Alpha", "CM1", NULL, "3B", "Zero", 116 "CM3", NULL, "Zero W", "3B+", "3A+", NULL, "CM3+", "4B", 117 }; 118 assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */ 119 int bt = FIELD_EX32(board_rev, REV_CODE, TYPE); 120 if (bt >= ARRAY_SIZE(types) || !types[bt]) { 121 return "Unknown"; 122 } 123 return types[bt]; 124 } 125 126 static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info) 127 { 128 static const ARMInsnFixup smpboot[] = { 129 { 0xe1a0e00f }, /* mov lr, pc */ 130 { 0xe3a0fe00 + (BOARDSETUP_ADDR >> 4) }, /* mov pc, BOARDSETUP_ADDR */ 131 { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5;get core ID */ 132 { 0xe7e10050 }, /* ubfx r0, r0, #0, #2 ;extract LSB */ 133 { 0xe59f5014 }, /* ldr r5, =0x400000CC ;load mbox base */ 134 { 0xe320f001 }, /* 1: yield */ 135 { 0xe7953200 }, /* ldr r3, [r5, r0, lsl #4] ;read mbox for our core */ 136 { 0xe3530000 }, /* cmp r3, #0 ;spin while zero */ 137 { 0x0afffffb }, /* beq 1b */ 138 { 0xe7853200 }, /* str r3, [r5, r0, lsl #4] ;clear mbox */ 139 { 0xe12fff13 }, /* bx r3 ;jump to target */ 140 { 0x400000cc }, /* (constant: mailbox 3 read/clear base) */ 141 { 0, FIXUP_TERMINATOR } 142 }; 143 static const uint32_t fixupcontext[FIXUP_MAX] = { 0 }; 144 145 /* check that we don't overrun board setup vectors */ 146 QEMU_BUILD_BUG_ON(SMPBOOT_ADDR + sizeof(smpboot) > MVBAR_ADDR); 147 /* check that board setup address is correctly relocated */ 148 QEMU_BUILD_BUG_ON((BOARDSETUP_ADDR & 0xf) != 0 149 || (BOARDSETUP_ADDR >> 4) >= 0x100); 150 151 arm_write_bootloader("raspi_smpboot", arm_boot_address_space(cpu, info), 152 info->smp_loader_start, smpboot, fixupcontext); 153 } 154 155 static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info) 156 { 157 AddressSpace *as = arm_boot_address_space(cpu, info); 158 /* Unlike the AArch32 version we don't need to call the board setup hook. 159 * The mechanism for doing the spin-table is also entirely different. 160 * We must have four 64-bit fields at absolute addresses 161 * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for 162 * our CPUs, and which we must ensure are zero initialized before 163 * the primary CPU goes into the kernel. We put these variables inside 164 * a rom blob, so that the reset for ROM contents zeroes them for us. 165 */ 166 static const ARMInsnFixup smpboot[] = { 167 { 0xd2801b05 }, /* mov x5, 0xd8 */ 168 { 0xd53800a6 }, /* mrs x6, mpidr_el1 */ 169 { 0x924004c6 }, /* and x6, x6, #0x3 */ 170 { 0xd503205f }, /* spin: wfe */ 171 { 0xf86678a4 }, /* ldr x4, [x5,x6,lsl #3] */ 172 { 0xb4ffffc4 }, /* cbz x4, spin */ 173 { 0xd2800000 }, /* mov x0, #0x0 */ 174 { 0xd2800001 }, /* mov x1, #0x0 */ 175 { 0xd2800002 }, /* mov x2, #0x0 */ 176 { 0xd2800003 }, /* mov x3, #0x0 */ 177 { 0xd61f0080 }, /* br x4 */ 178 { 0, FIXUP_TERMINATOR } 179 }; 180 static const uint32_t fixupcontext[FIXUP_MAX] = { 0 }; 181 182 static const uint64_t spintables[] = { 183 0, 0, 0, 0 184 }; 185 186 arm_write_bootloader("raspi_smpboot", as, info->smp_loader_start, 187 smpboot, fixupcontext); 188 rom_add_blob_fixed_as("raspi_spintables", spintables, sizeof(spintables), 189 SPINTABLE_ADDR, as); 190 } 191 192 static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info) 193 { 194 arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR); 195 } 196 197 static void reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info) 198 { 199 CPUState *cs = CPU(cpu); 200 cpu_set_pc(cs, info->smp_loader_start); 201 } 202 203 static void setup_boot(MachineState *machine, RaspiProcessorId processor_id, 204 size_t ram_size) 205 { 206 RaspiMachineState *s = RASPI_MACHINE(machine); 207 int r; 208 209 s->binfo.board_id = MACH_TYPE_BCM2708; 210 s->binfo.ram_size = ram_size; 211 212 if (processor_id <= PROCESSOR_ID_BCM2836) { 213 /* 214 * The BCM2835 and BCM2836 require some custom setup code to run 215 * in Secure mode before booting a kernel (to set up the SMC vectors 216 * so that we get a no-op SMC; this is used by Linux to call the 217 * firmware for some cache maintenance operations. 218 * The BCM2837 doesn't need this. 219 */ 220 s->binfo.board_setup_addr = BOARDSETUP_ADDR; 221 s->binfo.write_board_setup = write_board_setup; 222 s->binfo.secure_board_setup = true; 223 s->binfo.secure_boot = true; 224 } 225 226 /* BCM2836 and BCM2837 requires SMP setup */ 227 if (processor_id >= PROCESSOR_ID_BCM2836) { 228 s->binfo.smp_loader_start = SMPBOOT_ADDR; 229 if (processor_id == PROCESSOR_ID_BCM2836) { 230 s->binfo.write_secondary_boot = write_smpboot; 231 } else { 232 s->binfo.write_secondary_boot = write_smpboot64; 233 } 234 s->binfo.secondary_cpu_reset_hook = reset_secondary; 235 } 236 237 /* If the user specified a "firmware" image (e.g. UEFI), we bypass 238 * the normal Linux boot process 239 */ 240 if (machine->firmware) { 241 hwaddr firmware_addr = processor_id <= PROCESSOR_ID_BCM2836 242 ? FIRMWARE_ADDR_2 : FIRMWARE_ADDR_3; 243 /* load the firmware image (typically kernel.img) */ 244 r = load_image_targphys(machine->firmware, firmware_addr, 245 ram_size - firmware_addr); 246 if (r < 0) { 247 error_report("Failed to load firmware from %s", machine->firmware); 248 exit(1); 249 } 250 251 s->binfo.entry = firmware_addr; 252 s->binfo.firmware_loaded = true; 253 } 254 255 arm_load_kernel(&s->soc.cpu[0].core, machine, &s->binfo); 256 } 257 258 static void raspi_machine_init(MachineState *machine) 259 { 260 RaspiMachineClass *mc = RASPI_MACHINE_GET_CLASS(machine); 261 RaspiMachineState *s = RASPI_MACHINE(machine); 262 uint32_t board_rev = mc->board_rev; 263 uint64_t ram_size = board_ram_size(board_rev); 264 uint32_t vcram_size; 265 DriveInfo *di; 266 BlockBackend *blk; 267 BusState *bus; 268 DeviceState *carddev; 269 270 if (machine->ram_size != ram_size) { 271 char *size_str = size_to_str(ram_size); 272 error_report("Invalid RAM size, should be %s", size_str); 273 g_free(size_str); 274 exit(1); 275 } 276 277 /* FIXME: Remove when we have custom CPU address space support */ 278 memory_region_add_subregion_overlap(get_system_memory(), 0, 279 machine->ram, 0); 280 281 /* Setup the SOC */ 282 object_initialize_child(OBJECT(machine), "soc", &s->soc, 283 board_soc_type(board_rev)); 284 object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(machine->ram)); 285 object_property_set_int(OBJECT(&s->soc), "board-rev", board_rev, 286 &error_abort); 287 object_property_set_str(OBJECT(&s->soc), "command-line", 288 machine->kernel_cmdline, &error_abort); 289 qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); 290 291 /* Create and plug in the SD cards */ 292 di = drive_get(IF_SD, 0, 0); 293 blk = di ? blk_by_legacy_dinfo(di) : NULL; 294 bus = qdev_get_child_bus(DEVICE(&s->soc), "sd-bus"); 295 if (bus == NULL) { 296 error_report("No SD bus found in SOC object"); 297 exit(1); 298 } 299 carddev = qdev_new(TYPE_SD_CARD); 300 qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal); 301 qdev_realize_and_unref(carddev, bus, &error_fatal); 302 303 vcram_size = object_property_get_uint(OBJECT(&s->soc), "vcram-size", 304 &error_abort); 305 setup_boot(machine, board_processor_id(mc->board_rev), 306 machine->ram_size - vcram_size); 307 } 308 309 static void raspi_machine_class_common_init(MachineClass *mc, 310 uint32_t board_rev) 311 { 312 mc->desc = g_strdup_printf("Raspberry Pi %s (revision 1.%u)", 313 board_type(board_rev), 314 FIELD_EX32(board_rev, REV_CODE, REVISION)); 315 mc->init = raspi_machine_init; 316 mc->block_default_type = IF_SD; 317 mc->no_parallel = 1; 318 mc->no_floppy = 1; 319 mc->no_cdrom = 1; 320 mc->default_cpus = mc->min_cpus = mc->max_cpus = cores_count(board_rev); 321 mc->default_ram_size = board_ram_size(board_rev); 322 mc->default_ram_id = "ram"; 323 }; 324 325 static void raspi0_machine_class_init(ObjectClass *oc, void *data) 326 { 327 MachineClass *mc = MACHINE_CLASS(oc); 328 RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc); 329 330 rmc->board_rev = 0x920092; /* Revision 1.2 */ 331 raspi_machine_class_common_init(mc, rmc->board_rev); 332 }; 333 334 static void raspi1ap_machine_class_init(ObjectClass *oc, void *data) 335 { 336 MachineClass *mc = MACHINE_CLASS(oc); 337 RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc); 338 339 rmc->board_rev = 0x900021; /* Revision 1.1 */ 340 raspi_machine_class_common_init(mc, rmc->board_rev); 341 }; 342 343 static void raspi2b_machine_class_init(ObjectClass *oc, void *data) 344 { 345 MachineClass *mc = MACHINE_CLASS(oc); 346 RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc); 347 348 rmc->board_rev = 0xa21041; 349 raspi_machine_class_common_init(mc, rmc->board_rev); 350 }; 351 352 #ifdef TARGET_AARCH64 353 static void raspi3ap_machine_class_init(ObjectClass *oc, void *data) 354 { 355 MachineClass *mc = MACHINE_CLASS(oc); 356 RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc); 357 358 rmc->board_rev = 0x9020e0; /* Revision 1.0 */ 359 raspi_machine_class_common_init(mc, rmc->board_rev); 360 }; 361 362 static void raspi3b_machine_class_init(ObjectClass *oc, void *data) 363 { 364 MachineClass *mc = MACHINE_CLASS(oc); 365 RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc); 366 367 rmc->board_rev = 0xa02082; 368 raspi_machine_class_common_init(mc, rmc->board_rev); 369 }; 370 #endif /* TARGET_AARCH64 */ 371 372 static const TypeInfo raspi_machine_types[] = { 373 { 374 .name = MACHINE_TYPE_NAME("raspi0"), 375 .parent = TYPE_RASPI_MACHINE, 376 .class_init = raspi0_machine_class_init, 377 }, { 378 .name = MACHINE_TYPE_NAME("raspi1ap"), 379 .parent = TYPE_RASPI_MACHINE, 380 .class_init = raspi1ap_machine_class_init, 381 }, { 382 .name = MACHINE_TYPE_NAME("raspi2b"), 383 .parent = TYPE_RASPI_MACHINE, 384 .class_init = raspi2b_machine_class_init, 385 #ifdef TARGET_AARCH64 386 }, { 387 .name = MACHINE_TYPE_NAME("raspi3ap"), 388 .parent = TYPE_RASPI_MACHINE, 389 .class_init = raspi3ap_machine_class_init, 390 }, { 391 .name = MACHINE_TYPE_NAME("raspi3b"), 392 .parent = TYPE_RASPI_MACHINE, 393 .class_init = raspi3b_machine_class_init, 394 #endif 395 }, { 396 .name = TYPE_RASPI_MACHINE, 397 .parent = TYPE_MACHINE, 398 .instance_size = sizeof(RaspiMachineState), 399 .class_size = sizeof(RaspiMachineClass), 400 .abstract = true, 401 } 402 }; 403 404 DEFINE_TYPES(raspi_machine_types) 405