1 /* 2 * Intel XScale PXA Programmable Interrupt Controller. 3 * 4 * Copyright (c) 2006 Openedhand Ltd. 5 * Copyright (c) 2006 Thorsten Zitterell 6 * Written by Andrzej Zaborowski <balrog@zabor.org> 7 * 8 * This code is licensed under the GPL. 9 */ 10 11 #include "qemu/osdep.h" 12 #include "hw/hw.h" 13 #include "hw/arm/pxa.h" 14 #include "hw/sysbus.h" 15 16 #define ICIP 0x00 /* Interrupt Controller IRQ Pending register */ 17 #define ICMR 0x04 /* Interrupt Controller Mask register */ 18 #define ICLR 0x08 /* Interrupt Controller Level register */ 19 #define ICFP 0x0c /* Interrupt Controller FIQ Pending register */ 20 #define ICPR 0x10 /* Interrupt Controller Pending register */ 21 #define ICCR 0x14 /* Interrupt Controller Control register */ 22 #define ICHP 0x18 /* Interrupt Controller Highest Priority register */ 23 #define IPR0 0x1c /* Interrupt Controller Priority register 0 */ 24 #define IPR31 0x98 /* Interrupt Controller Priority register 31 */ 25 #define ICIP2 0x9c /* Interrupt Controller IRQ Pending register 2 */ 26 #define ICMR2 0xa0 /* Interrupt Controller Mask register 2 */ 27 #define ICLR2 0xa4 /* Interrupt Controller Level register 2 */ 28 #define ICFP2 0xa8 /* Interrupt Controller FIQ Pending register 2 */ 29 #define ICPR2 0xac /* Interrupt Controller Pending register 2 */ 30 #define IPR32 0xb0 /* Interrupt Controller Priority register 32 */ 31 #define IPR39 0xcc /* Interrupt Controller Priority register 39 */ 32 33 #define PXA2XX_PIC_SRCS 40 34 35 #define TYPE_PXA2XX_PIC "pxa2xx_pic" 36 #define PXA2XX_PIC(obj) \ 37 OBJECT_CHECK(PXA2xxPICState, (obj), TYPE_PXA2XX_PIC) 38 39 typedef struct { 40 /*< private >*/ 41 SysBusDevice parent_obj; 42 /*< public >*/ 43 44 MemoryRegion iomem; 45 ARMCPU *cpu; 46 uint32_t int_enabled[2]; 47 uint32_t int_pending[2]; 48 uint32_t is_fiq[2]; 49 uint32_t int_idle; 50 uint32_t priority[PXA2XX_PIC_SRCS]; 51 } PXA2xxPICState; 52 53 static void pxa2xx_pic_update(void *opaque) 54 { 55 uint32_t mask[2]; 56 PXA2xxPICState *s = (PXA2xxPICState *) opaque; 57 CPUState *cpu = CPU(s->cpu); 58 59 if (cpu->halted) { 60 mask[0] = s->int_pending[0] & (s->int_enabled[0] | s->int_idle); 61 mask[1] = s->int_pending[1] & (s->int_enabled[1] | s->int_idle); 62 if (mask[0] || mask[1]) { 63 cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB); 64 } 65 } 66 67 mask[0] = s->int_pending[0] & s->int_enabled[0]; 68 mask[1] = s->int_pending[1] & s->int_enabled[1]; 69 70 if ((mask[0] & s->is_fiq[0]) || (mask[1] & s->is_fiq[1])) { 71 cpu_interrupt(cpu, CPU_INTERRUPT_FIQ); 72 } else { 73 cpu_reset_interrupt(cpu, CPU_INTERRUPT_FIQ); 74 } 75 76 if ((mask[0] & ~s->is_fiq[0]) || (mask[1] & ~s->is_fiq[1])) { 77 cpu_interrupt(cpu, CPU_INTERRUPT_HARD); 78 } else { 79 cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD); 80 } 81 } 82 83 /* Note: Here level means state of the signal on a pin, not 84 * IRQ/FIQ distinction as in PXA Developer Manual. */ 85 static void pxa2xx_pic_set_irq(void *opaque, int irq, int level) 86 { 87 PXA2xxPICState *s = (PXA2xxPICState *) opaque; 88 int int_set = (irq >= 32); 89 irq &= 31; 90 91 if (level) 92 s->int_pending[int_set] |= 1 << irq; 93 else 94 s->int_pending[int_set] &= ~(1 << irq); 95 96 pxa2xx_pic_update(opaque); 97 } 98 99 static inline uint32_t pxa2xx_pic_highest(PXA2xxPICState *s) { 100 int i, int_set, irq; 101 uint32_t bit, mask[2]; 102 uint32_t ichp = 0x003f003f; /* Both IDs invalid */ 103 104 mask[0] = s->int_pending[0] & s->int_enabled[0]; 105 mask[1] = s->int_pending[1] & s->int_enabled[1]; 106 107 for (i = PXA2XX_PIC_SRCS - 1; i >= 0; i --) { 108 irq = s->priority[i] & 0x3f; 109 if ((s->priority[i] & (1U << 31)) && irq < PXA2XX_PIC_SRCS) { 110 /* Source peripheral ID is valid. */ 111 bit = 1 << (irq & 31); 112 int_set = (irq >= 32); 113 114 if (mask[int_set] & bit & s->is_fiq[int_set]) { 115 /* FIQ asserted */ 116 ichp &= 0xffff0000; 117 ichp |= (1 << 15) | irq; 118 } 119 120 if (mask[int_set] & bit & ~s->is_fiq[int_set]) { 121 /* IRQ asserted */ 122 ichp &= 0x0000ffff; 123 ichp |= (1U << 31) | (irq << 16); 124 } 125 } 126 } 127 128 return ichp; 129 } 130 131 static uint64_t pxa2xx_pic_mem_read(void *opaque, hwaddr offset, 132 unsigned size) 133 { 134 PXA2xxPICState *s = (PXA2xxPICState *) opaque; 135 136 switch (offset) { 137 case ICIP: /* IRQ Pending register */ 138 return s->int_pending[0] & ~s->is_fiq[0] & s->int_enabled[0]; 139 case ICIP2: /* IRQ Pending register 2 */ 140 return s->int_pending[1] & ~s->is_fiq[1] & s->int_enabled[1]; 141 case ICMR: /* Mask register */ 142 return s->int_enabled[0]; 143 case ICMR2: /* Mask register 2 */ 144 return s->int_enabled[1]; 145 case ICLR: /* Level register */ 146 return s->is_fiq[0]; 147 case ICLR2: /* Level register 2 */ 148 return s->is_fiq[1]; 149 case ICCR: /* Idle mask */ 150 return (s->int_idle == 0); 151 case ICFP: /* FIQ Pending register */ 152 return s->int_pending[0] & s->is_fiq[0] & s->int_enabled[0]; 153 case ICFP2: /* FIQ Pending register 2 */ 154 return s->int_pending[1] & s->is_fiq[1] & s->int_enabled[1]; 155 case ICPR: /* Pending register */ 156 return s->int_pending[0]; 157 case ICPR2: /* Pending register 2 */ 158 return s->int_pending[1]; 159 case IPR0 ... IPR31: 160 return s->priority[0 + ((offset - IPR0 ) >> 2)]; 161 case IPR32 ... IPR39: 162 return s->priority[32 + ((offset - IPR32) >> 2)]; 163 case ICHP: /* Highest Priority register */ 164 return pxa2xx_pic_highest(s); 165 default: 166 printf("%s: Bad register offset " REG_FMT "\n", __FUNCTION__, offset); 167 return 0; 168 } 169 } 170 171 static void pxa2xx_pic_mem_write(void *opaque, hwaddr offset, 172 uint64_t value, unsigned size) 173 { 174 PXA2xxPICState *s = (PXA2xxPICState *) opaque; 175 176 switch (offset) { 177 case ICMR: /* Mask register */ 178 s->int_enabled[0] = value; 179 break; 180 case ICMR2: /* Mask register 2 */ 181 s->int_enabled[1] = value; 182 break; 183 case ICLR: /* Level register */ 184 s->is_fiq[0] = value; 185 break; 186 case ICLR2: /* Level register 2 */ 187 s->is_fiq[1] = value; 188 break; 189 case ICCR: /* Idle mask */ 190 s->int_idle = (value & 1) ? 0 : ~0; 191 break; 192 case IPR0 ... IPR31: 193 s->priority[0 + ((offset - IPR0 ) >> 2)] = value & 0x8000003f; 194 break; 195 case IPR32 ... IPR39: 196 s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f; 197 break; 198 default: 199 printf("%s: Bad register offset " REG_FMT "\n", __FUNCTION__, offset); 200 return; 201 } 202 pxa2xx_pic_update(opaque); 203 } 204 205 /* Interrupt Controller Coprocessor Space Register Mapping */ 206 static const int pxa2xx_cp_reg_map[0x10] = { 207 [0x0 ... 0xf] = -1, 208 [0x0] = ICIP, 209 [0x1] = ICMR, 210 [0x2] = ICLR, 211 [0x3] = ICFP, 212 [0x4] = ICPR, 213 [0x5] = ICHP, 214 [0x6] = ICIP2, 215 [0x7] = ICMR2, 216 [0x8] = ICLR2, 217 [0x9] = ICFP2, 218 [0xa] = ICPR2, 219 }; 220 221 static uint64_t pxa2xx_pic_cp_read(CPUARMState *env, const ARMCPRegInfo *ri) 222 { 223 int offset = pxa2xx_cp_reg_map[ri->crn]; 224 return pxa2xx_pic_mem_read(ri->opaque, offset, 4); 225 } 226 227 static void pxa2xx_pic_cp_write(CPUARMState *env, const ARMCPRegInfo *ri, 228 uint64_t value) 229 { 230 int offset = pxa2xx_cp_reg_map[ri->crn]; 231 pxa2xx_pic_mem_write(ri->opaque, offset, value, 4); 232 } 233 234 #define REGINFO_FOR_PIC_CP(NAME, CRN) \ 235 { .name = NAME, .cp = 6, .crn = CRN, .crm = 0, .opc1 = 0, .opc2 = 0, \ 236 .access = PL1_RW, .type = ARM_CP_IO, \ 237 .readfn = pxa2xx_pic_cp_read, .writefn = pxa2xx_pic_cp_write } 238 239 static const ARMCPRegInfo pxa_pic_cp_reginfo[] = { 240 REGINFO_FOR_PIC_CP("ICIP", 0), 241 REGINFO_FOR_PIC_CP("ICMR", 1), 242 REGINFO_FOR_PIC_CP("ICLR", 2), 243 REGINFO_FOR_PIC_CP("ICFP", 3), 244 REGINFO_FOR_PIC_CP("ICPR", 4), 245 REGINFO_FOR_PIC_CP("ICHP", 5), 246 REGINFO_FOR_PIC_CP("ICIP2", 6), 247 REGINFO_FOR_PIC_CP("ICMR2", 7), 248 REGINFO_FOR_PIC_CP("ICLR2", 8), 249 REGINFO_FOR_PIC_CP("ICFP2", 9), 250 REGINFO_FOR_PIC_CP("ICPR2", 0xa), 251 REGINFO_SENTINEL 252 }; 253 254 static const MemoryRegionOps pxa2xx_pic_ops = { 255 .read = pxa2xx_pic_mem_read, 256 .write = pxa2xx_pic_mem_write, 257 .endianness = DEVICE_NATIVE_ENDIAN, 258 }; 259 260 static int pxa2xx_pic_post_load(void *opaque, int version_id) 261 { 262 pxa2xx_pic_update(opaque); 263 return 0; 264 } 265 266 DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu) 267 { 268 DeviceState *dev = qdev_create(NULL, TYPE_PXA2XX_PIC); 269 PXA2xxPICState *s = PXA2XX_PIC(dev); 270 271 s->cpu = cpu; 272 273 s->int_pending[0] = 0; 274 s->int_pending[1] = 0; 275 s->int_enabled[0] = 0; 276 s->int_enabled[1] = 0; 277 s->is_fiq[0] = 0; 278 s->is_fiq[1] = 0; 279 280 qdev_init_nofail(dev); 281 282 qdev_init_gpio_in(dev, pxa2xx_pic_set_irq, PXA2XX_PIC_SRCS); 283 284 /* Enable IC memory-mapped registers access. */ 285 memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_pic_ops, s, 286 "pxa2xx-pic", 0x00100000); 287 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); 288 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 289 290 /* Enable IC coprocessor access. */ 291 define_arm_cp_regs_with_opaque(cpu, pxa_pic_cp_reginfo, s); 292 293 return dev; 294 } 295 296 static VMStateDescription vmstate_pxa2xx_pic_regs = { 297 .name = "pxa2xx_pic", 298 .version_id = 0, 299 .minimum_version_id = 0, 300 .post_load = pxa2xx_pic_post_load, 301 .fields = (VMStateField[]) { 302 VMSTATE_UINT32_ARRAY(int_enabled, PXA2xxPICState, 2), 303 VMSTATE_UINT32_ARRAY(int_pending, PXA2xxPICState, 2), 304 VMSTATE_UINT32_ARRAY(is_fiq, PXA2xxPICState, 2), 305 VMSTATE_UINT32(int_idle, PXA2xxPICState), 306 VMSTATE_UINT32_ARRAY(priority, PXA2xxPICState, PXA2XX_PIC_SRCS), 307 VMSTATE_END_OF_LIST(), 308 }, 309 }; 310 311 static int pxa2xx_pic_initfn(SysBusDevice *dev) 312 { 313 return 0; 314 } 315 316 static void pxa2xx_pic_class_init(ObjectClass *klass, void *data) 317 { 318 DeviceClass *dc = DEVICE_CLASS(klass); 319 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 320 321 k->init = pxa2xx_pic_initfn; 322 dc->desc = "PXA2xx PIC"; 323 dc->vmsd = &vmstate_pxa2xx_pic_regs; 324 } 325 326 static const TypeInfo pxa2xx_pic_info = { 327 .name = TYPE_PXA2XX_PIC, 328 .parent = TYPE_SYS_BUS_DEVICE, 329 .instance_size = sizeof(PXA2xxPICState), 330 .class_init = pxa2xx_pic_class_init, 331 }; 332 333 static void pxa2xx_pic_register_types(void) 334 { 335 type_register_static(&pxa2xx_pic_info); 336 } 337 338 type_init(pxa2xx_pic_register_types) 339