1 /* 2 * Intel XScale PXA Programmable Interrupt Controller. 3 * 4 * Copyright (c) 2006 Openedhand Ltd. 5 * Copyright (c) 2006 Thorsten Zitterell 6 * Written by Andrzej Zaborowski <balrog@zabor.org> 7 * 8 * This code is licensed under the GPL. 9 */ 10 11 #include "qemu/osdep.h" 12 #include "qapi/error.h" 13 #include "qemu/module.h" 14 #include "qemu/log.h" 15 #include "cpu.h" 16 #include "hw/arm/pxa.h" 17 #include "hw/sysbus.h" 18 #include "hw/qdev-properties.h" 19 #include "migration/vmstate.h" 20 #include "qom/object.h" 21 #include "target/arm/cpregs.h" 22 23 #define ICIP 0x00 /* Interrupt Controller IRQ Pending register */ 24 #define ICMR 0x04 /* Interrupt Controller Mask register */ 25 #define ICLR 0x08 /* Interrupt Controller Level register */ 26 #define ICFP 0x0c /* Interrupt Controller FIQ Pending register */ 27 #define ICPR 0x10 /* Interrupt Controller Pending register */ 28 #define ICCR 0x14 /* Interrupt Controller Control register */ 29 #define ICHP 0x18 /* Interrupt Controller Highest Priority register */ 30 #define IPR0 0x1c /* Interrupt Controller Priority register 0 */ 31 #define IPR31 0x98 /* Interrupt Controller Priority register 31 */ 32 #define ICIP2 0x9c /* Interrupt Controller IRQ Pending register 2 */ 33 #define ICMR2 0xa0 /* Interrupt Controller Mask register 2 */ 34 #define ICLR2 0xa4 /* Interrupt Controller Level register 2 */ 35 #define ICFP2 0xa8 /* Interrupt Controller FIQ Pending register 2 */ 36 #define ICPR2 0xac /* Interrupt Controller Pending register 2 */ 37 #define IPR32 0xb0 /* Interrupt Controller Priority register 32 */ 38 #define IPR39 0xcc /* Interrupt Controller Priority register 39 */ 39 40 #define PXA2XX_PIC_SRCS 40 41 42 #define TYPE_PXA2XX_PIC "pxa2xx_pic" 43 OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxPICState, PXA2XX_PIC) 44 45 struct PXA2xxPICState { 46 /*< private >*/ 47 SysBusDevice parent_obj; 48 /*< public >*/ 49 50 MemoryRegion iomem; 51 ARMCPU *cpu; 52 uint32_t int_enabled[2]; 53 uint32_t int_pending[2]; 54 uint32_t is_fiq[2]; 55 uint32_t int_idle; 56 uint32_t priority[PXA2XX_PIC_SRCS]; 57 }; 58 59 static void pxa2xx_pic_update(void *opaque) 60 { 61 uint32_t mask[2]; 62 PXA2xxPICState *s = (PXA2xxPICState *) opaque; 63 CPUState *cpu = CPU(s->cpu); 64 65 if (cpu->halted) { 66 mask[0] = s->int_pending[0] & (s->int_enabled[0] | s->int_idle); 67 mask[1] = s->int_pending[1] & (s->int_enabled[1] | s->int_idle); 68 if (mask[0] || mask[1]) { 69 cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB); 70 } 71 } 72 73 mask[0] = s->int_pending[0] & s->int_enabled[0]; 74 mask[1] = s->int_pending[1] & s->int_enabled[1]; 75 76 if ((mask[0] & s->is_fiq[0]) || (mask[1] & s->is_fiq[1])) { 77 cpu_interrupt(cpu, CPU_INTERRUPT_FIQ); 78 } else { 79 cpu_reset_interrupt(cpu, CPU_INTERRUPT_FIQ); 80 } 81 82 if ((mask[0] & ~s->is_fiq[0]) || (mask[1] & ~s->is_fiq[1])) { 83 cpu_interrupt(cpu, CPU_INTERRUPT_HARD); 84 } else { 85 cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD); 86 } 87 } 88 89 /* Note: Here level means state of the signal on a pin, not 90 * IRQ/FIQ distinction as in PXA Developer Manual. */ 91 static void pxa2xx_pic_set_irq(void *opaque, int irq, int level) 92 { 93 PXA2xxPICState *s = (PXA2xxPICState *) opaque; 94 int int_set = (irq >= 32); 95 irq &= 31; 96 97 if (level) 98 s->int_pending[int_set] |= 1 << irq; 99 else 100 s->int_pending[int_set] &= ~(1 << irq); 101 102 pxa2xx_pic_update(opaque); 103 } 104 105 static inline uint32_t pxa2xx_pic_highest(PXA2xxPICState *s) { 106 int i, int_set, irq; 107 uint32_t bit, mask[2]; 108 uint32_t ichp = 0x003f003f; /* Both IDs invalid */ 109 110 mask[0] = s->int_pending[0] & s->int_enabled[0]; 111 mask[1] = s->int_pending[1] & s->int_enabled[1]; 112 113 for (i = PXA2XX_PIC_SRCS - 1; i >= 0; i --) { 114 irq = s->priority[i] & 0x3f; 115 if ((s->priority[i] & (1U << 31)) && irq < PXA2XX_PIC_SRCS) { 116 /* Source peripheral ID is valid. */ 117 bit = 1 << (irq & 31); 118 int_set = (irq >= 32); 119 120 if (mask[int_set] & bit & s->is_fiq[int_set]) { 121 /* FIQ asserted */ 122 ichp &= 0xffff0000; 123 ichp |= (1 << 15) | irq; 124 } 125 126 if (mask[int_set] & bit & ~s->is_fiq[int_set]) { 127 /* IRQ asserted */ 128 ichp &= 0x0000ffff; 129 ichp |= (1U << 31) | (irq << 16); 130 } 131 } 132 } 133 134 return ichp; 135 } 136 137 static uint64_t pxa2xx_pic_mem_read(void *opaque, hwaddr offset, 138 unsigned size) 139 { 140 PXA2xxPICState *s = (PXA2xxPICState *) opaque; 141 142 switch (offset) { 143 case ICIP: /* IRQ Pending register */ 144 return s->int_pending[0] & ~s->is_fiq[0] & s->int_enabled[0]; 145 case ICIP2: /* IRQ Pending register 2 */ 146 return s->int_pending[1] & ~s->is_fiq[1] & s->int_enabled[1]; 147 case ICMR: /* Mask register */ 148 return s->int_enabled[0]; 149 case ICMR2: /* Mask register 2 */ 150 return s->int_enabled[1]; 151 case ICLR: /* Level register */ 152 return s->is_fiq[0]; 153 case ICLR2: /* Level register 2 */ 154 return s->is_fiq[1]; 155 case ICCR: /* Idle mask */ 156 return (s->int_idle == 0); 157 case ICFP: /* FIQ Pending register */ 158 return s->int_pending[0] & s->is_fiq[0] & s->int_enabled[0]; 159 case ICFP2: /* FIQ Pending register 2 */ 160 return s->int_pending[1] & s->is_fiq[1] & s->int_enabled[1]; 161 case ICPR: /* Pending register */ 162 return s->int_pending[0]; 163 case ICPR2: /* Pending register 2 */ 164 return s->int_pending[1]; 165 case IPR0 ... IPR31: 166 return s->priority[0 + ((offset - IPR0 ) >> 2)]; 167 case IPR32 ... IPR39: 168 return s->priority[32 + ((offset - IPR32) >> 2)]; 169 case ICHP: /* Highest Priority register */ 170 return pxa2xx_pic_highest(s); 171 default: 172 qemu_log_mask(LOG_GUEST_ERROR, 173 "pxa2xx_pic_mem_read: bad register offset 0x%" HWADDR_PRIx 174 "\n", offset); 175 return 0; 176 } 177 } 178 179 static void pxa2xx_pic_mem_write(void *opaque, hwaddr offset, 180 uint64_t value, unsigned size) 181 { 182 PXA2xxPICState *s = (PXA2xxPICState *) opaque; 183 184 switch (offset) { 185 case ICMR: /* Mask register */ 186 s->int_enabled[0] = value; 187 break; 188 case ICMR2: /* Mask register 2 */ 189 s->int_enabled[1] = value; 190 break; 191 case ICLR: /* Level register */ 192 s->is_fiq[0] = value; 193 break; 194 case ICLR2: /* Level register 2 */ 195 s->is_fiq[1] = value; 196 break; 197 case ICCR: /* Idle mask */ 198 s->int_idle = (value & 1) ? 0 : ~0; 199 break; 200 case IPR0 ... IPR31: 201 s->priority[0 + ((offset - IPR0 ) >> 2)] = value & 0x8000003f; 202 break; 203 case IPR32 ... IPR39: 204 s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f; 205 break; 206 default: 207 qemu_log_mask(LOG_GUEST_ERROR, 208 "pxa2xx_pic_mem_write: bad register offset 0x%" 209 HWADDR_PRIx "\n", offset); 210 return; 211 } 212 pxa2xx_pic_update(opaque); 213 } 214 215 /* Interrupt Controller Coprocessor Space Register Mapping */ 216 static const int pxa2xx_cp_reg_map[0x10] = { 217 [0x0 ... 0xf] = -1, 218 [0x0] = ICIP, 219 [0x1] = ICMR, 220 [0x2] = ICLR, 221 [0x3] = ICFP, 222 [0x4] = ICPR, 223 [0x5] = ICHP, 224 [0x6] = ICIP2, 225 [0x7] = ICMR2, 226 [0x8] = ICLR2, 227 [0x9] = ICFP2, 228 [0xa] = ICPR2, 229 }; 230 231 static uint64_t pxa2xx_pic_cp_read(CPUARMState *env, const ARMCPRegInfo *ri) 232 { 233 int offset = pxa2xx_cp_reg_map[ri->crn]; 234 return pxa2xx_pic_mem_read(ri->opaque, offset, 4); 235 } 236 237 static void pxa2xx_pic_cp_write(CPUARMState *env, const ARMCPRegInfo *ri, 238 uint64_t value) 239 { 240 int offset = pxa2xx_cp_reg_map[ri->crn]; 241 pxa2xx_pic_mem_write(ri->opaque, offset, value, 4); 242 } 243 244 #define REGINFO_FOR_PIC_CP(NAME, CRN) \ 245 { .name = NAME, .cp = 6, .crn = CRN, .crm = 0, .opc1 = 0, .opc2 = 0, \ 246 .access = PL1_RW, .type = ARM_CP_IO, \ 247 .readfn = pxa2xx_pic_cp_read, .writefn = pxa2xx_pic_cp_write } 248 249 static const ARMCPRegInfo pxa_pic_cp_reginfo[] = { 250 REGINFO_FOR_PIC_CP("ICIP", 0), 251 REGINFO_FOR_PIC_CP("ICMR", 1), 252 REGINFO_FOR_PIC_CP("ICLR", 2), 253 REGINFO_FOR_PIC_CP("ICFP", 3), 254 REGINFO_FOR_PIC_CP("ICPR", 4), 255 REGINFO_FOR_PIC_CP("ICHP", 5), 256 REGINFO_FOR_PIC_CP("ICIP2", 6), 257 REGINFO_FOR_PIC_CP("ICMR2", 7), 258 REGINFO_FOR_PIC_CP("ICLR2", 8), 259 REGINFO_FOR_PIC_CP("ICFP2", 9), 260 REGINFO_FOR_PIC_CP("ICPR2", 0xa), 261 }; 262 263 static const MemoryRegionOps pxa2xx_pic_ops = { 264 .read = pxa2xx_pic_mem_read, 265 .write = pxa2xx_pic_mem_write, 266 .endianness = DEVICE_NATIVE_ENDIAN, 267 }; 268 269 static int pxa2xx_pic_post_load(void *opaque, int version_id) 270 { 271 pxa2xx_pic_update(opaque); 272 return 0; 273 } 274 275 static void pxa2xx_pic_reset_hold(Object *obj, ResetType type) 276 { 277 PXA2xxPICState *s = PXA2XX_PIC(obj); 278 279 s->int_pending[0] = 0; 280 s->int_pending[1] = 0; 281 s->int_enabled[0] = 0; 282 s->int_enabled[1] = 0; 283 s->is_fiq[0] = 0; 284 s->is_fiq[1] = 0; 285 } 286 287 DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu) 288 { 289 DeviceState *dev = qdev_new(TYPE_PXA2XX_PIC); 290 291 object_property_set_link(OBJECT(dev), "arm-cpu", 292 OBJECT(cpu), &error_abort); 293 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 294 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 295 296 return dev; 297 } 298 299 static void pxa2xx_pic_realize(DeviceState *dev, Error **errp) 300 { 301 PXA2xxPICState *s = PXA2XX_PIC(dev); 302 303 qdev_init_gpio_in(dev, pxa2xx_pic_set_irq, PXA2XX_PIC_SRCS); 304 305 /* Enable IC memory-mapped registers access. */ 306 memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_pic_ops, s, 307 "pxa2xx-pic", 0x00100000); 308 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); 309 310 /* Enable IC coprocessor access. */ 311 define_arm_cp_regs_with_opaque(s->cpu, pxa_pic_cp_reginfo, s); 312 } 313 314 static const VMStateDescription vmstate_pxa2xx_pic_regs = { 315 .name = "pxa2xx_pic", 316 .version_id = 0, 317 .minimum_version_id = 0, 318 .post_load = pxa2xx_pic_post_load, 319 .fields = (const VMStateField[]) { 320 VMSTATE_UINT32_ARRAY(int_enabled, PXA2xxPICState, 2), 321 VMSTATE_UINT32_ARRAY(int_pending, PXA2xxPICState, 2), 322 VMSTATE_UINT32_ARRAY(is_fiq, PXA2xxPICState, 2), 323 VMSTATE_UINT32(int_idle, PXA2xxPICState), 324 VMSTATE_UINT32_ARRAY(priority, PXA2xxPICState, PXA2XX_PIC_SRCS), 325 VMSTATE_END_OF_LIST(), 326 }, 327 }; 328 329 static Property pxa2xx_pic_properties[] = { 330 DEFINE_PROP_LINK("arm-cpu", PXA2xxPICState, cpu, 331 TYPE_ARM_CPU, ARMCPU *), 332 DEFINE_PROP_END_OF_LIST(), 333 }; 334 335 static void pxa2xx_pic_class_init(ObjectClass *klass, void *data) 336 { 337 DeviceClass *dc = DEVICE_CLASS(klass); 338 ResettableClass *rc = RESETTABLE_CLASS(klass); 339 340 device_class_set_props(dc, pxa2xx_pic_properties); 341 dc->realize = pxa2xx_pic_realize; 342 dc->desc = "PXA2xx PIC"; 343 dc->vmsd = &vmstate_pxa2xx_pic_regs; 344 rc->phases.hold = pxa2xx_pic_reset_hold; 345 } 346 347 static const TypeInfo pxa2xx_pic_info = { 348 .name = TYPE_PXA2XX_PIC, 349 .parent = TYPE_SYS_BUS_DEVICE, 350 .instance_size = sizeof(PXA2xxPICState), 351 .class_init = pxa2xx_pic_class_init, 352 }; 353 354 static void pxa2xx_pic_register_types(void) 355 { 356 type_register_static(&pxa2xx_pic_info); 357 } 358 359 type_init(pxa2xx_pic_register_types) 360