1 /* 2 * Intel XScale PXA255/270 GPIO controller emulation. 3 * 4 * Copyright (c) 2006 Openedhand Ltd. 5 * Written by Andrzej Zaborowski <balrog@zabor.org> 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "cpu.h" 12 #include "hw/hw.h" 13 #include "hw/sysbus.h" 14 #include "hw/arm/pxa.h" 15 #include "qemu/log.h" 16 #include "qemu/module.h" 17 18 #define PXA2XX_GPIO_BANKS 4 19 20 #define TYPE_PXA2XX_GPIO "pxa2xx-gpio" 21 #define PXA2XX_GPIO(obj) \ 22 OBJECT_CHECK(PXA2xxGPIOInfo, (obj), TYPE_PXA2XX_GPIO) 23 24 typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo; 25 struct PXA2xxGPIOInfo { 26 /*< private >*/ 27 SysBusDevice parent_obj; 28 /*< public >*/ 29 30 MemoryRegion iomem; 31 qemu_irq irq0, irq1, irqX; 32 int lines; 33 int ncpu; 34 ARMCPU *cpu; 35 36 /* XXX: GNU C vectors are more suitable */ 37 uint32_t ilevel[PXA2XX_GPIO_BANKS]; 38 uint32_t olevel[PXA2XX_GPIO_BANKS]; 39 uint32_t dir[PXA2XX_GPIO_BANKS]; 40 uint32_t rising[PXA2XX_GPIO_BANKS]; 41 uint32_t falling[PXA2XX_GPIO_BANKS]; 42 uint32_t status[PXA2XX_GPIO_BANKS]; 43 uint32_t gafr[PXA2XX_GPIO_BANKS * 2]; 44 45 uint32_t prev_level[PXA2XX_GPIO_BANKS]; 46 qemu_irq handler[PXA2XX_GPIO_BANKS * 32]; 47 qemu_irq read_notify; 48 }; 49 50 static struct { 51 enum { 52 GPIO_NONE, 53 GPLR, 54 GPSR, 55 GPCR, 56 GPDR, 57 GRER, 58 GFER, 59 GEDR, 60 GAFR_L, 61 GAFR_U, 62 } reg; 63 int bank; 64 } pxa2xx_gpio_regs[0x200] = { 65 [0 ... 0x1ff] = { GPIO_NONE, 0 }, 66 #define PXA2XX_REG(reg, a0, a1, a2, a3) \ 67 [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 }, 68 69 PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100) 70 PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118) 71 PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124) 72 PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c) 73 PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130) 74 PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c) 75 PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148) 76 PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c) 77 PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070) 78 }; 79 80 static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s) 81 { 82 if (s->status[0] & (1 << 0)) 83 qemu_irq_raise(s->irq0); 84 else 85 qemu_irq_lower(s->irq0); 86 87 if (s->status[0] & (1 << 1)) 88 qemu_irq_raise(s->irq1); 89 else 90 qemu_irq_lower(s->irq1); 91 92 if ((s->status[0] & ~3) | s->status[1] | s->status[2] | s->status[3]) 93 qemu_irq_raise(s->irqX); 94 else 95 qemu_irq_lower(s->irqX); 96 } 97 98 /* Bitmap of pins used as standby and sleep wake-up sources. */ 99 static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = { 100 0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f, 101 }; 102 103 static void pxa2xx_gpio_set(void *opaque, int line, int level) 104 { 105 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque; 106 CPUState *cpu = CPU(s->cpu); 107 int bank; 108 uint32_t mask; 109 110 if (line >= s->lines) { 111 printf("%s: No GPIO pin %i\n", __func__, line); 112 return; 113 } 114 115 bank = line >> 5; 116 mask = 1U << (line & 31); 117 118 if (level) { 119 s->status[bank] |= s->rising[bank] & mask & 120 ~s->ilevel[bank] & ~s->dir[bank]; 121 s->ilevel[bank] |= mask; 122 } else { 123 s->status[bank] |= s->falling[bank] & mask & 124 s->ilevel[bank] & ~s->dir[bank]; 125 s->ilevel[bank] &= ~mask; 126 } 127 128 if (s->status[bank] & mask) 129 pxa2xx_gpio_irq_update(s); 130 131 /* Wake-up GPIOs */ 132 if (cpu->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank])) { 133 cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB); 134 } 135 } 136 137 static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) { 138 uint32_t level, diff; 139 int i, bit, line; 140 for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) { 141 level = s->olevel[i] & s->dir[i]; 142 143 for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) { 144 bit = ctz32(diff); 145 line = bit + 32 * i; 146 qemu_set_irq(s->handler[line], (level >> bit) & 1); 147 } 148 149 s->prev_level[i] = level; 150 } 151 } 152 153 static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset, 154 unsigned size) 155 { 156 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque; 157 uint32_t ret; 158 int bank; 159 if (offset >= 0x200) 160 return 0; 161 162 bank = pxa2xx_gpio_regs[offset].bank; 163 switch (pxa2xx_gpio_regs[offset].reg) { 164 case GPDR: /* GPIO Pin-Direction registers */ 165 return s->dir[bank]; 166 167 case GPSR: /* GPIO Pin-Output Set registers */ 168 qemu_log_mask(LOG_GUEST_ERROR, 169 "pxa2xx GPIO: read from write only register GPSR\n"); 170 return 0; 171 172 case GPCR: /* GPIO Pin-Output Clear registers */ 173 qemu_log_mask(LOG_GUEST_ERROR, 174 "pxa2xx GPIO: read from write only register GPCR\n"); 175 return 0; 176 177 case GRER: /* GPIO Rising-Edge Detect Enable registers */ 178 return s->rising[bank]; 179 180 case GFER: /* GPIO Falling-Edge Detect Enable registers */ 181 return s->falling[bank]; 182 183 case GAFR_L: /* GPIO Alternate Function registers */ 184 return s->gafr[bank * 2]; 185 186 case GAFR_U: /* GPIO Alternate Function registers */ 187 return s->gafr[bank * 2 + 1]; 188 189 case GPLR: /* GPIO Pin-Level registers */ 190 ret = (s->olevel[bank] & s->dir[bank]) | 191 (s->ilevel[bank] & ~s->dir[bank]); 192 qemu_irq_raise(s->read_notify); 193 return ret; 194 195 case GEDR: /* GPIO Edge Detect Status registers */ 196 return s->status[bank]; 197 198 default: 199 hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset); 200 } 201 202 return 0; 203 } 204 205 static void pxa2xx_gpio_write(void *opaque, hwaddr offset, 206 uint64_t value, unsigned size) 207 { 208 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque; 209 int bank; 210 if (offset >= 0x200) 211 return; 212 213 bank = pxa2xx_gpio_regs[offset].bank; 214 switch (pxa2xx_gpio_regs[offset].reg) { 215 case GPDR: /* GPIO Pin-Direction registers */ 216 s->dir[bank] = value; 217 pxa2xx_gpio_handler_update(s); 218 break; 219 220 case GPSR: /* GPIO Pin-Output Set registers */ 221 s->olevel[bank] |= value; 222 pxa2xx_gpio_handler_update(s); 223 break; 224 225 case GPCR: /* GPIO Pin-Output Clear registers */ 226 s->olevel[bank] &= ~value; 227 pxa2xx_gpio_handler_update(s); 228 break; 229 230 case GRER: /* GPIO Rising-Edge Detect Enable registers */ 231 s->rising[bank] = value; 232 break; 233 234 case GFER: /* GPIO Falling-Edge Detect Enable registers */ 235 s->falling[bank] = value; 236 break; 237 238 case GAFR_L: /* GPIO Alternate Function registers */ 239 s->gafr[bank * 2] = value; 240 break; 241 242 case GAFR_U: /* GPIO Alternate Function registers */ 243 s->gafr[bank * 2 + 1] = value; 244 break; 245 246 case GEDR: /* GPIO Edge Detect Status registers */ 247 s->status[bank] &= ~value; 248 pxa2xx_gpio_irq_update(s); 249 break; 250 251 default: 252 hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset); 253 } 254 } 255 256 static const MemoryRegionOps pxa_gpio_ops = { 257 .read = pxa2xx_gpio_read, 258 .write = pxa2xx_gpio_write, 259 .endianness = DEVICE_NATIVE_ENDIAN, 260 }; 261 262 DeviceState *pxa2xx_gpio_init(hwaddr base, 263 ARMCPU *cpu, DeviceState *pic, int lines) 264 { 265 CPUState *cs = CPU(cpu); 266 DeviceState *dev; 267 268 dev = qdev_create(NULL, TYPE_PXA2XX_GPIO); 269 qdev_prop_set_int32(dev, "lines", lines); 270 qdev_prop_set_int32(dev, "ncpu", cs->cpu_index); 271 qdev_init_nofail(dev); 272 273 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 274 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 275 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0)); 276 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, 277 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1)); 278 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, 279 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X)); 280 281 return dev; 282 } 283 284 static void pxa2xx_gpio_initfn(Object *obj) 285 { 286 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 287 DeviceState *dev = DEVICE(sbd); 288 PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev); 289 290 memory_region_init_io(&s->iomem, obj, &pxa_gpio_ops, 291 s, "pxa2xx-gpio", 0x1000); 292 sysbus_init_mmio(sbd, &s->iomem); 293 sysbus_init_irq(sbd, &s->irq0); 294 sysbus_init_irq(sbd, &s->irq1); 295 sysbus_init_irq(sbd, &s->irqX); 296 } 297 298 static void pxa2xx_gpio_realize(DeviceState *dev, Error **errp) 299 { 300 PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev); 301 302 s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu)); 303 304 qdev_init_gpio_in(dev, pxa2xx_gpio_set, s->lines); 305 qdev_init_gpio_out(dev, s->handler, s->lines); 306 } 307 308 /* 309 * Registers a callback to notify on GPLR reads. This normally 310 * shouldn't be needed but it is used for the hack on Spitz machines. 311 */ 312 void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler) 313 { 314 PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev); 315 316 s->read_notify = handler; 317 } 318 319 static const VMStateDescription vmstate_pxa2xx_gpio_regs = { 320 .name = "pxa2xx-gpio", 321 .version_id = 1, 322 .minimum_version_id = 1, 323 .fields = (VMStateField[]) { 324 VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), 325 VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), 326 VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), 327 VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), 328 VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), 329 VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), 330 VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2), 331 VMSTATE_UINT32_ARRAY(prev_level, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), 332 VMSTATE_END_OF_LIST(), 333 }, 334 }; 335 336 static Property pxa2xx_gpio_properties[] = { 337 DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0), 338 DEFINE_PROP_INT32("ncpu", PXA2xxGPIOInfo, ncpu, 0), 339 DEFINE_PROP_END_OF_LIST(), 340 }; 341 342 static void pxa2xx_gpio_class_init(ObjectClass *klass, void *data) 343 { 344 DeviceClass *dc = DEVICE_CLASS(klass); 345 346 dc->desc = "PXA2xx GPIO controller"; 347 dc->props = pxa2xx_gpio_properties; 348 dc->vmsd = &vmstate_pxa2xx_gpio_regs; 349 dc->realize = pxa2xx_gpio_realize; 350 } 351 352 static const TypeInfo pxa2xx_gpio_info = { 353 .name = TYPE_PXA2XX_GPIO, 354 .parent = TYPE_SYS_BUS_DEVICE, 355 .instance_size = sizeof(PXA2xxGPIOInfo), 356 .instance_init = pxa2xx_gpio_initfn, 357 .class_init = pxa2xx_gpio_class_init, 358 }; 359 360 static void pxa2xx_gpio_register_types(void) 361 { 362 type_register_static(&pxa2xx_gpio_info); 363 } 364 365 type_init(pxa2xx_gpio_register_types) 366