1 /* 2 * Intel XScale PXA255/270 GPIO controller emulation. 3 * 4 * Copyright (c) 2006 Openedhand Ltd. 5 * Written by Andrzej Zaborowski <balrog@zabor.org> 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "hw/hw.h" 11 #include "hw/sysbus.h" 12 #include "hw/arm/pxa.h" 13 14 #define PXA2XX_GPIO_BANKS 4 15 16 #define TYPE_PXA2XX_GPIO "pxa2xx-gpio" 17 #define PXA2XX_GPIO(obj) \ 18 OBJECT_CHECK(PXA2xxGPIOInfo, (obj), TYPE_PXA2XX_GPIO) 19 20 typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo; 21 struct PXA2xxGPIOInfo { 22 /*< private >*/ 23 SysBusDevice parent_obj; 24 /*< public >*/ 25 26 MemoryRegion iomem; 27 qemu_irq irq0, irq1, irqX; 28 int lines; 29 int ncpu; 30 ARMCPU *cpu; 31 32 /* XXX: GNU C vectors are more suitable */ 33 uint32_t ilevel[PXA2XX_GPIO_BANKS]; 34 uint32_t olevel[PXA2XX_GPIO_BANKS]; 35 uint32_t dir[PXA2XX_GPIO_BANKS]; 36 uint32_t rising[PXA2XX_GPIO_BANKS]; 37 uint32_t falling[PXA2XX_GPIO_BANKS]; 38 uint32_t status[PXA2XX_GPIO_BANKS]; 39 uint32_t gpsr[PXA2XX_GPIO_BANKS]; 40 uint32_t gafr[PXA2XX_GPIO_BANKS * 2]; 41 42 uint32_t prev_level[PXA2XX_GPIO_BANKS]; 43 qemu_irq handler[PXA2XX_GPIO_BANKS * 32]; 44 qemu_irq read_notify; 45 }; 46 47 static struct { 48 enum { 49 GPIO_NONE, 50 GPLR, 51 GPSR, 52 GPCR, 53 GPDR, 54 GRER, 55 GFER, 56 GEDR, 57 GAFR_L, 58 GAFR_U, 59 } reg; 60 int bank; 61 } pxa2xx_gpio_regs[0x200] = { 62 [0 ... 0x1ff] = { GPIO_NONE, 0 }, 63 #define PXA2XX_REG(reg, a0, a1, a2, a3) \ 64 [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 }, 65 66 PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100) 67 PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118) 68 PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124) 69 PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c) 70 PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130) 71 PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c) 72 PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148) 73 PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c) 74 PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070) 75 }; 76 77 static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s) 78 { 79 if (s->status[0] & (1 << 0)) 80 qemu_irq_raise(s->irq0); 81 else 82 qemu_irq_lower(s->irq0); 83 84 if (s->status[0] & (1 << 1)) 85 qemu_irq_raise(s->irq1); 86 else 87 qemu_irq_lower(s->irq1); 88 89 if ((s->status[0] & ~3) | s->status[1] | s->status[2] | s->status[3]) 90 qemu_irq_raise(s->irqX); 91 else 92 qemu_irq_lower(s->irqX); 93 } 94 95 /* Bitmap of pins used as standby and sleep wake-up sources. */ 96 static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = { 97 0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f, 98 }; 99 100 static void pxa2xx_gpio_set(void *opaque, int line, int level) 101 { 102 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque; 103 CPUState *cpu = CPU(s->cpu); 104 int bank; 105 uint32_t mask; 106 107 if (line >= s->lines) { 108 printf("%s: No GPIO pin %i\n", __FUNCTION__, line); 109 return; 110 } 111 112 bank = line >> 5; 113 mask = 1U << (line & 31); 114 115 if (level) { 116 s->status[bank] |= s->rising[bank] & mask & 117 ~s->ilevel[bank] & ~s->dir[bank]; 118 s->ilevel[bank] |= mask; 119 } else { 120 s->status[bank] |= s->falling[bank] & mask & 121 s->ilevel[bank] & ~s->dir[bank]; 122 s->ilevel[bank] &= ~mask; 123 } 124 125 if (s->status[bank] & mask) 126 pxa2xx_gpio_irq_update(s); 127 128 /* Wake-up GPIOs */ 129 if (cpu->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank])) { 130 cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB); 131 } 132 } 133 134 static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) { 135 uint32_t level, diff; 136 int i, bit, line; 137 for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) { 138 level = s->olevel[i] & s->dir[i]; 139 140 for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) { 141 bit = ffs(diff) - 1; 142 line = bit + 32 * i; 143 qemu_set_irq(s->handler[line], (level >> bit) & 1); 144 } 145 146 s->prev_level[i] = level; 147 } 148 } 149 150 static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset, 151 unsigned size) 152 { 153 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque; 154 uint32_t ret; 155 int bank; 156 if (offset >= 0x200) 157 return 0; 158 159 bank = pxa2xx_gpio_regs[offset].bank; 160 switch (pxa2xx_gpio_regs[offset].reg) { 161 case GPDR: /* GPIO Pin-Direction registers */ 162 return s->dir[bank]; 163 164 case GPSR: /* GPIO Pin-Output Set registers */ 165 printf("%s: Read from a write-only register " REG_FMT "\n", 166 __FUNCTION__, offset); 167 return s->gpsr[bank]; /* Return last written value. */ 168 169 case GPCR: /* GPIO Pin-Output Clear registers */ 170 printf("%s: Read from a write-only register " REG_FMT "\n", 171 __FUNCTION__, offset); 172 return 31337; /* Specified as unpredictable in the docs. */ 173 174 case GRER: /* GPIO Rising-Edge Detect Enable registers */ 175 return s->rising[bank]; 176 177 case GFER: /* GPIO Falling-Edge Detect Enable registers */ 178 return s->falling[bank]; 179 180 case GAFR_L: /* GPIO Alternate Function registers */ 181 return s->gafr[bank * 2]; 182 183 case GAFR_U: /* GPIO Alternate Function registers */ 184 return s->gafr[bank * 2 + 1]; 185 186 case GPLR: /* GPIO Pin-Level registers */ 187 ret = (s->olevel[bank] & s->dir[bank]) | 188 (s->ilevel[bank] & ~s->dir[bank]); 189 qemu_irq_raise(s->read_notify); 190 return ret; 191 192 case GEDR: /* GPIO Edge Detect Status registers */ 193 return s->status[bank]; 194 195 default: 196 hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset); 197 } 198 199 return 0; 200 } 201 202 static void pxa2xx_gpio_write(void *opaque, hwaddr offset, 203 uint64_t value, unsigned size) 204 { 205 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque; 206 int bank; 207 if (offset >= 0x200) 208 return; 209 210 bank = pxa2xx_gpio_regs[offset].bank; 211 switch (pxa2xx_gpio_regs[offset].reg) { 212 case GPDR: /* GPIO Pin-Direction registers */ 213 s->dir[bank] = value; 214 pxa2xx_gpio_handler_update(s); 215 break; 216 217 case GPSR: /* GPIO Pin-Output Set registers */ 218 s->olevel[bank] |= value; 219 pxa2xx_gpio_handler_update(s); 220 s->gpsr[bank] = value; 221 break; 222 223 case GPCR: /* GPIO Pin-Output Clear registers */ 224 s->olevel[bank] &= ~value; 225 pxa2xx_gpio_handler_update(s); 226 break; 227 228 case GRER: /* GPIO Rising-Edge Detect Enable registers */ 229 s->rising[bank] = value; 230 break; 231 232 case GFER: /* GPIO Falling-Edge Detect Enable registers */ 233 s->falling[bank] = value; 234 break; 235 236 case GAFR_L: /* GPIO Alternate Function registers */ 237 s->gafr[bank * 2] = value; 238 break; 239 240 case GAFR_U: /* GPIO Alternate Function registers */ 241 s->gafr[bank * 2 + 1] = value; 242 break; 243 244 case GEDR: /* GPIO Edge Detect Status registers */ 245 s->status[bank] &= ~value; 246 pxa2xx_gpio_irq_update(s); 247 break; 248 249 default: 250 hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset); 251 } 252 } 253 254 static const MemoryRegionOps pxa_gpio_ops = { 255 .read = pxa2xx_gpio_read, 256 .write = pxa2xx_gpio_write, 257 .endianness = DEVICE_NATIVE_ENDIAN, 258 }; 259 260 DeviceState *pxa2xx_gpio_init(hwaddr base, 261 ARMCPU *cpu, DeviceState *pic, int lines) 262 { 263 CPUState *cs = CPU(cpu); 264 DeviceState *dev; 265 266 dev = qdev_create(NULL, TYPE_PXA2XX_GPIO); 267 qdev_prop_set_int32(dev, "lines", lines); 268 qdev_prop_set_int32(dev, "ncpu", cs->cpu_index); 269 qdev_init_nofail(dev); 270 271 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 272 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 273 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0)); 274 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, 275 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1)); 276 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, 277 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X)); 278 279 return dev; 280 } 281 282 static int pxa2xx_gpio_initfn(SysBusDevice *sbd) 283 { 284 DeviceState *dev = DEVICE(sbd); 285 PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev); 286 287 s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu)); 288 289 qdev_init_gpio_in(dev, pxa2xx_gpio_set, s->lines); 290 qdev_init_gpio_out(dev, s->handler, s->lines); 291 292 memory_region_init_io(&s->iomem, OBJECT(s), &pxa_gpio_ops, s, "pxa2xx-gpio", 0x1000); 293 sysbus_init_mmio(sbd, &s->iomem); 294 sysbus_init_irq(sbd, &s->irq0); 295 sysbus_init_irq(sbd, &s->irq1); 296 sysbus_init_irq(sbd, &s->irqX); 297 298 return 0; 299 } 300 301 /* 302 * Registers a callback to notify on GPLR reads. This normally 303 * shouldn't be needed but it is used for the hack on Spitz machines. 304 */ 305 void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler) 306 { 307 PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev); 308 309 s->read_notify = handler; 310 } 311 312 static const VMStateDescription vmstate_pxa2xx_gpio_regs = { 313 .name = "pxa2xx-gpio", 314 .version_id = 1, 315 .minimum_version_id = 1, 316 .minimum_version_id_old = 1, 317 .fields = (VMStateField []) { 318 VMSTATE_INT32(lines, PXA2xxGPIOInfo), 319 VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), 320 VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), 321 VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), 322 VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), 323 VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), 324 VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), 325 VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2), 326 VMSTATE_END_OF_LIST(), 327 }, 328 }; 329 330 static Property pxa2xx_gpio_properties[] = { 331 DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0), 332 DEFINE_PROP_INT32("ncpu", PXA2xxGPIOInfo, ncpu, 0), 333 DEFINE_PROP_END_OF_LIST(), 334 }; 335 336 static void pxa2xx_gpio_class_init(ObjectClass *klass, void *data) 337 { 338 DeviceClass *dc = DEVICE_CLASS(klass); 339 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 340 341 k->init = pxa2xx_gpio_initfn; 342 dc->desc = "PXA2xx GPIO controller"; 343 dc->props = pxa2xx_gpio_properties; 344 } 345 346 static const TypeInfo pxa2xx_gpio_info = { 347 .name = TYPE_PXA2XX_GPIO, 348 .parent = TYPE_SYS_BUS_DEVICE, 349 .instance_size = sizeof(PXA2xxGPIOInfo), 350 .class_init = pxa2xx_gpio_class_init, 351 }; 352 353 static void pxa2xx_gpio_register_types(void) 354 { 355 type_register_static(&pxa2xx_gpio_info); 356 } 357 358 type_init(pxa2xx_gpio_register_types) 359