1 /* 2 * Intel XScale PXA255/270 processor support. 3 * 4 * Copyright (c) 2006 Openedhand Ltd. 5 * Written by Andrzej Zaborowski <balrog@zabor.org> 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu-common.h" 12 #include "qemu/error-report.h" 13 #include "qemu/module.h" 14 #include "qapi/error.h" 15 #include "cpu.h" 16 #include "hw/sysbus.h" 17 #include "migration/vmstate.h" 18 #include "hw/arm/pxa.h" 19 #include "sysemu/sysemu.h" 20 #include "hw/char/serial.h" 21 #include "hw/i2c/i2c.h" 22 #include "hw/irq.h" 23 #include "hw/qdev-properties.h" 24 #include "hw/ssi/ssi.h" 25 #include "chardev/char-fe.h" 26 #include "sysemu/blockdev.h" 27 #include "sysemu/qtest.h" 28 #include "qemu/cutils.h" 29 #include "qemu/log.h" 30 31 static struct { 32 hwaddr io_base; 33 int irqn; 34 } pxa255_serial[] = { 35 { 0x40100000, PXA2XX_PIC_FFUART }, 36 { 0x40200000, PXA2XX_PIC_BTUART }, 37 { 0x40700000, PXA2XX_PIC_STUART }, 38 { 0x41600000, PXA25X_PIC_HWUART }, 39 { 0, 0 } 40 }, pxa270_serial[] = { 41 { 0x40100000, PXA2XX_PIC_FFUART }, 42 { 0x40200000, PXA2XX_PIC_BTUART }, 43 { 0x40700000, PXA2XX_PIC_STUART }, 44 { 0, 0 } 45 }; 46 47 typedef struct PXASSPDef { 48 hwaddr io_base; 49 int irqn; 50 } PXASSPDef; 51 52 #if 0 53 static PXASSPDef pxa250_ssp[] = { 54 { 0x41000000, PXA2XX_PIC_SSP }, 55 { 0, 0 } 56 }; 57 #endif 58 59 static PXASSPDef pxa255_ssp[] = { 60 { 0x41000000, PXA2XX_PIC_SSP }, 61 { 0x41400000, PXA25X_PIC_NSSP }, 62 { 0, 0 } 63 }; 64 65 #if 0 66 static PXASSPDef pxa26x_ssp[] = { 67 { 0x41000000, PXA2XX_PIC_SSP }, 68 { 0x41400000, PXA25X_PIC_NSSP }, 69 { 0x41500000, PXA26X_PIC_ASSP }, 70 { 0, 0 } 71 }; 72 #endif 73 74 static PXASSPDef pxa27x_ssp[] = { 75 { 0x41000000, PXA2XX_PIC_SSP }, 76 { 0x41700000, PXA27X_PIC_SSP2 }, 77 { 0x41900000, PXA2XX_PIC_SSP3 }, 78 { 0, 0 } 79 }; 80 81 #define PMCR 0x00 /* Power Manager Control register */ 82 #define PSSR 0x04 /* Power Manager Sleep Status register */ 83 #define PSPR 0x08 /* Power Manager Scratch-Pad register */ 84 #define PWER 0x0c /* Power Manager Wake-Up Enable register */ 85 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */ 86 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */ 87 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */ 88 #define PCFR 0x1c /* Power Manager General Configuration register */ 89 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */ 90 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */ 91 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */ 92 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */ 93 #define RCSR 0x30 /* Reset Controller Status register */ 94 #define PSLR 0x34 /* Power Manager Sleep Configuration register */ 95 #define PTSR 0x38 /* Power Manager Standby Configuration register */ 96 #define PVCR 0x40 /* Power Manager Voltage Change Control register */ 97 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */ 98 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */ 99 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */ 100 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */ 101 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */ 102 103 static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr, 104 unsigned size) 105 { 106 PXA2xxState *s = (PXA2xxState *) opaque; 107 108 switch (addr) { 109 case PMCR ... PCMD31: 110 if (addr & 3) 111 goto fail; 112 113 return s->pm_regs[addr >> 2]; 114 default: 115 fail: 116 qemu_log_mask(LOG_GUEST_ERROR, 117 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 118 __func__, addr); 119 break; 120 } 121 return 0; 122 } 123 124 static void pxa2xx_pm_write(void *opaque, hwaddr addr, 125 uint64_t value, unsigned size) 126 { 127 PXA2xxState *s = (PXA2xxState *) opaque; 128 129 switch (addr) { 130 case PMCR: 131 /* Clear the write-one-to-clear bits... */ 132 s->pm_regs[addr >> 2] &= ~(value & 0x2a); 133 /* ...and set the plain r/w bits */ 134 s->pm_regs[addr >> 2] &= ~0x15; 135 s->pm_regs[addr >> 2] |= value & 0x15; 136 break; 137 138 case PSSR: /* Read-clean registers */ 139 case RCSR: 140 case PKSR: 141 s->pm_regs[addr >> 2] &= ~value; 142 break; 143 144 default: /* Read-write registers */ 145 if (!(addr & 3)) { 146 s->pm_regs[addr >> 2] = value; 147 break; 148 } 149 qemu_log_mask(LOG_GUEST_ERROR, 150 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 151 __func__, addr); 152 break; 153 } 154 } 155 156 static const MemoryRegionOps pxa2xx_pm_ops = { 157 .read = pxa2xx_pm_read, 158 .write = pxa2xx_pm_write, 159 .endianness = DEVICE_NATIVE_ENDIAN, 160 }; 161 162 static const VMStateDescription vmstate_pxa2xx_pm = { 163 .name = "pxa2xx_pm", 164 .version_id = 0, 165 .minimum_version_id = 0, 166 .fields = (VMStateField[]) { 167 VMSTATE_UINT32_ARRAY(pm_regs, PXA2xxState, 0x40), 168 VMSTATE_END_OF_LIST() 169 } 170 }; 171 172 #define CCCR 0x00 /* Core Clock Configuration register */ 173 #define CKEN 0x04 /* Clock Enable register */ 174 #define OSCC 0x08 /* Oscillator Configuration register */ 175 #define CCSR 0x0c /* Core Clock Status register */ 176 177 static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr, 178 unsigned size) 179 { 180 PXA2xxState *s = (PXA2xxState *) opaque; 181 182 switch (addr) { 183 case CCCR: 184 case CKEN: 185 case OSCC: 186 return s->cm_regs[addr >> 2]; 187 188 case CCSR: 189 return s->cm_regs[CCCR >> 2] | (3 << 28); 190 191 default: 192 qemu_log_mask(LOG_GUEST_ERROR, 193 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 194 __func__, addr); 195 break; 196 } 197 return 0; 198 } 199 200 static void pxa2xx_cm_write(void *opaque, hwaddr addr, 201 uint64_t value, unsigned size) 202 { 203 PXA2xxState *s = (PXA2xxState *) opaque; 204 205 switch (addr) { 206 case CCCR: 207 case CKEN: 208 s->cm_regs[addr >> 2] = value; 209 break; 210 211 case OSCC: 212 s->cm_regs[addr >> 2] &= ~0x6c; 213 s->cm_regs[addr >> 2] |= value & 0x6e; 214 if ((value >> 1) & 1) /* OON */ 215 s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */ 216 break; 217 218 default: 219 qemu_log_mask(LOG_GUEST_ERROR, 220 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 221 __func__, addr); 222 break; 223 } 224 } 225 226 static const MemoryRegionOps pxa2xx_cm_ops = { 227 .read = pxa2xx_cm_read, 228 .write = pxa2xx_cm_write, 229 .endianness = DEVICE_NATIVE_ENDIAN, 230 }; 231 232 static const VMStateDescription vmstate_pxa2xx_cm = { 233 .name = "pxa2xx_cm", 234 .version_id = 0, 235 .minimum_version_id = 0, 236 .fields = (VMStateField[]) { 237 VMSTATE_UINT32_ARRAY(cm_regs, PXA2xxState, 4), 238 VMSTATE_UINT32(clkcfg, PXA2xxState), 239 VMSTATE_UINT32(pmnc, PXA2xxState), 240 VMSTATE_END_OF_LIST() 241 } 242 }; 243 244 static uint64_t pxa2xx_clkcfg_read(CPUARMState *env, const ARMCPRegInfo *ri) 245 { 246 PXA2xxState *s = (PXA2xxState *)ri->opaque; 247 return s->clkcfg; 248 } 249 250 static void pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri, 251 uint64_t value) 252 { 253 PXA2xxState *s = (PXA2xxState *)ri->opaque; 254 s->clkcfg = value & 0xf; 255 if (value & 2) { 256 printf("%s: CPU frequency change attempt\n", __func__); 257 } 258 } 259 260 static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri, 261 uint64_t value) 262 { 263 PXA2xxState *s = (PXA2xxState *)ri->opaque; 264 static const char *pwrmode[8] = { 265 "Normal", "Idle", "Deep-idle", "Standby", 266 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep", 267 }; 268 269 if (value & 8) { 270 printf("%s: CPU voltage change attempt\n", __func__); 271 } 272 switch (value & 7) { 273 case 0: 274 /* Do nothing */ 275 break; 276 277 case 1: 278 /* Idle */ 279 if (!(s->cm_regs[CCCR >> 2] & (1U << 31))) { /* CPDIS */ 280 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); 281 break; 282 } 283 /* Fall through. */ 284 285 case 2: 286 /* Deep-Idle */ 287 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); 288 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ 289 goto message; 290 291 case 3: 292 s->cpu->env.uncached_cpsr = ARM_CPU_MODE_SVC; 293 s->cpu->env.daif = PSTATE_A | PSTATE_F | PSTATE_I; 294 s->cpu->env.cp15.sctlr_ns = 0; 295 s->cpu->env.cp15.cpacr_el1 = 0; 296 s->cpu->env.cp15.ttbr0_el[1] = 0; 297 s->cpu->env.cp15.dacr_ns = 0; 298 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ 299 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ 300 301 /* 302 * The scratch-pad register is almost universally used 303 * for storing the return address on suspend. For the 304 * lack of a resuming bootloader, perform a jump 305 * directly to that address. 306 */ 307 memset(s->cpu->env.regs, 0, 4 * 15); 308 s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2]; 309 310 #if 0 311 buffer = 0xe59ff000; /* ldr pc, [pc, #0] */ 312 cpu_physical_memory_write(0, &buffer, 4); 313 buffer = s->pm_regs[PSPR >> 2]; 314 cpu_physical_memory_write(8, &buffer, 4); 315 #endif 316 317 /* Suspend */ 318 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); 319 320 goto message; 321 322 default: 323 message: 324 printf("%s: machine entered %s mode\n", __func__, 325 pwrmode[value & 7]); 326 } 327 } 328 329 static uint64_t pxa2xx_cppmnc_read(CPUARMState *env, const ARMCPRegInfo *ri) 330 { 331 PXA2xxState *s = (PXA2xxState *)ri->opaque; 332 return s->pmnc; 333 } 334 335 static void pxa2xx_cppmnc_write(CPUARMState *env, const ARMCPRegInfo *ri, 336 uint64_t value) 337 { 338 PXA2xxState *s = (PXA2xxState *)ri->opaque; 339 s->pmnc = value; 340 } 341 342 static uint64_t pxa2xx_cpccnt_read(CPUARMState *env, const ARMCPRegInfo *ri) 343 { 344 PXA2xxState *s = (PXA2xxState *)ri->opaque; 345 if (s->pmnc & 1) { 346 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 347 } else { 348 return 0; 349 } 350 } 351 352 static const ARMCPRegInfo pxa_cp_reginfo[] = { 353 /* cp14 crm==1: perf registers */ 354 { .name = "CPPMNC", .cp = 14, .crn = 0, .crm = 1, .opc1 = 0, .opc2 = 0, 355 .access = PL1_RW, .type = ARM_CP_IO, 356 .readfn = pxa2xx_cppmnc_read, .writefn = pxa2xx_cppmnc_write }, 357 { .name = "CPCCNT", .cp = 14, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, 358 .access = PL1_RW, .type = ARM_CP_IO, 359 .readfn = pxa2xx_cpccnt_read, .writefn = arm_cp_write_ignore }, 360 { .name = "CPINTEN", .cp = 14, .crn = 4, .crm = 1, .opc1 = 0, .opc2 = 0, 361 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 362 { .name = "CPFLAG", .cp = 14, .crn = 5, .crm = 1, .opc1 = 0, .opc2 = 0, 363 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 364 { .name = "CPEVTSEL", .cp = 14, .crn = 8, .crm = 1, .opc1 = 0, .opc2 = 0, 365 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 366 /* cp14 crm==2: performance count registers */ 367 { .name = "CPPMN0", .cp = 14, .crn = 0, .crm = 2, .opc1 = 0, .opc2 = 0, 368 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 369 { .name = "CPPMN1", .cp = 14, .crn = 1, .crm = 2, .opc1 = 0, .opc2 = 0, 370 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 371 { .name = "CPPMN2", .cp = 14, .crn = 2, .crm = 2, .opc1 = 0, .opc2 = 0, 372 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 373 { .name = "CPPMN3", .cp = 14, .crn = 2, .crm = 3, .opc1 = 0, .opc2 = 0, 374 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 375 /* cp14 crn==6: CLKCFG */ 376 { .name = "CLKCFG", .cp = 14, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, 377 .access = PL1_RW, .type = ARM_CP_IO, 378 .readfn = pxa2xx_clkcfg_read, .writefn = pxa2xx_clkcfg_write }, 379 /* cp14 crn==7: PWRMODE */ 380 { .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0, 381 .access = PL1_RW, .type = ARM_CP_IO, 382 .readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write }, 383 REGINFO_SENTINEL 384 }; 385 386 static void pxa2xx_setup_cp14(PXA2xxState *s) 387 { 388 define_arm_cp_regs_with_opaque(s->cpu, pxa_cp_reginfo, s); 389 } 390 391 #define MDCNFG 0x00 /* SDRAM Configuration register */ 392 #define MDREFR 0x04 /* SDRAM Refresh Control register */ 393 #define MSC0 0x08 /* Static Memory Control register 0 */ 394 #define MSC1 0x0c /* Static Memory Control register 1 */ 395 #define MSC2 0x10 /* Static Memory Control register 2 */ 396 #define MECR 0x14 /* Expansion Memory Bus Config register */ 397 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */ 398 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */ 399 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */ 400 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */ 401 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */ 402 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */ 403 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */ 404 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */ 405 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */ 406 #define ARB_CNTL 0x48 /* Arbiter Control register */ 407 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */ 408 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */ 409 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */ 410 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */ 411 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */ 412 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */ 413 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */ 414 415 static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr, 416 unsigned size) 417 { 418 PXA2xxState *s = (PXA2xxState *) opaque; 419 420 switch (addr) { 421 case MDCNFG ... SA1110: 422 if ((addr & 3) == 0) 423 return s->mm_regs[addr >> 2]; 424 /* fall through */ 425 default: 426 qemu_log_mask(LOG_GUEST_ERROR, 427 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 428 __func__, addr); 429 break; 430 } 431 return 0; 432 } 433 434 static void pxa2xx_mm_write(void *opaque, hwaddr addr, 435 uint64_t value, unsigned size) 436 { 437 PXA2xxState *s = (PXA2xxState *) opaque; 438 439 switch (addr) { 440 case MDCNFG ... SA1110: 441 if ((addr & 3) == 0) { 442 s->mm_regs[addr >> 2] = value; 443 break; 444 } 445 446 default: 447 qemu_log_mask(LOG_GUEST_ERROR, 448 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 449 __func__, addr); 450 break; 451 } 452 } 453 454 static const MemoryRegionOps pxa2xx_mm_ops = { 455 .read = pxa2xx_mm_read, 456 .write = pxa2xx_mm_write, 457 .endianness = DEVICE_NATIVE_ENDIAN, 458 }; 459 460 static const VMStateDescription vmstate_pxa2xx_mm = { 461 .name = "pxa2xx_mm", 462 .version_id = 0, 463 .minimum_version_id = 0, 464 .fields = (VMStateField[]) { 465 VMSTATE_UINT32_ARRAY(mm_regs, PXA2xxState, 0x1a), 466 VMSTATE_END_OF_LIST() 467 } 468 }; 469 470 #define TYPE_PXA2XX_SSP "pxa2xx-ssp" 471 #define PXA2XX_SSP(obj) \ 472 OBJECT_CHECK(PXA2xxSSPState, (obj), TYPE_PXA2XX_SSP) 473 474 /* Synchronous Serial Ports */ 475 typedef struct { 476 /*< private >*/ 477 SysBusDevice parent_obj; 478 /*< public >*/ 479 480 MemoryRegion iomem; 481 qemu_irq irq; 482 uint32_t enable; 483 SSIBus *bus; 484 485 uint32_t sscr[2]; 486 uint32_t sspsp; 487 uint32_t ssto; 488 uint32_t ssitr; 489 uint32_t sssr; 490 uint8_t sstsa; 491 uint8_t ssrsa; 492 uint8_t ssacd; 493 494 uint32_t rx_fifo[16]; 495 uint32_t rx_level; 496 uint32_t rx_start; 497 } PXA2xxSSPState; 498 499 static bool pxa2xx_ssp_vmstate_validate(void *opaque, int version_id) 500 { 501 PXA2xxSSPState *s = opaque; 502 503 return s->rx_start < sizeof(s->rx_fifo); 504 } 505 506 static const VMStateDescription vmstate_pxa2xx_ssp = { 507 .name = "pxa2xx-ssp", 508 .version_id = 1, 509 .minimum_version_id = 1, 510 .fields = (VMStateField[]) { 511 VMSTATE_UINT32(enable, PXA2xxSSPState), 512 VMSTATE_UINT32_ARRAY(sscr, PXA2xxSSPState, 2), 513 VMSTATE_UINT32(sspsp, PXA2xxSSPState), 514 VMSTATE_UINT32(ssto, PXA2xxSSPState), 515 VMSTATE_UINT32(ssitr, PXA2xxSSPState), 516 VMSTATE_UINT32(sssr, PXA2xxSSPState), 517 VMSTATE_UINT8(sstsa, PXA2xxSSPState), 518 VMSTATE_UINT8(ssrsa, PXA2xxSSPState), 519 VMSTATE_UINT8(ssacd, PXA2xxSSPState), 520 VMSTATE_UINT32(rx_level, PXA2xxSSPState), 521 VMSTATE_UINT32(rx_start, PXA2xxSSPState), 522 VMSTATE_VALIDATE("fifo is 16 bytes", pxa2xx_ssp_vmstate_validate), 523 VMSTATE_UINT32_ARRAY(rx_fifo, PXA2xxSSPState, 16), 524 VMSTATE_END_OF_LIST() 525 } 526 }; 527 528 #define SSCR0 0x00 /* SSP Control register 0 */ 529 #define SSCR1 0x04 /* SSP Control register 1 */ 530 #define SSSR 0x08 /* SSP Status register */ 531 #define SSITR 0x0c /* SSP Interrupt Test register */ 532 #define SSDR 0x10 /* SSP Data register */ 533 #define SSTO 0x28 /* SSP Time-Out register */ 534 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */ 535 #define SSTSA 0x30 /* SSP TX Time Slot Active register */ 536 #define SSRSA 0x34 /* SSP RX Time Slot Active register */ 537 #define SSTSS 0x38 /* SSP Time Slot Status register */ 538 #define SSACD 0x3c /* SSP Audio Clock Divider register */ 539 540 /* Bitfields for above registers */ 541 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00) 542 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10) 543 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20) 544 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30) 545 #define SSCR0_SSE (1 << 7) 546 #define SSCR0_RIM (1 << 22) 547 #define SSCR0_TIM (1 << 23) 548 #define SSCR0_MOD (1U << 31) 549 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1) 550 #define SSCR1_RIE (1 << 0) 551 #define SSCR1_TIE (1 << 1) 552 #define SSCR1_LBM (1 << 2) 553 #define SSCR1_MWDS (1 << 5) 554 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1) 555 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1) 556 #define SSCR1_EFWR (1 << 14) 557 #define SSCR1_PINTE (1 << 18) 558 #define SSCR1_TINTE (1 << 19) 559 #define SSCR1_RSRE (1 << 20) 560 #define SSCR1_TSRE (1 << 21) 561 #define SSCR1_EBCEI (1 << 29) 562 #define SSITR_INT (7 << 5) 563 #define SSSR_TNF (1 << 2) 564 #define SSSR_RNE (1 << 3) 565 #define SSSR_TFS (1 << 5) 566 #define SSSR_RFS (1 << 6) 567 #define SSSR_ROR (1 << 7) 568 #define SSSR_PINT (1 << 18) 569 #define SSSR_TINT (1 << 19) 570 #define SSSR_EOC (1 << 20) 571 #define SSSR_TUR (1 << 21) 572 #define SSSR_BCE (1 << 23) 573 #define SSSR_RW 0x00bc0080 574 575 static void pxa2xx_ssp_int_update(PXA2xxSSPState *s) 576 { 577 int level = 0; 578 579 level |= s->ssitr & SSITR_INT; 580 level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI); 581 level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM); 582 level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT)); 583 level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE); 584 level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE); 585 level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM); 586 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE); 587 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE); 588 qemu_set_irq(s->irq, !!level); 589 } 590 591 static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s) 592 { 593 s->sssr &= ~(0xf << 12); /* Clear RFL */ 594 s->sssr &= ~(0xf << 8); /* Clear TFL */ 595 s->sssr &= ~SSSR_TFS; 596 s->sssr &= ~SSSR_TNF; 597 if (s->enable) { 598 s->sssr |= ((s->rx_level - 1) & 0xf) << 12; 599 if (s->rx_level >= SSCR1_RFT(s->sscr[1])) 600 s->sssr |= SSSR_RFS; 601 else 602 s->sssr &= ~SSSR_RFS; 603 if (s->rx_level) 604 s->sssr |= SSSR_RNE; 605 else 606 s->sssr &= ~SSSR_RNE; 607 /* TX FIFO is never filled, so it is always in underrun 608 condition if SSP is enabled */ 609 s->sssr |= SSSR_TFS; 610 s->sssr |= SSSR_TNF; 611 } 612 613 pxa2xx_ssp_int_update(s); 614 } 615 616 static uint64_t pxa2xx_ssp_read(void *opaque, hwaddr addr, 617 unsigned size) 618 { 619 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; 620 uint32_t retval; 621 622 switch (addr) { 623 case SSCR0: 624 return s->sscr[0]; 625 case SSCR1: 626 return s->sscr[1]; 627 case SSPSP: 628 return s->sspsp; 629 case SSTO: 630 return s->ssto; 631 case SSITR: 632 return s->ssitr; 633 case SSSR: 634 return s->sssr | s->ssitr; 635 case SSDR: 636 if (!s->enable) 637 return 0xffffffff; 638 if (s->rx_level < 1) { 639 printf("%s: SSP Rx Underrun\n", __func__); 640 return 0xffffffff; 641 } 642 s->rx_level --; 643 retval = s->rx_fifo[s->rx_start ++]; 644 s->rx_start &= 0xf; 645 pxa2xx_ssp_fifo_update(s); 646 return retval; 647 case SSTSA: 648 return s->sstsa; 649 case SSRSA: 650 return s->ssrsa; 651 case SSTSS: 652 return 0; 653 case SSACD: 654 return s->ssacd; 655 default: 656 qemu_log_mask(LOG_GUEST_ERROR, 657 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 658 __func__, addr); 659 break; 660 } 661 return 0; 662 } 663 664 static void pxa2xx_ssp_write(void *opaque, hwaddr addr, 665 uint64_t value64, unsigned size) 666 { 667 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; 668 uint32_t value = value64; 669 670 switch (addr) { 671 case SSCR0: 672 s->sscr[0] = value & 0xc7ffffff; 673 s->enable = value & SSCR0_SSE; 674 if (value & SSCR0_MOD) 675 printf("%s: Attempt to use network mode\n", __func__); 676 if (s->enable && SSCR0_DSS(value) < 4) 677 printf("%s: Wrong data size: %i bits\n", __func__, 678 SSCR0_DSS(value)); 679 if (!(value & SSCR0_SSE)) { 680 s->sssr = 0; 681 s->ssitr = 0; 682 s->rx_level = 0; 683 } 684 pxa2xx_ssp_fifo_update(s); 685 break; 686 687 case SSCR1: 688 s->sscr[1] = value; 689 if (value & (SSCR1_LBM | SSCR1_EFWR)) 690 printf("%s: Attempt to use SSP test mode\n", __func__); 691 pxa2xx_ssp_fifo_update(s); 692 break; 693 694 case SSPSP: 695 s->sspsp = value; 696 break; 697 698 case SSTO: 699 s->ssto = value; 700 break; 701 702 case SSITR: 703 s->ssitr = value & SSITR_INT; 704 pxa2xx_ssp_int_update(s); 705 break; 706 707 case SSSR: 708 s->sssr &= ~(value & SSSR_RW); 709 pxa2xx_ssp_int_update(s); 710 break; 711 712 case SSDR: 713 if (SSCR0_UWIRE(s->sscr[0])) { 714 if (s->sscr[1] & SSCR1_MWDS) 715 value &= 0xffff; 716 else 717 value &= 0xff; 718 } else 719 /* Note how 32bits overflow does no harm here */ 720 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1; 721 722 /* Data goes from here to the Tx FIFO and is shifted out from 723 * there directly to the slave, no need to buffer it. 724 */ 725 if (s->enable) { 726 uint32_t readval; 727 readval = ssi_transfer(s->bus, value); 728 if (s->rx_level < 0x10) { 729 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval; 730 } else { 731 s->sssr |= SSSR_ROR; 732 } 733 } 734 pxa2xx_ssp_fifo_update(s); 735 break; 736 737 case SSTSA: 738 s->sstsa = value; 739 break; 740 741 case SSRSA: 742 s->ssrsa = value; 743 break; 744 745 case SSACD: 746 s->ssacd = value; 747 break; 748 749 default: 750 qemu_log_mask(LOG_GUEST_ERROR, 751 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 752 __func__, addr); 753 break; 754 } 755 } 756 757 static const MemoryRegionOps pxa2xx_ssp_ops = { 758 .read = pxa2xx_ssp_read, 759 .write = pxa2xx_ssp_write, 760 .endianness = DEVICE_NATIVE_ENDIAN, 761 }; 762 763 static void pxa2xx_ssp_reset(DeviceState *d) 764 { 765 PXA2xxSSPState *s = PXA2XX_SSP(d); 766 767 s->enable = 0; 768 s->sscr[0] = s->sscr[1] = 0; 769 s->sspsp = 0; 770 s->ssto = 0; 771 s->ssitr = 0; 772 s->sssr = 0; 773 s->sstsa = 0; 774 s->ssrsa = 0; 775 s->ssacd = 0; 776 s->rx_start = s->rx_level = 0; 777 } 778 779 static void pxa2xx_ssp_init(Object *obj) 780 { 781 DeviceState *dev = DEVICE(obj); 782 PXA2xxSSPState *s = PXA2XX_SSP(obj); 783 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 784 sysbus_init_irq(sbd, &s->irq); 785 786 memory_region_init_io(&s->iomem, obj, &pxa2xx_ssp_ops, s, 787 "pxa2xx-ssp", 0x1000); 788 sysbus_init_mmio(sbd, &s->iomem); 789 790 s->bus = ssi_create_bus(dev, "ssi"); 791 } 792 793 /* Real-Time Clock */ 794 #define RCNR 0x00 /* RTC Counter register */ 795 #define RTAR 0x04 /* RTC Alarm register */ 796 #define RTSR 0x08 /* RTC Status register */ 797 #define RTTR 0x0c /* RTC Timer Trim register */ 798 #define RDCR 0x10 /* RTC Day Counter register */ 799 #define RYCR 0x14 /* RTC Year Counter register */ 800 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */ 801 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */ 802 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */ 803 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */ 804 #define SWCR 0x28 /* RTC Stopwatch Counter register */ 805 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */ 806 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */ 807 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */ 808 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */ 809 810 #define TYPE_PXA2XX_RTC "pxa2xx_rtc" 811 #define PXA2XX_RTC(obj) \ 812 OBJECT_CHECK(PXA2xxRTCState, (obj), TYPE_PXA2XX_RTC) 813 814 typedef struct { 815 /*< private >*/ 816 SysBusDevice parent_obj; 817 /*< public >*/ 818 819 MemoryRegion iomem; 820 uint32_t rttr; 821 uint32_t rtsr; 822 uint32_t rtar; 823 uint32_t rdar1; 824 uint32_t rdar2; 825 uint32_t ryar1; 826 uint32_t ryar2; 827 uint32_t swar1; 828 uint32_t swar2; 829 uint32_t piar; 830 uint32_t last_rcnr; 831 uint32_t last_rdcr; 832 uint32_t last_rycr; 833 uint32_t last_swcr; 834 uint32_t last_rtcpicr; 835 int64_t last_hz; 836 int64_t last_sw; 837 int64_t last_pi; 838 QEMUTimer *rtc_hz; 839 QEMUTimer *rtc_rdal1; 840 QEMUTimer *rtc_rdal2; 841 QEMUTimer *rtc_swal1; 842 QEMUTimer *rtc_swal2; 843 QEMUTimer *rtc_pi; 844 qemu_irq rtc_irq; 845 } PXA2xxRTCState; 846 847 static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s) 848 { 849 qemu_set_irq(s->rtc_irq, !!(s->rtsr & 0x2553)); 850 } 851 852 static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s) 853 { 854 int64_t rt = qemu_clock_get_ms(rtc_clock); 855 s->last_rcnr += ((rt - s->last_hz) << 15) / 856 (1000 * ((s->rttr & 0xffff) + 1)); 857 s->last_rdcr += ((rt - s->last_hz) << 15) / 858 (1000 * ((s->rttr & 0xffff) + 1)); 859 s->last_hz = rt; 860 } 861 862 static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s) 863 { 864 int64_t rt = qemu_clock_get_ms(rtc_clock); 865 if (s->rtsr & (1 << 12)) 866 s->last_swcr += (rt - s->last_sw) / 10; 867 s->last_sw = rt; 868 } 869 870 static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s) 871 { 872 int64_t rt = qemu_clock_get_ms(rtc_clock); 873 if (s->rtsr & (1 << 15)) 874 s->last_swcr += rt - s->last_pi; 875 s->last_pi = rt; 876 } 877 878 static inline void pxa2xx_rtc_alarm_update(PXA2xxRTCState *s, 879 uint32_t rtsr) 880 { 881 if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0))) 882 timer_mod(s->rtc_hz, s->last_hz + 883 (((s->rtar - s->last_rcnr) * 1000 * 884 ((s->rttr & 0xffff) + 1)) >> 15)); 885 else 886 timer_del(s->rtc_hz); 887 888 if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4))) 889 timer_mod(s->rtc_rdal1, s->last_hz + 890 (((s->rdar1 - s->last_rdcr) * 1000 * 891 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */ 892 else 893 timer_del(s->rtc_rdal1); 894 895 if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6))) 896 timer_mod(s->rtc_rdal2, s->last_hz + 897 (((s->rdar2 - s->last_rdcr) * 1000 * 898 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */ 899 else 900 timer_del(s->rtc_rdal2); 901 902 if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8))) 903 timer_mod(s->rtc_swal1, s->last_sw + 904 (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */ 905 else 906 timer_del(s->rtc_swal1); 907 908 if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10))) 909 timer_mod(s->rtc_swal2, s->last_sw + 910 (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */ 911 else 912 timer_del(s->rtc_swal2); 913 914 if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13))) 915 timer_mod(s->rtc_pi, s->last_pi + 916 (s->piar & 0xffff) - s->last_rtcpicr); 917 else 918 timer_del(s->rtc_pi); 919 } 920 921 static inline void pxa2xx_rtc_hz_tick(void *opaque) 922 { 923 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 924 s->rtsr |= (1 << 0); 925 pxa2xx_rtc_alarm_update(s, s->rtsr); 926 pxa2xx_rtc_int_update(s); 927 } 928 929 static inline void pxa2xx_rtc_rdal1_tick(void *opaque) 930 { 931 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 932 s->rtsr |= (1 << 4); 933 pxa2xx_rtc_alarm_update(s, s->rtsr); 934 pxa2xx_rtc_int_update(s); 935 } 936 937 static inline void pxa2xx_rtc_rdal2_tick(void *opaque) 938 { 939 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 940 s->rtsr |= (1 << 6); 941 pxa2xx_rtc_alarm_update(s, s->rtsr); 942 pxa2xx_rtc_int_update(s); 943 } 944 945 static inline void pxa2xx_rtc_swal1_tick(void *opaque) 946 { 947 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 948 s->rtsr |= (1 << 8); 949 pxa2xx_rtc_alarm_update(s, s->rtsr); 950 pxa2xx_rtc_int_update(s); 951 } 952 953 static inline void pxa2xx_rtc_swal2_tick(void *opaque) 954 { 955 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 956 s->rtsr |= (1 << 10); 957 pxa2xx_rtc_alarm_update(s, s->rtsr); 958 pxa2xx_rtc_int_update(s); 959 } 960 961 static inline void pxa2xx_rtc_pi_tick(void *opaque) 962 { 963 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 964 s->rtsr |= (1 << 13); 965 pxa2xx_rtc_piupdate(s); 966 s->last_rtcpicr = 0; 967 pxa2xx_rtc_alarm_update(s, s->rtsr); 968 pxa2xx_rtc_int_update(s); 969 } 970 971 static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr, 972 unsigned size) 973 { 974 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 975 976 switch (addr) { 977 case RTTR: 978 return s->rttr; 979 case RTSR: 980 return s->rtsr; 981 case RTAR: 982 return s->rtar; 983 case RDAR1: 984 return s->rdar1; 985 case RDAR2: 986 return s->rdar2; 987 case RYAR1: 988 return s->ryar1; 989 case RYAR2: 990 return s->ryar2; 991 case SWAR1: 992 return s->swar1; 993 case SWAR2: 994 return s->swar2; 995 case PIAR: 996 return s->piar; 997 case RCNR: 998 return s->last_rcnr + 999 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / 1000 (1000 * ((s->rttr & 0xffff) + 1)); 1001 case RDCR: 1002 return s->last_rdcr + 1003 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / 1004 (1000 * ((s->rttr & 0xffff) + 1)); 1005 case RYCR: 1006 return s->last_rycr; 1007 case SWCR: 1008 if (s->rtsr & (1 << 12)) 1009 return s->last_swcr + 1010 (qemu_clock_get_ms(rtc_clock) - s->last_sw) / 10; 1011 else 1012 return s->last_swcr; 1013 default: 1014 qemu_log_mask(LOG_GUEST_ERROR, 1015 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 1016 __func__, addr); 1017 break; 1018 } 1019 return 0; 1020 } 1021 1022 static void pxa2xx_rtc_write(void *opaque, hwaddr addr, 1023 uint64_t value64, unsigned size) 1024 { 1025 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 1026 uint32_t value = value64; 1027 1028 switch (addr) { 1029 case RTTR: 1030 if (!(s->rttr & (1U << 31))) { 1031 pxa2xx_rtc_hzupdate(s); 1032 s->rttr = value; 1033 pxa2xx_rtc_alarm_update(s, s->rtsr); 1034 } 1035 break; 1036 1037 case RTSR: 1038 if ((s->rtsr ^ value) & (1 << 15)) 1039 pxa2xx_rtc_piupdate(s); 1040 1041 if ((s->rtsr ^ value) & (1 << 12)) 1042 pxa2xx_rtc_swupdate(s); 1043 1044 if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac)) 1045 pxa2xx_rtc_alarm_update(s, value); 1046 1047 s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac)); 1048 pxa2xx_rtc_int_update(s); 1049 break; 1050 1051 case RTAR: 1052 s->rtar = value; 1053 pxa2xx_rtc_alarm_update(s, s->rtsr); 1054 break; 1055 1056 case RDAR1: 1057 s->rdar1 = value; 1058 pxa2xx_rtc_alarm_update(s, s->rtsr); 1059 break; 1060 1061 case RDAR2: 1062 s->rdar2 = value; 1063 pxa2xx_rtc_alarm_update(s, s->rtsr); 1064 break; 1065 1066 case RYAR1: 1067 s->ryar1 = value; 1068 pxa2xx_rtc_alarm_update(s, s->rtsr); 1069 break; 1070 1071 case RYAR2: 1072 s->ryar2 = value; 1073 pxa2xx_rtc_alarm_update(s, s->rtsr); 1074 break; 1075 1076 case SWAR1: 1077 pxa2xx_rtc_swupdate(s); 1078 s->swar1 = value; 1079 s->last_swcr = 0; 1080 pxa2xx_rtc_alarm_update(s, s->rtsr); 1081 break; 1082 1083 case SWAR2: 1084 s->swar2 = value; 1085 pxa2xx_rtc_alarm_update(s, s->rtsr); 1086 break; 1087 1088 case PIAR: 1089 s->piar = value; 1090 pxa2xx_rtc_alarm_update(s, s->rtsr); 1091 break; 1092 1093 case RCNR: 1094 pxa2xx_rtc_hzupdate(s); 1095 s->last_rcnr = value; 1096 pxa2xx_rtc_alarm_update(s, s->rtsr); 1097 break; 1098 1099 case RDCR: 1100 pxa2xx_rtc_hzupdate(s); 1101 s->last_rdcr = value; 1102 pxa2xx_rtc_alarm_update(s, s->rtsr); 1103 break; 1104 1105 case RYCR: 1106 s->last_rycr = value; 1107 break; 1108 1109 case SWCR: 1110 pxa2xx_rtc_swupdate(s); 1111 s->last_swcr = value; 1112 pxa2xx_rtc_alarm_update(s, s->rtsr); 1113 break; 1114 1115 case RTCPICR: 1116 pxa2xx_rtc_piupdate(s); 1117 s->last_rtcpicr = value & 0xffff; 1118 pxa2xx_rtc_alarm_update(s, s->rtsr); 1119 break; 1120 1121 default: 1122 qemu_log_mask(LOG_GUEST_ERROR, 1123 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 1124 __func__, addr); 1125 } 1126 } 1127 1128 static const MemoryRegionOps pxa2xx_rtc_ops = { 1129 .read = pxa2xx_rtc_read, 1130 .write = pxa2xx_rtc_write, 1131 .endianness = DEVICE_NATIVE_ENDIAN, 1132 }; 1133 1134 static void pxa2xx_rtc_init(Object *obj) 1135 { 1136 PXA2xxRTCState *s = PXA2XX_RTC(obj); 1137 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 1138 struct tm tm; 1139 int wom; 1140 1141 s->rttr = 0x7fff; 1142 s->rtsr = 0; 1143 1144 qemu_get_timedate(&tm, 0); 1145 wom = ((tm.tm_mday - 1) / 7) + 1; 1146 1147 s->last_rcnr = (uint32_t) mktimegm(&tm); 1148 s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) | 1149 (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec; 1150 s->last_rycr = ((tm.tm_year + 1900) << 9) | 1151 ((tm.tm_mon + 1) << 5) | tm.tm_mday; 1152 s->last_swcr = (tm.tm_hour << 19) | 1153 (tm.tm_min << 13) | (tm.tm_sec << 7); 1154 s->last_rtcpicr = 0; 1155 s->last_hz = s->last_sw = s->last_pi = qemu_clock_get_ms(rtc_clock); 1156 1157 sysbus_init_irq(dev, &s->rtc_irq); 1158 1159 memory_region_init_io(&s->iomem, obj, &pxa2xx_rtc_ops, s, 1160 "pxa2xx-rtc", 0x10000); 1161 sysbus_init_mmio(dev, &s->iomem); 1162 } 1163 1164 static void pxa2xx_rtc_realize(DeviceState *dev, Error **errp) 1165 { 1166 PXA2xxRTCState *s = PXA2XX_RTC(dev); 1167 s->rtc_hz = timer_new_ms(rtc_clock, pxa2xx_rtc_hz_tick, s); 1168 s->rtc_rdal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal1_tick, s); 1169 s->rtc_rdal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal2_tick, s); 1170 s->rtc_swal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal1_tick, s); 1171 s->rtc_swal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal2_tick, s); 1172 s->rtc_pi = timer_new_ms(rtc_clock, pxa2xx_rtc_pi_tick, s); 1173 } 1174 1175 static int pxa2xx_rtc_pre_save(void *opaque) 1176 { 1177 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 1178 1179 pxa2xx_rtc_hzupdate(s); 1180 pxa2xx_rtc_piupdate(s); 1181 pxa2xx_rtc_swupdate(s); 1182 1183 return 0; 1184 } 1185 1186 static int pxa2xx_rtc_post_load(void *opaque, int version_id) 1187 { 1188 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 1189 1190 pxa2xx_rtc_alarm_update(s, s->rtsr); 1191 1192 return 0; 1193 } 1194 1195 static const VMStateDescription vmstate_pxa2xx_rtc_regs = { 1196 .name = "pxa2xx_rtc", 1197 .version_id = 0, 1198 .minimum_version_id = 0, 1199 .pre_save = pxa2xx_rtc_pre_save, 1200 .post_load = pxa2xx_rtc_post_load, 1201 .fields = (VMStateField[]) { 1202 VMSTATE_UINT32(rttr, PXA2xxRTCState), 1203 VMSTATE_UINT32(rtsr, PXA2xxRTCState), 1204 VMSTATE_UINT32(rtar, PXA2xxRTCState), 1205 VMSTATE_UINT32(rdar1, PXA2xxRTCState), 1206 VMSTATE_UINT32(rdar2, PXA2xxRTCState), 1207 VMSTATE_UINT32(ryar1, PXA2xxRTCState), 1208 VMSTATE_UINT32(ryar2, PXA2xxRTCState), 1209 VMSTATE_UINT32(swar1, PXA2xxRTCState), 1210 VMSTATE_UINT32(swar2, PXA2xxRTCState), 1211 VMSTATE_UINT32(piar, PXA2xxRTCState), 1212 VMSTATE_UINT32(last_rcnr, PXA2xxRTCState), 1213 VMSTATE_UINT32(last_rdcr, PXA2xxRTCState), 1214 VMSTATE_UINT32(last_rycr, PXA2xxRTCState), 1215 VMSTATE_UINT32(last_swcr, PXA2xxRTCState), 1216 VMSTATE_UINT32(last_rtcpicr, PXA2xxRTCState), 1217 VMSTATE_INT64(last_hz, PXA2xxRTCState), 1218 VMSTATE_INT64(last_sw, PXA2xxRTCState), 1219 VMSTATE_INT64(last_pi, PXA2xxRTCState), 1220 VMSTATE_END_OF_LIST(), 1221 }, 1222 }; 1223 1224 static void pxa2xx_rtc_sysbus_class_init(ObjectClass *klass, void *data) 1225 { 1226 DeviceClass *dc = DEVICE_CLASS(klass); 1227 1228 dc->desc = "PXA2xx RTC Controller"; 1229 dc->vmsd = &vmstate_pxa2xx_rtc_regs; 1230 dc->realize = pxa2xx_rtc_realize; 1231 } 1232 1233 static const TypeInfo pxa2xx_rtc_sysbus_info = { 1234 .name = TYPE_PXA2XX_RTC, 1235 .parent = TYPE_SYS_BUS_DEVICE, 1236 .instance_size = sizeof(PXA2xxRTCState), 1237 .instance_init = pxa2xx_rtc_init, 1238 .class_init = pxa2xx_rtc_sysbus_class_init, 1239 }; 1240 1241 /* I2C Interface */ 1242 1243 #define TYPE_PXA2XX_I2C_SLAVE "pxa2xx-i2c-slave" 1244 #define PXA2XX_I2C_SLAVE(obj) \ 1245 OBJECT_CHECK(PXA2xxI2CSlaveState, (obj), TYPE_PXA2XX_I2C_SLAVE) 1246 1247 typedef struct PXA2xxI2CSlaveState { 1248 I2CSlave parent_obj; 1249 1250 PXA2xxI2CState *host; 1251 } PXA2xxI2CSlaveState; 1252 1253 #define TYPE_PXA2XX_I2C "pxa2xx_i2c" 1254 #define PXA2XX_I2C(obj) \ 1255 OBJECT_CHECK(PXA2xxI2CState, (obj), TYPE_PXA2XX_I2C) 1256 1257 struct PXA2xxI2CState { 1258 /*< private >*/ 1259 SysBusDevice parent_obj; 1260 /*< public >*/ 1261 1262 MemoryRegion iomem; 1263 PXA2xxI2CSlaveState *slave; 1264 I2CBus *bus; 1265 qemu_irq irq; 1266 uint32_t offset; 1267 uint32_t region_size; 1268 1269 uint16_t control; 1270 uint16_t status; 1271 uint8_t ibmr; 1272 uint8_t data; 1273 }; 1274 1275 #define IBMR 0x80 /* I2C Bus Monitor register */ 1276 #define IDBR 0x88 /* I2C Data Buffer register */ 1277 #define ICR 0x90 /* I2C Control register */ 1278 #define ISR 0x98 /* I2C Status register */ 1279 #define ISAR 0xa0 /* I2C Slave Address register */ 1280 1281 static void pxa2xx_i2c_update(PXA2xxI2CState *s) 1282 { 1283 uint16_t level = 0; 1284 level |= s->status & s->control & (1 << 10); /* BED */ 1285 level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */ 1286 level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */ 1287 level |= s->status & (1 << 9); /* SAD */ 1288 qemu_set_irq(s->irq, !!level); 1289 } 1290 1291 /* These are only stubs now. */ 1292 static int pxa2xx_i2c_event(I2CSlave *i2c, enum i2c_event event) 1293 { 1294 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c); 1295 PXA2xxI2CState *s = slave->host; 1296 1297 switch (event) { 1298 case I2C_START_SEND: 1299 s->status |= (1 << 9); /* set SAD */ 1300 s->status &= ~(1 << 0); /* clear RWM */ 1301 break; 1302 case I2C_START_RECV: 1303 s->status |= (1 << 9); /* set SAD */ 1304 s->status |= 1 << 0; /* set RWM */ 1305 break; 1306 case I2C_FINISH: 1307 s->status |= (1 << 4); /* set SSD */ 1308 break; 1309 case I2C_NACK: 1310 s->status |= 1 << 1; /* set ACKNAK */ 1311 break; 1312 } 1313 pxa2xx_i2c_update(s); 1314 1315 return 0; 1316 } 1317 1318 static uint8_t pxa2xx_i2c_rx(I2CSlave *i2c) 1319 { 1320 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c); 1321 PXA2xxI2CState *s = slave->host; 1322 1323 if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) { 1324 return 0; 1325 } 1326 1327 if (s->status & (1 << 0)) { /* RWM */ 1328 s->status |= 1 << 6; /* set ITE */ 1329 } 1330 pxa2xx_i2c_update(s); 1331 1332 return s->data; 1333 } 1334 1335 static int pxa2xx_i2c_tx(I2CSlave *i2c, uint8_t data) 1336 { 1337 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c); 1338 PXA2xxI2CState *s = slave->host; 1339 1340 if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) { 1341 return 1; 1342 } 1343 1344 if (!(s->status & (1 << 0))) { /* RWM */ 1345 s->status |= 1 << 7; /* set IRF */ 1346 s->data = data; 1347 } 1348 pxa2xx_i2c_update(s); 1349 1350 return 1; 1351 } 1352 1353 static uint64_t pxa2xx_i2c_read(void *opaque, hwaddr addr, 1354 unsigned size) 1355 { 1356 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; 1357 I2CSlave *slave; 1358 1359 addr -= s->offset; 1360 switch (addr) { 1361 case ICR: 1362 return s->control; 1363 case ISR: 1364 return s->status | (i2c_bus_busy(s->bus) << 2); 1365 case ISAR: 1366 slave = I2C_SLAVE(s->slave); 1367 return slave->address; 1368 case IDBR: 1369 return s->data; 1370 case IBMR: 1371 if (s->status & (1 << 2)) 1372 s->ibmr ^= 3; /* Fake SCL and SDA pin changes */ 1373 else 1374 s->ibmr = 0; 1375 return s->ibmr; 1376 default: 1377 qemu_log_mask(LOG_GUEST_ERROR, 1378 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 1379 __func__, addr); 1380 break; 1381 } 1382 return 0; 1383 } 1384 1385 static void pxa2xx_i2c_write(void *opaque, hwaddr addr, 1386 uint64_t value64, unsigned size) 1387 { 1388 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; 1389 uint32_t value = value64; 1390 int ack; 1391 1392 addr -= s->offset; 1393 switch (addr) { 1394 case ICR: 1395 s->control = value & 0xfff7; 1396 if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */ 1397 /* TODO: slave mode */ 1398 if (value & (1 << 0)) { /* START condition */ 1399 if (s->data & 1) 1400 s->status |= 1 << 0; /* set RWM */ 1401 else 1402 s->status &= ~(1 << 0); /* clear RWM */ 1403 ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1); 1404 } else { 1405 if (s->status & (1 << 0)) { /* RWM */ 1406 s->data = i2c_recv(s->bus); 1407 if (value & (1 << 2)) /* ACKNAK */ 1408 i2c_nack(s->bus); 1409 ack = 1; 1410 } else 1411 ack = !i2c_send(s->bus, s->data); 1412 } 1413 1414 if (value & (1 << 1)) /* STOP condition */ 1415 i2c_end_transfer(s->bus); 1416 1417 if (ack) { 1418 if (value & (1 << 0)) /* START condition */ 1419 s->status |= 1 << 6; /* set ITE */ 1420 else 1421 if (s->status & (1 << 0)) /* RWM */ 1422 s->status |= 1 << 7; /* set IRF */ 1423 else 1424 s->status |= 1 << 6; /* set ITE */ 1425 s->status &= ~(1 << 1); /* clear ACKNAK */ 1426 } else { 1427 s->status |= 1 << 6; /* set ITE */ 1428 s->status |= 1 << 10; /* set BED */ 1429 s->status |= 1 << 1; /* set ACKNAK */ 1430 } 1431 } 1432 if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */ 1433 if (value & (1 << 4)) /* MA */ 1434 i2c_end_transfer(s->bus); 1435 pxa2xx_i2c_update(s); 1436 break; 1437 1438 case ISR: 1439 s->status &= ~(value & 0x07f0); 1440 pxa2xx_i2c_update(s); 1441 break; 1442 1443 case ISAR: 1444 i2c_set_slave_address(I2C_SLAVE(s->slave), value & 0x7f); 1445 break; 1446 1447 case IDBR: 1448 s->data = value & 0xff; 1449 break; 1450 1451 default: 1452 qemu_log_mask(LOG_GUEST_ERROR, 1453 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 1454 __func__, addr); 1455 } 1456 } 1457 1458 static const MemoryRegionOps pxa2xx_i2c_ops = { 1459 .read = pxa2xx_i2c_read, 1460 .write = pxa2xx_i2c_write, 1461 .endianness = DEVICE_NATIVE_ENDIAN, 1462 }; 1463 1464 static const VMStateDescription vmstate_pxa2xx_i2c_slave = { 1465 .name = "pxa2xx_i2c_slave", 1466 .version_id = 1, 1467 .minimum_version_id = 1, 1468 .fields = (VMStateField[]) { 1469 VMSTATE_I2C_SLAVE(parent_obj, PXA2xxI2CSlaveState), 1470 VMSTATE_END_OF_LIST() 1471 } 1472 }; 1473 1474 static const VMStateDescription vmstate_pxa2xx_i2c = { 1475 .name = "pxa2xx_i2c", 1476 .version_id = 1, 1477 .minimum_version_id = 1, 1478 .fields = (VMStateField[]) { 1479 VMSTATE_UINT16(control, PXA2xxI2CState), 1480 VMSTATE_UINT16(status, PXA2xxI2CState), 1481 VMSTATE_UINT8(ibmr, PXA2xxI2CState), 1482 VMSTATE_UINT8(data, PXA2xxI2CState), 1483 VMSTATE_STRUCT_POINTER(slave, PXA2xxI2CState, 1484 vmstate_pxa2xx_i2c_slave, PXA2xxI2CSlaveState), 1485 VMSTATE_END_OF_LIST() 1486 } 1487 }; 1488 1489 static void pxa2xx_i2c_slave_class_init(ObjectClass *klass, void *data) 1490 { 1491 I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); 1492 1493 k->event = pxa2xx_i2c_event; 1494 k->recv = pxa2xx_i2c_rx; 1495 k->send = pxa2xx_i2c_tx; 1496 } 1497 1498 static const TypeInfo pxa2xx_i2c_slave_info = { 1499 .name = TYPE_PXA2XX_I2C_SLAVE, 1500 .parent = TYPE_I2C_SLAVE, 1501 .instance_size = sizeof(PXA2xxI2CSlaveState), 1502 .class_init = pxa2xx_i2c_slave_class_init, 1503 }; 1504 1505 PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base, 1506 qemu_irq irq, uint32_t region_size) 1507 { 1508 DeviceState *dev; 1509 SysBusDevice *i2c_dev; 1510 PXA2xxI2CState *s; 1511 I2CBus *i2cbus; 1512 1513 dev = qdev_new(TYPE_PXA2XX_I2C); 1514 qdev_prop_set_uint32(dev, "size", region_size + 1); 1515 qdev_prop_set_uint32(dev, "offset", base & region_size); 1516 1517 i2c_dev = SYS_BUS_DEVICE(dev); 1518 sysbus_realize_and_unref(i2c_dev, &error_fatal); 1519 sysbus_mmio_map(i2c_dev, 0, base & ~region_size); 1520 sysbus_connect_irq(i2c_dev, 0, irq); 1521 1522 s = PXA2XX_I2C(i2c_dev); 1523 /* FIXME: Should the slave device really be on a separate bus? */ 1524 i2cbus = i2c_init_bus(dev, "dummy"); 1525 s->slave = PXA2XX_I2C_SLAVE(i2c_slave_create_simple(i2cbus, 1526 TYPE_PXA2XX_I2C_SLAVE, 1527 0)); 1528 s->slave->host = s; 1529 1530 return s; 1531 } 1532 1533 static void pxa2xx_i2c_initfn(Object *obj) 1534 { 1535 DeviceState *dev = DEVICE(obj); 1536 PXA2xxI2CState *s = PXA2XX_I2C(obj); 1537 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1538 1539 s->bus = i2c_init_bus(dev, NULL); 1540 1541 memory_region_init_io(&s->iomem, obj, &pxa2xx_i2c_ops, s, 1542 "pxa2xx-i2c", s->region_size); 1543 sysbus_init_mmio(sbd, &s->iomem); 1544 sysbus_init_irq(sbd, &s->irq); 1545 } 1546 1547 I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s) 1548 { 1549 return s->bus; 1550 } 1551 1552 static Property pxa2xx_i2c_properties[] = { 1553 DEFINE_PROP_UINT32("size", PXA2xxI2CState, region_size, 0x10000), 1554 DEFINE_PROP_UINT32("offset", PXA2xxI2CState, offset, 0), 1555 DEFINE_PROP_END_OF_LIST(), 1556 }; 1557 1558 static void pxa2xx_i2c_class_init(ObjectClass *klass, void *data) 1559 { 1560 DeviceClass *dc = DEVICE_CLASS(klass); 1561 1562 dc->desc = "PXA2xx I2C Bus Controller"; 1563 dc->vmsd = &vmstate_pxa2xx_i2c; 1564 device_class_set_props(dc, pxa2xx_i2c_properties); 1565 } 1566 1567 static const TypeInfo pxa2xx_i2c_info = { 1568 .name = TYPE_PXA2XX_I2C, 1569 .parent = TYPE_SYS_BUS_DEVICE, 1570 .instance_size = sizeof(PXA2xxI2CState), 1571 .instance_init = pxa2xx_i2c_initfn, 1572 .class_init = pxa2xx_i2c_class_init, 1573 }; 1574 1575 /* PXA Inter-IC Sound Controller */ 1576 static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s) 1577 { 1578 i2s->rx_len = 0; 1579 i2s->tx_len = 0; 1580 i2s->fifo_len = 0; 1581 i2s->clk = 0x1a; 1582 i2s->control[0] = 0x00; 1583 i2s->control[1] = 0x00; 1584 i2s->status = 0x00; 1585 i2s->mask = 0x00; 1586 } 1587 1588 #define SACR_TFTH(val) ((val >> 8) & 0xf) 1589 #define SACR_RFTH(val) ((val >> 12) & 0xf) 1590 #define SACR_DREC(val) (val & (1 << 3)) 1591 #define SACR_DPRL(val) (val & (1 << 4)) 1592 1593 static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s) 1594 { 1595 int rfs, tfs; 1596 rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len && 1597 !SACR_DREC(i2s->control[1]); 1598 tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) && 1599 i2s->enable && !SACR_DPRL(i2s->control[1]); 1600 1601 qemu_set_irq(i2s->rx_dma, rfs); 1602 qemu_set_irq(i2s->tx_dma, tfs); 1603 1604 i2s->status &= 0xe0; 1605 if (i2s->fifo_len < 16 || !i2s->enable) 1606 i2s->status |= 1 << 0; /* TNF */ 1607 if (i2s->rx_len) 1608 i2s->status |= 1 << 1; /* RNE */ 1609 if (i2s->enable) 1610 i2s->status |= 1 << 2; /* BSY */ 1611 if (tfs) 1612 i2s->status |= 1 << 3; /* TFS */ 1613 if (rfs) 1614 i2s->status |= 1 << 4; /* RFS */ 1615 if (!(i2s->tx_len && i2s->enable)) 1616 i2s->status |= i2s->fifo_len << 8; /* TFL */ 1617 i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */ 1618 1619 qemu_set_irq(i2s->irq, i2s->status & i2s->mask); 1620 } 1621 1622 #define SACR0 0x00 /* Serial Audio Global Control register */ 1623 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */ 1624 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */ 1625 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */ 1626 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */ 1627 #define SADIV 0x60 /* Serial Audio Clock Divider register */ 1628 #define SADR 0x80 /* Serial Audio Data register */ 1629 1630 static uint64_t pxa2xx_i2s_read(void *opaque, hwaddr addr, 1631 unsigned size) 1632 { 1633 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; 1634 1635 switch (addr) { 1636 case SACR0: 1637 return s->control[0]; 1638 case SACR1: 1639 return s->control[1]; 1640 case SASR0: 1641 return s->status; 1642 case SAIMR: 1643 return s->mask; 1644 case SAICR: 1645 return 0; 1646 case SADIV: 1647 return s->clk; 1648 case SADR: 1649 if (s->rx_len > 0) { 1650 s->rx_len --; 1651 pxa2xx_i2s_update(s); 1652 return s->codec_in(s->opaque); 1653 } 1654 return 0; 1655 default: 1656 qemu_log_mask(LOG_GUEST_ERROR, 1657 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 1658 __func__, addr); 1659 break; 1660 } 1661 return 0; 1662 } 1663 1664 static void pxa2xx_i2s_write(void *opaque, hwaddr addr, 1665 uint64_t value, unsigned size) 1666 { 1667 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; 1668 uint32_t *sample; 1669 1670 switch (addr) { 1671 case SACR0: 1672 if (value & (1 << 3)) /* RST */ 1673 pxa2xx_i2s_reset(s); 1674 s->control[0] = value & 0xff3d; 1675 if (!s->enable && (value & 1) && s->tx_len) { /* ENB */ 1676 for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++) 1677 s->codec_out(s->opaque, *sample); 1678 s->status &= ~(1 << 7); /* I2SOFF */ 1679 } 1680 if (value & (1 << 4)) /* EFWR */ 1681 printf("%s: Attempt to use special function\n", __func__); 1682 s->enable = (value & 9) == 1; /* ENB && !RST*/ 1683 pxa2xx_i2s_update(s); 1684 break; 1685 case SACR1: 1686 s->control[1] = value & 0x0039; 1687 if (value & (1 << 5)) /* ENLBF */ 1688 printf("%s: Attempt to use loopback function\n", __func__); 1689 if (value & (1 << 4)) /* DPRL */ 1690 s->fifo_len = 0; 1691 pxa2xx_i2s_update(s); 1692 break; 1693 case SAIMR: 1694 s->mask = value & 0x0078; 1695 pxa2xx_i2s_update(s); 1696 break; 1697 case SAICR: 1698 s->status &= ~(value & (3 << 5)); 1699 pxa2xx_i2s_update(s); 1700 break; 1701 case SADIV: 1702 s->clk = value & 0x007f; 1703 break; 1704 case SADR: 1705 if (s->tx_len && s->enable) { 1706 s->tx_len --; 1707 pxa2xx_i2s_update(s); 1708 s->codec_out(s->opaque, value); 1709 } else if (s->fifo_len < 16) { 1710 s->fifo[s->fifo_len ++] = value; 1711 pxa2xx_i2s_update(s); 1712 } 1713 break; 1714 default: 1715 qemu_log_mask(LOG_GUEST_ERROR, 1716 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 1717 __func__, addr); 1718 } 1719 } 1720 1721 static const MemoryRegionOps pxa2xx_i2s_ops = { 1722 .read = pxa2xx_i2s_read, 1723 .write = pxa2xx_i2s_write, 1724 .endianness = DEVICE_NATIVE_ENDIAN, 1725 }; 1726 1727 static const VMStateDescription vmstate_pxa2xx_i2s = { 1728 .name = "pxa2xx_i2s", 1729 .version_id = 0, 1730 .minimum_version_id = 0, 1731 .fields = (VMStateField[]) { 1732 VMSTATE_UINT32_ARRAY(control, PXA2xxI2SState, 2), 1733 VMSTATE_UINT32(status, PXA2xxI2SState), 1734 VMSTATE_UINT32(mask, PXA2xxI2SState), 1735 VMSTATE_UINT32(clk, PXA2xxI2SState), 1736 VMSTATE_INT32(enable, PXA2xxI2SState), 1737 VMSTATE_INT32(rx_len, PXA2xxI2SState), 1738 VMSTATE_INT32(tx_len, PXA2xxI2SState), 1739 VMSTATE_INT32(fifo_len, PXA2xxI2SState), 1740 VMSTATE_END_OF_LIST() 1741 } 1742 }; 1743 1744 static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx) 1745 { 1746 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; 1747 uint32_t *sample; 1748 1749 /* Signal FIFO errors */ 1750 if (s->enable && s->tx_len) 1751 s->status |= 1 << 5; /* TUR */ 1752 if (s->enable && s->rx_len) 1753 s->status |= 1 << 6; /* ROR */ 1754 1755 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to 1756 * handle the cases where it makes a difference. */ 1757 s->tx_len = tx - s->fifo_len; 1758 s->rx_len = rx; 1759 /* Note that is s->codec_out wasn't set, we wouldn't get called. */ 1760 if (s->enable) 1761 for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++) 1762 s->codec_out(s->opaque, *sample); 1763 pxa2xx_i2s_update(s); 1764 } 1765 1766 static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem, 1767 hwaddr base, 1768 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma) 1769 { 1770 PXA2xxI2SState *s = g_new0(PXA2xxI2SState, 1); 1771 1772 s->irq = irq; 1773 s->rx_dma = rx_dma; 1774 s->tx_dma = tx_dma; 1775 s->data_req = pxa2xx_i2s_data_req; 1776 1777 pxa2xx_i2s_reset(s); 1778 1779 memory_region_init_io(&s->iomem, NULL, &pxa2xx_i2s_ops, s, 1780 "pxa2xx-i2s", 0x100000); 1781 memory_region_add_subregion(sysmem, base, &s->iomem); 1782 1783 vmstate_register(NULL, base, &vmstate_pxa2xx_i2s, s); 1784 1785 return s; 1786 } 1787 1788 /* PXA Fast Infra-red Communications Port */ 1789 #define TYPE_PXA2XX_FIR "pxa2xx-fir" 1790 #define PXA2XX_FIR(obj) OBJECT_CHECK(PXA2xxFIrState, (obj), TYPE_PXA2XX_FIR) 1791 1792 struct PXA2xxFIrState { 1793 /*< private >*/ 1794 SysBusDevice parent_obj; 1795 /*< public >*/ 1796 1797 MemoryRegion iomem; 1798 qemu_irq irq; 1799 qemu_irq rx_dma; 1800 qemu_irq tx_dma; 1801 uint32_t enable; 1802 CharBackend chr; 1803 1804 uint8_t control[3]; 1805 uint8_t status[2]; 1806 1807 uint32_t rx_len; 1808 uint32_t rx_start; 1809 uint8_t rx_fifo[64]; 1810 }; 1811 1812 static void pxa2xx_fir_reset(DeviceState *d) 1813 { 1814 PXA2xxFIrState *s = PXA2XX_FIR(d); 1815 1816 s->control[0] = 0x00; 1817 s->control[1] = 0x00; 1818 s->control[2] = 0x00; 1819 s->status[0] = 0x00; 1820 s->status[1] = 0x00; 1821 s->enable = 0; 1822 } 1823 1824 static inline void pxa2xx_fir_update(PXA2xxFIrState *s) 1825 { 1826 static const int tresh[4] = { 8, 16, 32, 0 }; 1827 int intr = 0; 1828 if ((s->control[0] & (1 << 4)) && /* RXE */ 1829 s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */ 1830 s->status[0] |= 1 << 4; /* RFS */ 1831 else 1832 s->status[0] &= ~(1 << 4); /* RFS */ 1833 if (s->control[0] & (1 << 3)) /* TXE */ 1834 s->status[0] |= 1 << 3; /* TFS */ 1835 else 1836 s->status[0] &= ~(1 << 3); /* TFS */ 1837 if (s->rx_len) 1838 s->status[1] |= 1 << 2; /* RNE */ 1839 else 1840 s->status[1] &= ~(1 << 2); /* RNE */ 1841 if (s->control[0] & (1 << 4)) /* RXE */ 1842 s->status[1] |= 1 << 0; /* RSY */ 1843 else 1844 s->status[1] &= ~(1 << 0); /* RSY */ 1845 1846 intr |= (s->control[0] & (1 << 5)) && /* RIE */ 1847 (s->status[0] & (1 << 4)); /* RFS */ 1848 intr |= (s->control[0] & (1 << 6)) && /* TIE */ 1849 (s->status[0] & (1 << 3)); /* TFS */ 1850 intr |= (s->control[2] & (1 << 4)) && /* TRAIL */ 1851 (s->status[0] & (1 << 6)); /* EOC */ 1852 intr |= (s->control[0] & (1 << 2)) && /* TUS */ 1853 (s->status[0] & (1 << 1)); /* TUR */ 1854 intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */ 1855 1856 qemu_set_irq(s->rx_dma, (s->status[0] >> 4) & 1); 1857 qemu_set_irq(s->tx_dma, (s->status[0] >> 3) & 1); 1858 1859 qemu_set_irq(s->irq, intr && s->enable); 1860 } 1861 1862 #define ICCR0 0x00 /* FICP Control register 0 */ 1863 #define ICCR1 0x04 /* FICP Control register 1 */ 1864 #define ICCR2 0x08 /* FICP Control register 2 */ 1865 #define ICDR 0x0c /* FICP Data register */ 1866 #define ICSR0 0x14 /* FICP Status register 0 */ 1867 #define ICSR1 0x18 /* FICP Status register 1 */ 1868 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */ 1869 1870 static uint64_t pxa2xx_fir_read(void *opaque, hwaddr addr, 1871 unsigned size) 1872 { 1873 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1874 uint8_t ret; 1875 1876 switch (addr) { 1877 case ICCR0: 1878 return s->control[0]; 1879 case ICCR1: 1880 return s->control[1]; 1881 case ICCR2: 1882 return s->control[2]; 1883 case ICDR: 1884 s->status[0] &= ~0x01; 1885 s->status[1] &= ~0x72; 1886 if (s->rx_len) { 1887 s->rx_len --; 1888 ret = s->rx_fifo[s->rx_start ++]; 1889 s->rx_start &= 63; 1890 pxa2xx_fir_update(s); 1891 return ret; 1892 } 1893 printf("%s: Rx FIFO underrun.\n", __func__); 1894 break; 1895 case ICSR0: 1896 return s->status[0]; 1897 case ICSR1: 1898 return s->status[1] | (1 << 3); /* TNF */ 1899 case ICFOR: 1900 return s->rx_len; 1901 default: 1902 qemu_log_mask(LOG_GUEST_ERROR, 1903 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 1904 __func__, addr); 1905 break; 1906 } 1907 return 0; 1908 } 1909 1910 static void pxa2xx_fir_write(void *opaque, hwaddr addr, 1911 uint64_t value64, unsigned size) 1912 { 1913 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1914 uint32_t value = value64; 1915 uint8_t ch; 1916 1917 switch (addr) { 1918 case ICCR0: 1919 s->control[0] = value; 1920 if (!(value & (1 << 4))) /* RXE */ 1921 s->rx_len = s->rx_start = 0; 1922 if (!(value & (1 << 3))) { /* TXE */ 1923 /* Nop */ 1924 } 1925 s->enable = value & 1; /* ITR */ 1926 if (!s->enable) 1927 s->status[0] = 0; 1928 pxa2xx_fir_update(s); 1929 break; 1930 case ICCR1: 1931 s->control[1] = value; 1932 break; 1933 case ICCR2: 1934 s->control[2] = value & 0x3f; 1935 pxa2xx_fir_update(s); 1936 break; 1937 case ICDR: 1938 if (s->control[2] & (1 << 2)) { /* TXP */ 1939 ch = value; 1940 } else { 1941 ch = ~value; 1942 } 1943 if (s->enable && (s->control[0] & (1 << 3))) { /* TXE */ 1944 /* XXX this blocks entire thread. Rewrite to use 1945 * qemu_chr_fe_write and background I/O callbacks */ 1946 qemu_chr_fe_write_all(&s->chr, &ch, 1); 1947 } 1948 break; 1949 case ICSR0: 1950 s->status[0] &= ~(value & 0x66); 1951 pxa2xx_fir_update(s); 1952 break; 1953 case ICFOR: 1954 break; 1955 default: 1956 qemu_log_mask(LOG_GUEST_ERROR, 1957 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 1958 __func__, addr); 1959 } 1960 } 1961 1962 static const MemoryRegionOps pxa2xx_fir_ops = { 1963 .read = pxa2xx_fir_read, 1964 .write = pxa2xx_fir_write, 1965 .endianness = DEVICE_NATIVE_ENDIAN, 1966 }; 1967 1968 static int pxa2xx_fir_is_empty(void *opaque) 1969 { 1970 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1971 return (s->rx_len < 64); 1972 } 1973 1974 static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size) 1975 { 1976 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1977 if (!(s->control[0] & (1 << 4))) /* RXE */ 1978 return; 1979 1980 while (size --) { 1981 s->status[1] |= 1 << 4; /* EOF */ 1982 if (s->rx_len >= 64) { 1983 s->status[1] |= 1 << 6; /* ROR */ 1984 break; 1985 } 1986 1987 if (s->control[2] & (1 << 3)) /* RXP */ 1988 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++); 1989 else 1990 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++); 1991 } 1992 1993 pxa2xx_fir_update(s); 1994 } 1995 1996 static void pxa2xx_fir_event(void *opaque, QEMUChrEvent event) 1997 { 1998 } 1999 2000 static void pxa2xx_fir_instance_init(Object *obj) 2001 { 2002 PXA2xxFIrState *s = PXA2XX_FIR(obj); 2003 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 2004 2005 memory_region_init_io(&s->iomem, obj, &pxa2xx_fir_ops, s, 2006 "pxa2xx-fir", 0x1000); 2007 sysbus_init_mmio(sbd, &s->iomem); 2008 sysbus_init_irq(sbd, &s->irq); 2009 sysbus_init_irq(sbd, &s->rx_dma); 2010 sysbus_init_irq(sbd, &s->tx_dma); 2011 } 2012 2013 static void pxa2xx_fir_realize(DeviceState *dev, Error **errp) 2014 { 2015 PXA2xxFIrState *s = PXA2XX_FIR(dev); 2016 2017 qemu_chr_fe_set_handlers(&s->chr, pxa2xx_fir_is_empty, 2018 pxa2xx_fir_rx, pxa2xx_fir_event, NULL, s, NULL, 2019 true); 2020 } 2021 2022 static bool pxa2xx_fir_vmstate_validate(void *opaque, int version_id) 2023 { 2024 PXA2xxFIrState *s = opaque; 2025 2026 return s->rx_start < ARRAY_SIZE(s->rx_fifo); 2027 } 2028 2029 static const VMStateDescription pxa2xx_fir_vmsd = { 2030 .name = "pxa2xx-fir", 2031 .version_id = 1, 2032 .minimum_version_id = 1, 2033 .fields = (VMStateField[]) { 2034 VMSTATE_UINT32(enable, PXA2xxFIrState), 2035 VMSTATE_UINT8_ARRAY(control, PXA2xxFIrState, 3), 2036 VMSTATE_UINT8_ARRAY(status, PXA2xxFIrState, 2), 2037 VMSTATE_UINT32(rx_len, PXA2xxFIrState), 2038 VMSTATE_UINT32(rx_start, PXA2xxFIrState), 2039 VMSTATE_VALIDATE("fifo is 64 bytes", pxa2xx_fir_vmstate_validate), 2040 VMSTATE_UINT8_ARRAY(rx_fifo, PXA2xxFIrState, 64), 2041 VMSTATE_END_OF_LIST() 2042 } 2043 }; 2044 2045 static Property pxa2xx_fir_properties[] = { 2046 DEFINE_PROP_CHR("chardev", PXA2xxFIrState, chr), 2047 DEFINE_PROP_END_OF_LIST(), 2048 }; 2049 2050 static void pxa2xx_fir_class_init(ObjectClass *klass, void *data) 2051 { 2052 DeviceClass *dc = DEVICE_CLASS(klass); 2053 2054 dc->realize = pxa2xx_fir_realize; 2055 dc->vmsd = &pxa2xx_fir_vmsd; 2056 device_class_set_props(dc, pxa2xx_fir_properties); 2057 dc->reset = pxa2xx_fir_reset; 2058 } 2059 2060 static const TypeInfo pxa2xx_fir_info = { 2061 .name = TYPE_PXA2XX_FIR, 2062 .parent = TYPE_SYS_BUS_DEVICE, 2063 .instance_size = sizeof(PXA2xxFIrState), 2064 .class_init = pxa2xx_fir_class_init, 2065 .instance_init = pxa2xx_fir_instance_init, 2066 }; 2067 2068 static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem, 2069 hwaddr base, 2070 qemu_irq irq, qemu_irq rx_dma, 2071 qemu_irq tx_dma, 2072 Chardev *chr) 2073 { 2074 DeviceState *dev; 2075 SysBusDevice *sbd; 2076 2077 dev = qdev_new(TYPE_PXA2XX_FIR); 2078 qdev_prop_set_chr(dev, "chardev", chr); 2079 sbd = SYS_BUS_DEVICE(dev); 2080 sysbus_realize_and_unref(sbd, &error_fatal); 2081 sysbus_mmio_map(sbd, 0, base); 2082 sysbus_connect_irq(sbd, 0, irq); 2083 sysbus_connect_irq(sbd, 1, rx_dma); 2084 sysbus_connect_irq(sbd, 2, tx_dma); 2085 return PXA2XX_FIR(dev); 2086 } 2087 2088 static void pxa2xx_reset(void *opaque, int line, int level) 2089 { 2090 PXA2xxState *s = (PXA2xxState *) opaque; 2091 2092 if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */ 2093 cpu_reset(CPU(s->cpu)); 2094 /* TODO: reset peripherals */ 2095 } 2096 } 2097 2098 /* Initialise a PXA270 integrated chip (ARM based core). */ 2099 PXA2xxState *pxa270_init(MemoryRegion *address_space, 2100 unsigned int sdram_size, const char *cpu_type) 2101 { 2102 PXA2xxState *s; 2103 int i; 2104 DriveInfo *dinfo; 2105 s = g_new0(PXA2xxState, 1); 2106 2107 if (strncmp(cpu_type, "pxa27", 5)) { 2108 error_report("Machine requires a PXA27x processor"); 2109 exit(1); 2110 } 2111 2112 s->cpu = ARM_CPU(cpu_create(cpu_type)); 2113 s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0); 2114 2115 /* SDRAM & Internal Memory Storage */ 2116 memory_region_init_ram(&s->sdram, NULL, "pxa270.sdram", sdram_size, 2117 &error_fatal); 2118 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram); 2119 memory_region_init_ram(&s->internal, NULL, "pxa270.internal", 0x40000, 2120 &error_fatal); 2121 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE, 2122 &s->internal); 2123 2124 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu); 2125 2126 s->dma = pxa27x_dma_init(0x40000000, 2127 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA)); 2128 2129 sysbus_create_varargs("pxa27x-timer", 0x40a00000, 2130 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0), 2131 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1), 2132 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2), 2133 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3), 2134 qdev_get_gpio_in(s->pic, PXA27X_PIC_OST_4_11), 2135 NULL); 2136 2137 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 121); 2138 2139 dinfo = drive_get(IF_SD, 0, 0); 2140 if (!dinfo && !qtest_enabled()) { 2141 warn_report("missing SecureDigital device"); 2142 } 2143 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, 2144 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 2145 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), 2146 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), 2147 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); 2148 2149 for (i = 0; pxa270_serial[i].io_base; i++) { 2150 if (serial_hd(i)) { 2151 serial_mm_init(address_space, pxa270_serial[i].io_base, 2, 2152 qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn), 2153 14857000 / 16, serial_hd(i), 2154 DEVICE_NATIVE_ENDIAN); 2155 } else { 2156 break; 2157 } 2158 } 2159 if (serial_hd(i)) 2160 s->fir = pxa2xx_fir_init(address_space, 0x40800000, 2161 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), 2162 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), 2163 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), 2164 serial_hd(i)); 2165 2166 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000, 2167 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); 2168 2169 s->cm_base = 0x41300000; 2170 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */ 2171 s->clkcfg = 0x00000009; /* Turbo mode active */ 2172 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000); 2173 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); 2174 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); 2175 2176 pxa2xx_setup_cp14(s); 2177 2178 s->mm_base = 0x48000000; 2179 s->mm_regs[MDMRS >> 2] = 0x00020002; 2180 s->mm_regs[MDREFR >> 2] = 0x03ca4000; 2181 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ 2182 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000); 2183 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem); 2184 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s); 2185 2186 s->pm_base = 0x40f00000; 2187 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100); 2188 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem); 2189 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s); 2190 2191 for (i = 0; pxa27x_ssp[i].io_base; i ++); 2192 s->ssp = g_new0(SSIBus *, i); 2193 for (i = 0; pxa27x_ssp[i].io_base; i ++) { 2194 DeviceState *dev; 2195 dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa27x_ssp[i].io_base, 2196 qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn)); 2197 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi"); 2198 } 2199 2200 sysbus_create_simple("sysbus-ohci", 0x4c000000, 2201 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1)); 2202 2203 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000); 2204 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000); 2205 2206 sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000, 2207 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM)); 2208 2209 s->i2c[0] = pxa2xx_i2c_init(0x40301600, 2210 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff); 2211 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, 2212 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff); 2213 2214 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000, 2215 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), 2216 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), 2217 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); 2218 2219 s->kp = pxa27x_keypad_init(address_space, 0x41500000, 2220 qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD)); 2221 2222 /* GPIO1 resets the processor */ 2223 /* The handler can be overridden by board-specific code */ 2224 qdev_connect_gpio_out(s->gpio, 1, s->reset); 2225 return s; 2226 } 2227 2228 /* Initialise a PXA255 integrated chip (ARM based core). */ 2229 PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size) 2230 { 2231 PXA2xxState *s; 2232 int i; 2233 DriveInfo *dinfo; 2234 2235 s = g_new0(PXA2xxState, 1); 2236 2237 s->cpu = ARM_CPU(cpu_create(ARM_CPU_TYPE_NAME("pxa255"))); 2238 s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0); 2239 2240 /* SDRAM & Internal Memory Storage */ 2241 memory_region_init_ram(&s->sdram, NULL, "pxa255.sdram", sdram_size, 2242 &error_fatal); 2243 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram); 2244 memory_region_init_ram(&s->internal, NULL, "pxa255.internal", 2245 PXA2XX_INTERNAL_SIZE, &error_fatal); 2246 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE, 2247 &s->internal); 2248 2249 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu); 2250 2251 s->dma = pxa255_dma_init(0x40000000, 2252 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA)); 2253 2254 sysbus_create_varargs("pxa25x-timer", 0x40a00000, 2255 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0), 2256 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1), 2257 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2), 2258 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3), 2259 NULL); 2260 2261 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 85); 2262 2263 dinfo = drive_get(IF_SD, 0, 0); 2264 if (!dinfo && !qtest_enabled()) { 2265 warn_report("missing SecureDigital device"); 2266 } 2267 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, 2268 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 2269 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), 2270 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), 2271 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); 2272 2273 for (i = 0; pxa255_serial[i].io_base; i++) { 2274 if (serial_hd(i)) { 2275 serial_mm_init(address_space, pxa255_serial[i].io_base, 2, 2276 qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn), 2277 14745600 / 16, serial_hd(i), 2278 DEVICE_NATIVE_ENDIAN); 2279 } else { 2280 break; 2281 } 2282 } 2283 if (serial_hd(i)) 2284 s->fir = pxa2xx_fir_init(address_space, 0x40800000, 2285 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), 2286 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), 2287 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), 2288 serial_hd(i)); 2289 2290 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000, 2291 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); 2292 2293 s->cm_base = 0x41300000; 2294 s->cm_regs[CCCR >> 2] = 0x00000121; /* from datasheet */ 2295 s->cm_regs[CKEN >> 2] = 0x00017def; /* from datasheet */ 2296 2297 s->clkcfg = 0x00000009; /* Turbo mode active */ 2298 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000); 2299 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); 2300 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); 2301 2302 pxa2xx_setup_cp14(s); 2303 2304 s->mm_base = 0x48000000; 2305 s->mm_regs[MDMRS >> 2] = 0x00020002; 2306 s->mm_regs[MDREFR >> 2] = 0x03ca4000; 2307 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ 2308 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000); 2309 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem); 2310 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s); 2311 2312 s->pm_base = 0x40f00000; 2313 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100); 2314 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem); 2315 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s); 2316 2317 for (i = 0; pxa255_ssp[i].io_base; i ++); 2318 s->ssp = g_new0(SSIBus *, i); 2319 for (i = 0; pxa255_ssp[i].io_base; i ++) { 2320 DeviceState *dev; 2321 dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa255_ssp[i].io_base, 2322 qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn)); 2323 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi"); 2324 } 2325 2326 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000); 2327 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000); 2328 2329 sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000, 2330 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM)); 2331 2332 s->i2c[0] = pxa2xx_i2c_init(0x40301600, 2333 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff); 2334 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, 2335 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff); 2336 2337 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000, 2338 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), 2339 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), 2340 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); 2341 2342 /* GPIO1 resets the processor */ 2343 /* The handler can be overridden by board-specific code */ 2344 qdev_connect_gpio_out(s->gpio, 1, s->reset); 2345 return s; 2346 } 2347 2348 static void pxa2xx_ssp_class_init(ObjectClass *klass, void *data) 2349 { 2350 DeviceClass *dc = DEVICE_CLASS(klass); 2351 2352 dc->reset = pxa2xx_ssp_reset; 2353 dc->vmsd = &vmstate_pxa2xx_ssp; 2354 } 2355 2356 static const TypeInfo pxa2xx_ssp_info = { 2357 .name = TYPE_PXA2XX_SSP, 2358 .parent = TYPE_SYS_BUS_DEVICE, 2359 .instance_size = sizeof(PXA2xxSSPState), 2360 .instance_init = pxa2xx_ssp_init, 2361 .class_init = pxa2xx_ssp_class_init, 2362 }; 2363 2364 static void pxa2xx_register_types(void) 2365 { 2366 type_register_static(&pxa2xx_i2c_slave_info); 2367 type_register_static(&pxa2xx_ssp_info); 2368 type_register_static(&pxa2xx_i2c_info); 2369 type_register_static(&pxa2xx_rtc_sysbus_info); 2370 type_register_static(&pxa2xx_fir_info); 2371 } 2372 2373 type_init(pxa2xx_register_types) 2374