1 /* 2 * Intel XScale PXA255/270 processor support. 3 * 4 * Copyright (c) 2006 Openedhand Ltd. 5 * Written by Andrzej Zaborowski <balrog@zabor.org> 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "hw/sysbus.h" 11 #include "hw/arm/pxa.h" 12 #include "sysemu/sysemu.h" 13 #include "hw/char/serial.h" 14 #include "hw/i2c/i2c.h" 15 #include "hw/ssi.h" 16 #include "sysemu/char.h" 17 #include "sysemu/block-backend.h" 18 #include "sysemu/blockdev.h" 19 20 static struct { 21 hwaddr io_base; 22 int irqn; 23 } pxa255_serial[] = { 24 { 0x40100000, PXA2XX_PIC_FFUART }, 25 { 0x40200000, PXA2XX_PIC_BTUART }, 26 { 0x40700000, PXA2XX_PIC_STUART }, 27 { 0x41600000, PXA25X_PIC_HWUART }, 28 { 0, 0 } 29 }, pxa270_serial[] = { 30 { 0x40100000, PXA2XX_PIC_FFUART }, 31 { 0x40200000, PXA2XX_PIC_BTUART }, 32 { 0x40700000, PXA2XX_PIC_STUART }, 33 { 0, 0 } 34 }; 35 36 typedef struct PXASSPDef { 37 hwaddr io_base; 38 int irqn; 39 } PXASSPDef; 40 41 #if 0 42 static PXASSPDef pxa250_ssp[] = { 43 { 0x41000000, PXA2XX_PIC_SSP }, 44 { 0, 0 } 45 }; 46 #endif 47 48 static PXASSPDef pxa255_ssp[] = { 49 { 0x41000000, PXA2XX_PIC_SSP }, 50 { 0x41400000, PXA25X_PIC_NSSP }, 51 { 0, 0 } 52 }; 53 54 #if 0 55 static PXASSPDef pxa26x_ssp[] = { 56 { 0x41000000, PXA2XX_PIC_SSP }, 57 { 0x41400000, PXA25X_PIC_NSSP }, 58 { 0x41500000, PXA26X_PIC_ASSP }, 59 { 0, 0 } 60 }; 61 #endif 62 63 static PXASSPDef pxa27x_ssp[] = { 64 { 0x41000000, PXA2XX_PIC_SSP }, 65 { 0x41700000, PXA27X_PIC_SSP2 }, 66 { 0x41900000, PXA2XX_PIC_SSP3 }, 67 { 0, 0 } 68 }; 69 70 #define PMCR 0x00 /* Power Manager Control register */ 71 #define PSSR 0x04 /* Power Manager Sleep Status register */ 72 #define PSPR 0x08 /* Power Manager Scratch-Pad register */ 73 #define PWER 0x0c /* Power Manager Wake-Up Enable register */ 74 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */ 75 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */ 76 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */ 77 #define PCFR 0x1c /* Power Manager General Configuration register */ 78 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */ 79 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */ 80 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */ 81 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */ 82 #define RCSR 0x30 /* Reset Controller Status register */ 83 #define PSLR 0x34 /* Power Manager Sleep Configuration register */ 84 #define PTSR 0x38 /* Power Manager Standby Configuration register */ 85 #define PVCR 0x40 /* Power Manager Voltage Change Control register */ 86 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */ 87 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */ 88 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */ 89 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */ 90 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */ 91 92 static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr, 93 unsigned size) 94 { 95 PXA2xxState *s = (PXA2xxState *) opaque; 96 97 switch (addr) { 98 case PMCR ... PCMD31: 99 if (addr & 3) 100 goto fail; 101 102 return s->pm_regs[addr >> 2]; 103 default: 104 fail: 105 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 106 break; 107 } 108 return 0; 109 } 110 111 static void pxa2xx_pm_write(void *opaque, hwaddr addr, 112 uint64_t value, unsigned size) 113 { 114 PXA2xxState *s = (PXA2xxState *) opaque; 115 116 switch (addr) { 117 case PMCR: 118 /* Clear the write-one-to-clear bits... */ 119 s->pm_regs[addr >> 2] &= ~(value & 0x2a); 120 /* ...and set the plain r/w bits */ 121 s->pm_regs[addr >> 2] &= ~0x15; 122 s->pm_regs[addr >> 2] |= value & 0x15; 123 break; 124 125 case PSSR: /* Read-clean registers */ 126 case RCSR: 127 case PKSR: 128 s->pm_regs[addr >> 2] &= ~value; 129 break; 130 131 default: /* Read-write registers */ 132 if (!(addr & 3)) { 133 s->pm_regs[addr >> 2] = value; 134 break; 135 } 136 137 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 138 break; 139 } 140 } 141 142 static const MemoryRegionOps pxa2xx_pm_ops = { 143 .read = pxa2xx_pm_read, 144 .write = pxa2xx_pm_write, 145 .endianness = DEVICE_NATIVE_ENDIAN, 146 }; 147 148 static const VMStateDescription vmstate_pxa2xx_pm = { 149 .name = "pxa2xx_pm", 150 .version_id = 0, 151 .minimum_version_id = 0, 152 .fields = (VMStateField[]) { 153 VMSTATE_UINT32_ARRAY(pm_regs, PXA2xxState, 0x40), 154 VMSTATE_END_OF_LIST() 155 } 156 }; 157 158 #define CCCR 0x00 /* Core Clock Configuration register */ 159 #define CKEN 0x04 /* Clock Enable register */ 160 #define OSCC 0x08 /* Oscillator Configuration register */ 161 #define CCSR 0x0c /* Core Clock Status register */ 162 163 static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr, 164 unsigned size) 165 { 166 PXA2xxState *s = (PXA2xxState *) opaque; 167 168 switch (addr) { 169 case CCCR: 170 case CKEN: 171 case OSCC: 172 return s->cm_regs[addr >> 2]; 173 174 case CCSR: 175 return s->cm_regs[CCCR >> 2] | (3 << 28); 176 177 default: 178 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 179 break; 180 } 181 return 0; 182 } 183 184 static void pxa2xx_cm_write(void *opaque, hwaddr addr, 185 uint64_t value, unsigned size) 186 { 187 PXA2xxState *s = (PXA2xxState *) opaque; 188 189 switch (addr) { 190 case CCCR: 191 case CKEN: 192 s->cm_regs[addr >> 2] = value; 193 break; 194 195 case OSCC: 196 s->cm_regs[addr >> 2] &= ~0x6c; 197 s->cm_regs[addr >> 2] |= value & 0x6e; 198 if ((value >> 1) & 1) /* OON */ 199 s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */ 200 break; 201 202 default: 203 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 204 break; 205 } 206 } 207 208 static const MemoryRegionOps pxa2xx_cm_ops = { 209 .read = pxa2xx_cm_read, 210 .write = pxa2xx_cm_write, 211 .endianness = DEVICE_NATIVE_ENDIAN, 212 }; 213 214 static const VMStateDescription vmstate_pxa2xx_cm = { 215 .name = "pxa2xx_cm", 216 .version_id = 0, 217 .minimum_version_id = 0, 218 .fields = (VMStateField[]) { 219 VMSTATE_UINT32_ARRAY(cm_regs, PXA2xxState, 4), 220 VMSTATE_UINT32(clkcfg, PXA2xxState), 221 VMSTATE_UINT32(pmnc, PXA2xxState), 222 VMSTATE_END_OF_LIST() 223 } 224 }; 225 226 static uint64_t pxa2xx_clkcfg_read(CPUARMState *env, const ARMCPRegInfo *ri) 227 { 228 PXA2xxState *s = (PXA2xxState *)ri->opaque; 229 return s->clkcfg; 230 } 231 232 static void pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri, 233 uint64_t value) 234 { 235 PXA2xxState *s = (PXA2xxState *)ri->opaque; 236 s->clkcfg = value & 0xf; 237 if (value & 2) { 238 printf("%s: CPU frequency change attempt\n", __func__); 239 } 240 } 241 242 static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri, 243 uint64_t value) 244 { 245 PXA2xxState *s = (PXA2xxState *)ri->opaque; 246 static const char *pwrmode[8] = { 247 "Normal", "Idle", "Deep-idle", "Standby", 248 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep", 249 }; 250 251 if (value & 8) { 252 printf("%s: CPU voltage change attempt\n", __func__); 253 } 254 switch (value & 7) { 255 case 0: 256 /* Do nothing */ 257 break; 258 259 case 1: 260 /* Idle */ 261 if (!(s->cm_regs[CCCR >> 2] & (1U << 31))) { /* CPDIS */ 262 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); 263 break; 264 } 265 /* Fall through. */ 266 267 case 2: 268 /* Deep-Idle */ 269 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); 270 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ 271 goto message; 272 273 case 3: 274 s->cpu->env.uncached_cpsr = ARM_CPU_MODE_SVC; 275 s->cpu->env.daif = PSTATE_A | PSTATE_F | PSTATE_I; 276 s->cpu->env.cp15.sctlr_ns = 0; 277 s->cpu->env.cp15.c1_coproc = 0; 278 s->cpu->env.cp15.ttbr0_el[1] = 0; 279 s->cpu->env.cp15.dacr_ns = 0; 280 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ 281 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ 282 283 /* 284 * The scratch-pad register is almost universally used 285 * for storing the return address on suspend. For the 286 * lack of a resuming bootloader, perform a jump 287 * directly to that address. 288 */ 289 memset(s->cpu->env.regs, 0, 4 * 15); 290 s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2]; 291 292 #if 0 293 buffer = 0xe59ff000; /* ldr pc, [pc, #0] */ 294 cpu_physical_memory_write(0, &buffer, 4); 295 buffer = s->pm_regs[PSPR >> 2]; 296 cpu_physical_memory_write(8, &buffer, 4); 297 #endif 298 299 /* Suspend */ 300 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); 301 302 goto message; 303 304 default: 305 message: 306 printf("%s: machine entered %s mode\n", __func__, 307 pwrmode[value & 7]); 308 } 309 } 310 311 static uint64_t pxa2xx_cppmnc_read(CPUARMState *env, const ARMCPRegInfo *ri) 312 { 313 PXA2xxState *s = (PXA2xxState *)ri->opaque; 314 return s->pmnc; 315 } 316 317 static void pxa2xx_cppmnc_write(CPUARMState *env, const ARMCPRegInfo *ri, 318 uint64_t value) 319 { 320 PXA2xxState *s = (PXA2xxState *)ri->opaque; 321 s->pmnc = value; 322 } 323 324 static uint64_t pxa2xx_cpccnt_read(CPUARMState *env, const ARMCPRegInfo *ri) 325 { 326 PXA2xxState *s = (PXA2xxState *)ri->opaque; 327 if (s->pmnc & 1) { 328 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 329 } else { 330 return 0; 331 } 332 } 333 334 static const ARMCPRegInfo pxa_cp_reginfo[] = { 335 /* cp14 crm==1: perf registers */ 336 { .name = "CPPMNC", .cp = 14, .crn = 0, .crm = 1, .opc1 = 0, .opc2 = 0, 337 .access = PL1_RW, 338 .readfn = pxa2xx_cppmnc_read, .writefn = pxa2xx_cppmnc_write }, 339 { .name = "CPCCNT", .cp = 14, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, 340 .access = PL1_RW, 341 .readfn = pxa2xx_cpccnt_read, .writefn = arm_cp_write_ignore }, 342 { .name = "CPINTEN", .cp = 14, .crn = 4, .crm = 1, .opc1 = 0, .opc2 = 0, 343 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 344 { .name = "CPFLAG", .cp = 14, .crn = 5, .crm = 1, .opc1 = 0, .opc2 = 0, 345 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 346 { .name = "CPEVTSEL", .cp = 14, .crn = 8, .crm = 1, .opc1 = 0, .opc2 = 0, 347 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 348 /* cp14 crm==2: performance count registers */ 349 { .name = "CPPMN0", .cp = 14, .crn = 0, .crm = 2, .opc1 = 0, .opc2 = 0, 350 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 351 { .name = "CPPMN1", .cp = 14, .crn = 1, .crm = 2, .opc1 = 0, .opc2 = 0, 352 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 353 { .name = "CPPMN2", .cp = 14, .crn = 2, .crm = 2, .opc1 = 0, .opc2 = 0, 354 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 355 { .name = "CPPMN3", .cp = 14, .crn = 2, .crm = 3, .opc1 = 0, .opc2 = 0, 356 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 357 /* cp14 crn==6: CLKCFG */ 358 { .name = "CLKCFG", .cp = 14, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, 359 .access = PL1_RW, 360 .readfn = pxa2xx_clkcfg_read, .writefn = pxa2xx_clkcfg_write }, 361 /* cp14 crn==7: PWRMODE */ 362 { .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0, 363 .access = PL1_RW, 364 .readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write }, 365 REGINFO_SENTINEL 366 }; 367 368 static void pxa2xx_setup_cp14(PXA2xxState *s) 369 { 370 define_arm_cp_regs_with_opaque(s->cpu, pxa_cp_reginfo, s); 371 } 372 373 #define MDCNFG 0x00 /* SDRAM Configuration register */ 374 #define MDREFR 0x04 /* SDRAM Refresh Control register */ 375 #define MSC0 0x08 /* Static Memory Control register 0 */ 376 #define MSC1 0x0c /* Static Memory Control register 1 */ 377 #define MSC2 0x10 /* Static Memory Control register 2 */ 378 #define MECR 0x14 /* Expansion Memory Bus Config register */ 379 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */ 380 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */ 381 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */ 382 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */ 383 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */ 384 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */ 385 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */ 386 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */ 387 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */ 388 #define ARB_CNTL 0x48 /* Arbiter Control register */ 389 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */ 390 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */ 391 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */ 392 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */ 393 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */ 394 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */ 395 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */ 396 397 static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr, 398 unsigned size) 399 { 400 PXA2xxState *s = (PXA2xxState *) opaque; 401 402 switch (addr) { 403 case MDCNFG ... SA1110: 404 if ((addr & 3) == 0) 405 return s->mm_regs[addr >> 2]; 406 407 default: 408 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 409 break; 410 } 411 return 0; 412 } 413 414 static void pxa2xx_mm_write(void *opaque, hwaddr addr, 415 uint64_t value, unsigned size) 416 { 417 PXA2xxState *s = (PXA2xxState *) opaque; 418 419 switch (addr) { 420 case MDCNFG ... SA1110: 421 if ((addr & 3) == 0) { 422 s->mm_regs[addr >> 2] = value; 423 break; 424 } 425 426 default: 427 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 428 break; 429 } 430 } 431 432 static const MemoryRegionOps pxa2xx_mm_ops = { 433 .read = pxa2xx_mm_read, 434 .write = pxa2xx_mm_write, 435 .endianness = DEVICE_NATIVE_ENDIAN, 436 }; 437 438 static const VMStateDescription vmstate_pxa2xx_mm = { 439 .name = "pxa2xx_mm", 440 .version_id = 0, 441 .minimum_version_id = 0, 442 .fields = (VMStateField[]) { 443 VMSTATE_UINT32_ARRAY(mm_regs, PXA2xxState, 0x1a), 444 VMSTATE_END_OF_LIST() 445 } 446 }; 447 448 #define TYPE_PXA2XX_SSP "pxa2xx-ssp" 449 #define PXA2XX_SSP(obj) \ 450 OBJECT_CHECK(PXA2xxSSPState, (obj), TYPE_PXA2XX_SSP) 451 452 /* Synchronous Serial Ports */ 453 typedef struct { 454 /*< private >*/ 455 SysBusDevice parent_obj; 456 /*< public >*/ 457 458 MemoryRegion iomem; 459 qemu_irq irq; 460 int enable; 461 SSIBus *bus; 462 463 uint32_t sscr[2]; 464 uint32_t sspsp; 465 uint32_t ssto; 466 uint32_t ssitr; 467 uint32_t sssr; 468 uint8_t sstsa; 469 uint8_t ssrsa; 470 uint8_t ssacd; 471 472 uint32_t rx_fifo[16]; 473 int rx_level; 474 int rx_start; 475 } PXA2xxSSPState; 476 477 #define SSCR0 0x00 /* SSP Control register 0 */ 478 #define SSCR1 0x04 /* SSP Control register 1 */ 479 #define SSSR 0x08 /* SSP Status register */ 480 #define SSITR 0x0c /* SSP Interrupt Test register */ 481 #define SSDR 0x10 /* SSP Data register */ 482 #define SSTO 0x28 /* SSP Time-Out register */ 483 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */ 484 #define SSTSA 0x30 /* SSP TX Time Slot Active register */ 485 #define SSRSA 0x34 /* SSP RX Time Slot Active register */ 486 #define SSTSS 0x38 /* SSP Time Slot Status register */ 487 #define SSACD 0x3c /* SSP Audio Clock Divider register */ 488 489 /* Bitfields for above registers */ 490 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00) 491 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10) 492 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20) 493 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30) 494 #define SSCR0_SSE (1 << 7) 495 #define SSCR0_RIM (1 << 22) 496 #define SSCR0_TIM (1 << 23) 497 #define SSCR0_MOD (1U << 31) 498 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1) 499 #define SSCR1_RIE (1 << 0) 500 #define SSCR1_TIE (1 << 1) 501 #define SSCR1_LBM (1 << 2) 502 #define SSCR1_MWDS (1 << 5) 503 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1) 504 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1) 505 #define SSCR1_EFWR (1 << 14) 506 #define SSCR1_PINTE (1 << 18) 507 #define SSCR1_TINTE (1 << 19) 508 #define SSCR1_RSRE (1 << 20) 509 #define SSCR1_TSRE (1 << 21) 510 #define SSCR1_EBCEI (1 << 29) 511 #define SSITR_INT (7 << 5) 512 #define SSSR_TNF (1 << 2) 513 #define SSSR_RNE (1 << 3) 514 #define SSSR_TFS (1 << 5) 515 #define SSSR_RFS (1 << 6) 516 #define SSSR_ROR (1 << 7) 517 #define SSSR_PINT (1 << 18) 518 #define SSSR_TINT (1 << 19) 519 #define SSSR_EOC (1 << 20) 520 #define SSSR_TUR (1 << 21) 521 #define SSSR_BCE (1 << 23) 522 #define SSSR_RW 0x00bc0080 523 524 static void pxa2xx_ssp_int_update(PXA2xxSSPState *s) 525 { 526 int level = 0; 527 528 level |= s->ssitr & SSITR_INT; 529 level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI); 530 level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM); 531 level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT)); 532 level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE); 533 level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE); 534 level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM); 535 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE); 536 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE); 537 qemu_set_irq(s->irq, !!level); 538 } 539 540 static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s) 541 { 542 s->sssr &= ~(0xf << 12); /* Clear RFL */ 543 s->sssr &= ~(0xf << 8); /* Clear TFL */ 544 s->sssr &= ~SSSR_TFS; 545 s->sssr &= ~SSSR_TNF; 546 if (s->enable) { 547 s->sssr |= ((s->rx_level - 1) & 0xf) << 12; 548 if (s->rx_level >= SSCR1_RFT(s->sscr[1])) 549 s->sssr |= SSSR_RFS; 550 else 551 s->sssr &= ~SSSR_RFS; 552 if (s->rx_level) 553 s->sssr |= SSSR_RNE; 554 else 555 s->sssr &= ~SSSR_RNE; 556 /* TX FIFO is never filled, so it is always in underrun 557 condition if SSP is enabled */ 558 s->sssr |= SSSR_TFS; 559 s->sssr |= SSSR_TNF; 560 } 561 562 pxa2xx_ssp_int_update(s); 563 } 564 565 static uint64_t pxa2xx_ssp_read(void *opaque, hwaddr addr, 566 unsigned size) 567 { 568 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; 569 uint32_t retval; 570 571 switch (addr) { 572 case SSCR0: 573 return s->sscr[0]; 574 case SSCR1: 575 return s->sscr[1]; 576 case SSPSP: 577 return s->sspsp; 578 case SSTO: 579 return s->ssto; 580 case SSITR: 581 return s->ssitr; 582 case SSSR: 583 return s->sssr | s->ssitr; 584 case SSDR: 585 if (!s->enable) 586 return 0xffffffff; 587 if (s->rx_level < 1) { 588 printf("%s: SSP Rx Underrun\n", __FUNCTION__); 589 return 0xffffffff; 590 } 591 s->rx_level --; 592 retval = s->rx_fifo[s->rx_start ++]; 593 s->rx_start &= 0xf; 594 pxa2xx_ssp_fifo_update(s); 595 return retval; 596 case SSTSA: 597 return s->sstsa; 598 case SSRSA: 599 return s->ssrsa; 600 case SSTSS: 601 return 0; 602 case SSACD: 603 return s->ssacd; 604 default: 605 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 606 break; 607 } 608 return 0; 609 } 610 611 static void pxa2xx_ssp_write(void *opaque, hwaddr addr, 612 uint64_t value64, unsigned size) 613 { 614 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; 615 uint32_t value = value64; 616 617 switch (addr) { 618 case SSCR0: 619 s->sscr[0] = value & 0xc7ffffff; 620 s->enable = value & SSCR0_SSE; 621 if (value & SSCR0_MOD) 622 printf("%s: Attempt to use network mode\n", __FUNCTION__); 623 if (s->enable && SSCR0_DSS(value) < 4) 624 printf("%s: Wrong data size: %i bits\n", __FUNCTION__, 625 SSCR0_DSS(value)); 626 if (!(value & SSCR0_SSE)) { 627 s->sssr = 0; 628 s->ssitr = 0; 629 s->rx_level = 0; 630 } 631 pxa2xx_ssp_fifo_update(s); 632 break; 633 634 case SSCR1: 635 s->sscr[1] = value; 636 if (value & (SSCR1_LBM | SSCR1_EFWR)) 637 printf("%s: Attempt to use SSP test mode\n", __FUNCTION__); 638 pxa2xx_ssp_fifo_update(s); 639 break; 640 641 case SSPSP: 642 s->sspsp = value; 643 break; 644 645 case SSTO: 646 s->ssto = value; 647 break; 648 649 case SSITR: 650 s->ssitr = value & SSITR_INT; 651 pxa2xx_ssp_int_update(s); 652 break; 653 654 case SSSR: 655 s->sssr &= ~(value & SSSR_RW); 656 pxa2xx_ssp_int_update(s); 657 break; 658 659 case SSDR: 660 if (SSCR0_UWIRE(s->sscr[0])) { 661 if (s->sscr[1] & SSCR1_MWDS) 662 value &= 0xffff; 663 else 664 value &= 0xff; 665 } else 666 /* Note how 32bits overflow does no harm here */ 667 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1; 668 669 /* Data goes from here to the Tx FIFO and is shifted out from 670 * there directly to the slave, no need to buffer it. 671 */ 672 if (s->enable) { 673 uint32_t readval; 674 readval = ssi_transfer(s->bus, value); 675 if (s->rx_level < 0x10) { 676 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval; 677 } else { 678 s->sssr |= SSSR_ROR; 679 } 680 } 681 pxa2xx_ssp_fifo_update(s); 682 break; 683 684 case SSTSA: 685 s->sstsa = value; 686 break; 687 688 case SSRSA: 689 s->ssrsa = value; 690 break; 691 692 case SSACD: 693 s->ssacd = value; 694 break; 695 696 default: 697 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 698 break; 699 } 700 } 701 702 static const MemoryRegionOps pxa2xx_ssp_ops = { 703 .read = pxa2xx_ssp_read, 704 .write = pxa2xx_ssp_write, 705 .endianness = DEVICE_NATIVE_ENDIAN, 706 }; 707 708 static void pxa2xx_ssp_save(QEMUFile *f, void *opaque) 709 { 710 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; 711 int i; 712 713 qemu_put_be32(f, s->enable); 714 715 qemu_put_be32s(f, &s->sscr[0]); 716 qemu_put_be32s(f, &s->sscr[1]); 717 qemu_put_be32s(f, &s->sspsp); 718 qemu_put_be32s(f, &s->ssto); 719 qemu_put_be32s(f, &s->ssitr); 720 qemu_put_be32s(f, &s->sssr); 721 qemu_put_8s(f, &s->sstsa); 722 qemu_put_8s(f, &s->ssrsa); 723 qemu_put_8s(f, &s->ssacd); 724 725 qemu_put_byte(f, s->rx_level); 726 for (i = 0; i < s->rx_level; i ++) 727 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 0xf]); 728 } 729 730 static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id) 731 { 732 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; 733 int i, v; 734 735 s->enable = qemu_get_be32(f); 736 737 qemu_get_be32s(f, &s->sscr[0]); 738 qemu_get_be32s(f, &s->sscr[1]); 739 qemu_get_be32s(f, &s->sspsp); 740 qemu_get_be32s(f, &s->ssto); 741 qemu_get_be32s(f, &s->ssitr); 742 qemu_get_be32s(f, &s->sssr); 743 qemu_get_8s(f, &s->sstsa); 744 qemu_get_8s(f, &s->ssrsa); 745 qemu_get_8s(f, &s->ssacd); 746 747 v = qemu_get_byte(f); 748 if (v < 0 || v > ARRAY_SIZE(s->rx_fifo)) { 749 return -EINVAL; 750 } 751 s->rx_level = v; 752 s->rx_start = 0; 753 for (i = 0; i < s->rx_level; i ++) 754 s->rx_fifo[i] = qemu_get_byte(f); 755 756 return 0; 757 } 758 759 static int pxa2xx_ssp_init(SysBusDevice *sbd) 760 { 761 DeviceState *dev = DEVICE(sbd); 762 PXA2xxSSPState *s = PXA2XX_SSP(dev); 763 764 sysbus_init_irq(sbd, &s->irq); 765 766 memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_ssp_ops, s, 767 "pxa2xx-ssp", 0x1000); 768 sysbus_init_mmio(sbd, &s->iomem); 769 register_savevm(dev, "pxa2xx_ssp", -1, 0, 770 pxa2xx_ssp_save, pxa2xx_ssp_load, s); 771 772 s->bus = ssi_create_bus(dev, "ssi"); 773 return 0; 774 } 775 776 /* Real-Time Clock */ 777 #define RCNR 0x00 /* RTC Counter register */ 778 #define RTAR 0x04 /* RTC Alarm register */ 779 #define RTSR 0x08 /* RTC Status register */ 780 #define RTTR 0x0c /* RTC Timer Trim register */ 781 #define RDCR 0x10 /* RTC Day Counter register */ 782 #define RYCR 0x14 /* RTC Year Counter register */ 783 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */ 784 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */ 785 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */ 786 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */ 787 #define SWCR 0x28 /* RTC Stopwatch Counter register */ 788 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */ 789 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */ 790 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */ 791 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */ 792 793 #define TYPE_PXA2XX_RTC "pxa2xx_rtc" 794 #define PXA2XX_RTC(obj) \ 795 OBJECT_CHECK(PXA2xxRTCState, (obj), TYPE_PXA2XX_RTC) 796 797 typedef struct { 798 /*< private >*/ 799 SysBusDevice parent_obj; 800 /*< public >*/ 801 802 MemoryRegion iomem; 803 uint32_t rttr; 804 uint32_t rtsr; 805 uint32_t rtar; 806 uint32_t rdar1; 807 uint32_t rdar2; 808 uint32_t ryar1; 809 uint32_t ryar2; 810 uint32_t swar1; 811 uint32_t swar2; 812 uint32_t piar; 813 uint32_t last_rcnr; 814 uint32_t last_rdcr; 815 uint32_t last_rycr; 816 uint32_t last_swcr; 817 uint32_t last_rtcpicr; 818 int64_t last_hz; 819 int64_t last_sw; 820 int64_t last_pi; 821 QEMUTimer *rtc_hz; 822 QEMUTimer *rtc_rdal1; 823 QEMUTimer *rtc_rdal2; 824 QEMUTimer *rtc_swal1; 825 QEMUTimer *rtc_swal2; 826 QEMUTimer *rtc_pi; 827 qemu_irq rtc_irq; 828 } PXA2xxRTCState; 829 830 static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s) 831 { 832 qemu_set_irq(s->rtc_irq, !!(s->rtsr & 0x2553)); 833 } 834 835 static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s) 836 { 837 int64_t rt = qemu_clock_get_ms(rtc_clock); 838 s->last_rcnr += ((rt - s->last_hz) << 15) / 839 (1000 * ((s->rttr & 0xffff) + 1)); 840 s->last_rdcr += ((rt - s->last_hz) << 15) / 841 (1000 * ((s->rttr & 0xffff) + 1)); 842 s->last_hz = rt; 843 } 844 845 static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s) 846 { 847 int64_t rt = qemu_clock_get_ms(rtc_clock); 848 if (s->rtsr & (1 << 12)) 849 s->last_swcr += (rt - s->last_sw) / 10; 850 s->last_sw = rt; 851 } 852 853 static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s) 854 { 855 int64_t rt = qemu_clock_get_ms(rtc_clock); 856 if (s->rtsr & (1 << 15)) 857 s->last_swcr += rt - s->last_pi; 858 s->last_pi = rt; 859 } 860 861 static inline void pxa2xx_rtc_alarm_update(PXA2xxRTCState *s, 862 uint32_t rtsr) 863 { 864 if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0))) 865 timer_mod(s->rtc_hz, s->last_hz + 866 (((s->rtar - s->last_rcnr) * 1000 * 867 ((s->rttr & 0xffff) + 1)) >> 15)); 868 else 869 timer_del(s->rtc_hz); 870 871 if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4))) 872 timer_mod(s->rtc_rdal1, s->last_hz + 873 (((s->rdar1 - s->last_rdcr) * 1000 * 874 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */ 875 else 876 timer_del(s->rtc_rdal1); 877 878 if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6))) 879 timer_mod(s->rtc_rdal2, s->last_hz + 880 (((s->rdar2 - s->last_rdcr) * 1000 * 881 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */ 882 else 883 timer_del(s->rtc_rdal2); 884 885 if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8))) 886 timer_mod(s->rtc_swal1, s->last_sw + 887 (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */ 888 else 889 timer_del(s->rtc_swal1); 890 891 if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10))) 892 timer_mod(s->rtc_swal2, s->last_sw + 893 (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */ 894 else 895 timer_del(s->rtc_swal2); 896 897 if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13))) 898 timer_mod(s->rtc_pi, s->last_pi + 899 (s->piar & 0xffff) - s->last_rtcpicr); 900 else 901 timer_del(s->rtc_pi); 902 } 903 904 static inline void pxa2xx_rtc_hz_tick(void *opaque) 905 { 906 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 907 s->rtsr |= (1 << 0); 908 pxa2xx_rtc_alarm_update(s, s->rtsr); 909 pxa2xx_rtc_int_update(s); 910 } 911 912 static inline void pxa2xx_rtc_rdal1_tick(void *opaque) 913 { 914 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 915 s->rtsr |= (1 << 4); 916 pxa2xx_rtc_alarm_update(s, s->rtsr); 917 pxa2xx_rtc_int_update(s); 918 } 919 920 static inline void pxa2xx_rtc_rdal2_tick(void *opaque) 921 { 922 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 923 s->rtsr |= (1 << 6); 924 pxa2xx_rtc_alarm_update(s, s->rtsr); 925 pxa2xx_rtc_int_update(s); 926 } 927 928 static inline void pxa2xx_rtc_swal1_tick(void *opaque) 929 { 930 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 931 s->rtsr |= (1 << 8); 932 pxa2xx_rtc_alarm_update(s, s->rtsr); 933 pxa2xx_rtc_int_update(s); 934 } 935 936 static inline void pxa2xx_rtc_swal2_tick(void *opaque) 937 { 938 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 939 s->rtsr |= (1 << 10); 940 pxa2xx_rtc_alarm_update(s, s->rtsr); 941 pxa2xx_rtc_int_update(s); 942 } 943 944 static inline void pxa2xx_rtc_pi_tick(void *opaque) 945 { 946 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 947 s->rtsr |= (1 << 13); 948 pxa2xx_rtc_piupdate(s); 949 s->last_rtcpicr = 0; 950 pxa2xx_rtc_alarm_update(s, s->rtsr); 951 pxa2xx_rtc_int_update(s); 952 } 953 954 static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr, 955 unsigned size) 956 { 957 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 958 959 switch (addr) { 960 case RTTR: 961 return s->rttr; 962 case RTSR: 963 return s->rtsr; 964 case RTAR: 965 return s->rtar; 966 case RDAR1: 967 return s->rdar1; 968 case RDAR2: 969 return s->rdar2; 970 case RYAR1: 971 return s->ryar1; 972 case RYAR2: 973 return s->ryar2; 974 case SWAR1: 975 return s->swar1; 976 case SWAR2: 977 return s->swar2; 978 case PIAR: 979 return s->piar; 980 case RCNR: 981 return s->last_rcnr + 982 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / 983 (1000 * ((s->rttr & 0xffff) + 1)); 984 case RDCR: 985 return s->last_rdcr + 986 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / 987 (1000 * ((s->rttr & 0xffff) + 1)); 988 case RYCR: 989 return s->last_rycr; 990 case SWCR: 991 if (s->rtsr & (1 << 12)) 992 return s->last_swcr + 993 (qemu_clock_get_ms(rtc_clock) - s->last_sw) / 10; 994 else 995 return s->last_swcr; 996 default: 997 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 998 break; 999 } 1000 return 0; 1001 } 1002 1003 static void pxa2xx_rtc_write(void *opaque, hwaddr addr, 1004 uint64_t value64, unsigned size) 1005 { 1006 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 1007 uint32_t value = value64; 1008 1009 switch (addr) { 1010 case RTTR: 1011 if (!(s->rttr & (1U << 31))) { 1012 pxa2xx_rtc_hzupdate(s); 1013 s->rttr = value; 1014 pxa2xx_rtc_alarm_update(s, s->rtsr); 1015 } 1016 break; 1017 1018 case RTSR: 1019 if ((s->rtsr ^ value) & (1 << 15)) 1020 pxa2xx_rtc_piupdate(s); 1021 1022 if ((s->rtsr ^ value) & (1 << 12)) 1023 pxa2xx_rtc_swupdate(s); 1024 1025 if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac)) 1026 pxa2xx_rtc_alarm_update(s, value); 1027 1028 s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac)); 1029 pxa2xx_rtc_int_update(s); 1030 break; 1031 1032 case RTAR: 1033 s->rtar = value; 1034 pxa2xx_rtc_alarm_update(s, s->rtsr); 1035 break; 1036 1037 case RDAR1: 1038 s->rdar1 = value; 1039 pxa2xx_rtc_alarm_update(s, s->rtsr); 1040 break; 1041 1042 case RDAR2: 1043 s->rdar2 = value; 1044 pxa2xx_rtc_alarm_update(s, s->rtsr); 1045 break; 1046 1047 case RYAR1: 1048 s->ryar1 = value; 1049 pxa2xx_rtc_alarm_update(s, s->rtsr); 1050 break; 1051 1052 case RYAR2: 1053 s->ryar2 = value; 1054 pxa2xx_rtc_alarm_update(s, s->rtsr); 1055 break; 1056 1057 case SWAR1: 1058 pxa2xx_rtc_swupdate(s); 1059 s->swar1 = value; 1060 s->last_swcr = 0; 1061 pxa2xx_rtc_alarm_update(s, s->rtsr); 1062 break; 1063 1064 case SWAR2: 1065 s->swar2 = value; 1066 pxa2xx_rtc_alarm_update(s, s->rtsr); 1067 break; 1068 1069 case PIAR: 1070 s->piar = value; 1071 pxa2xx_rtc_alarm_update(s, s->rtsr); 1072 break; 1073 1074 case RCNR: 1075 pxa2xx_rtc_hzupdate(s); 1076 s->last_rcnr = value; 1077 pxa2xx_rtc_alarm_update(s, s->rtsr); 1078 break; 1079 1080 case RDCR: 1081 pxa2xx_rtc_hzupdate(s); 1082 s->last_rdcr = value; 1083 pxa2xx_rtc_alarm_update(s, s->rtsr); 1084 break; 1085 1086 case RYCR: 1087 s->last_rycr = value; 1088 break; 1089 1090 case SWCR: 1091 pxa2xx_rtc_swupdate(s); 1092 s->last_swcr = value; 1093 pxa2xx_rtc_alarm_update(s, s->rtsr); 1094 break; 1095 1096 case RTCPICR: 1097 pxa2xx_rtc_piupdate(s); 1098 s->last_rtcpicr = value & 0xffff; 1099 pxa2xx_rtc_alarm_update(s, s->rtsr); 1100 break; 1101 1102 default: 1103 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1104 } 1105 } 1106 1107 static const MemoryRegionOps pxa2xx_rtc_ops = { 1108 .read = pxa2xx_rtc_read, 1109 .write = pxa2xx_rtc_write, 1110 .endianness = DEVICE_NATIVE_ENDIAN, 1111 }; 1112 1113 static int pxa2xx_rtc_init(SysBusDevice *dev) 1114 { 1115 PXA2xxRTCState *s = PXA2XX_RTC(dev); 1116 struct tm tm; 1117 int wom; 1118 1119 s->rttr = 0x7fff; 1120 s->rtsr = 0; 1121 1122 qemu_get_timedate(&tm, 0); 1123 wom = ((tm.tm_mday - 1) / 7) + 1; 1124 1125 s->last_rcnr = (uint32_t) mktimegm(&tm); 1126 s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) | 1127 (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec; 1128 s->last_rycr = ((tm.tm_year + 1900) << 9) | 1129 ((tm.tm_mon + 1) << 5) | tm.tm_mday; 1130 s->last_swcr = (tm.tm_hour << 19) | 1131 (tm.tm_min << 13) | (tm.tm_sec << 7); 1132 s->last_rtcpicr = 0; 1133 s->last_hz = s->last_sw = s->last_pi = qemu_clock_get_ms(rtc_clock); 1134 1135 s->rtc_hz = timer_new_ms(rtc_clock, pxa2xx_rtc_hz_tick, s); 1136 s->rtc_rdal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal1_tick, s); 1137 s->rtc_rdal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal2_tick, s); 1138 s->rtc_swal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal1_tick, s); 1139 s->rtc_swal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal2_tick, s); 1140 s->rtc_pi = timer_new_ms(rtc_clock, pxa2xx_rtc_pi_tick, s); 1141 1142 sysbus_init_irq(dev, &s->rtc_irq); 1143 1144 memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_rtc_ops, s, 1145 "pxa2xx-rtc", 0x10000); 1146 sysbus_init_mmio(dev, &s->iomem); 1147 1148 return 0; 1149 } 1150 1151 static void pxa2xx_rtc_pre_save(void *opaque) 1152 { 1153 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 1154 1155 pxa2xx_rtc_hzupdate(s); 1156 pxa2xx_rtc_piupdate(s); 1157 pxa2xx_rtc_swupdate(s); 1158 } 1159 1160 static int pxa2xx_rtc_post_load(void *opaque, int version_id) 1161 { 1162 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 1163 1164 pxa2xx_rtc_alarm_update(s, s->rtsr); 1165 1166 return 0; 1167 } 1168 1169 static const VMStateDescription vmstate_pxa2xx_rtc_regs = { 1170 .name = "pxa2xx_rtc", 1171 .version_id = 0, 1172 .minimum_version_id = 0, 1173 .pre_save = pxa2xx_rtc_pre_save, 1174 .post_load = pxa2xx_rtc_post_load, 1175 .fields = (VMStateField[]) { 1176 VMSTATE_UINT32(rttr, PXA2xxRTCState), 1177 VMSTATE_UINT32(rtsr, PXA2xxRTCState), 1178 VMSTATE_UINT32(rtar, PXA2xxRTCState), 1179 VMSTATE_UINT32(rdar1, PXA2xxRTCState), 1180 VMSTATE_UINT32(rdar2, PXA2xxRTCState), 1181 VMSTATE_UINT32(ryar1, PXA2xxRTCState), 1182 VMSTATE_UINT32(ryar2, PXA2xxRTCState), 1183 VMSTATE_UINT32(swar1, PXA2xxRTCState), 1184 VMSTATE_UINT32(swar2, PXA2xxRTCState), 1185 VMSTATE_UINT32(piar, PXA2xxRTCState), 1186 VMSTATE_UINT32(last_rcnr, PXA2xxRTCState), 1187 VMSTATE_UINT32(last_rdcr, PXA2xxRTCState), 1188 VMSTATE_UINT32(last_rycr, PXA2xxRTCState), 1189 VMSTATE_UINT32(last_swcr, PXA2xxRTCState), 1190 VMSTATE_UINT32(last_rtcpicr, PXA2xxRTCState), 1191 VMSTATE_INT64(last_hz, PXA2xxRTCState), 1192 VMSTATE_INT64(last_sw, PXA2xxRTCState), 1193 VMSTATE_INT64(last_pi, PXA2xxRTCState), 1194 VMSTATE_END_OF_LIST(), 1195 }, 1196 }; 1197 1198 static void pxa2xx_rtc_sysbus_class_init(ObjectClass *klass, void *data) 1199 { 1200 DeviceClass *dc = DEVICE_CLASS(klass); 1201 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 1202 1203 k->init = pxa2xx_rtc_init; 1204 dc->desc = "PXA2xx RTC Controller"; 1205 dc->vmsd = &vmstate_pxa2xx_rtc_regs; 1206 } 1207 1208 static const TypeInfo pxa2xx_rtc_sysbus_info = { 1209 .name = TYPE_PXA2XX_RTC, 1210 .parent = TYPE_SYS_BUS_DEVICE, 1211 .instance_size = sizeof(PXA2xxRTCState), 1212 .class_init = pxa2xx_rtc_sysbus_class_init, 1213 }; 1214 1215 /* I2C Interface */ 1216 1217 #define TYPE_PXA2XX_I2C_SLAVE "pxa2xx-i2c-slave" 1218 #define PXA2XX_I2C_SLAVE(obj) \ 1219 OBJECT_CHECK(PXA2xxI2CSlaveState, (obj), TYPE_PXA2XX_I2C_SLAVE) 1220 1221 typedef struct PXA2xxI2CSlaveState { 1222 I2CSlave parent_obj; 1223 1224 PXA2xxI2CState *host; 1225 } PXA2xxI2CSlaveState; 1226 1227 #define TYPE_PXA2XX_I2C "pxa2xx_i2c" 1228 #define PXA2XX_I2C(obj) \ 1229 OBJECT_CHECK(PXA2xxI2CState, (obj), TYPE_PXA2XX_I2C) 1230 1231 struct PXA2xxI2CState { 1232 /*< private >*/ 1233 SysBusDevice parent_obj; 1234 /*< public >*/ 1235 1236 MemoryRegion iomem; 1237 PXA2xxI2CSlaveState *slave; 1238 I2CBus *bus; 1239 qemu_irq irq; 1240 uint32_t offset; 1241 uint32_t region_size; 1242 1243 uint16_t control; 1244 uint16_t status; 1245 uint8_t ibmr; 1246 uint8_t data; 1247 }; 1248 1249 #define IBMR 0x80 /* I2C Bus Monitor register */ 1250 #define IDBR 0x88 /* I2C Data Buffer register */ 1251 #define ICR 0x90 /* I2C Control register */ 1252 #define ISR 0x98 /* I2C Status register */ 1253 #define ISAR 0xa0 /* I2C Slave Address register */ 1254 1255 static void pxa2xx_i2c_update(PXA2xxI2CState *s) 1256 { 1257 uint16_t level = 0; 1258 level |= s->status & s->control & (1 << 10); /* BED */ 1259 level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */ 1260 level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */ 1261 level |= s->status & (1 << 9); /* SAD */ 1262 qemu_set_irq(s->irq, !!level); 1263 } 1264 1265 /* These are only stubs now. */ 1266 static void pxa2xx_i2c_event(I2CSlave *i2c, enum i2c_event event) 1267 { 1268 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c); 1269 PXA2xxI2CState *s = slave->host; 1270 1271 switch (event) { 1272 case I2C_START_SEND: 1273 s->status |= (1 << 9); /* set SAD */ 1274 s->status &= ~(1 << 0); /* clear RWM */ 1275 break; 1276 case I2C_START_RECV: 1277 s->status |= (1 << 9); /* set SAD */ 1278 s->status |= 1 << 0; /* set RWM */ 1279 break; 1280 case I2C_FINISH: 1281 s->status |= (1 << 4); /* set SSD */ 1282 break; 1283 case I2C_NACK: 1284 s->status |= 1 << 1; /* set ACKNAK */ 1285 break; 1286 } 1287 pxa2xx_i2c_update(s); 1288 } 1289 1290 static int pxa2xx_i2c_rx(I2CSlave *i2c) 1291 { 1292 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c); 1293 PXA2xxI2CState *s = slave->host; 1294 1295 if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) { 1296 return 0; 1297 } 1298 1299 if (s->status & (1 << 0)) { /* RWM */ 1300 s->status |= 1 << 6; /* set ITE */ 1301 } 1302 pxa2xx_i2c_update(s); 1303 1304 return s->data; 1305 } 1306 1307 static int pxa2xx_i2c_tx(I2CSlave *i2c, uint8_t data) 1308 { 1309 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c); 1310 PXA2xxI2CState *s = slave->host; 1311 1312 if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) { 1313 return 1; 1314 } 1315 1316 if (!(s->status & (1 << 0))) { /* RWM */ 1317 s->status |= 1 << 7; /* set IRF */ 1318 s->data = data; 1319 } 1320 pxa2xx_i2c_update(s); 1321 1322 return 1; 1323 } 1324 1325 static uint64_t pxa2xx_i2c_read(void *opaque, hwaddr addr, 1326 unsigned size) 1327 { 1328 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; 1329 I2CSlave *slave; 1330 1331 addr -= s->offset; 1332 switch (addr) { 1333 case ICR: 1334 return s->control; 1335 case ISR: 1336 return s->status | (i2c_bus_busy(s->bus) << 2); 1337 case ISAR: 1338 slave = I2C_SLAVE(s->slave); 1339 return slave->address; 1340 case IDBR: 1341 return s->data; 1342 case IBMR: 1343 if (s->status & (1 << 2)) 1344 s->ibmr ^= 3; /* Fake SCL and SDA pin changes */ 1345 else 1346 s->ibmr = 0; 1347 return s->ibmr; 1348 default: 1349 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1350 break; 1351 } 1352 return 0; 1353 } 1354 1355 static void pxa2xx_i2c_write(void *opaque, hwaddr addr, 1356 uint64_t value64, unsigned size) 1357 { 1358 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; 1359 uint32_t value = value64; 1360 int ack; 1361 1362 addr -= s->offset; 1363 switch (addr) { 1364 case ICR: 1365 s->control = value & 0xfff7; 1366 if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */ 1367 /* TODO: slave mode */ 1368 if (value & (1 << 0)) { /* START condition */ 1369 if (s->data & 1) 1370 s->status |= 1 << 0; /* set RWM */ 1371 else 1372 s->status &= ~(1 << 0); /* clear RWM */ 1373 ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1); 1374 } else { 1375 if (s->status & (1 << 0)) { /* RWM */ 1376 s->data = i2c_recv(s->bus); 1377 if (value & (1 << 2)) /* ACKNAK */ 1378 i2c_nack(s->bus); 1379 ack = 1; 1380 } else 1381 ack = !i2c_send(s->bus, s->data); 1382 } 1383 1384 if (value & (1 << 1)) /* STOP condition */ 1385 i2c_end_transfer(s->bus); 1386 1387 if (ack) { 1388 if (value & (1 << 0)) /* START condition */ 1389 s->status |= 1 << 6; /* set ITE */ 1390 else 1391 if (s->status & (1 << 0)) /* RWM */ 1392 s->status |= 1 << 7; /* set IRF */ 1393 else 1394 s->status |= 1 << 6; /* set ITE */ 1395 s->status &= ~(1 << 1); /* clear ACKNAK */ 1396 } else { 1397 s->status |= 1 << 6; /* set ITE */ 1398 s->status |= 1 << 10; /* set BED */ 1399 s->status |= 1 << 1; /* set ACKNAK */ 1400 } 1401 } 1402 if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */ 1403 if (value & (1 << 4)) /* MA */ 1404 i2c_end_transfer(s->bus); 1405 pxa2xx_i2c_update(s); 1406 break; 1407 1408 case ISR: 1409 s->status &= ~(value & 0x07f0); 1410 pxa2xx_i2c_update(s); 1411 break; 1412 1413 case ISAR: 1414 i2c_set_slave_address(I2C_SLAVE(s->slave), value & 0x7f); 1415 break; 1416 1417 case IDBR: 1418 s->data = value & 0xff; 1419 break; 1420 1421 default: 1422 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1423 } 1424 } 1425 1426 static const MemoryRegionOps pxa2xx_i2c_ops = { 1427 .read = pxa2xx_i2c_read, 1428 .write = pxa2xx_i2c_write, 1429 .endianness = DEVICE_NATIVE_ENDIAN, 1430 }; 1431 1432 static const VMStateDescription vmstate_pxa2xx_i2c_slave = { 1433 .name = "pxa2xx_i2c_slave", 1434 .version_id = 1, 1435 .minimum_version_id = 1, 1436 .fields = (VMStateField[]) { 1437 VMSTATE_I2C_SLAVE(parent_obj, PXA2xxI2CSlaveState), 1438 VMSTATE_END_OF_LIST() 1439 } 1440 }; 1441 1442 static const VMStateDescription vmstate_pxa2xx_i2c = { 1443 .name = "pxa2xx_i2c", 1444 .version_id = 1, 1445 .minimum_version_id = 1, 1446 .fields = (VMStateField[]) { 1447 VMSTATE_UINT16(control, PXA2xxI2CState), 1448 VMSTATE_UINT16(status, PXA2xxI2CState), 1449 VMSTATE_UINT8(ibmr, PXA2xxI2CState), 1450 VMSTATE_UINT8(data, PXA2xxI2CState), 1451 VMSTATE_STRUCT_POINTER(slave, PXA2xxI2CState, 1452 vmstate_pxa2xx_i2c_slave, PXA2xxI2CSlaveState), 1453 VMSTATE_END_OF_LIST() 1454 } 1455 }; 1456 1457 static int pxa2xx_i2c_slave_init(I2CSlave *i2c) 1458 { 1459 /* Nothing to do. */ 1460 return 0; 1461 } 1462 1463 static void pxa2xx_i2c_slave_class_init(ObjectClass *klass, void *data) 1464 { 1465 I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); 1466 1467 k->init = pxa2xx_i2c_slave_init; 1468 k->event = pxa2xx_i2c_event; 1469 k->recv = pxa2xx_i2c_rx; 1470 k->send = pxa2xx_i2c_tx; 1471 } 1472 1473 static const TypeInfo pxa2xx_i2c_slave_info = { 1474 .name = TYPE_PXA2XX_I2C_SLAVE, 1475 .parent = TYPE_I2C_SLAVE, 1476 .instance_size = sizeof(PXA2xxI2CSlaveState), 1477 .class_init = pxa2xx_i2c_slave_class_init, 1478 }; 1479 1480 PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base, 1481 qemu_irq irq, uint32_t region_size) 1482 { 1483 DeviceState *dev; 1484 SysBusDevice *i2c_dev; 1485 PXA2xxI2CState *s; 1486 I2CBus *i2cbus; 1487 1488 dev = qdev_create(NULL, TYPE_PXA2XX_I2C); 1489 qdev_prop_set_uint32(dev, "size", region_size + 1); 1490 qdev_prop_set_uint32(dev, "offset", base & region_size); 1491 qdev_init_nofail(dev); 1492 1493 i2c_dev = SYS_BUS_DEVICE(dev); 1494 sysbus_mmio_map(i2c_dev, 0, base & ~region_size); 1495 sysbus_connect_irq(i2c_dev, 0, irq); 1496 1497 s = PXA2XX_I2C(i2c_dev); 1498 /* FIXME: Should the slave device really be on a separate bus? */ 1499 i2cbus = i2c_init_bus(dev, "dummy"); 1500 dev = i2c_create_slave(i2cbus, TYPE_PXA2XX_I2C_SLAVE, 0); 1501 s->slave = PXA2XX_I2C_SLAVE(dev); 1502 s->slave->host = s; 1503 1504 return s; 1505 } 1506 1507 static int pxa2xx_i2c_initfn(SysBusDevice *sbd) 1508 { 1509 DeviceState *dev = DEVICE(sbd); 1510 PXA2xxI2CState *s = PXA2XX_I2C(dev); 1511 1512 s->bus = i2c_init_bus(dev, "i2c"); 1513 1514 memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_i2c_ops, s, 1515 "pxa2xx-i2c", s->region_size); 1516 sysbus_init_mmio(sbd, &s->iomem); 1517 sysbus_init_irq(sbd, &s->irq); 1518 1519 return 0; 1520 } 1521 1522 I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s) 1523 { 1524 return s->bus; 1525 } 1526 1527 static Property pxa2xx_i2c_properties[] = { 1528 DEFINE_PROP_UINT32("size", PXA2xxI2CState, region_size, 0x10000), 1529 DEFINE_PROP_UINT32("offset", PXA2xxI2CState, offset, 0), 1530 DEFINE_PROP_END_OF_LIST(), 1531 }; 1532 1533 static void pxa2xx_i2c_class_init(ObjectClass *klass, void *data) 1534 { 1535 DeviceClass *dc = DEVICE_CLASS(klass); 1536 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 1537 1538 k->init = pxa2xx_i2c_initfn; 1539 dc->desc = "PXA2xx I2C Bus Controller"; 1540 dc->vmsd = &vmstate_pxa2xx_i2c; 1541 dc->props = pxa2xx_i2c_properties; 1542 } 1543 1544 static const TypeInfo pxa2xx_i2c_info = { 1545 .name = TYPE_PXA2XX_I2C, 1546 .parent = TYPE_SYS_BUS_DEVICE, 1547 .instance_size = sizeof(PXA2xxI2CState), 1548 .class_init = pxa2xx_i2c_class_init, 1549 }; 1550 1551 /* PXA Inter-IC Sound Controller */ 1552 static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s) 1553 { 1554 i2s->rx_len = 0; 1555 i2s->tx_len = 0; 1556 i2s->fifo_len = 0; 1557 i2s->clk = 0x1a; 1558 i2s->control[0] = 0x00; 1559 i2s->control[1] = 0x00; 1560 i2s->status = 0x00; 1561 i2s->mask = 0x00; 1562 } 1563 1564 #define SACR_TFTH(val) ((val >> 8) & 0xf) 1565 #define SACR_RFTH(val) ((val >> 12) & 0xf) 1566 #define SACR_DREC(val) (val & (1 << 3)) 1567 #define SACR_DPRL(val) (val & (1 << 4)) 1568 1569 static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s) 1570 { 1571 int rfs, tfs; 1572 rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len && 1573 !SACR_DREC(i2s->control[1]); 1574 tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) && 1575 i2s->enable && !SACR_DPRL(i2s->control[1]); 1576 1577 qemu_set_irq(i2s->rx_dma, rfs); 1578 qemu_set_irq(i2s->tx_dma, tfs); 1579 1580 i2s->status &= 0xe0; 1581 if (i2s->fifo_len < 16 || !i2s->enable) 1582 i2s->status |= 1 << 0; /* TNF */ 1583 if (i2s->rx_len) 1584 i2s->status |= 1 << 1; /* RNE */ 1585 if (i2s->enable) 1586 i2s->status |= 1 << 2; /* BSY */ 1587 if (tfs) 1588 i2s->status |= 1 << 3; /* TFS */ 1589 if (rfs) 1590 i2s->status |= 1 << 4; /* RFS */ 1591 if (!(i2s->tx_len && i2s->enable)) 1592 i2s->status |= i2s->fifo_len << 8; /* TFL */ 1593 i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */ 1594 1595 qemu_set_irq(i2s->irq, i2s->status & i2s->mask); 1596 } 1597 1598 #define SACR0 0x00 /* Serial Audio Global Control register */ 1599 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */ 1600 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */ 1601 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */ 1602 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */ 1603 #define SADIV 0x60 /* Serial Audio Clock Divider register */ 1604 #define SADR 0x80 /* Serial Audio Data register */ 1605 1606 static uint64_t pxa2xx_i2s_read(void *opaque, hwaddr addr, 1607 unsigned size) 1608 { 1609 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; 1610 1611 switch (addr) { 1612 case SACR0: 1613 return s->control[0]; 1614 case SACR1: 1615 return s->control[1]; 1616 case SASR0: 1617 return s->status; 1618 case SAIMR: 1619 return s->mask; 1620 case SAICR: 1621 return 0; 1622 case SADIV: 1623 return s->clk; 1624 case SADR: 1625 if (s->rx_len > 0) { 1626 s->rx_len --; 1627 pxa2xx_i2s_update(s); 1628 return s->codec_in(s->opaque); 1629 } 1630 return 0; 1631 default: 1632 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1633 break; 1634 } 1635 return 0; 1636 } 1637 1638 static void pxa2xx_i2s_write(void *opaque, hwaddr addr, 1639 uint64_t value, unsigned size) 1640 { 1641 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; 1642 uint32_t *sample; 1643 1644 switch (addr) { 1645 case SACR0: 1646 if (value & (1 << 3)) /* RST */ 1647 pxa2xx_i2s_reset(s); 1648 s->control[0] = value & 0xff3d; 1649 if (!s->enable && (value & 1) && s->tx_len) { /* ENB */ 1650 for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++) 1651 s->codec_out(s->opaque, *sample); 1652 s->status &= ~(1 << 7); /* I2SOFF */ 1653 } 1654 if (value & (1 << 4)) /* EFWR */ 1655 printf("%s: Attempt to use special function\n", __FUNCTION__); 1656 s->enable = (value & 9) == 1; /* ENB && !RST*/ 1657 pxa2xx_i2s_update(s); 1658 break; 1659 case SACR1: 1660 s->control[1] = value & 0x0039; 1661 if (value & (1 << 5)) /* ENLBF */ 1662 printf("%s: Attempt to use loopback function\n", __FUNCTION__); 1663 if (value & (1 << 4)) /* DPRL */ 1664 s->fifo_len = 0; 1665 pxa2xx_i2s_update(s); 1666 break; 1667 case SAIMR: 1668 s->mask = value & 0x0078; 1669 pxa2xx_i2s_update(s); 1670 break; 1671 case SAICR: 1672 s->status &= ~(value & (3 << 5)); 1673 pxa2xx_i2s_update(s); 1674 break; 1675 case SADIV: 1676 s->clk = value & 0x007f; 1677 break; 1678 case SADR: 1679 if (s->tx_len && s->enable) { 1680 s->tx_len --; 1681 pxa2xx_i2s_update(s); 1682 s->codec_out(s->opaque, value); 1683 } else if (s->fifo_len < 16) { 1684 s->fifo[s->fifo_len ++] = value; 1685 pxa2xx_i2s_update(s); 1686 } 1687 break; 1688 default: 1689 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1690 } 1691 } 1692 1693 static const MemoryRegionOps pxa2xx_i2s_ops = { 1694 .read = pxa2xx_i2s_read, 1695 .write = pxa2xx_i2s_write, 1696 .endianness = DEVICE_NATIVE_ENDIAN, 1697 }; 1698 1699 static const VMStateDescription vmstate_pxa2xx_i2s = { 1700 .name = "pxa2xx_i2s", 1701 .version_id = 0, 1702 .minimum_version_id = 0, 1703 .fields = (VMStateField[]) { 1704 VMSTATE_UINT32_ARRAY(control, PXA2xxI2SState, 2), 1705 VMSTATE_UINT32(status, PXA2xxI2SState), 1706 VMSTATE_UINT32(mask, PXA2xxI2SState), 1707 VMSTATE_UINT32(clk, PXA2xxI2SState), 1708 VMSTATE_INT32(enable, PXA2xxI2SState), 1709 VMSTATE_INT32(rx_len, PXA2xxI2SState), 1710 VMSTATE_INT32(tx_len, PXA2xxI2SState), 1711 VMSTATE_INT32(fifo_len, PXA2xxI2SState), 1712 VMSTATE_END_OF_LIST() 1713 } 1714 }; 1715 1716 static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx) 1717 { 1718 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; 1719 uint32_t *sample; 1720 1721 /* Signal FIFO errors */ 1722 if (s->enable && s->tx_len) 1723 s->status |= 1 << 5; /* TUR */ 1724 if (s->enable && s->rx_len) 1725 s->status |= 1 << 6; /* ROR */ 1726 1727 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to 1728 * handle the cases where it makes a difference. */ 1729 s->tx_len = tx - s->fifo_len; 1730 s->rx_len = rx; 1731 /* Note that is s->codec_out wasn't set, we wouldn't get called. */ 1732 if (s->enable) 1733 for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++) 1734 s->codec_out(s->opaque, *sample); 1735 pxa2xx_i2s_update(s); 1736 } 1737 1738 static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem, 1739 hwaddr base, 1740 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma) 1741 { 1742 PXA2xxI2SState *s = (PXA2xxI2SState *) 1743 g_malloc0(sizeof(PXA2xxI2SState)); 1744 1745 s->irq = irq; 1746 s->rx_dma = rx_dma; 1747 s->tx_dma = tx_dma; 1748 s->data_req = pxa2xx_i2s_data_req; 1749 1750 pxa2xx_i2s_reset(s); 1751 1752 memory_region_init_io(&s->iomem, NULL, &pxa2xx_i2s_ops, s, 1753 "pxa2xx-i2s", 0x100000); 1754 memory_region_add_subregion(sysmem, base, &s->iomem); 1755 1756 vmstate_register(NULL, base, &vmstate_pxa2xx_i2s, s); 1757 1758 return s; 1759 } 1760 1761 /* PXA Fast Infra-red Communications Port */ 1762 struct PXA2xxFIrState { 1763 MemoryRegion iomem; 1764 qemu_irq irq; 1765 qemu_irq rx_dma; 1766 qemu_irq tx_dma; 1767 int enable; 1768 CharDriverState *chr; 1769 1770 uint8_t control[3]; 1771 uint8_t status[2]; 1772 1773 int rx_len; 1774 int rx_start; 1775 uint8_t rx_fifo[64]; 1776 }; 1777 1778 static void pxa2xx_fir_reset(PXA2xxFIrState *s) 1779 { 1780 s->control[0] = 0x00; 1781 s->control[1] = 0x00; 1782 s->control[2] = 0x00; 1783 s->status[0] = 0x00; 1784 s->status[1] = 0x00; 1785 s->enable = 0; 1786 } 1787 1788 static inline void pxa2xx_fir_update(PXA2xxFIrState *s) 1789 { 1790 static const int tresh[4] = { 8, 16, 32, 0 }; 1791 int intr = 0; 1792 if ((s->control[0] & (1 << 4)) && /* RXE */ 1793 s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */ 1794 s->status[0] |= 1 << 4; /* RFS */ 1795 else 1796 s->status[0] &= ~(1 << 4); /* RFS */ 1797 if (s->control[0] & (1 << 3)) /* TXE */ 1798 s->status[0] |= 1 << 3; /* TFS */ 1799 else 1800 s->status[0] &= ~(1 << 3); /* TFS */ 1801 if (s->rx_len) 1802 s->status[1] |= 1 << 2; /* RNE */ 1803 else 1804 s->status[1] &= ~(1 << 2); /* RNE */ 1805 if (s->control[0] & (1 << 4)) /* RXE */ 1806 s->status[1] |= 1 << 0; /* RSY */ 1807 else 1808 s->status[1] &= ~(1 << 0); /* RSY */ 1809 1810 intr |= (s->control[0] & (1 << 5)) && /* RIE */ 1811 (s->status[0] & (1 << 4)); /* RFS */ 1812 intr |= (s->control[0] & (1 << 6)) && /* TIE */ 1813 (s->status[0] & (1 << 3)); /* TFS */ 1814 intr |= (s->control[2] & (1 << 4)) && /* TRAIL */ 1815 (s->status[0] & (1 << 6)); /* EOC */ 1816 intr |= (s->control[0] & (1 << 2)) && /* TUS */ 1817 (s->status[0] & (1 << 1)); /* TUR */ 1818 intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */ 1819 1820 qemu_set_irq(s->rx_dma, (s->status[0] >> 4) & 1); 1821 qemu_set_irq(s->tx_dma, (s->status[0] >> 3) & 1); 1822 1823 qemu_set_irq(s->irq, intr && s->enable); 1824 } 1825 1826 #define ICCR0 0x00 /* FICP Control register 0 */ 1827 #define ICCR1 0x04 /* FICP Control register 1 */ 1828 #define ICCR2 0x08 /* FICP Control register 2 */ 1829 #define ICDR 0x0c /* FICP Data register */ 1830 #define ICSR0 0x14 /* FICP Status register 0 */ 1831 #define ICSR1 0x18 /* FICP Status register 1 */ 1832 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */ 1833 1834 static uint64_t pxa2xx_fir_read(void *opaque, hwaddr addr, 1835 unsigned size) 1836 { 1837 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1838 uint8_t ret; 1839 1840 switch (addr) { 1841 case ICCR0: 1842 return s->control[0]; 1843 case ICCR1: 1844 return s->control[1]; 1845 case ICCR2: 1846 return s->control[2]; 1847 case ICDR: 1848 s->status[0] &= ~0x01; 1849 s->status[1] &= ~0x72; 1850 if (s->rx_len) { 1851 s->rx_len --; 1852 ret = s->rx_fifo[s->rx_start ++]; 1853 s->rx_start &= 63; 1854 pxa2xx_fir_update(s); 1855 return ret; 1856 } 1857 printf("%s: Rx FIFO underrun.\n", __FUNCTION__); 1858 break; 1859 case ICSR0: 1860 return s->status[0]; 1861 case ICSR1: 1862 return s->status[1] | (1 << 3); /* TNF */ 1863 case ICFOR: 1864 return s->rx_len; 1865 default: 1866 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1867 break; 1868 } 1869 return 0; 1870 } 1871 1872 static void pxa2xx_fir_write(void *opaque, hwaddr addr, 1873 uint64_t value64, unsigned size) 1874 { 1875 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1876 uint32_t value = value64; 1877 uint8_t ch; 1878 1879 switch (addr) { 1880 case ICCR0: 1881 s->control[0] = value; 1882 if (!(value & (1 << 4))) /* RXE */ 1883 s->rx_len = s->rx_start = 0; 1884 if (!(value & (1 << 3))) { /* TXE */ 1885 /* Nop */ 1886 } 1887 s->enable = value & 1; /* ITR */ 1888 if (!s->enable) 1889 s->status[0] = 0; 1890 pxa2xx_fir_update(s); 1891 break; 1892 case ICCR1: 1893 s->control[1] = value; 1894 break; 1895 case ICCR2: 1896 s->control[2] = value & 0x3f; 1897 pxa2xx_fir_update(s); 1898 break; 1899 case ICDR: 1900 if (s->control[2] & (1 << 2)) /* TXP */ 1901 ch = value; 1902 else 1903 ch = ~value; 1904 if (s->chr && s->enable && (s->control[0] & (1 << 3))) /* TXE */ 1905 qemu_chr_fe_write(s->chr, &ch, 1); 1906 break; 1907 case ICSR0: 1908 s->status[0] &= ~(value & 0x66); 1909 pxa2xx_fir_update(s); 1910 break; 1911 case ICFOR: 1912 break; 1913 default: 1914 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1915 } 1916 } 1917 1918 static const MemoryRegionOps pxa2xx_fir_ops = { 1919 .read = pxa2xx_fir_read, 1920 .write = pxa2xx_fir_write, 1921 .endianness = DEVICE_NATIVE_ENDIAN, 1922 }; 1923 1924 static int pxa2xx_fir_is_empty(void *opaque) 1925 { 1926 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1927 return (s->rx_len < 64); 1928 } 1929 1930 static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size) 1931 { 1932 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1933 if (!(s->control[0] & (1 << 4))) /* RXE */ 1934 return; 1935 1936 while (size --) { 1937 s->status[1] |= 1 << 4; /* EOF */ 1938 if (s->rx_len >= 64) { 1939 s->status[1] |= 1 << 6; /* ROR */ 1940 break; 1941 } 1942 1943 if (s->control[2] & (1 << 3)) /* RXP */ 1944 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++); 1945 else 1946 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++); 1947 } 1948 1949 pxa2xx_fir_update(s); 1950 } 1951 1952 static void pxa2xx_fir_event(void *opaque, int event) 1953 { 1954 } 1955 1956 static void pxa2xx_fir_save(QEMUFile *f, void *opaque) 1957 { 1958 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1959 int i; 1960 1961 qemu_put_be32(f, s->enable); 1962 1963 qemu_put_8s(f, &s->control[0]); 1964 qemu_put_8s(f, &s->control[1]); 1965 qemu_put_8s(f, &s->control[2]); 1966 qemu_put_8s(f, &s->status[0]); 1967 qemu_put_8s(f, &s->status[1]); 1968 1969 qemu_put_byte(f, s->rx_len); 1970 for (i = 0; i < s->rx_len; i ++) 1971 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 63]); 1972 } 1973 1974 static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id) 1975 { 1976 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1977 int i; 1978 1979 s->enable = qemu_get_be32(f); 1980 1981 qemu_get_8s(f, &s->control[0]); 1982 qemu_get_8s(f, &s->control[1]); 1983 qemu_get_8s(f, &s->control[2]); 1984 qemu_get_8s(f, &s->status[0]); 1985 qemu_get_8s(f, &s->status[1]); 1986 1987 s->rx_len = qemu_get_byte(f); 1988 s->rx_start = 0; 1989 for (i = 0; i < s->rx_len; i ++) 1990 s->rx_fifo[i] = qemu_get_byte(f); 1991 1992 return 0; 1993 } 1994 1995 static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem, 1996 hwaddr base, 1997 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma, 1998 CharDriverState *chr) 1999 { 2000 PXA2xxFIrState *s = (PXA2xxFIrState *) 2001 g_malloc0(sizeof(PXA2xxFIrState)); 2002 2003 s->irq = irq; 2004 s->rx_dma = rx_dma; 2005 s->tx_dma = tx_dma; 2006 s->chr = chr; 2007 2008 pxa2xx_fir_reset(s); 2009 2010 memory_region_init_io(&s->iomem, NULL, &pxa2xx_fir_ops, s, "pxa2xx-fir", 0x1000); 2011 memory_region_add_subregion(sysmem, base, &s->iomem); 2012 2013 if (chr) { 2014 qemu_chr_fe_claim_no_fail(chr); 2015 qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty, 2016 pxa2xx_fir_rx, pxa2xx_fir_event, s); 2017 } 2018 2019 register_savevm(NULL, "pxa2xx_fir", 0, 0, pxa2xx_fir_save, 2020 pxa2xx_fir_load, s); 2021 2022 return s; 2023 } 2024 2025 static void pxa2xx_reset(void *opaque, int line, int level) 2026 { 2027 PXA2xxState *s = (PXA2xxState *) opaque; 2028 2029 if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */ 2030 cpu_reset(CPU(s->cpu)); 2031 /* TODO: reset peripherals */ 2032 } 2033 } 2034 2035 /* Initialise a PXA270 integrated chip (ARM based core). */ 2036 PXA2xxState *pxa270_init(MemoryRegion *address_space, 2037 unsigned int sdram_size, const char *revision) 2038 { 2039 PXA2xxState *s; 2040 int i; 2041 DriveInfo *dinfo; 2042 s = (PXA2xxState *) g_malloc0(sizeof(PXA2xxState)); 2043 2044 if (revision && strncmp(revision, "pxa27", 5)) { 2045 fprintf(stderr, "Machine requires a PXA27x processor.\n"); 2046 exit(1); 2047 } 2048 if (!revision) 2049 revision = "pxa270"; 2050 2051 s->cpu = cpu_arm_init(revision); 2052 if (s->cpu == NULL) { 2053 fprintf(stderr, "Unable to find CPU definition\n"); 2054 exit(1); 2055 } 2056 s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0); 2057 2058 /* SDRAM & Internal Memory Storage */ 2059 memory_region_init_ram(&s->sdram, NULL, "pxa270.sdram", sdram_size, 2060 &error_abort); 2061 vmstate_register_ram_global(&s->sdram); 2062 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram); 2063 memory_region_init_ram(&s->internal, NULL, "pxa270.internal", 0x40000, 2064 &error_abort); 2065 vmstate_register_ram_global(&s->internal); 2066 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE, 2067 &s->internal); 2068 2069 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu); 2070 2071 s->dma = pxa27x_dma_init(0x40000000, 2072 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA)); 2073 2074 sysbus_create_varargs("pxa27x-timer", 0x40a00000, 2075 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0), 2076 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1), 2077 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2), 2078 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3), 2079 qdev_get_gpio_in(s->pic, PXA27X_PIC_OST_4_11), 2080 NULL); 2081 2082 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 121); 2083 2084 dinfo = drive_get(IF_SD, 0, 0); 2085 if (!dinfo) { 2086 fprintf(stderr, "qemu: missing SecureDigital device\n"); 2087 exit(1); 2088 } 2089 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, 2090 blk_by_legacy_dinfo(dinfo), 2091 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), 2092 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), 2093 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); 2094 2095 for (i = 0; pxa270_serial[i].io_base; i++) { 2096 if (serial_hds[i]) { 2097 serial_mm_init(address_space, pxa270_serial[i].io_base, 2, 2098 qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn), 2099 14857000 / 16, serial_hds[i], 2100 DEVICE_NATIVE_ENDIAN); 2101 } else { 2102 break; 2103 } 2104 } 2105 if (serial_hds[i]) 2106 s->fir = pxa2xx_fir_init(address_space, 0x40800000, 2107 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), 2108 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), 2109 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), 2110 serial_hds[i]); 2111 2112 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000, 2113 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); 2114 2115 s->cm_base = 0x41300000; 2116 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */ 2117 s->clkcfg = 0x00000009; /* Turbo mode active */ 2118 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000); 2119 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); 2120 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); 2121 2122 pxa2xx_setup_cp14(s); 2123 2124 s->mm_base = 0x48000000; 2125 s->mm_regs[MDMRS >> 2] = 0x00020002; 2126 s->mm_regs[MDREFR >> 2] = 0x03ca4000; 2127 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ 2128 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000); 2129 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem); 2130 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s); 2131 2132 s->pm_base = 0x40f00000; 2133 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100); 2134 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem); 2135 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s); 2136 2137 for (i = 0; pxa27x_ssp[i].io_base; i ++); 2138 s->ssp = (SSIBus **)g_malloc0(sizeof(SSIBus *) * i); 2139 for (i = 0; pxa27x_ssp[i].io_base; i ++) { 2140 DeviceState *dev; 2141 dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa27x_ssp[i].io_base, 2142 qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn)); 2143 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi"); 2144 } 2145 2146 if (usb_enabled()) { 2147 sysbus_create_simple("sysbus-ohci", 0x4c000000, 2148 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1)); 2149 } 2150 2151 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000); 2152 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000); 2153 2154 sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000, 2155 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM)); 2156 2157 s->i2c[0] = pxa2xx_i2c_init(0x40301600, 2158 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff); 2159 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, 2160 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff); 2161 2162 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000, 2163 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), 2164 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), 2165 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); 2166 2167 s->kp = pxa27x_keypad_init(address_space, 0x41500000, 2168 qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD)); 2169 2170 /* GPIO1 resets the processor */ 2171 /* The handler can be overridden by board-specific code */ 2172 qdev_connect_gpio_out(s->gpio, 1, s->reset); 2173 return s; 2174 } 2175 2176 /* Initialise a PXA255 integrated chip (ARM based core). */ 2177 PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size) 2178 { 2179 PXA2xxState *s; 2180 int i; 2181 DriveInfo *dinfo; 2182 2183 s = (PXA2xxState *) g_malloc0(sizeof(PXA2xxState)); 2184 2185 s->cpu = cpu_arm_init("pxa255"); 2186 if (s->cpu == NULL) { 2187 fprintf(stderr, "Unable to find CPU definition\n"); 2188 exit(1); 2189 } 2190 s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0); 2191 2192 /* SDRAM & Internal Memory Storage */ 2193 memory_region_init_ram(&s->sdram, NULL, "pxa255.sdram", sdram_size, 2194 &error_abort); 2195 vmstate_register_ram_global(&s->sdram); 2196 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram); 2197 memory_region_init_ram(&s->internal, NULL, "pxa255.internal", 2198 PXA2XX_INTERNAL_SIZE, &error_abort); 2199 vmstate_register_ram_global(&s->internal); 2200 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE, 2201 &s->internal); 2202 2203 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu); 2204 2205 s->dma = pxa255_dma_init(0x40000000, 2206 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA)); 2207 2208 sysbus_create_varargs("pxa25x-timer", 0x40a00000, 2209 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0), 2210 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1), 2211 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2), 2212 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3), 2213 NULL); 2214 2215 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 85); 2216 2217 dinfo = drive_get(IF_SD, 0, 0); 2218 if (!dinfo) { 2219 fprintf(stderr, "qemu: missing SecureDigital device\n"); 2220 exit(1); 2221 } 2222 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, 2223 blk_by_legacy_dinfo(dinfo), 2224 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), 2225 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), 2226 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); 2227 2228 for (i = 0; pxa255_serial[i].io_base; i++) { 2229 if (serial_hds[i]) { 2230 serial_mm_init(address_space, pxa255_serial[i].io_base, 2, 2231 qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn), 2232 14745600 / 16, serial_hds[i], 2233 DEVICE_NATIVE_ENDIAN); 2234 } else { 2235 break; 2236 } 2237 } 2238 if (serial_hds[i]) 2239 s->fir = pxa2xx_fir_init(address_space, 0x40800000, 2240 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), 2241 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), 2242 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), 2243 serial_hds[i]); 2244 2245 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000, 2246 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); 2247 2248 s->cm_base = 0x41300000; 2249 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */ 2250 s->clkcfg = 0x00000009; /* Turbo mode active */ 2251 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000); 2252 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); 2253 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); 2254 2255 pxa2xx_setup_cp14(s); 2256 2257 s->mm_base = 0x48000000; 2258 s->mm_regs[MDMRS >> 2] = 0x00020002; 2259 s->mm_regs[MDREFR >> 2] = 0x03ca4000; 2260 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ 2261 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000); 2262 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem); 2263 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s); 2264 2265 s->pm_base = 0x40f00000; 2266 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100); 2267 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem); 2268 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s); 2269 2270 for (i = 0; pxa255_ssp[i].io_base; i ++); 2271 s->ssp = (SSIBus **)g_malloc0(sizeof(SSIBus *) * i); 2272 for (i = 0; pxa255_ssp[i].io_base; i ++) { 2273 DeviceState *dev; 2274 dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa255_ssp[i].io_base, 2275 qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn)); 2276 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi"); 2277 } 2278 2279 if (usb_enabled()) { 2280 sysbus_create_simple("sysbus-ohci", 0x4c000000, 2281 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1)); 2282 } 2283 2284 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000); 2285 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000); 2286 2287 sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000, 2288 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM)); 2289 2290 s->i2c[0] = pxa2xx_i2c_init(0x40301600, 2291 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff); 2292 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, 2293 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff); 2294 2295 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000, 2296 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), 2297 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), 2298 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); 2299 2300 /* GPIO1 resets the processor */ 2301 /* The handler can be overridden by board-specific code */ 2302 qdev_connect_gpio_out(s->gpio, 1, s->reset); 2303 return s; 2304 } 2305 2306 static void pxa2xx_ssp_class_init(ObjectClass *klass, void *data) 2307 { 2308 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 2309 2310 sdc->init = pxa2xx_ssp_init; 2311 } 2312 2313 static const TypeInfo pxa2xx_ssp_info = { 2314 .name = TYPE_PXA2XX_SSP, 2315 .parent = TYPE_SYS_BUS_DEVICE, 2316 .instance_size = sizeof(PXA2xxSSPState), 2317 .class_init = pxa2xx_ssp_class_init, 2318 }; 2319 2320 static void pxa2xx_register_types(void) 2321 { 2322 type_register_static(&pxa2xx_i2c_slave_info); 2323 type_register_static(&pxa2xx_ssp_info); 2324 type_register_static(&pxa2xx_i2c_info); 2325 type_register_static(&pxa2xx_rtc_sysbus_info); 2326 } 2327 2328 type_init(pxa2xx_register_types) 2329