1 /* 2 * Intel XScale PXA255/270 processor support. 3 * 4 * Copyright (c) 2006 Openedhand Ltd. 5 * Written by Andrzej Zaborowski <balrog@zabor.org> 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu-common.h" 12 #include "qemu/error-report.h" 13 #include "qemu/module.h" 14 #include "qapi/error.h" 15 #include "cpu.h" 16 #include "hw/sysbus.h" 17 #include "migration/vmstate.h" 18 #include "hw/arm/pxa.h" 19 #include "sysemu/sysemu.h" 20 #include "hw/char/serial.h" 21 #include "hw/i2c/i2c.h" 22 #include "hw/irq.h" 23 #include "hw/qdev-properties.h" 24 #include "hw/ssi/ssi.h" 25 #include "chardev/char-fe.h" 26 #include "sysemu/blockdev.h" 27 #include "sysemu/qtest.h" 28 #include "qemu/cutils.h" 29 30 static struct { 31 hwaddr io_base; 32 int irqn; 33 } pxa255_serial[] = { 34 { 0x40100000, PXA2XX_PIC_FFUART }, 35 { 0x40200000, PXA2XX_PIC_BTUART }, 36 { 0x40700000, PXA2XX_PIC_STUART }, 37 { 0x41600000, PXA25X_PIC_HWUART }, 38 { 0, 0 } 39 }, pxa270_serial[] = { 40 { 0x40100000, PXA2XX_PIC_FFUART }, 41 { 0x40200000, PXA2XX_PIC_BTUART }, 42 { 0x40700000, PXA2XX_PIC_STUART }, 43 { 0, 0 } 44 }; 45 46 typedef struct PXASSPDef { 47 hwaddr io_base; 48 int irqn; 49 } PXASSPDef; 50 51 #if 0 52 static PXASSPDef pxa250_ssp[] = { 53 { 0x41000000, PXA2XX_PIC_SSP }, 54 { 0, 0 } 55 }; 56 #endif 57 58 static PXASSPDef pxa255_ssp[] = { 59 { 0x41000000, PXA2XX_PIC_SSP }, 60 { 0x41400000, PXA25X_PIC_NSSP }, 61 { 0, 0 } 62 }; 63 64 #if 0 65 static PXASSPDef pxa26x_ssp[] = { 66 { 0x41000000, PXA2XX_PIC_SSP }, 67 { 0x41400000, PXA25X_PIC_NSSP }, 68 { 0x41500000, PXA26X_PIC_ASSP }, 69 { 0, 0 } 70 }; 71 #endif 72 73 static PXASSPDef pxa27x_ssp[] = { 74 { 0x41000000, PXA2XX_PIC_SSP }, 75 { 0x41700000, PXA27X_PIC_SSP2 }, 76 { 0x41900000, PXA2XX_PIC_SSP3 }, 77 { 0, 0 } 78 }; 79 80 #define PMCR 0x00 /* Power Manager Control register */ 81 #define PSSR 0x04 /* Power Manager Sleep Status register */ 82 #define PSPR 0x08 /* Power Manager Scratch-Pad register */ 83 #define PWER 0x0c /* Power Manager Wake-Up Enable register */ 84 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */ 85 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */ 86 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */ 87 #define PCFR 0x1c /* Power Manager General Configuration register */ 88 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */ 89 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */ 90 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */ 91 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */ 92 #define RCSR 0x30 /* Reset Controller Status register */ 93 #define PSLR 0x34 /* Power Manager Sleep Configuration register */ 94 #define PTSR 0x38 /* Power Manager Standby Configuration register */ 95 #define PVCR 0x40 /* Power Manager Voltage Change Control register */ 96 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */ 97 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */ 98 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */ 99 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */ 100 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */ 101 102 static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr, 103 unsigned size) 104 { 105 PXA2xxState *s = (PXA2xxState *) opaque; 106 107 switch (addr) { 108 case PMCR ... PCMD31: 109 if (addr & 3) 110 goto fail; 111 112 return s->pm_regs[addr >> 2]; 113 default: 114 fail: 115 printf("%s: Bad register " REG_FMT "\n", __func__, addr); 116 break; 117 } 118 return 0; 119 } 120 121 static void pxa2xx_pm_write(void *opaque, hwaddr addr, 122 uint64_t value, unsigned size) 123 { 124 PXA2xxState *s = (PXA2xxState *) opaque; 125 126 switch (addr) { 127 case PMCR: 128 /* Clear the write-one-to-clear bits... */ 129 s->pm_regs[addr >> 2] &= ~(value & 0x2a); 130 /* ...and set the plain r/w bits */ 131 s->pm_regs[addr >> 2] &= ~0x15; 132 s->pm_regs[addr >> 2] |= value & 0x15; 133 break; 134 135 case PSSR: /* Read-clean registers */ 136 case RCSR: 137 case PKSR: 138 s->pm_regs[addr >> 2] &= ~value; 139 break; 140 141 default: /* Read-write registers */ 142 if (!(addr & 3)) { 143 s->pm_regs[addr >> 2] = value; 144 break; 145 } 146 147 printf("%s: Bad register " REG_FMT "\n", __func__, addr); 148 break; 149 } 150 } 151 152 static const MemoryRegionOps pxa2xx_pm_ops = { 153 .read = pxa2xx_pm_read, 154 .write = pxa2xx_pm_write, 155 .endianness = DEVICE_NATIVE_ENDIAN, 156 }; 157 158 static const VMStateDescription vmstate_pxa2xx_pm = { 159 .name = "pxa2xx_pm", 160 .version_id = 0, 161 .minimum_version_id = 0, 162 .fields = (VMStateField[]) { 163 VMSTATE_UINT32_ARRAY(pm_regs, PXA2xxState, 0x40), 164 VMSTATE_END_OF_LIST() 165 } 166 }; 167 168 #define CCCR 0x00 /* Core Clock Configuration register */ 169 #define CKEN 0x04 /* Clock Enable register */ 170 #define OSCC 0x08 /* Oscillator Configuration register */ 171 #define CCSR 0x0c /* Core Clock Status register */ 172 173 static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr, 174 unsigned size) 175 { 176 PXA2xxState *s = (PXA2xxState *) opaque; 177 178 switch (addr) { 179 case CCCR: 180 case CKEN: 181 case OSCC: 182 return s->cm_regs[addr >> 2]; 183 184 case CCSR: 185 return s->cm_regs[CCCR >> 2] | (3 << 28); 186 187 default: 188 printf("%s: Bad register " REG_FMT "\n", __func__, addr); 189 break; 190 } 191 return 0; 192 } 193 194 static void pxa2xx_cm_write(void *opaque, hwaddr addr, 195 uint64_t value, unsigned size) 196 { 197 PXA2xxState *s = (PXA2xxState *) opaque; 198 199 switch (addr) { 200 case CCCR: 201 case CKEN: 202 s->cm_regs[addr >> 2] = value; 203 break; 204 205 case OSCC: 206 s->cm_regs[addr >> 2] &= ~0x6c; 207 s->cm_regs[addr >> 2] |= value & 0x6e; 208 if ((value >> 1) & 1) /* OON */ 209 s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */ 210 break; 211 212 default: 213 printf("%s: Bad register " REG_FMT "\n", __func__, addr); 214 break; 215 } 216 } 217 218 static const MemoryRegionOps pxa2xx_cm_ops = { 219 .read = pxa2xx_cm_read, 220 .write = pxa2xx_cm_write, 221 .endianness = DEVICE_NATIVE_ENDIAN, 222 }; 223 224 static const VMStateDescription vmstate_pxa2xx_cm = { 225 .name = "pxa2xx_cm", 226 .version_id = 0, 227 .minimum_version_id = 0, 228 .fields = (VMStateField[]) { 229 VMSTATE_UINT32_ARRAY(cm_regs, PXA2xxState, 4), 230 VMSTATE_UINT32(clkcfg, PXA2xxState), 231 VMSTATE_UINT32(pmnc, PXA2xxState), 232 VMSTATE_END_OF_LIST() 233 } 234 }; 235 236 static uint64_t pxa2xx_clkcfg_read(CPUARMState *env, const ARMCPRegInfo *ri) 237 { 238 PXA2xxState *s = (PXA2xxState *)ri->opaque; 239 return s->clkcfg; 240 } 241 242 static void pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri, 243 uint64_t value) 244 { 245 PXA2xxState *s = (PXA2xxState *)ri->opaque; 246 s->clkcfg = value & 0xf; 247 if (value & 2) { 248 printf("%s: CPU frequency change attempt\n", __func__); 249 } 250 } 251 252 static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri, 253 uint64_t value) 254 { 255 PXA2xxState *s = (PXA2xxState *)ri->opaque; 256 static const char *pwrmode[8] = { 257 "Normal", "Idle", "Deep-idle", "Standby", 258 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep", 259 }; 260 261 if (value & 8) { 262 printf("%s: CPU voltage change attempt\n", __func__); 263 } 264 switch (value & 7) { 265 case 0: 266 /* Do nothing */ 267 break; 268 269 case 1: 270 /* Idle */ 271 if (!(s->cm_regs[CCCR >> 2] & (1U << 31))) { /* CPDIS */ 272 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); 273 break; 274 } 275 /* Fall through. */ 276 277 case 2: 278 /* Deep-Idle */ 279 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); 280 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ 281 goto message; 282 283 case 3: 284 s->cpu->env.uncached_cpsr = ARM_CPU_MODE_SVC; 285 s->cpu->env.daif = PSTATE_A | PSTATE_F | PSTATE_I; 286 s->cpu->env.cp15.sctlr_ns = 0; 287 s->cpu->env.cp15.cpacr_el1 = 0; 288 s->cpu->env.cp15.ttbr0_el[1] = 0; 289 s->cpu->env.cp15.dacr_ns = 0; 290 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ 291 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ 292 293 /* 294 * The scratch-pad register is almost universally used 295 * for storing the return address on suspend. For the 296 * lack of a resuming bootloader, perform a jump 297 * directly to that address. 298 */ 299 memset(s->cpu->env.regs, 0, 4 * 15); 300 s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2]; 301 302 #if 0 303 buffer = 0xe59ff000; /* ldr pc, [pc, #0] */ 304 cpu_physical_memory_write(0, &buffer, 4); 305 buffer = s->pm_regs[PSPR >> 2]; 306 cpu_physical_memory_write(8, &buffer, 4); 307 #endif 308 309 /* Suspend */ 310 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); 311 312 goto message; 313 314 default: 315 message: 316 printf("%s: machine entered %s mode\n", __func__, 317 pwrmode[value & 7]); 318 } 319 } 320 321 static uint64_t pxa2xx_cppmnc_read(CPUARMState *env, const ARMCPRegInfo *ri) 322 { 323 PXA2xxState *s = (PXA2xxState *)ri->opaque; 324 return s->pmnc; 325 } 326 327 static void pxa2xx_cppmnc_write(CPUARMState *env, const ARMCPRegInfo *ri, 328 uint64_t value) 329 { 330 PXA2xxState *s = (PXA2xxState *)ri->opaque; 331 s->pmnc = value; 332 } 333 334 static uint64_t pxa2xx_cpccnt_read(CPUARMState *env, const ARMCPRegInfo *ri) 335 { 336 PXA2xxState *s = (PXA2xxState *)ri->opaque; 337 if (s->pmnc & 1) { 338 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 339 } else { 340 return 0; 341 } 342 } 343 344 static const ARMCPRegInfo pxa_cp_reginfo[] = { 345 /* cp14 crm==1: perf registers */ 346 { .name = "CPPMNC", .cp = 14, .crn = 0, .crm = 1, .opc1 = 0, .opc2 = 0, 347 .access = PL1_RW, .type = ARM_CP_IO, 348 .readfn = pxa2xx_cppmnc_read, .writefn = pxa2xx_cppmnc_write }, 349 { .name = "CPCCNT", .cp = 14, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, 350 .access = PL1_RW, .type = ARM_CP_IO, 351 .readfn = pxa2xx_cpccnt_read, .writefn = arm_cp_write_ignore }, 352 { .name = "CPINTEN", .cp = 14, .crn = 4, .crm = 1, .opc1 = 0, .opc2 = 0, 353 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 354 { .name = "CPFLAG", .cp = 14, .crn = 5, .crm = 1, .opc1 = 0, .opc2 = 0, 355 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 356 { .name = "CPEVTSEL", .cp = 14, .crn = 8, .crm = 1, .opc1 = 0, .opc2 = 0, 357 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 358 /* cp14 crm==2: performance count registers */ 359 { .name = "CPPMN0", .cp = 14, .crn = 0, .crm = 2, .opc1 = 0, .opc2 = 0, 360 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 361 { .name = "CPPMN1", .cp = 14, .crn = 1, .crm = 2, .opc1 = 0, .opc2 = 0, 362 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 363 { .name = "CPPMN2", .cp = 14, .crn = 2, .crm = 2, .opc1 = 0, .opc2 = 0, 364 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 365 { .name = "CPPMN3", .cp = 14, .crn = 2, .crm = 3, .opc1 = 0, .opc2 = 0, 366 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 367 /* cp14 crn==6: CLKCFG */ 368 { .name = "CLKCFG", .cp = 14, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, 369 .access = PL1_RW, .type = ARM_CP_IO, 370 .readfn = pxa2xx_clkcfg_read, .writefn = pxa2xx_clkcfg_write }, 371 /* cp14 crn==7: PWRMODE */ 372 { .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0, 373 .access = PL1_RW, .type = ARM_CP_IO, 374 .readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write }, 375 REGINFO_SENTINEL 376 }; 377 378 static void pxa2xx_setup_cp14(PXA2xxState *s) 379 { 380 define_arm_cp_regs_with_opaque(s->cpu, pxa_cp_reginfo, s); 381 } 382 383 #define MDCNFG 0x00 /* SDRAM Configuration register */ 384 #define MDREFR 0x04 /* SDRAM Refresh Control register */ 385 #define MSC0 0x08 /* Static Memory Control register 0 */ 386 #define MSC1 0x0c /* Static Memory Control register 1 */ 387 #define MSC2 0x10 /* Static Memory Control register 2 */ 388 #define MECR 0x14 /* Expansion Memory Bus Config register */ 389 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */ 390 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */ 391 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */ 392 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */ 393 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */ 394 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */ 395 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */ 396 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */ 397 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */ 398 #define ARB_CNTL 0x48 /* Arbiter Control register */ 399 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */ 400 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */ 401 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */ 402 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */ 403 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */ 404 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */ 405 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */ 406 407 static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr, 408 unsigned size) 409 { 410 PXA2xxState *s = (PXA2xxState *) opaque; 411 412 switch (addr) { 413 case MDCNFG ... SA1110: 414 if ((addr & 3) == 0) 415 return s->mm_regs[addr >> 2]; 416 /* fall through */ 417 default: 418 printf("%s: Bad register " REG_FMT "\n", __func__, addr); 419 break; 420 } 421 return 0; 422 } 423 424 static void pxa2xx_mm_write(void *opaque, hwaddr addr, 425 uint64_t value, unsigned size) 426 { 427 PXA2xxState *s = (PXA2xxState *) opaque; 428 429 switch (addr) { 430 case MDCNFG ... SA1110: 431 if ((addr & 3) == 0) { 432 s->mm_regs[addr >> 2] = value; 433 break; 434 } 435 436 default: 437 printf("%s: Bad register " REG_FMT "\n", __func__, addr); 438 break; 439 } 440 } 441 442 static const MemoryRegionOps pxa2xx_mm_ops = { 443 .read = pxa2xx_mm_read, 444 .write = pxa2xx_mm_write, 445 .endianness = DEVICE_NATIVE_ENDIAN, 446 }; 447 448 static const VMStateDescription vmstate_pxa2xx_mm = { 449 .name = "pxa2xx_mm", 450 .version_id = 0, 451 .minimum_version_id = 0, 452 .fields = (VMStateField[]) { 453 VMSTATE_UINT32_ARRAY(mm_regs, PXA2xxState, 0x1a), 454 VMSTATE_END_OF_LIST() 455 } 456 }; 457 458 #define TYPE_PXA2XX_SSP "pxa2xx-ssp" 459 #define PXA2XX_SSP(obj) \ 460 OBJECT_CHECK(PXA2xxSSPState, (obj), TYPE_PXA2XX_SSP) 461 462 /* Synchronous Serial Ports */ 463 typedef struct { 464 /*< private >*/ 465 SysBusDevice parent_obj; 466 /*< public >*/ 467 468 MemoryRegion iomem; 469 qemu_irq irq; 470 uint32_t enable; 471 SSIBus *bus; 472 473 uint32_t sscr[2]; 474 uint32_t sspsp; 475 uint32_t ssto; 476 uint32_t ssitr; 477 uint32_t sssr; 478 uint8_t sstsa; 479 uint8_t ssrsa; 480 uint8_t ssacd; 481 482 uint32_t rx_fifo[16]; 483 uint32_t rx_level; 484 uint32_t rx_start; 485 } PXA2xxSSPState; 486 487 static bool pxa2xx_ssp_vmstate_validate(void *opaque, int version_id) 488 { 489 PXA2xxSSPState *s = opaque; 490 491 return s->rx_start < sizeof(s->rx_fifo); 492 } 493 494 static const VMStateDescription vmstate_pxa2xx_ssp = { 495 .name = "pxa2xx-ssp", 496 .version_id = 1, 497 .minimum_version_id = 1, 498 .fields = (VMStateField[]) { 499 VMSTATE_UINT32(enable, PXA2xxSSPState), 500 VMSTATE_UINT32_ARRAY(sscr, PXA2xxSSPState, 2), 501 VMSTATE_UINT32(sspsp, PXA2xxSSPState), 502 VMSTATE_UINT32(ssto, PXA2xxSSPState), 503 VMSTATE_UINT32(ssitr, PXA2xxSSPState), 504 VMSTATE_UINT32(sssr, PXA2xxSSPState), 505 VMSTATE_UINT8(sstsa, PXA2xxSSPState), 506 VMSTATE_UINT8(ssrsa, PXA2xxSSPState), 507 VMSTATE_UINT8(ssacd, PXA2xxSSPState), 508 VMSTATE_UINT32(rx_level, PXA2xxSSPState), 509 VMSTATE_UINT32(rx_start, PXA2xxSSPState), 510 VMSTATE_VALIDATE("fifo is 16 bytes", pxa2xx_ssp_vmstate_validate), 511 VMSTATE_UINT32_ARRAY(rx_fifo, PXA2xxSSPState, 16), 512 VMSTATE_END_OF_LIST() 513 } 514 }; 515 516 #define SSCR0 0x00 /* SSP Control register 0 */ 517 #define SSCR1 0x04 /* SSP Control register 1 */ 518 #define SSSR 0x08 /* SSP Status register */ 519 #define SSITR 0x0c /* SSP Interrupt Test register */ 520 #define SSDR 0x10 /* SSP Data register */ 521 #define SSTO 0x28 /* SSP Time-Out register */ 522 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */ 523 #define SSTSA 0x30 /* SSP TX Time Slot Active register */ 524 #define SSRSA 0x34 /* SSP RX Time Slot Active register */ 525 #define SSTSS 0x38 /* SSP Time Slot Status register */ 526 #define SSACD 0x3c /* SSP Audio Clock Divider register */ 527 528 /* Bitfields for above registers */ 529 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00) 530 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10) 531 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20) 532 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30) 533 #define SSCR0_SSE (1 << 7) 534 #define SSCR0_RIM (1 << 22) 535 #define SSCR0_TIM (1 << 23) 536 #define SSCR0_MOD (1U << 31) 537 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1) 538 #define SSCR1_RIE (1 << 0) 539 #define SSCR1_TIE (1 << 1) 540 #define SSCR1_LBM (1 << 2) 541 #define SSCR1_MWDS (1 << 5) 542 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1) 543 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1) 544 #define SSCR1_EFWR (1 << 14) 545 #define SSCR1_PINTE (1 << 18) 546 #define SSCR1_TINTE (1 << 19) 547 #define SSCR1_RSRE (1 << 20) 548 #define SSCR1_TSRE (1 << 21) 549 #define SSCR1_EBCEI (1 << 29) 550 #define SSITR_INT (7 << 5) 551 #define SSSR_TNF (1 << 2) 552 #define SSSR_RNE (1 << 3) 553 #define SSSR_TFS (1 << 5) 554 #define SSSR_RFS (1 << 6) 555 #define SSSR_ROR (1 << 7) 556 #define SSSR_PINT (1 << 18) 557 #define SSSR_TINT (1 << 19) 558 #define SSSR_EOC (1 << 20) 559 #define SSSR_TUR (1 << 21) 560 #define SSSR_BCE (1 << 23) 561 #define SSSR_RW 0x00bc0080 562 563 static void pxa2xx_ssp_int_update(PXA2xxSSPState *s) 564 { 565 int level = 0; 566 567 level |= s->ssitr & SSITR_INT; 568 level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI); 569 level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM); 570 level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT)); 571 level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE); 572 level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE); 573 level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM); 574 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE); 575 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE); 576 qemu_set_irq(s->irq, !!level); 577 } 578 579 static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s) 580 { 581 s->sssr &= ~(0xf << 12); /* Clear RFL */ 582 s->sssr &= ~(0xf << 8); /* Clear TFL */ 583 s->sssr &= ~SSSR_TFS; 584 s->sssr &= ~SSSR_TNF; 585 if (s->enable) { 586 s->sssr |= ((s->rx_level - 1) & 0xf) << 12; 587 if (s->rx_level >= SSCR1_RFT(s->sscr[1])) 588 s->sssr |= SSSR_RFS; 589 else 590 s->sssr &= ~SSSR_RFS; 591 if (s->rx_level) 592 s->sssr |= SSSR_RNE; 593 else 594 s->sssr &= ~SSSR_RNE; 595 /* TX FIFO is never filled, so it is always in underrun 596 condition if SSP is enabled */ 597 s->sssr |= SSSR_TFS; 598 s->sssr |= SSSR_TNF; 599 } 600 601 pxa2xx_ssp_int_update(s); 602 } 603 604 static uint64_t pxa2xx_ssp_read(void *opaque, hwaddr addr, 605 unsigned size) 606 { 607 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; 608 uint32_t retval; 609 610 switch (addr) { 611 case SSCR0: 612 return s->sscr[0]; 613 case SSCR1: 614 return s->sscr[1]; 615 case SSPSP: 616 return s->sspsp; 617 case SSTO: 618 return s->ssto; 619 case SSITR: 620 return s->ssitr; 621 case SSSR: 622 return s->sssr | s->ssitr; 623 case SSDR: 624 if (!s->enable) 625 return 0xffffffff; 626 if (s->rx_level < 1) { 627 printf("%s: SSP Rx Underrun\n", __func__); 628 return 0xffffffff; 629 } 630 s->rx_level --; 631 retval = s->rx_fifo[s->rx_start ++]; 632 s->rx_start &= 0xf; 633 pxa2xx_ssp_fifo_update(s); 634 return retval; 635 case SSTSA: 636 return s->sstsa; 637 case SSRSA: 638 return s->ssrsa; 639 case SSTSS: 640 return 0; 641 case SSACD: 642 return s->ssacd; 643 default: 644 printf("%s: Bad register " REG_FMT "\n", __func__, addr); 645 break; 646 } 647 return 0; 648 } 649 650 static void pxa2xx_ssp_write(void *opaque, hwaddr addr, 651 uint64_t value64, unsigned size) 652 { 653 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; 654 uint32_t value = value64; 655 656 switch (addr) { 657 case SSCR0: 658 s->sscr[0] = value & 0xc7ffffff; 659 s->enable = value & SSCR0_SSE; 660 if (value & SSCR0_MOD) 661 printf("%s: Attempt to use network mode\n", __func__); 662 if (s->enable && SSCR0_DSS(value) < 4) 663 printf("%s: Wrong data size: %i bits\n", __func__, 664 SSCR0_DSS(value)); 665 if (!(value & SSCR0_SSE)) { 666 s->sssr = 0; 667 s->ssitr = 0; 668 s->rx_level = 0; 669 } 670 pxa2xx_ssp_fifo_update(s); 671 break; 672 673 case SSCR1: 674 s->sscr[1] = value; 675 if (value & (SSCR1_LBM | SSCR1_EFWR)) 676 printf("%s: Attempt to use SSP test mode\n", __func__); 677 pxa2xx_ssp_fifo_update(s); 678 break; 679 680 case SSPSP: 681 s->sspsp = value; 682 break; 683 684 case SSTO: 685 s->ssto = value; 686 break; 687 688 case SSITR: 689 s->ssitr = value & SSITR_INT; 690 pxa2xx_ssp_int_update(s); 691 break; 692 693 case SSSR: 694 s->sssr &= ~(value & SSSR_RW); 695 pxa2xx_ssp_int_update(s); 696 break; 697 698 case SSDR: 699 if (SSCR0_UWIRE(s->sscr[0])) { 700 if (s->sscr[1] & SSCR1_MWDS) 701 value &= 0xffff; 702 else 703 value &= 0xff; 704 } else 705 /* Note how 32bits overflow does no harm here */ 706 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1; 707 708 /* Data goes from here to the Tx FIFO and is shifted out from 709 * there directly to the slave, no need to buffer it. 710 */ 711 if (s->enable) { 712 uint32_t readval; 713 readval = ssi_transfer(s->bus, value); 714 if (s->rx_level < 0x10) { 715 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval; 716 } else { 717 s->sssr |= SSSR_ROR; 718 } 719 } 720 pxa2xx_ssp_fifo_update(s); 721 break; 722 723 case SSTSA: 724 s->sstsa = value; 725 break; 726 727 case SSRSA: 728 s->ssrsa = value; 729 break; 730 731 case SSACD: 732 s->ssacd = value; 733 break; 734 735 default: 736 printf("%s: Bad register " REG_FMT "\n", __func__, addr); 737 break; 738 } 739 } 740 741 static const MemoryRegionOps pxa2xx_ssp_ops = { 742 .read = pxa2xx_ssp_read, 743 .write = pxa2xx_ssp_write, 744 .endianness = DEVICE_NATIVE_ENDIAN, 745 }; 746 747 static void pxa2xx_ssp_reset(DeviceState *d) 748 { 749 PXA2xxSSPState *s = PXA2XX_SSP(d); 750 751 s->enable = 0; 752 s->sscr[0] = s->sscr[1] = 0; 753 s->sspsp = 0; 754 s->ssto = 0; 755 s->ssitr = 0; 756 s->sssr = 0; 757 s->sstsa = 0; 758 s->ssrsa = 0; 759 s->ssacd = 0; 760 s->rx_start = s->rx_level = 0; 761 } 762 763 static void pxa2xx_ssp_init(Object *obj) 764 { 765 DeviceState *dev = DEVICE(obj); 766 PXA2xxSSPState *s = PXA2XX_SSP(obj); 767 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 768 sysbus_init_irq(sbd, &s->irq); 769 770 memory_region_init_io(&s->iomem, obj, &pxa2xx_ssp_ops, s, 771 "pxa2xx-ssp", 0x1000); 772 sysbus_init_mmio(sbd, &s->iomem); 773 774 s->bus = ssi_create_bus(dev, "ssi"); 775 } 776 777 /* Real-Time Clock */ 778 #define RCNR 0x00 /* RTC Counter register */ 779 #define RTAR 0x04 /* RTC Alarm register */ 780 #define RTSR 0x08 /* RTC Status register */ 781 #define RTTR 0x0c /* RTC Timer Trim register */ 782 #define RDCR 0x10 /* RTC Day Counter register */ 783 #define RYCR 0x14 /* RTC Year Counter register */ 784 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */ 785 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */ 786 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */ 787 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */ 788 #define SWCR 0x28 /* RTC Stopwatch Counter register */ 789 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */ 790 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */ 791 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */ 792 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */ 793 794 #define TYPE_PXA2XX_RTC "pxa2xx_rtc" 795 #define PXA2XX_RTC(obj) \ 796 OBJECT_CHECK(PXA2xxRTCState, (obj), TYPE_PXA2XX_RTC) 797 798 typedef struct { 799 /*< private >*/ 800 SysBusDevice parent_obj; 801 /*< public >*/ 802 803 MemoryRegion iomem; 804 uint32_t rttr; 805 uint32_t rtsr; 806 uint32_t rtar; 807 uint32_t rdar1; 808 uint32_t rdar2; 809 uint32_t ryar1; 810 uint32_t ryar2; 811 uint32_t swar1; 812 uint32_t swar2; 813 uint32_t piar; 814 uint32_t last_rcnr; 815 uint32_t last_rdcr; 816 uint32_t last_rycr; 817 uint32_t last_swcr; 818 uint32_t last_rtcpicr; 819 int64_t last_hz; 820 int64_t last_sw; 821 int64_t last_pi; 822 QEMUTimer *rtc_hz; 823 QEMUTimer *rtc_rdal1; 824 QEMUTimer *rtc_rdal2; 825 QEMUTimer *rtc_swal1; 826 QEMUTimer *rtc_swal2; 827 QEMUTimer *rtc_pi; 828 qemu_irq rtc_irq; 829 } PXA2xxRTCState; 830 831 static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s) 832 { 833 qemu_set_irq(s->rtc_irq, !!(s->rtsr & 0x2553)); 834 } 835 836 static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s) 837 { 838 int64_t rt = qemu_clock_get_ms(rtc_clock); 839 s->last_rcnr += ((rt - s->last_hz) << 15) / 840 (1000 * ((s->rttr & 0xffff) + 1)); 841 s->last_rdcr += ((rt - s->last_hz) << 15) / 842 (1000 * ((s->rttr & 0xffff) + 1)); 843 s->last_hz = rt; 844 } 845 846 static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s) 847 { 848 int64_t rt = qemu_clock_get_ms(rtc_clock); 849 if (s->rtsr & (1 << 12)) 850 s->last_swcr += (rt - s->last_sw) / 10; 851 s->last_sw = rt; 852 } 853 854 static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s) 855 { 856 int64_t rt = qemu_clock_get_ms(rtc_clock); 857 if (s->rtsr & (1 << 15)) 858 s->last_swcr += rt - s->last_pi; 859 s->last_pi = rt; 860 } 861 862 static inline void pxa2xx_rtc_alarm_update(PXA2xxRTCState *s, 863 uint32_t rtsr) 864 { 865 if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0))) 866 timer_mod(s->rtc_hz, s->last_hz + 867 (((s->rtar - s->last_rcnr) * 1000 * 868 ((s->rttr & 0xffff) + 1)) >> 15)); 869 else 870 timer_del(s->rtc_hz); 871 872 if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4))) 873 timer_mod(s->rtc_rdal1, s->last_hz + 874 (((s->rdar1 - s->last_rdcr) * 1000 * 875 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */ 876 else 877 timer_del(s->rtc_rdal1); 878 879 if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6))) 880 timer_mod(s->rtc_rdal2, s->last_hz + 881 (((s->rdar2 - s->last_rdcr) * 1000 * 882 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */ 883 else 884 timer_del(s->rtc_rdal2); 885 886 if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8))) 887 timer_mod(s->rtc_swal1, s->last_sw + 888 (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */ 889 else 890 timer_del(s->rtc_swal1); 891 892 if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10))) 893 timer_mod(s->rtc_swal2, s->last_sw + 894 (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */ 895 else 896 timer_del(s->rtc_swal2); 897 898 if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13))) 899 timer_mod(s->rtc_pi, s->last_pi + 900 (s->piar & 0xffff) - s->last_rtcpicr); 901 else 902 timer_del(s->rtc_pi); 903 } 904 905 static inline void pxa2xx_rtc_hz_tick(void *opaque) 906 { 907 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 908 s->rtsr |= (1 << 0); 909 pxa2xx_rtc_alarm_update(s, s->rtsr); 910 pxa2xx_rtc_int_update(s); 911 } 912 913 static inline void pxa2xx_rtc_rdal1_tick(void *opaque) 914 { 915 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 916 s->rtsr |= (1 << 4); 917 pxa2xx_rtc_alarm_update(s, s->rtsr); 918 pxa2xx_rtc_int_update(s); 919 } 920 921 static inline void pxa2xx_rtc_rdal2_tick(void *opaque) 922 { 923 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 924 s->rtsr |= (1 << 6); 925 pxa2xx_rtc_alarm_update(s, s->rtsr); 926 pxa2xx_rtc_int_update(s); 927 } 928 929 static inline void pxa2xx_rtc_swal1_tick(void *opaque) 930 { 931 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 932 s->rtsr |= (1 << 8); 933 pxa2xx_rtc_alarm_update(s, s->rtsr); 934 pxa2xx_rtc_int_update(s); 935 } 936 937 static inline void pxa2xx_rtc_swal2_tick(void *opaque) 938 { 939 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 940 s->rtsr |= (1 << 10); 941 pxa2xx_rtc_alarm_update(s, s->rtsr); 942 pxa2xx_rtc_int_update(s); 943 } 944 945 static inline void pxa2xx_rtc_pi_tick(void *opaque) 946 { 947 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 948 s->rtsr |= (1 << 13); 949 pxa2xx_rtc_piupdate(s); 950 s->last_rtcpicr = 0; 951 pxa2xx_rtc_alarm_update(s, s->rtsr); 952 pxa2xx_rtc_int_update(s); 953 } 954 955 static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr, 956 unsigned size) 957 { 958 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 959 960 switch (addr) { 961 case RTTR: 962 return s->rttr; 963 case RTSR: 964 return s->rtsr; 965 case RTAR: 966 return s->rtar; 967 case RDAR1: 968 return s->rdar1; 969 case RDAR2: 970 return s->rdar2; 971 case RYAR1: 972 return s->ryar1; 973 case RYAR2: 974 return s->ryar2; 975 case SWAR1: 976 return s->swar1; 977 case SWAR2: 978 return s->swar2; 979 case PIAR: 980 return s->piar; 981 case RCNR: 982 return s->last_rcnr + 983 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / 984 (1000 * ((s->rttr & 0xffff) + 1)); 985 case RDCR: 986 return s->last_rdcr + 987 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / 988 (1000 * ((s->rttr & 0xffff) + 1)); 989 case RYCR: 990 return s->last_rycr; 991 case SWCR: 992 if (s->rtsr & (1 << 12)) 993 return s->last_swcr + 994 (qemu_clock_get_ms(rtc_clock) - s->last_sw) / 10; 995 else 996 return s->last_swcr; 997 default: 998 printf("%s: Bad register " REG_FMT "\n", __func__, addr); 999 break; 1000 } 1001 return 0; 1002 } 1003 1004 static void pxa2xx_rtc_write(void *opaque, hwaddr addr, 1005 uint64_t value64, unsigned size) 1006 { 1007 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 1008 uint32_t value = value64; 1009 1010 switch (addr) { 1011 case RTTR: 1012 if (!(s->rttr & (1U << 31))) { 1013 pxa2xx_rtc_hzupdate(s); 1014 s->rttr = value; 1015 pxa2xx_rtc_alarm_update(s, s->rtsr); 1016 } 1017 break; 1018 1019 case RTSR: 1020 if ((s->rtsr ^ value) & (1 << 15)) 1021 pxa2xx_rtc_piupdate(s); 1022 1023 if ((s->rtsr ^ value) & (1 << 12)) 1024 pxa2xx_rtc_swupdate(s); 1025 1026 if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac)) 1027 pxa2xx_rtc_alarm_update(s, value); 1028 1029 s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac)); 1030 pxa2xx_rtc_int_update(s); 1031 break; 1032 1033 case RTAR: 1034 s->rtar = value; 1035 pxa2xx_rtc_alarm_update(s, s->rtsr); 1036 break; 1037 1038 case RDAR1: 1039 s->rdar1 = value; 1040 pxa2xx_rtc_alarm_update(s, s->rtsr); 1041 break; 1042 1043 case RDAR2: 1044 s->rdar2 = value; 1045 pxa2xx_rtc_alarm_update(s, s->rtsr); 1046 break; 1047 1048 case RYAR1: 1049 s->ryar1 = value; 1050 pxa2xx_rtc_alarm_update(s, s->rtsr); 1051 break; 1052 1053 case RYAR2: 1054 s->ryar2 = value; 1055 pxa2xx_rtc_alarm_update(s, s->rtsr); 1056 break; 1057 1058 case SWAR1: 1059 pxa2xx_rtc_swupdate(s); 1060 s->swar1 = value; 1061 s->last_swcr = 0; 1062 pxa2xx_rtc_alarm_update(s, s->rtsr); 1063 break; 1064 1065 case SWAR2: 1066 s->swar2 = value; 1067 pxa2xx_rtc_alarm_update(s, s->rtsr); 1068 break; 1069 1070 case PIAR: 1071 s->piar = value; 1072 pxa2xx_rtc_alarm_update(s, s->rtsr); 1073 break; 1074 1075 case RCNR: 1076 pxa2xx_rtc_hzupdate(s); 1077 s->last_rcnr = value; 1078 pxa2xx_rtc_alarm_update(s, s->rtsr); 1079 break; 1080 1081 case RDCR: 1082 pxa2xx_rtc_hzupdate(s); 1083 s->last_rdcr = value; 1084 pxa2xx_rtc_alarm_update(s, s->rtsr); 1085 break; 1086 1087 case RYCR: 1088 s->last_rycr = value; 1089 break; 1090 1091 case SWCR: 1092 pxa2xx_rtc_swupdate(s); 1093 s->last_swcr = value; 1094 pxa2xx_rtc_alarm_update(s, s->rtsr); 1095 break; 1096 1097 case RTCPICR: 1098 pxa2xx_rtc_piupdate(s); 1099 s->last_rtcpicr = value & 0xffff; 1100 pxa2xx_rtc_alarm_update(s, s->rtsr); 1101 break; 1102 1103 default: 1104 printf("%s: Bad register " REG_FMT "\n", __func__, addr); 1105 } 1106 } 1107 1108 static const MemoryRegionOps pxa2xx_rtc_ops = { 1109 .read = pxa2xx_rtc_read, 1110 .write = pxa2xx_rtc_write, 1111 .endianness = DEVICE_NATIVE_ENDIAN, 1112 }; 1113 1114 static void pxa2xx_rtc_init(Object *obj) 1115 { 1116 PXA2xxRTCState *s = PXA2XX_RTC(obj); 1117 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 1118 struct tm tm; 1119 int wom; 1120 1121 s->rttr = 0x7fff; 1122 s->rtsr = 0; 1123 1124 qemu_get_timedate(&tm, 0); 1125 wom = ((tm.tm_mday - 1) / 7) + 1; 1126 1127 s->last_rcnr = (uint32_t) mktimegm(&tm); 1128 s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) | 1129 (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec; 1130 s->last_rycr = ((tm.tm_year + 1900) << 9) | 1131 ((tm.tm_mon + 1) << 5) | tm.tm_mday; 1132 s->last_swcr = (tm.tm_hour << 19) | 1133 (tm.tm_min << 13) | (tm.tm_sec << 7); 1134 s->last_rtcpicr = 0; 1135 s->last_hz = s->last_sw = s->last_pi = qemu_clock_get_ms(rtc_clock); 1136 1137 sysbus_init_irq(dev, &s->rtc_irq); 1138 1139 memory_region_init_io(&s->iomem, obj, &pxa2xx_rtc_ops, s, 1140 "pxa2xx-rtc", 0x10000); 1141 sysbus_init_mmio(dev, &s->iomem); 1142 } 1143 1144 static void pxa2xx_rtc_realize(DeviceState *dev, Error **errp) 1145 { 1146 PXA2xxRTCState *s = PXA2XX_RTC(dev); 1147 s->rtc_hz = timer_new_ms(rtc_clock, pxa2xx_rtc_hz_tick, s); 1148 s->rtc_rdal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal1_tick, s); 1149 s->rtc_rdal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal2_tick, s); 1150 s->rtc_swal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal1_tick, s); 1151 s->rtc_swal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal2_tick, s); 1152 s->rtc_pi = timer_new_ms(rtc_clock, pxa2xx_rtc_pi_tick, s); 1153 } 1154 1155 static int pxa2xx_rtc_pre_save(void *opaque) 1156 { 1157 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 1158 1159 pxa2xx_rtc_hzupdate(s); 1160 pxa2xx_rtc_piupdate(s); 1161 pxa2xx_rtc_swupdate(s); 1162 1163 return 0; 1164 } 1165 1166 static int pxa2xx_rtc_post_load(void *opaque, int version_id) 1167 { 1168 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 1169 1170 pxa2xx_rtc_alarm_update(s, s->rtsr); 1171 1172 return 0; 1173 } 1174 1175 static const VMStateDescription vmstate_pxa2xx_rtc_regs = { 1176 .name = "pxa2xx_rtc", 1177 .version_id = 0, 1178 .minimum_version_id = 0, 1179 .pre_save = pxa2xx_rtc_pre_save, 1180 .post_load = pxa2xx_rtc_post_load, 1181 .fields = (VMStateField[]) { 1182 VMSTATE_UINT32(rttr, PXA2xxRTCState), 1183 VMSTATE_UINT32(rtsr, PXA2xxRTCState), 1184 VMSTATE_UINT32(rtar, PXA2xxRTCState), 1185 VMSTATE_UINT32(rdar1, PXA2xxRTCState), 1186 VMSTATE_UINT32(rdar2, PXA2xxRTCState), 1187 VMSTATE_UINT32(ryar1, PXA2xxRTCState), 1188 VMSTATE_UINT32(ryar2, PXA2xxRTCState), 1189 VMSTATE_UINT32(swar1, PXA2xxRTCState), 1190 VMSTATE_UINT32(swar2, PXA2xxRTCState), 1191 VMSTATE_UINT32(piar, PXA2xxRTCState), 1192 VMSTATE_UINT32(last_rcnr, PXA2xxRTCState), 1193 VMSTATE_UINT32(last_rdcr, PXA2xxRTCState), 1194 VMSTATE_UINT32(last_rycr, PXA2xxRTCState), 1195 VMSTATE_UINT32(last_swcr, PXA2xxRTCState), 1196 VMSTATE_UINT32(last_rtcpicr, PXA2xxRTCState), 1197 VMSTATE_INT64(last_hz, PXA2xxRTCState), 1198 VMSTATE_INT64(last_sw, PXA2xxRTCState), 1199 VMSTATE_INT64(last_pi, PXA2xxRTCState), 1200 VMSTATE_END_OF_LIST(), 1201 }, 1202 }; 1203 1204 static void pxa2xx_rtc_sysbus_class_init(ObjectClass *klass, void *data) 1205 { 1206 DeviceClass *dc = DEVICE_CLASS(klass); 1207 1208 dc->desc = "PXA2xx RTC Controller"; 1209 dc->vmsd = &vmstate_pxa2xx_rtc_regs; 1210 dc->realize = pxa2xx_rtc_realize; 1211 } 1212 1213 static const TypeInfo pxa2xx_rtc_sysbus_info = { 1214 .name = TYPE_PXA2XX_RTC, 1215 .parent = TYPE_SYS_BUS_DEVICE, 1216 .instance_size = sizeof(PXA2xxRTCState), 1217 .instance_init = pxa2xx_rtc_init, 1218 .class_init = pxa2xx_rtc_sysbus_class_init, 1219 }; 1220 1221 /* I2C Interface */ 1222 1223 #define TYPE_PXA2XX_I2C_SLAVE "pxa2xx-i2c-slave" 1224 #define PXA2XX_I2C_SLAVE(obj) \ 1225 OBJECT_CHECK(PXA2xxI2CSlaveState, (obj), TYPE_PXA2XX_I2C_SLAVE) 1226 1227 typedef struct PXA2xxI2CSlaveState { 1228 I2CSlave parent_obj; 1229 1230 PXA2xxI2CState *host; 1231 } PXA2xxI2CSlaveState; 1232 1233 #define TYPE_PXA2XX_I2C "pxa2xx_i2c" 1234 #define PXA2XX_I2C(obj) \ 1235 OBJECT_CHECK(PXA2xxI2CState, (obj), TYPE_PXA2XX_I2C) 1236 1237 struct PXA2xxI2CState { 1238 /*< private >*/ 1239 SysBusDevice parent_obj; 1240 /*< public >*/ 1241 1242 MemoryRegion iomem; 1243 PXA2xxI2CSlaveState *slave; 1244 I2CBus *bus; 1245 qemu_irq irq; 1246 uint32_t offset; 1247 uint32_t region_size; 1248 1249 uint16_t control; 1250 uint16_t status; 1251 uint8_t ibmr; 1252 uint8_t data; 1253 }; 1254 1255 #define IBMR 0x80 /* I2C Bus Monitor register */ 1256 #define IDBR 0x88 /* I2C Data Buffer register */ 1257 #define ICR 0x90 /* I2C Control register */ 1258 #define ISR 0x98 /* I2C Status register */ 1259 #define ISAR 0xa0 /* I2C Slave Address register */ 1260 1261 static void pxa2xx_i2c_update(PXA2xxI2CState *s) 1262 { 1263 uint16_t level = 0; 1264 level |= s->status & s->control & (1 << 10); /* BED */ 1265 level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */ 1266 level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */ 1267 level |= s->status & (1 << 9); /* SAD */ 1268 qemu_set_irq(s->irq, !!level); 1269 } 1270 1271 /* These are only stubs now. */ 1272 static int pxa2xx_i2c_event(I2CSlave *i2c, enum i2c_event event) 1273 { 1274 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c); 1275 PXA2xxI2CState *s = slave->host; 1276 1277 switch (event) { 1278 case I2C_START_SEND: 1279 s->status |= (1 << 9); /* set SAD */ 1280 s->status &= ~(1 << 0); /* clear RWM */ 1281 break; 1282 case I2C_START_RECV: 1283 s->status |= (1 << 9); /* set SAD */ 1284 s->status |= 1 << 0; /* set RWM */ 1285 break; 1286 case I2C_FINISH: 1287 s->status |= (1 << 4); /* set SSD */ 1288 break; 1289 case I2C_NACK: 1290 s->status |= 1 << 1; /* set ACKNAK */ 1291 break; 1292 } 1293 pxa2xx_i2c_update(s); 1294 1295 return 0; 1296 } 1297 1298 static uint8_t pxa2xx_i2c_rx(I2CSlave *i2c) 1299 { 1300 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c); 1301 PXA2xxI2CState *s = slave->host; 1302 1303 if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) { 1304 return 0; 1305 } 1306 1307 if (s->status & (1 << 0)) { /* RWM */ 1308 s->status |= 1 << 6; /* set ITE */ 1309 } 1310 pxa2xx_i2c_update(s); 1311 1312 return s->data; 1313 } 1314 1315 static int pxa2xx_i2c_tx(I2CSlave *i2c, uint8_t data) 1316 { 1317 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c); 1318 PXA2xxI2CState *s = slave->host; 1319 1320 if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) { 1321 return 1; 1322 } 1323 1324 if (!(s->status & (1 << 0))) { /* RWM */ 1325 s->status |= 1 << 7; /* set IRF */ 1326 s->data = data; 1327 } 1328 pxa2xx_i2c_update(s); 1329 1330 return 1; 1331 } 1332 1333 static uint64_t pxa2xx_i2c_read(void *opaque, hwaddr addr, 1334 unsigned size) 1335 { 1336 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; 1337 I2CSlave *slave; 1338 1339 addr -= s->offset; 1340 switch (addr) { 1341 case ICR: 1342 return s->control; 1343 case ISR: 1344 return s->status | (i2c_bus_busy(s->bus) << 2); 1345 case ISAR: 1346 slave = I2C_SLAVE(s->slave); 1347 return slave->address; 1348 case IDBR: 1349 return s->data; 1350 case IBMR: 1351 if (s->status & (1 << 2)) 1352 s->ibmr ^= 3; /* Fake SCL and SDA pin changes */ 1353 else 1354 s->ibmr = 0; 1355 return s->ibmr; 1356 default: 1357 printf("%s: Bad register " REG_FMT "\n", __func__, addr); 1358 break; 1359 } 1360 return 0; 1361 } 1362 1363 static void pxa2xx_i2c_write(void *opaque, hwaddr addr, 1364 uint64_t value64, unsigned size) 1365 { 1366 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; 1367 uint32_t value = value64; 1368 int ack; 1369 1370 addr -= s->offset; 1371 switch (addr) { 1372 case ICR: 1373 s->control = value & 0xfff7; 1374 if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */ 1375 /* TODO: slave mode */ 1376 if (value & (1 << 0)) { /* START condition */ 1377 if (s->data & 1) 1378 s->status |= 1 << 0; /* set RWM */ 1379 else 1380 s->status &= ~(1 << 0); /* clear RWM */ 1381 ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1); 1382 } else { 1383 if (s->status & (1 << 0)) { /* RWM */ 1384 s->data = i2c_recv(s->bus); 1385 if (value & (1 << 2)) /* ACKNAK */ 1386 i2c_nack(s->bus); 1387 ack = 1; 1388 } else 1389 ack = !i2c_send(s->bus, s->data); 1390 } 1391 1392 if (value & (1 << 1)) /* STOP condition */ 1393 i2c_end_transfer(s->bus); 1394 1395 if (ack) { 1396 if (value & (1 << 0)) /* START condition */ 1397 s->status |= 1 << 6; /* set ITE */ 1398 else 1399 if (s->status & (1 << 0)) /* RWM */ 1400 s->status |= 1 << 7; /* set IRF */ 1401 else 1402 s->status |= 1 << 6; /* set ITE */ 1403 s->status &= ~(1 << 1); /* clear ACKNAK */ 1404 } else { 1405 s->status |= 1 << 6; /* set ITE */ 1406 s->status |= 1 << 10; /* set BED */ 1407 s->status |= 1 << 1; /* set ACKNAK */ 1408 } 1409 } 1410 if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */ 1411 if (value & (1 << 4)) /* MA */ 1412 i2c_end_transfer(s->bus); 1413 pxa2xx_i2c_update(s); 1414 break; 1415 1416 case ISR: 1417 s->status &= ~(value & 0x07f0); 1418 pxa2xx_i2c_update(s); 1419 break; 1420 1421 case ISAR: 1422 i2c_set_slave_address(I2C_SLAVE(s->slave), value & 0x7f); 1423 break; 1424 1425 case IDBR: 1426 s->data = value & 0xff; 1427 break; 1428 1429 default: 1430 printf("%s: Bad register " REG_FMT "\n", __func__, addr); 1431 } 1432 } 1433 1434 static const MemoryRegionOps pxa2xx_i2c_ops = { 1435 .read = pxa2xx_i2c_read, 1436 .write = pxa2xx_i2c_write, 1437 .endianness = DEVICE_NATIVE_ENDIAN, 1438 }; 1439 1440 static const VMStateDescription vmstate_pxa2xx_i2c_slave = { 1441 .name = "pxa2xx_i2c_slave", 1442 .version_id = 1, 1443 .minimum_version_id = 1, 1444 .fields = (VMStateField[]) { 1445 VMSTATE_I2C_SLAVE(parent_obj, PXA2xxI2CSlaveState), 1446 VMSTATE_END_OF_LIST() 1447 } 1448 }; 1449 1450 static const VMStateDescription vmstate_pxa2xx_i2c = { 1451 .name = "pxa2xx_i2c", 1452 .version_id = 1, 1453 .minimum_version_id = 1, 1454 .fields = (VMStateField[]) { 1455 VMSTATE_UINT16(control, PXA2xxI2CState), 1456 VMSTATE_UINT16(status, PXA2xxI2CState), 1457 VMSTATE_UINT8(ibmr, PXA2xxI2CState), 1458 VMSTATE_UINT8(data, PXA2xxI2CState), 1459 VMSTATE_STRUCT_POINTER(slave, PXA2xxI2CState, 1460 vmstate_pxa2xx_i2c_slave, PXA2xxI2CSlaveState), 1461 VMSTATE_END_OF_LIST() 1462 } 1463 }; 1464 1465 static void pxa2xx_i2c_slave_class_init(ObjectClass *klass, void *data) 1466 { 1467 I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); 1468 1469 k->event = pxa2xx_i2c_event; 1470 k->recv = pxa2xx_i2c_rx; 1471 k->send = pxa2xx_i2c_tx; 1472 } 1473 1474 static const TypeInfo pxa2xx_i2c_slave_info = { 1475 .name = TYPE_PXA2XX_I2C_SLAVE, 1476 .parent = TYPE_I2C_SLAVE, 1477 .instance_size = sizeof(PXA2xxI2CSlaveState), 1478 .class_init = pxa2xx_i2c_slave_class_init, 1479 }; 1480 1481 PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base, 1482 qemu_irq irq, uint32_t region_size) 1483 { 1484 DeviceState *dev; 1485 SysBusDevice *i2c_dev; 1486 PXA2xxI2CState *s; 1487 I2CBus *i2cbus; 1488 1489 dev = qdev_create(NULL, TYPE_PXA2XX_I2C); 1490 qdev_prop_set_uint32(dev, "size", region_size + 1); 1491 qdev_prop_set_uint32(dev, "offset", base & region_size); 1492 qdev_init_nofail(dev); 1493 1494 i2c_dev = SYS_BUS_DEVICE(dev); 1495 sysbus_mmio_map(i2c_dev, 0, base & ~region_size); 1496 sysbus_connect_irq(i2c_dev, 0, irq); 1497 1498 s = PXA2XX_I2C(i2c_dev); 1499 /* FIXME: Should the slave device really be on a separate bus? */ 1500 i2cbus = i2c_init_bus(dev, "dummy"); 1501 dev = i2c_create_slave(i2cbus, TYPE_PXA2XX_I2C_SLAVE, 0); 1502 s->slave = PXA2XX_I2C_SLAVE(dev); 1503 s->slave->host = s; 1504 1505 return s; 1506 } 1507 1508 static void pxa2xx_i2c_initfn(Object *obj) 1509 { 1510 DeviceState *dev = DEVICE(obj); 1511 PXA2xxI2CState *s = PXA2XX_I2C(obj); 1512 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1513 1514 s->bus = i2c_init_bus(dev, NULL); 1515 1516 memory_region_init_io(&s->iomem, obj, &pxa2xx_i2c_ops, s, 1517 "pxa2xx-i2c", s->region_size); 1518 sysbus_init_mmio(sbd, &s->iomem); 1519 sysbus_init_irq(sbd, &s->irq); 1520 } 1521 1522 I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s) 1523 { 1524 return s->bus; 1525 } 1526 1527 static Property pxa2xx_i2c_properties[] = { 1528 DEFINE_PROP_UINT32("size", PXA2xxI2CState, region_size, 0x10000), 1529 DEFINE_PROP_UINT32("offset", PXA2xxI2CState, offset, 0), 1530 DEFINE_PROP_END_OF_LIST(), 1531 }; 1532 1533 static void pxa2xx_i2c_class_init(ObjectClass *klass, void *data) 1534 { 1535 DeviceClass *dc = DEVICE_CLASS(klass); 1536 1537 dc->desc = "PXA2xx I2C Bus Controller"; 1538 dc->vmsd = &vmstate_pxa2xx_i2c; 1539 device_class_set_props(dc, pxa2xx_i2c_properties); 1540 } 1541 1542 static const TypeInfo pxa2xx_i2c_info = { 1543 .name = TYPE_PXA2XX_I2C, 1544 .parent = TYPE_SYS_BUS_DEVICE, 1545 .instance_size = sizeof(PXA2xxI2CState), 1546 .instance_init = pxa2xx_i2c_initfn, 1547 .class_init = pxa2xx_i2c_class_init, 1548 }; 1549 1550 /* PXA Inter-IC Sound Controller */ 1551 static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s) 1552 { 1553 i2s->rx_len = 0; 1554 i2s->tx_len = 0; 1555 i2s->fifo_len = 0; 1556 i2s->clk = 0x1a; 1557 i2s->control[0] = 0x00; 1558 i2s->control[1] = 0x00; 1559 i2s->status = 0x00; 1560 i2s->mask = 0x00; 1561 } 1562 1563 #define SACR_TFTH(val) ((val >> 8) & 0xf) 1564 #define SACR_RFTH(val) ((val >> 12) & 0xf) 1565 #define SACR_DREC(val) (val & (1 << 3)) 1566 #define SACR_DPRL(val) (val & (1 << 4)) 1567 1568 static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s) 1569 { 1570 int rfs, tfs; 1571 rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len && 1572 !SACR_DREC(i2s->control[1]); 1573 tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) && 1574 i2s->enable && !SACR_DPRL(i2s->control[1]); 1575 1576 qemu_set_irq(i2s->rx_dma, rfs); 1577 qemu_set_irq(i2s->tx_dma, tfs); 1578 1579 i2s->status &= 0xe0; 1580 if (i2s->fifo_len < 16 || !i2s->enable) 1581 i2s->status |= 1 << 0; /* TNF */ 1582 if (i2s->rx_len) 1583 i2s->status |= 1 << 1; /* RNE */ 1584 if (i2s->enable) 1585 i2s->status |= 1 << 2; /* BSY */ 1586 if (tfs) 1587 i2s->status |= 1 << 3; /* TFS */ 1588 if (rfs) 1589 i2s->status |= 1 << 4; /* RFS */ 1590 if (!(i2s->tx_len && i2s->enable)) 1591 i2s->status |= i2s->fifo_len << 8; /* TFL */ 1592 i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */ 1593 1594 qemu_set_irq(i2s->irq, i2s->status & i2s->mask); 1595 } 1596 1597 #define SACR0 0x00 /* Serial Audio Global Control register */ 1598 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */ 1599 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */ 1600 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */ 1601 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */ 1602 #define SADIV 0x60 /* Serial Audio Clock Divider register */ 1603 #define SADR 0x80 /* Serial Audio Data register */ 1604 1605 static uint64_t pxa2xx_i2s_read(void *opaque, hwaddr addr, 1606 unsigned size) 1607 { 1608 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; 1609 1610 switch (addr) { 1611 case SACR0: 1612 return s->control[0]; 1613 case SACR1: 1614 return s->control[1]; 1615 case SASR0: 1616 return s->status; 1617 case SAIMR: 1618 return s->mask; 1619 case SAICR: 1620 return 0; 1621 case SADIV: 1622 return s->clk; 1623 case SADR: 1624 if (s->rx_len > 0) { 1625 s->rx_len --; 1626 pxa2xx_i2s_update(s); 1627 return s->codec_in(s->opaque); 1628 } 1629 return 0; 1630 default: 1631 printf("%s: Bad register " REG_FMT "\n", __func__, addr); 1632 break; 1633 } 1634 return 0; 1635 } 1636 1637 static void pxa2xx_i2s_write(void *opaque, hwaddr addr, 1638 uint64_t value, unsigned size) 1639 { 1640 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; 1641 uint32_t *sample; 1642 1643 switch (addr) { 1644 case SACR0: 1645 if (value & (1 << 3)) /* RST */ 1646 pxa2xx_i2s_reset(s); 1647 s->control[0] = value & 0xff3d; 1648 if (!s->enable && (value & 1) && s->tx_len) { /* ENB */ 1649 for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++) 1650 s->codec_out(s->opaque, *sample); 1651 s->status &= ~(1 << 7); /* I2SOFF */ 1652 } 1653 if (value & (1 << 4)) /* EFWR */ 1654 printf("%s: Attempt to use special function\n", __func__); 1655 s->enable = (value & 9) == 1; /* ENB && !RST*/ 1656 pxa2xx_i2s_update(s); 1657 break; 1658 case SACR1: 1659 s->control[1] = value & 0x0039; 1660 if (value & (1 << 5)) /* ENLBF */ 1661 printf("%s: Attempt to use loopback function\n", __func__); 1662 if (value & (1 << 4)) /* DPRL */ 1663 s->fifo_len = 0; 1664 pxa2xx_i2s_update(s); 1665 break; 1666 case SAIMR: 1667 s->mask = value & 0x0078; 1668 pxa2xx_i2s_update(s); 1669 break; 1670 case SAICR: 1671 s->status &= ~(value & (3 << 5)); 1672 pxa2xx_i2s_update(s); 1673 break; 1674 case SADIV: 1675 s->clk = value & 0x007f; 1676 break; 1677 case SADR: 1678 if (s->tx_len && s->enable) { 1679 s->tx_len --; 1680 pxa2xx_i2s_update(s); 1681 s->codec_out(s->opaque, value); 1682 } else if (s->fifo_len < 16) { 1683 s->fifo[s->fifo_len ++] = value; 1684 pxa2xx_i2s_update(s); 1685 } 1686 break; 1687 default: 1688 printf("%s: Bad register " REG_FMT "\n", __func__, addr); 1689 } 1690 } 1691 1692 static const MemoryRegionOps pxa2xx_i2s_ops = { 1693 .read = pxa2xx_i2s_read, 1694 .write = pxa2xx_i2s_write, 1695 .endianness = DEVICE_NATIVE_ENDIAN, 1696 }; 1697 1698 static const VMStateDescription vmstate_pxa2xx_i2s = { 1699 .name = "pxa2xx_i2s", 1700 .version_id = 0, 1701 .minimum_version_id = 0, 1702 .fields = (VMStateField[]) { 1703 VMSTATE_UINT32_ARRAY(control, PXA2xxI2SState, 2), 1704 VMSTATE_UINT32(status, PXA2xxI2SState), 1705 VMSTATE_UINT32(mask, PXA2xxI2SState), 1706 VMSTATE_UINT32(clk, PXA2xxI2SState), 1707 VMSTATE_INT32(enable, PXA2xxI2SState), 1708 VMSTATE_INT32(rx_len, PXA2xxI2SState), 1709 VMSTATE_INT32(tx_len, PXA2xxI2SState), 1710 VMSTATE_INT32(fifo_len, PXA2xxI2SState), 1711 VMSTATE_END_OF_LIST() 1712 } 1713 }; 1714 1715 static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx) 1716 { 1717 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; 1718 uint32_t *sample; 1719 1720 /* Signal FIFO errors */ 1721 if (s->enable && s->tx_len) 1722 s->status |= 1 << 5; /* TUR */ 1723 if (s->enable && s->rx_len) 1724 s->status |= 1 << 6; /* ROR */ 1725 1726 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to 1727 * handle the cases where it makes a difference. */ 1728 s->tx_len = tx - s->fifo_len; 1729 s->rx_len = rx; 1730 /* Note that is s->codec_out wasn't set, we wouldn't get called. */ 1731 if (s->enable) 1732 for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++) 1733 s->codec_out(s->opaque, *sample); 1734 pxa2xx_i2s_update(s); 1735 } 1736 1737 static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem, 1738 hwaddr base, 1739 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma) 1740 { 1741 PXA2xxI2SState *s = g_new0(PXA2xxI2SState, 1); 1742 1743 s->irq = irq; 1744 s->rx_dma = rx_dma; 1745 s->tx_dma = tx_dma; 1746 s->data_req = pxa2xx_i2s_data_req; 1747 1748 pxa2xx_i2s_reset(s); 1749 1750 memory_region_init_io(&s->iomem, NULL, &pxa2xx_i2s_ops, s, 1751 "pxa2xx-i2s", 0x100000); 1752 memory_region_add_subregion(sysmem, base, &s->iomem); 1753 1754 vmstate_register(NULL, base, &vmstate_pxa2xx_i2s, s); 1755 1756 return s; 1757 } 1758 1759 /* PXA Fast Infra-red Communications Port */ 1760 #define TYPE_PXA2XX_FIR "pxa2xx-fir" 1761 #define PXA2XX_FIR(obj) OBJECT_CHECK(PXA2xxFIrState, (obj), TYPE_PXA2XX_FIR) 1762 1763 struct PXA2xxFIrState { 1764 /*< private >*/ 1765 SysBusDevice parent_obj; 1766 /*< public >*/ 1767 1768 MemoryRegion iomem; 1769 qemu_irq irq; 1770 qemu_irq rx_dma; 1771 qemu_irq tx_dma; 1772 uint32_t enable; 1773 CharBackend chr; 1774 1775 uint8_t control[3]; 1776 uint8_t status[2]; 1777 1778 uint32_t rx_len; 1779 uint32_t rx_start; 1780 uint8_t rx_fifo[64]; 1781 }; 1782 1783 static void pxa2xx_fir_reset(DeviceState *d) 1784 { 1785 PXA2xxFIrState *s = PXA2XX_FIR(d); 1786 1787 s->control[0] = 0x00; 1788 s->control[1] = 0x00; 1789 s->control[2] = 0x00; 1790 s->status[0] = 0x00; 1791 s->status[1] = 0x00; 1792 s->enable = 0; 1793 } 1794 1795 static inline void pxa2xx_fir_update(PXA2xxFIrState *s) 1796 { 1797 static const int tresh[4] = { 8, 16, 32, 0 }; 1798 int intr = 0; 1799 if ((s->control[0] & (1 << 4)) && /* RXE */ 1800 s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */ 1801 s->status[0] |= 1 << 4; /* RFS */ 1802 else 1803 s->status[0] &= ~(1 << 4); /* RFS */ 1804 if (s->control[0] & (1 << 3)) /* TXE */ 1805 s->status[0] |= 1 << 3; /* TFS */ 1806 else 1807 s->status[0] &= ~(1 << 3); /* TFS */ 1808 if (s->rx_len) 1809 s->status[1] |= 1 << 2; /* RNE */ 1810 else 1811 s->status[1] &= ~(1 << 2); /* RNE */ 1812 if (s->control[0] & (1 << 4)) /* RXE */ 1813 s->status[1] |= 1 << 0; /* RSY */ 1814 else 1815 s->status[1] &= ~(1 << 0); /* RSY */ 1816 1817 intr |= (s->control[0] & (1 << 5)) && /* RIE */ 1818 (s->status[0] & (1 << 4)); /* RFS */ 1819 intr |= (s->control[0] & (1 << 6)) && /* TIE */ 1820 (s->status[0] & (1 << 3)); /* TFS */ 1821 intr |= (s->control[2] & (1 << 4)) && /* TRAIL */ 1822 (s->status[0] & (1 << 6)); /* EOC */ 1823 intr |= (s->control[0] & (1 << 2)) && /* TUS */ 1824 (s->status[0] & (1 << 1)); /* TUR */ 1825 intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */ 1826 1827 qemu_set_irq(s->rx_dma, (s->status[0] >> 4) & 1); 1828 qemu_set_irq(s->tx_dma, (s->status[0] >> 3) & 1); 1829 1830 qemu_set_irq(s->irq, intr && s->enable); 1831 } 1832 1833 #define ICCR0 0x00 /* FICP Control register 0 */ 1834 #define ICCR1 0x04 /* FICP Control register 1 */ 1835 #define ICCR2 0x08 /* FICP Control register 2 */ 1836 #define ICDR 0x0c /* FICP Data register */ 1837 #define ICSR0 0x14 /* FICP Status register 0 */ 1838 #define ICSR1 0x18 /* FICP Status register 1 */ 1839 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */ 1840 1841 static uint64_t pxa2xx_fir_read(void *opaque, hwaddr addr, 1842 unsigned size) 1843 { 1844 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1845 uint8_t ret; 1846 1847 switch (addr) { 1848 case ICCR0: 1849 return s->control[0]; 1850 case ICCR1: 1851 return s->control[1]; 1852 case ICCR2: 1853 return s->control[2]; 1854 case ICDR: 1855 s->status[0] &= ~0x01; 1856 s->status[1] &= ~0x72; 1857 if (s->rx_len) { 1858 s->rx_len --; 1859 ret = s->rx_fifo[s->rx_start ++]; 1860 s->rx_start &= 63; 1861 pxa2xx_fir_update(s); 1862 return ret; 1863 } 1864 printf("%s: Rx FIFO underrun.\n", __func__); 1865 break; 1866 case ICSR0: 1867 return s->status[0]; 1868 case ICSR1: 1869 return s->status[1] | (1 << 3); /* TNF */ 1870 case ICFOR: 1871 return s->rx_len; 1872 default: 1873 printf("%s: Bad register " REG_FMT "\n", __func__, addr); 1874 break; 1875 } 1876 return 0; 1877 } 1878 1879 static void pxa2xx_fir_write(void *opaque, hwaddr addr, 1880 uint64_t value64, unsigned size) 1881 { 1882 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1883 uint32_t value = value64; 1884 uint8_t ch; 1885 1886 switch (addr) { 1887 case ICCR0: 1888 s->control[0] = value; 1889 if (!(value & (1 << 4))) /* RXE */ 1890 s->rx_len = s->rx_start = 0; 1891 if (!(value & (1 << 3))) { /* TXE */ 1892 /* Nop */ 1893 } 1894 s->enable = value & 1; /* ITR */ 1895 if (!s->enable) 1896 s->status[0] = 0; 1897 pxa2xx_fir_update(s); 1898 break; 1899 case ICCR1: 1900 s->control[1] = value; 1901 break; 1902 case ICCR2: 1903 s->control[2] = value & 0x3f; 1904 pxa2xx_fir_update(s); 1905 break; 1906 case ICDR: 1907 if (s->control[2] & (1 << 2)) { /* TXP */ 1908 ch = value; 1909 } else { 1910 ch = ~value; 1911 } 1912 if (s->enable && (s->control[0] & (1 << 3))) { /* TXE */ 1913 /* XXX this blocks entire thread. Rewrite to use 1914 * qemu_chr_fe_write and background I/O callbacks */ 1915 qemu_chr_fe_write_all(&s->chr, &ch, 1); 1916 } 1917 break; 1918 case ICSR0: 1919 s->status[0] &= ~(value & 0x66); 1920 pxa2xx_fir_update(s); 1921 break; 1922 case ICFOR: 1923 break; 1924 default: 1925 printf("%s: Bad register " REG_FMT "\n", __func__, addr); 1926 } 1927 } 1928 1929 static const MemoryRegionOps pxa2xx_fir_ops = { 1930 .read = pxa2xx_fir_read, 1931 .write = pxa2xx_fir_write, 1932 .endianness = DEVICE_NATIVE_ENDIAN, 1933 }; 1934 1935 static int pxa2xx_fir_is_empty(void *opaque) 1936 { 1937 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1938 return (s->rx_len < 64); 1939 } 1940 1941 static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size) 1942 { 1943 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1944 if (!(s->control[0] & (1 << 4))) /* RXE */ 1945 return; 1946 1947 while (size --) { 1948 s->status[1] |= 1 << 4; /* EOF */ 1949 if (s->rx_len >= 64) { 1950 s->status[1] |= 1 << 6; /* ROR */ 1951 break; 1952 } 1953 1954 if (s->control[2] & (1 << 3)) /* RXP */ 1955 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++); 1956 else 1957 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++); 1958 } 1959 1960 pxa2xx_fir_update(s); 1961 } 1962 1963 static void pxa2xx_fir_event(void *opaque, QEMUChrEvent event) 1964 { 1965 } 1966 1967 static void pxa2xx_fir_instance_init(Object *obj) 1968 { 1969 PXA2xxFIrState *s = PXA2XX_FIR(obj); 1970 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1971 1972 memory_region_init_io(&s->iomem, obj, &pxa2xx_fir_ops, s, 1973 "pxa2xx-fir", 0x1000); 1974 sysbus_init_mmio(sbd, &s->iomem); 1975 sysbus_init_irq(sbd, &s->irq); 1976 sysbus_init_irq(sbd, &s->rx_dma); 1977 sysbus_init_irq(sbd, &s->tx_dma); 1978 } 1979 1980 static void pxa2xx_fir_realize(DeviceState *dev, Error **errp) 1981 { 1982 PXA2xxFIrState *s = PXA2XX_FIR(dev); 1983 1984 qemu_chr_fe_set_handlers(&s->chr, pxa2xx_fir_is_empty, 1985 pxa2xx_fir_rx, pxa2xx_fir_event, NULL, s, NULL, 1986 true); 1987 } 1988 1989 static bool pxa2xx_fir_vmstate_validate(void *opaque, int version_id) 1990 { 1991 PXA2xxFIrState *s = opaque; 1992 1993 return s->rx_start < ARRAY_SIZE(s->rx_fifo); 1994 } 1995 1996 static const VMStateDescription pxa2xx_fir_vmsd = { 1997 .name = "pxa2xx-fir", 1998 .version_id = 1, 1999 .minimum_version_id = 1, 2000 .fields = (VMStateField[]) { 2001 VMSTATE_UINT32(enable, PXA2xxFIrState), 2002 VMSTATE_UINT8_ARRAY(control, PXA2xxFIrState, 3), 2003 VMSTATE_UINT8_ARRAY(status, PXA2xxFIrState, 2), 2004 VMSTATE_UINT32(rx_len, PXA2xxFIrState), 2005 VMSTATE_UINT32(rx_start, PXA2xxFIrState), 2006 VMSTATE_VALIDATE("fifo is 64 bytes", pxa2xx_fir_vmstate_validate), 2007 VMSTATE_UINT8_ARRAY(rx_fifo, PXA2xxFIrState, 64), 2008 VMSTATE_END_OF_LIST() 2009 } 2010 }; 2011 2012 static Property pxa2xx_fir_properties[] = { 2013 DEFINE_PROP_CHR("chardev", PXA2xxFIrState, chr), 2014 DEFINE_PROP_END_OF_LIST(), 2015 }; 2016 2017 static void pxa2xx_fir_class_init(ObjectClass *klass, void *data) 2018 { 2019 DeviceClass *dc = DEVICE_CLASS(klass); 2020 2021 dc->realize = pxa2xx_fir_realize; 2022 dc->vmsd = &pxa2xx_fir_vmsd; 2023 device_class_set_props(dc, pxa2xx_fir_properties); 2024 dc->reset = pxa2xx_fir_reset; 2025 } 2026 2027 static const TypeInfo pxa2xx_fir_info = { 2028 .name = TYPE_PXA2XX_FIR, 2029 .parent = TYPE_SYS_BUS_DEVICE, 2030 .instance_size = sizeof(PXA2xxFIrState), 2031 .class_init = pxa2xx_fir_class_init, 2032 .instance_init = pxa2xx_fir_instance_init, 2033 }; 2034 2035 static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem, 2036 hwaddr base, 2037 qemu_irq irq, qemu_irq rx_dma, 2038 qemu_irq tx_dma, 2039 Chardev *chr) 2040 { 2041 DeviceState *dev; 2042 SysBusDevice *sbd; 2043 2044 dev = qdev_create(NULL, TYPE_PXA2XX_FIR); 2045 qdev_prop_set_chr(dev, "chardev", chr); 2046 qdev_init_nofail(dev); 2047 sbd = SYS_BUS_DEVICE(dev); 2048 sysbus_mmio_map(sbd, 0, base); 2049 sysbus_connect_irq(sbd, 0, irq); 2050 sysbus_connect_irq(sbd, 1, rx_dma); 2051 sysbus_connect_irq(sbd, 2, tx_dma); 2052 return PXA2XX_FIR(dev); 2053 } 2054 2055 static void pxa2xx_reset(void *opaque, int line, int level) 2056 { 2057 PXA2xxState *s = (PXA2xxState *) opaque; 2058 2059 if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */ 2060 cpu_reset(CPU(s->cpu)); 2061 /* TODO: reset peripherals */ 2062 } 2063 } 2064 2065 /* Initialise a PXA270 integrated chip (ARM based core). */ 2066 PXA2xxState *pxa270_init(MemoryRegion *address_space, 2067 unsigned int sdram_size, const char *cpu_type) 2068 { 2069 PXA2xxState *s; 2070 int i; 2071 DriveInfo *dinfo; 2072 s = g_new0(PXA2xxState, 1); 2073 2074 if (strncmp(cpu_type, "pxa27", 5)) { 2075 error_report("Machine requires a PXA27x processor"); 2076 exit(1); 2077 } 2078 2079 s->cpu = ARM_CPU(cpu_create(cpu_type)); 2080 s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0); 2081 2082 /* SDRAM & Internal Memory Storage */ 2083 memory_region_init_ram(&s->sdram, NULL, "pxa270.sdram", sdram_size, 2084 &error_fatal); 2085 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram); 2086 memory_region_init_ram(&s->internal, NULL, "pxa270.internal", 0x40000, 2087 &error_fatal); 2088 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE, 2089 &s->internal); 2090 2091 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu); 2092 2093 s->dma = pxa27x_dma_init(0x40000000, 2094 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA)); 2095 2096 sysbus_create_varargs("pxa27x-timer", 0x40a00000, 2097 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0), 2098 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1), 2099 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2), 2100 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3), 2101 qdev_get_gpio_in(s->pic, PXA27X_PIC_OST_4_11), 2102 NULL); 2103 2104 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 121); 2105 2106 dinfo = drive_get(IF_SD, 0, 0); 2107 if (!dinfo && !qtest_enabled()) { 2108 warn_report("missing SecureDigital device"); 2109 } 2110 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, 2111 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 2112 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), 2113 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), 2114 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); 2115 2116 for (i = 0; pxa270_serial[i].io_base; i++) { 2117 if (serial_hd(i)) { 2118 serial_mm_init(address_space, pxa270_serial[i].io_base, 2, 2119 qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn), 2120 14857000 / 16, serial_hd(i), 2121 DEVICE_NATIVE_ENDIAN); 2122 } else { 2123 break; 2124 } 2125 } 2126 if (serial_hd(i)) 2127 s->fir = pxa2xx_fir_init(address_space, 0x40800000, 2128 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), 2129 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), 2130 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), 2131 serial_hd(i)); 2132 2133 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000, 2134 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); 2135 2136 s->cm_base = 0x41300000; 2137 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */ 2138 s->clkcfg = 0x00000009; /* Turbo mode active */ 2139 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000); 2140 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); 2141 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); 2142 2143 pxa2xx_setup_cp14(s); 2144 2145 s->mm_base = 0x48000000; 2146 s->mm_regs[MDMRS >> 2] = 0x00020002; 2147 s->mm_regs[MDREFR >> 2] = 0x03ca4000; 2148 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ 2149 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000); 2150 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem); 2151 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s); 2152 2153 s->pm_base = 0x40f00000; 2154 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100); 2155 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem); 2156 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s); 2157 2158 for (i = 0; pxa27x_ssp[i].io_base; i ++); 2159 s->ssp = g_new0(SSIBus *, i); 2160 for (i = 0; pxa27x_ssp[i].io_base; i ++) { 2161 DeviceState *dev; 2162 dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa27x_ssp[i].io_base, 2163 qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn)); 2164 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi"); 2165 } 2166 2167 sysbus_create_simple("sysbus-ohci", 0x4c000000, 2168 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1)); 2169 2170 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000); 2171 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000); 2172 2173 sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000, 2174 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM)); 2175 2176 s->i2c[0] = pxa2xx_i2c_init(0x40301600, 2177 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff); 2178 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, 2179 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff); 2180 2181 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000, 2182 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), 2183 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), 2184 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); 2185 2186 s->kp = pxa27x_keypad_init(address_space, 0x41500000, 2187 qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD)); 2188 2189 /* GPIO1 resets the processor */ 2190 /* The handler can be overridden by board-specific code */ 2191 qdev_connect_gpio_out(s->gpio, 1, s->reset); 2192 return s; 2193 } 2194 2195 /* Initialise a PXA255 integrated chip (ARM based core). */ 2196 PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size) 2197 { 2198 PXA2xxState *s; 2199 int i; 2200 DriveInfo *dinfo; 2201 2202 s = g_new0(PXA2xxState, 1); 2203 2204 s->cpu = ARM_CPU(cpu_create(ARM_CPU_TYPE_NAME("pxa255"))); 2205 s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0); 2206 2207 /* SDRAM & Internal Memory Storage */ 2208 memory_region_init_ram(&s->sdram, NULL, "pxa255.sdram", sdram_size, 2209 &error_fatal); 2210 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram); 2211 memory_region_init_ram(&s->internal, NULL, "pxa255.internal", 2212 PXA2XX_INTERNAL_SIZE, &error_fatal); 2213 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE, 2214 &s->internal); 2215 2216 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu); 2217 2218 s->dma = pxa255_dma_init(0x40000000, 2219 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA)); 2220 2221 sysbus_create_varargs("pxa25x-timer", 0x40a00000, 2222 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0), 2223 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1), 2224 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2), 2225 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3), 2226 NULL); 2227 2228 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 85); 2229 2230 dinfo = drive_get(IF_SD, 0, 0); 2231 if (!dinfo && !qtest_enabled()) { 2232 warn_report("missing SecureDigital device"); 2233 } 2234 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, 2235 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 2236 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), 2237 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), 2238 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); 2239 2240 for (i = 0; pxa255_serial[i].io_base; i++) { 2241 if (serial_hd(i)) { 2242 serial_mm_init(address_space, pxa255_serial[i].io_base, 2, 2243 qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn), 2244 14745600 / 16, serial_hd(i), 2245 DEVICE_NATIVE_ENDIAN); 2246 } else { 2247 break; 2248 } 2249 } 2250 if (serial_hd(i)) 2251 s->fir = pxa2xx_fir_init(address_space, 0x40800000, 2252 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), 2253 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), 2254 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), 2255 serial_hd(i)); 2256 2257 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000, 2258 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); 2259 2260 s->cm_base = 0x41300000; 2261 s->cm_regs[CCCR >> 2] = 0x00000121; /* from datasheet */ 2262 s->cm_regs[CKEN >> 2] = 0x00017def; /* from datasheet */ 2263 2264 s->clkcfg = 0x00000009; /* Turbo mode active */ 2265 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000); 2266 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); 2267 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); 2268 2269 pxa2xx_setup_cp14(s); 2270 2271 s->mm_base = 0x48000000; 2272 s->mm_regs[MDMRS >> 2] = 0x00020002; 2273 s->mm_regs[MDREFR >> 2] = 0x03ca4000; 2274 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ 2275 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000); 2276 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem); 2277 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s); 2278 2279 s->pm_base = 0x40f00000; 2280 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100); 2281 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem); 2282 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s); 2283 2284 for (i = 0; pxa255_ssp[i].io_base; i ++); 2285 s->ssp = g_new0(SSIBus *, i); 2286 for (i = 0; pxa255_ssp[i].io_base; i ++) { 2287 DeviceState *dev; 2288 dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa255_ssp[i].io_base, 2289 qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn)); 2290 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi"); 2291 } 2292 2293 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000); 2294 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000); 2295 2296 sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000, 2297 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM)); 2298 2299 s->i2c[0] = pxa2xx_i2c_init(0x40301600, 2300 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff); 2301 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, 2302 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff); 2303 2304 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000, 2305 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), 2306 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), 2307 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); 2308 2309 /* GPIO1 resets the processor */ 2310 /* The handler can be overridden by board-specific code */ 2311 qdev_connect_gpio_out(s->gpio, 1, s->reset); 2312 return s; 2313 } 2314 2315 static void pxa2xx_ssp_class_init(ObjectClass *klass, void *data) 2316 { 2317 DeviceClass *dc = DEVICE_CLASS(klass); 2318 2319 dc->reset = pxa2xx_ssp_reset; 2320 dc->vmsd = &vmstate_pxa2xx_ssp; 2321 } 2322 2323 static const TypeInfo pxa2xx_ssp_info = { 2324 .name = TYPE_PXA2XX_SSP, 2325 .parent = TYPE_SYS_BUS_DEVICE, 2326 .instance_size = sizeof(PXA2xxSSPState), 2327 .instance_init = pxa2xx_ssp_init, 2328 .class_init = pxa2xx_ssp_class_init, 2329 }; 2330 2331 static void pxa2xx_register_types(void) 2332 { 2333 type_register_static(&pxa2xx_i2c_slave_info); 2334 type_register_static(&pxa2xx_ssp_info); 2335 type_register_static(&pxa2xx_i2c_info); 2336 type_register_static(&pxa2xx_rtc_sysbus_info); 2337 type_register_static(&pxa2xx_fir_info); 2338 } 2339 2340 type_init(pxa2xx_register_types) 2341