1 /* 2 * Intel XScale PXA255/270 processor support. 3 * 4 * Copyright (c) 2006 Openedhand Ltd. 5 * Written by Andrzej Zaborowski <balrog@zabor.org> 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "hw/sysbus.h" 11 #include "hw/arm/pxa.h" 12 #include "sysemu/sysemu.h" 13 #include "hw/char/serial.h" 14 #include "hw/i2c/i2c.h" 15 #include "hw/ssi.h" 16 #include "sysemu/char.h" 17 #include "sysemu/blockdev.h" 18 19 static struct { 20 hwaddr io_base; 21 int irqn; 22 } pxa255_serial[] = { 23 { 0x40100000, PXA2XX_PIC_FFUART }, 24 { 0x40200000, PXA2XX_PIC_BTUART }, 25 { 0x40700000, PXA2XX_PIC_STUART }, 26 { 0x41600000, PXA25X_PIC_HWUART }, 27 { 0, 0 } 28 }, pxa270_serial[] = { 29 { 0x40100000, PXA2XX_PIC_FFUART }, 30 { 0x40200000, PXA2XX_PIC_BTUART }, 31 { 0x40700000, PXA2XX_PIC_STUART }, 32 { 0, 0 } 33 }; 34 35 typedef struct PXASSPDef { 36 hwaddr io_base; 37 int irqn; 38 } PXASSPDef; 39 40 #if 0 41 static PXASSPDef pxa250_ssp[] = { 42 { 0x41000000, PXA2XX_PIC_SSP }, 43 { 0, 0 } 44 }; 45 #endif 46 47 static PXASSPDef pxa255_ssp[] = { 48 { 0x41000000, PXA2XX_PIC_SSP }, 49 { 0x41400000, PXA25X_PIC_NSSP }, 50 { 0, 0 } 51 }; 52 53 #if 0 54 static PXASSPDef pxa26x_ssp[] = { 55 { 0x41000000, PXA2XX_PIC_SSP }, 56 { 0x41400000, PXA25X_PIC_NSSP }, 57 { 0x41500000, PXA26X_PIC_ASSP }, 58 { 0, 0 } 59 }; 60 #endif 61 62 static PXASSPDef pxa27x_ssp[] = { 63 { 0x41000000, PXA2XX_PIC_SSP }, 64 { 0x41700000, PXA27X_PIC_SSP2 }, 65 { 0x41900000, PXA2XX_PIC_SSP3 }, 66 { 0, 0 } 67 }; 68 69 #define PMCR 0x00 /* Power Manager Control register */ 70 #define PSSR 0x04 /* Power Manager Sleep Status register */ 71 #define PSPR 0x08 /* Power Manager Scratch-Pad register */ 72 #define PWER 0x0c /* Power Manager Wake-Up Enable register */ 73 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */ 74 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */ 75 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */ 76 #define PCFR 0x1c /* Power Manager General Configuration register */ 77 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */ 78 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */ 79 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */ 80 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */ 81 #define RCSR 0x30 /* Reset Controller Status register */ 82 #define PSLR 0x34 /* Power Manager Sleep Configuration register */ 83 #define PTSR 0x38 /* Power Manager Standby Configuration register */ 84 #define PVCR 0x40 /* Power Manager Voltage Change Control register */ 85 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */ 86 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */ 87 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */ 88 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */ 89 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */ 90 91 static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr, 92 unsigned size) 93 { 94 PXA2xxState *s = (PXA2xxState *) opaque; 95 96 switch (addr) { 97 case PMCR ... PCMD31: 98 if (addr & 3) 99 goto fail; 100 101 return s->pm_regs[addr >> 2]; 102 default: 103 fail: 104 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 105 break; 106 } 107 return 0; 108 } 109 110 static void pxa2xx_pm_write(void *opaque, hwaddr addr, 111 uint64_t value, unsigned size) 112 { 113 PXA2xxState *s = (PXA2xxState *) opaque; 114 115 switch (addr) { 116 case PMCR: 117 /* Clear the write-one-to-clear bits... */ 118 s->pm_regs[addr >> 2] &= ~(value & 0x2a); 119 /* ...and set the plain r/w bits */ 120 s->pm_regs[addr >> 2] &= ~0x15; 121 s->pm_regs[addr >> 2] |= value & 0x15; 122 break; 123 124 case PSSR: /* Read-clean registers */ 125 case RCSR: 126 case PKSR: 127 s->pm_regs[addr >> 2] &= ~value; 128 break; 129 130 default: /* Read-write registers */ 131 if (!(addr & 3)) { 132 s->pm_regs[addr >> 2] = value; 133 break; 134 } 135 136 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 137 break; 138 } 139 } 140 141 static const MemoryRegionOps pxa2xx_pm_ops = { 142 .read = pxa2xx_pm_read, 143 .write = pxa2xx_pm_write, 144 .endianness = DEVICE_NATIVE_ENDIAN, 145 }; 146 147 static const VMStateDescription vmstate_pxa2xx_pm = { 148 .name = "pxa2xx_pm", 149 .version_id = 0, 150 .minimum_version_id = 0, 151 .minimum_version_id_old = 0, 152 .fields = (VMStateField[]) { 153 VMSTATE_UINT32_ARRAY(pm_regs, PXA2xxState, 0x40), 154 VMSTATE_END_OF_LIST() 155 } 156 }; 157 158 #define CCCR 0x00 /* Core Clock Configuration register */ 159 #define CKEN 0x04 /* Clock Enable register */ 160 #define OSCC 0x08 /* Oscillator Configuration register */ 161 #define CCSR 0x0c /* Core Clock Status register */ 162 163 static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr, 164 unsigned size) 165 { 166 PXA2xxState *s = (PXA2xxState *) opaque; 167 168 switch (addr) { 169 case CCCR: 170 case CKEN: 171 case OSCC: 172 return s->cm_regs[addr >> 2]; 173 174 case CCSR: 175 return s->cm_regs[CCCR >> 2] | (3 << 28); 176 177 default: 178 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 179 break; 180 } 181 return 0; 182 } 183 184 static void pxa2xx_cm_write(void *opaque, hwaddr addr, 185 uint64_t value, unsigned size) 186 { 187 PXA2xxState *s = (PXA2xxState *) opaque; 188 189 switch (addr) { 190 case CCCR: 191 case CKEN: 192 s->cm_regs[addr >> 2] = value; 193 break; 194 195 case OSCC: 196 s->cm_regs[addr >> 2] &= ~0x6c; 197 s->cm_regs[addr >> 2] |= value & 0x6e; 198 if ((value >> 1) & 1) /* OON */ 199 s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */ 200 break; 201 202 default: 203 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 204 break; 205 } 206 } 207 208 static const MemoryRegionOps pxa2xx_cm_ops = { 209 .read = pxa2xx_cm_read, 210 .write = pxa2xx_cm_write, 211 .endianness = DEVICE_NATIVE_ENDIAN, 212 }; 213 214 static const VMStateDescription vmstate_pxa2xx_cm = { 215 .name = "pxa2xx_cm", 216 .version_id = 0, 217 .minimum_version_id = 0, 218 .minimum_version_id_old = 0, 219 .fields = (VMStateField[]) { 220 VMSTATE_UINT32_ARRAY(cm_regs, PXA2xxState, 4), 221 VMSTATE_UINT32(clkcfg, PXA2xxState), 222 VMSTATE_UINT32(pmnc, PXA2xxState), 223 VMSTATE_END_OF_LIST() 224 } 225 }; 226 227 static int pxa2xx_clkcfg_read(CPUARMState *env, const ARMCPRegInfo *ri, 228 uint64_t *value) 229 { 230 PXA2xxState *s = (PXA2xxState *)ri->opaque; 231 *value = s->clkcfg; 232 return 0; 233 } 234 235 static int pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri, 236 uint64_t value) 237 { 238 PXA2xxState *s = (PXA2xxState *)ri->opaque; 239 s->clkcfg = value & 0xf; 240 if (value & 2) { 241 printf("%s: CPU frequency change attempt\n", __func__); 242 } 243 return 0; 244 } 245 246 static int pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri, 247 uint64_t value) 248 { 249 PXA2xxState *s = (PXA2xxState *)ri->opaque; 250 static const char *pwrmode[8] = { 251 "Normal", "Idle", "Deep-idle", "Standby", 252 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep", 253 }; 254 255 if (value & 8) { 256 printf("%s: CPU voltage change attempt\n", __func__); 257 } 258 switch (value & 7) { 259 case 0: 260 /* Do nothing */ 261 break; 262 263 case 1: 264 /* Idle */ 265 if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) { /* CPDIS */ 266 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); 267 break; 268 } 269 /* Fall through. */ 270 271 case 2: 272 /* Deep-Idle */ 273 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); 274 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ 275 goto message; 276 277 case 3: 278 s->cpu->env.uncached_cpsr = 279 ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I; 280 s->cpu->env.cp15.c1_sys = 0; 281 s->cpu->env.cp15.c1_coproc = 0; 282 s->cpu->env.cp15.c2_base0 = 0; 283 s->cpu->env.cp15.c3 = 0; 284 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ 285 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ 286 287 /* 288 * The scratch-pad register is almost universally used 289 * for storing the return address on suspend. For the 290 * lack of a resuming bootloader, perform a jump 291 * directly to that address. 292 */ 293 memset(s->cpu->env.regs, 0, 4 * 15); 294 s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2]; 295 296 #if 0 297 buffer = 0xe59ff000; /* ldr pc, [pc, #0] */ 298 cpu_physical_memory_write(0, &buffer, 4); 299 buffer = s->pm_regs[PSPR >> 2]; 300 cpu_physical_memory_write(8, &buffer, 4); 301 #endif 302 303 /* Suspend */ 304 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); 305 306 goto message; 307 308 default: 309 message: 310 printf("%s: machine entered %s mode\n", __func__, 311 pwrmode[value & 7]); 312 } 313 314 return 0; 315 } 316 317 static int pxa2xx_cppmnc_read(CPUARMState *env, const ARMCPRegInfo *ri, 318 uint64_t *value) 319 { 320 PXA2xxState *s = (PXA2xxState *)ri->opaque; 321 *value = s->pmnc; 322 return 0; 323 } 324 325 static int pxa2xx_cppmnc_write(CPUARMState *env, const ARMCPRegInfo *ri, 326 uint64_t value) 327 { 328 PXA2xxState *s = (PXA2xxState *)ri->opaque; 329 s->pmnc = value; 330 return 0; 331 } 332 333 static int pxa2xx_cpccnt_read(CPUARMState *env, const ARMCPRegInfo *ri, 334 uint64_t *value) 335 { 336 PXA2xxState *s = (PXA2xxState *)ri->opaque; 337 if (s->pmnc & 1) { 338 *value = qemu_get_clock_ns(vm_clock); 339 } else { 340 *value = 0; 341 } 342 return 0; 343 } 344 345 static const ARMCPRegInfo pxa_cp_reginfo[] = { 346 /* cp14 crm==1: perf registers */ 347 { .name = "CPPMNC", .cp = 14, .crn = 0, .crm = 1, .opc1 = 0, .opc2 = 0, 348 .access = PL1_RW, 349 .readfn = pxa2xx_cppmnc_read, .writefn = pxa2xx_cppmnc_write }, 350 { .name = "CPCCNT", .cp = 14, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, 351 .access = PL1_RW, 352 .readfn = pxa2xx_cpccnt_read, .writefn = arm_cp_write_ignore }, 353 { .name = "CPINTEN", .cp = 14, .crn = 4, .crm = 1, .opc1 = 0, .opc2 = 0, 354 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 355 { .name = "CPFLAG", .cp = 14, .crn = 5, .crm = 1, .opc1 = 0, .opc2 = 0, 356 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 357 { .name = "CPEVTSEL", .cp = 14, .crn = 8, .crm = 1, .opc1 = 0, .opc2 = 0, 358 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 359 /* cp14 crm==2: performance count registers */ 360 { .name = "CPPMN0", .cp = 14, .crn = 0, .crm = 2, .opc1 = 0, .opc2 = 0, 361 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 362 { .name = "CPPMN1", .cp = 14, .crn = 1, .crm = 2, .opc1 = 0, .opc2 = 0, 363 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 364 { .name = "CPPMN2", .cp = 14, .crn = 2, .crm = 2, .opc1 = 0, .opc2 = 0, 365 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 366 { .name = "CPPMN3", .cp = 14, .crn = 2, .crm = 3, .opc1 = 0, .opc2 = 0, 367 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 368 /* cp14 crn==6: CLKCFG */ 369 { .name = "CLKCFG", .cp = 14, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, 370 .access = PL1_RW, 371 .readfn = pxa2xx_clkcfg_read, .writefn = pxa2xx_clkcfg_write }, 372 /* cp14 crn==7: PWRMODE */ 373 { .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0, 374 .access = PL1_RW, 375 .readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write }, 376 REGINFO_SENTINEL 377 }; 378 379 static void pxa2xx_setup_cp14(PXA2xxState *s) 380 { 381 define_arm_cp_regs_with_opaque(s->cpu, pxa_cp_reginfo, s); 382 } 383 384 #define MDCNFG 0x00 /* SDRAM Configuration register */ 385 #define MDREFR 0x04 /* SDRAM Refresh Control register */ 386 #define MSC0 0x08 /* Static Memory Control register 0 */ 387 #define MSC1 0x0c /* Static Memory Control register 1 */ 388 #define MSC2 0x10 /* Static Memory Control register 2 */ 389 #define MECR 0x14 /* Expansion Memory Bus Config register */ 390 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */ 391 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */ 392 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */ 393 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */ 394 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */ 395 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */ 396 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */ 397 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */ 398 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */ 399 #define ARB_CNTL 0x48 /* Arbiter Control register */ 400 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */ 401 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */ 402 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */ 403 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */ 404 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */ 405 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */ 406 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */ 407 408 static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr, 409 unsigned size) 410 { 411 PXA2xxState *s = (PXA2xxState *) opaque; 412 413 switch (addr) { 414 case MDCNFG ... SA1110: 415 if ((addr & 3) == 0) 416 return s->mm_regs[addr >> 2]; 417 418 default: 419 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 420 break; 421 } 422 return 0; 423 } 424 425 static void pxa2xx_mm_write(void *opaque, hwaddr addr, 426 uint64_t value, unsigned size) 427 { 428 PXA2xxState *s = (PXA2xxState *) opaque; 429 430 switch (addr) { 431 case MDCNFG ... SA1110: 432 if ((addr & 3) == 0) { 433 s->mm_regs[addr >> 2] = value; 434 break; 435 } 436 437 default: 438 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 439 break; 440 } 441 } 442 443 static const MemoryRegionOps pxa2xx_mm_ops = { 444 .read = pxa2xx_mm_read, 445 .write = pxa2xx_mm_write, 446 .endianness = DEVICE_NATIVE_ENDIAN, 447 }; 448 449 static const VMStateDescription vmstate_pxa2xx_mm = { 450 .name = "pxa2xx_mm", 451 .version_id = 0, 452 .minimum_version_id = 0, 453 .minimum_version_id_old = 0, 454 .fields = (VMStateField[]) { 455 VMSTATE_UINT32_ARRAY(mm_regs, PXA2xxState, 0x1a), 456 VMSTATE_END_OF_LIST() 457 } 458 }; 459 460 /* Synchronous Serial Ports */ 461 typedef struct { 462 SysBusDevice busdev; 463 MemoryRegion iomem; 464 qemu_irq irq; 465 int enable; 466 SSIBus *bus; 467 468 uint32_t sscr[2]; 469 uint32_t sspsp; 470 uint32_t ssto; 471 uint32_t ssitr; 472 uint32_t sssr; 473 uint8_t sstsa; 474 uint8_t ssrsa; 475 uint8_t ssacd; 476 477 uint32_t rx_fifo[16]; 478 int rx_level; 479 int rx_start; 480 } PXA2xxSSPState; 481 482 #define SSCR0 0x00 /* SSP Control register 0 */ 483 #define SSCR1 0x04 /* SSP Control register 1 */ 484 #define SSSR 0x08 /* SSP Status register */ 485 #define SSITR 0x0c /* SSP Interrupt Test register */ 486 #define SSDR 0x10 /* SSP Data register */ 487 #define SSTO 0x28 /* SSP Time-Out register */ 488 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */ 489 #define SSTSA 0x30 /* SSP TX Time Slot Active register */ 490 #define SSRSA 0x34 /* SSP RX Time Slot Active register */ 491 #define SSTSS 0x38 /* SSP Time Slot Status register */ 492 #define SSACD 0x3c /* SSP Audio Clock Divider register */ 493 494 /* Bitfields for above registers */ 495 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00) 496 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10) 497 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20) 498 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30) 499 #define SSCR0_SSE (1 << 7) 500 #define SSCR0_RIM (1 << 22) 501 #define SSCR0_TIM (1 << 23) 502 #define SSCR0_MOD (1 << 31) 503 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1) 504 #define SSCR1_RIE (1 << 0) 505 #define SSCR1_TIE (1 << 1) 506 #define SSCR1_LBM (1 << 2) 507 #define SSCR1_MWDS (1 << 5) 508 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1) 509 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1) 510 #define SSCR1_EFWR (1 << 14) 511 #define SSCR1_PINTE (1 << 18) 512 #define SSCR1_TINTE (1 << 19) 513 #define SSCR1_RSRE (1 << 20) 514 #define SSCR1_TSRE (1 << 21) 515 #define SSCR1_EBCEI (1 << 29) 516 #define SSITR_INT (7 << 5) 517 #define SSSR_TNF (1 << 2) 518 #define SSSR_RNE (1 << 3) 519 #define SSSR_TFS (1 << 5) 520 #define SSSR_RFS (1 << 6) 521 #define SSSR_ROR (1 << 7) 522 #define SSSR_PINT (1 << 18) 523 #define SSSR_TINT (1 << 19) 524 #define SSSR_EOC (1 << 20) 525 #define SSSR_TUR (1 << 21) 526 #define SSSR_BCE (1 << 23) 527 #define SSSR_RW 0x00bc0080 528 529 static void pxa2xx_ssp_int_update(PXA2xxSSPState *s) 530 { 531 int level = 0; 532 533 level |= s->ssitr & SSITR_INT; 534 level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI); 535 level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM); 536 level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT)); 537 level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE); 538 level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE); 539 level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM); 540 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE); 541 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE); 542 qemu_set_irq(s->irq, !!level); 543 } 544 545 static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s) 546 { 547 s->sssr &= ~(0xf << 12); /* Clear RFL */ 548 s->sssr &= ~(0xf << 8); /* Clear TFL */ 549 s->sssr &= ~SSSR_TFS; 550 s->sssr &= ~SSSR_TNF; 551 if (s->enable) { 552 s->sssr |= ((s->rx_level - 1) & 0xf) << 12; 553 if (s->rx_level >= SSCR1_RFT(s->sscr[1])) 554 s->sssr |= SSSR_RFS; 555 else 556 s->sssr &= ~SSSR_RFS; 557 if (s->rx_level) 558 s->sssr |= SSSR_RNE; 559 else 560 s->sssr &= ~SSSR_RNE; 561 /* TX FIFO is never filled, so it is always in underrun 562 condition if SSP is enabled */ 563 s->sssr |= SSSR_TFS; 564 s->sssr |= SSSR_TNF; 565 } 566 567 pxa2xx_ssp_int_update(s); 568 } 569 570 static uint64_t pxa2xx_ssp_read(void *opaque, hwaddr addr, 571 unsigned size) 572 { 573 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; 574 uint32_t retval; 575 576 switch (addr) { 577 case SSCR0: 578 return s->sscr[0]; 579 case SSCR1: 580 return s->sscr[1]; 581 case SSPSP: 582 return s->sspsp; 583 case SSTO: 584 return s->ssto; 585 case SSITR: 586 return s->ssitr; 587 case SSSR: 588 return s->sssr | s->ssitr; 589 case SSDR: 590 if (!s->enable) 591 return 0xffffffff; 592 if (s->rx_level < 1) { 593 printf("%s: SSP Rx Underrun\n", __FUNCTION__); 594 return 0xffffffff; 595 } 596 s->rx_level --; 597 retval = s->rx_fifo[s->rx_start ++]; 598 s->rx_start &= 0xf; 599 pxa2xx_ssp_fifo_update(s); 600 return retval; 601 case SSTSA: 602 return s->sstsa; 603 case SSRSA: 604 return s->ssrsa; 605 case SSTSS: 606 return 0; 607 case SSACD: 608 return s->ssacd; 609 default: 610 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 611 break; 612 } 613 return 0; 614 } 615 616 static void pxa2xx_ssp_write(void *opaque, hwaddr addr, 617 uint64_t value64, unsigned size) 618 { 619 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; 620 uint32_t value = value64; 621 622 switch (addr) { 623 case SSCR0: 624 s->sscr[0] = value & 0xc7ffffff; 625 s->enable = value & SSCR0_SSE; 626 if (value & SSCR0_MOD) 627 printf("%s: Attempt to use network mode\n", __FUNCTION__); 628 if (s->enable && SSCR0_DSS(value) < 4) 629 printf("%s: Wrong data size: %i bits\n", __FUNCTION__, 630 SSCR0_DSS(value)); 631 if (!(value & SSCR0_SSE)) { 632 s->sssr = 0; 633 s->ssitr = 0; 634 s->rx_level = 0; 635 } 636 pxa2xx_ssp_fifo_update(s); 637 break; 638 639 case SSCR1: 640 s->sscr[1] = value; 641 if (value & (SSCR1_LBM | SSCR1_EFWR)) 642 printf("%s: Attempt to use SSP test mode\n", __FUNCTION__); 643 pxa2xx_ssp_fifo_update(s); 644 break; 645 646 case SSPSP: 647 s->sspsp = value; 648 break; 649 650 case SSTO: 651 s->ssto = value; 652 break; 653 654 case SSITR: 655 s->ssitr = value & SSITR_INT; 656 pxa2xx_ssp_int_update(s); 657 break; 658 659 case SSSR: 660 s->sssr &= ~(value & SSSR_RW); 661 pxa2xx_ssp_int_update(s); 662 break; 663 664 case SSDR: 665 if (SSCR0_UWIRE(s->sscr[0])) { 666 if (s->sscr[1] & SSCR1_MWDS) 667 value &= 0xffff; 668 else 669 value &= 0xff; 670 } else 671 /* Note how 32bits overflow does no harm here */ 672 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1; 673 674 /* Data goes from here to the Tx FIFO and is shifted out from 675 * there directly to the slave, no need to buffer it. 676 */ 677 if (s->enable) { 678 uint32_t readval; 679 readval = ssi_transfer(s->bus, value); 680 if (s->rx_level < 0x10) { 681 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval; 682 } else { 683 s->sssr |= SSSR_ROR; 684 } 685 } 686 pxa2xx_ssp_fifo_update(s); 687 break; 688 689 case SSTSA: 690 s->sstsa = value; 691 break; 692 693 case SSRSA: 694 s->ssrsa = value; 695 break; 696 697 case SSACD: 698 s->ssacd = value; 699 break; 700 701 default: 702 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 703 break; 704 } 705 } 706 707 static const MemoryRegionOps pxa2xx_ssp_ops = { 708 .read = pxa2xx_ssp_read, 709 .write = pxa2xx_ssp_write, 710 .endianness = DEVICE_NATIVE_ENDIAN, 711 }; 712 713 static void pxa2xx_ssp_save(QEMUFile *f, void *opaque) 714 { 715 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; 716 int i; 717 718 qemu_put_be32(f, s->enable); 719 720 qemu_put_be32s(f, &s->sscr[0]); 721 qemu_put_be32s(f, &s->sscr[1]); 722 qemu_put_be32s(f, &s->sspsp); 723 qemu_put_be32s(f, &s->ssto); 724 qemu_put_be32s(f, &s->ssitr); 725 qemu_put_be32s(f, &s->sssr); 726 qemu_put_8s(f, &s->sstsa); 727 qemu_put_8s(f, &s->ssrsa); 728 qemu_put_8s(f, &s->ssacd); 729 730 qemu_put_byte(f, s->rx_level); 731 for (i = 0; i < s->rx_level; i ++) 732 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 0xf]); 733 } 734 735 static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id) 736 { 737 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; 738 int i; 739 740 s->enable = qemu_get_be32(f); 741 742 qemu_get_be32s(f, &s->sscr[0]); 743 qemu_get_be32s(f, &s->sscr[1]); 744 qemu_get_be32s(f, &s->sspsp); 745 qemu_get_be32s(f, &s->ssto); 746 qemu_get_be32s(f, &s->ssitr); 747 qemu_get_be32s(f, &s->sssr); 748 qemu_get_8s(f, &s->sstsa); 749 qemu_get_8s(f, &s->ssrsa); 750 qemu_get_8s(f, &s->ssacd); 751 752 s->rx_level = qemu_get_byte(f); 753 s->rx_start = 0; 754 for (i = 0; i < s->rx_level; i ++) 755 s->rx_fifo[i] = qemu_get_byte(f); 756 757 return 0; 758 } 759 760 static int pxa2xx_ssp_init(SysBusDevice *dev) 761 { 762 PXA2xxSSPState *s = FROM_SYSBUS(PXA2xxSSPState, dev); 763 764 sysbus_init_irq(dev, &s->irq); 765 766 memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_ssp_ops, s, 767 "pxa2xx-ssp", 0x1000); 768 sysbus_init_mmio(dev, &s->iomem); 769 register_savevm(&dev->qdev, "pxa2xx_ssp", -1, 0, 770 pxa2xx_ssp_save, pxa2xx_ssp_load, s); 771 772 s->bus = ssi_create_bus(&dev->qdev, "ssi"); 773 return 0; 774 } 775 776 /* Real-Time Clock */ 777 #define RCNR 0x00 /* RTC Counter register */ 778 #define RTAR 0x04 /* RTC Alarm register */ 779 #define RTSR 0x08 /* RTC Status register */ 780 #define RTTR 0x0c /* RTC Timer Trim register */ 781 #define RDCR 0x10 /* RTC Day Counter register */ 782 #define RYCR 0x14 /* RTC Year Counter register */ 783 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */ 784 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */ 785 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */ 786 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */ 787 #define SWCR 0x28 /* RTC Stopwatch Counter register */ 788 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */ 789 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */ 790 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */ 791 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */ 792 793 typedef struct { 794 SysBusDevice busdev; 795 MemoryRegion iomem; 796 uint32_t rttr; 797 uint32_t rtsr; 798 uint32_t rtar; 799 uint32_t rdar1; 800 uint32_t rdar2; 801 uint32_t ryar1; 802 uint32_t ryar2; 803 uint32_t swar1; 804 uint32_t swar2; 805 uint32_t piar; 806 uint32_t last_rcnr; 807 uint32_t last_rdcr; 808 uint32_t last_rycr; 809 uint32_t last_swcr; 810 uint32_t last_rtcpicr; 811 int64_t last_hz; 812 int64_t last_sw; 813 int64_t last_pi; 814 QEMUTimer *rtc_hz; 815 QEMUTimer *rtc_rdal1; 816 QEMUTimer *rtc_rdal2; 817 QEMUTimer *rtc_swal1; 818 QEMUTimer *rtc_swal2; 819 QEMUTimer *rtc_pi; 820 qemu_irq rtc_irq; 821 } PXA2xxRTCState; 822 823 static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s) 824 { 825 qemu_set_irq(s->rtc_irq, !!(s->rtsr & 0x2553)); 826 } 827 828 static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s) 829 { 830 int64_t rt = qemu_get_clock_ms(rtc_clock); 831 s->last_rcnr += ((rt - s->last_hz) << 15) / 832 (1000 * ((s->rttr & 0xffff) + 1)); 833 s->last_rdcr += ((rt - s->last_hz) << 15) / 834 (1000 * ((s->rttr & 0xffff) + 1)); 835 s->last_hz = rt; 836 } 837 838 static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s) 839 { 840 int64_t rt = qemu_get_clock_ms(rtc_clock); 841 if (s->rtsr & (1 << 12)) 842 s->last_swcr += (rt - s->last_sw) / 10; 843 s->last_sw = rt; 844 } 845 846 static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s) 847 { 848 int64_t rt = qemu_get_clock_ms(rtc_clock); 849 if (s->rtsr & (1 << 15)) 850 s->last_swcr += rt - s->last_pi; 851 s->last_pi = rt; 852 } 853 854 static inline void pxa2xx_rtc_alarm_update(PXA2xxRTCState *s, 855 uint32_t rtsr) 856 { 857 if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0))) 858 qemu_mod_timer(s->rtc_hz, s->last_hz + 859 (((s->rtar - s->last_rcnr) * 1000 * 860 ((s->rttr & 0xffff) + 1)) >> 15)); 861 else 862 qemu_del_timer(s->rtc_hz); 863 864 if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4))) 865 qemu_mod_timer(s->rtc_rdal1, s->last_hz + 866 (((s->rdar1 - s->last_rdcr) * 1000 * 867 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */ 868 else 869 qemu_del_timer(s->rtc_rdal1); 870 871 if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6))) 872 qemu_mod_timer(s->rtc_rdal2, s->last_hz + 873 (((s->rdar2 - s->last_rdcr) * 1000 * 874 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */ 875 else 876 qemu_del_timer(s->rtc_rdal2); 877 878 if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8))) 879 qemu_mod_timer(s->rtc_swal1, s->last_sw + 880 (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */ 881 else 882 qemu_del_timer(s->rtc_swal1); 883 884 if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10))) 885 qemu_mod_timer(s->rtc_swal2, s->last_sw + 886 (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */ 887 else 888 qemu_del_timer(s->rtc_swal2); 889 890 if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13))) 891 qemu_mod_timer(s->rtc_pi, s->last_pi + 892 (s->piar & 0xffff) - s->last_rtcpicr); 893 else 894 qemu_del_timer(s->rtc_pi); 895 } 896 897 static inline void pxa2xx_rtc_hz_tick(void *opaque) 898 { 899 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 900 s->rtsr |= (1 << 0); 901 pxa2xx_rtc_alarm_update(s, s->rtsr); 902 pxa2xx_rtc_int_update(s); 903 } 904 905 static inline void pxa2xx_rtc_rdal1_tick(void *opaque) 906 { 907 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 908 s->rtsr |= (1 << 4); 909 pxa2xx_rtc_alarm_update(s, s->rtsr); 910 pxa2xx_rtc_int_update(s); 911 } 912 913 static inline void pxa2xx_rtc_rdal2_tick(void *opaque) 914 { 915 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 916 s->rtsr |= (1 << 6); 917 pxa2xx_rtc_alarm_update(s, s->rtsr); 918 pxa2xx_rtc_int_update(s); 919 } 920 921 static inline void pxa2xx_rtc_swal1_tick(void *opaque) 922 { 923 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 924 s->rtsr |= (1 << 8); 925 pxa2xx_rtc_alarm_update(s, s->rtsr); 926 pxa2xx_rtc_int_update(s); 927 } 928 929 static inline void pxa2xx_rtc_swal2_tick(void *opaque) 930 { 931 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 932 s->rtsr |= (1 << 10); 933 pxa2xx_rtc_alarm_update(s, s->rtsr); 934 pxa2xx_rtc_int_update(s); 935 } 936 937 static inline void pxa2xx_rtc_pi_tick(void *opaque) 938 { 939 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 940 s->rtsr |= (1 << 13); 941 pxa2xx_rtc_piupdate(s); 942 s->last_rtcpicr = 0; 943 pxa2xx_rtc_alarm_update(s, s->rtsr); 944 pxa2xx_rtc_int_update(s); 945 } 946 947 static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr, 948 unsigned size) 949 { 950 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 951 952 switch (addr) { 953 case RTTR: 954 return s->rttr; 955 case RTSR: 956 return s->rtsr; 957 case RTAR: 958 return s->rtar; 959 case RDAR1: 960 return s->rdar1; 961 case RDAR2: 962 return s->rdar2; 963 case RYAR1: 964 return s->ryar1; 965 case RYAR2: 966 return s->ryar2; 967 case SWAR1: 968 return s->swar1; 969 case SWAR2: 970 return s->swar2; 971 case PIAR: 972 return s->piar; 973 case RCNR: 974 return s->last_rcnr + ((qemu_get_clock_ms(rtc_clock) - s->last_hz) << 15) / 975 (1000 * ((s->rttr & 0xffff) + 1)); 976 case RDCR: 977 return s->last_rdcr + ((qemu_get_clock_ms(rtc_clock) - s->last_hz) << 15) / 978 (1000 * ((s->rttr & 0xffff) + 1)); 979 case RYCR: 980 return s->last_rycr; 981 case SWCR: 982 if (s->rtsr & (1 << 12)) 983 return s->last_swcr + (qemu_get_clock_ms(rtc_clock) - s->last_sw) / 10; 984 else 985 return s->last_swcr; 986 default: 987 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 988 break; 989 } 990 return 0; 991 } 992 993 static void pxa2xx_rtc_write(void *opaque, hwaddr addr, 994 uint64_t value64, unsigned size) 995 { 996 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 997 uint32_t value = value64; 998 999 switch (addr) { 1000 case RTTR: 1001 if (!(s->rttr & (1 << 31))) { 1002 pxa2xx_rtc_hzupdate(s); 1003 s->rttr = value; 1004 pxa2xx_rtc_alarm_update(s, s->rtsr); 1005 } 1006 break; 1007 1008 case RTSR: 1009 if ((s->rtsr ^ value) & (1 << 15)) 1010 pxa2xx_rtc_piupdate(s); 1011 1012 if ((s->rtsr ^ value) & (1 << 12)) 1013 pxa2xx_rtc_swupdate(s); 1014 1015 if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac)) 1016 pxa2xx_rtc_alarm_update(s, value); 1017 1018 s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac)); 1019 pxa2xx_rtc_int_update(s); 1020 break; 1021 1022 case RTAR: 1023 s->rtar = value; 1024 pxa2xx_rtc_alarm_update(s, s->rtsr); 1025 break; 1026 1027 case RDAR1: 1028 s->rdar1 = value; 1029 pxa2xx_rtc_alarm_update(s, s->rtsr); 1030 break; 1031 1032 case RDAR2: 1033 s->rdar2 = value; 1034 pxa2xx_rtc_alarm_update(s, s->rtsr); 1035 break; 1036 1037 case RYAR1: 1038 s->ryar1 = value; 1039 pxa2xx_rtc_alarm_update(s, s->rtsr); 1040 break; 1041 1042 case RYAR2: 1043 s->ryar2 = value; 1044 pxa2xx_rtc_alarm_update(s, s->rtsr); 1045 break; 1046 1047 case SWAR1: 1048 pxa2xx_rtc_swupdate(s); 1049 s->swar1 = value; 1050 s->last_swcr = 0; 1051 pxa2xx_rtc_alarm_update(s, s->rtsr); 1052 break; 1053 1054 case SWAR2: 1055 s->swar2 = value; 1056 pxa2xx_rtc_alarm_update(s, s->rtsr); 1057 break; 1058 1059 case PIAR: 1060 s->piar = value; 1061 pxa2xx_rtc_alarm_update(s, s->rtsr); 1062 break; 1063 1064 case RCNR: 1065 pxa2xx_rtc_hzupdate(s); 1066 s->last_rcnr = value; 1067 pxa2xx_rtc_alarm_update(s, s->rtsr); 1068 break; 1069 1070 case RDCR: 1071 pxa2xx_rtc_hzupdate(s); 1072 s->last_rdcr = value; 1073 pxa2xx_rtc_alarm_update(s, s->rtsr); 1074 break; 1075 1076 case RYCR: 1077 s->last_rycr = value; 1078 break; 1079 1080 case SWCR: 1081 pxa2xx_rtc_swupdate(s); 1082 s->last_swcr = value; 1083 pxa2xx_rtc_alarm_update(s, s->rtsr); 1084 break; 1085 1086 case RTCPICR: 1087 pxa2xx_rtc_piupdate(s); 1088 s->last_rtcpicr = value & 0xffff; 1089 pxa2xx_rtc_alarm_update(s, s->rtsr); 1090 break; 1091 1092 default: 1093 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1094 } 1095 } 1096 1097 static const MemoryRegionOps pxa2xx_rtc_ops = { 1098 .read = pxa2xx_rtc_read, 1099 .write = pxa2xx_rtc_write, 1100 .endianness = DEVICE_NATIVE_ENDIAN, 1101 }; 1102 1103 static int pxa2xx_rtc_init(SysBusDevice *dev) 1104 { 1105 PXA2xxRTCState *s = FROM_SYSBUS(PXA2xxRTCState, dev); 1106 struct tm tm; 1107 int wom; 1108 1109 s->rttr = 0x7fff; 1110 s->rtsr = 0; 1111 1112 qemu_get_timedate(&tm, 0); 1113 wom = ((tm.tm_mday - 1) / 7) + 1; 1114 1115 s->last_rcnr = (uint32_t) mktimegm(&tm); 1116 s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) | 1117 (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec; 1118 s->last_rycr = ((tm.tm_year + 1900) << 9) | 1119 ((tm.tm_mon + 1) << 5) | tm.tm_mday; 1120 s->last_swcr = (tm.tm_hour << 19) | 1121 (tm.tm_min << 13) | (tm.tm_sec << 7); 1122 s->last_rtcpicr = 0; 1123 s->last_hz = s->last_sw = s->last_pi = qemu_get_clock_ms(rtc_clock); 1124 1125 s->rtc_hz = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_hz_tick, s); 1126 s->rtc_rdal1 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_rdal1_tick, s); 1127 s->rtc_rdal2 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_rdal2_tick, s); 1128 s->rtc_swal1 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_swal1_tick, s); 1129 s->rtc_swal2 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_swal2_tick, s); 1130 s->rtc_pi = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_pi_tick, s); 1131 1132 sysbus_init_irq(dev, &s->rtc_irq); 1133 1134 memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_rtc_ops, s, 1135 "pxa2xx-rtc", 0x10000); 1136 sysbus_init_mmio(dev, &s->iomem); 1137 1138 return 0; 1139 } 1140 1141 static void pxa2xx_rtc_pre_save(void *opaque) 1142 { 1143 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 1144 1145 pxa2xx_rtc_hzupdate(s); 1146 pxa2xx_rtc_piupdate(s); 1147 pxa2xx_rtc_swupdate(s); 1148 } 1149 1150 static int pxa2xx_rtc_post_load(void *opaque, int version_id) 1151 { 1152 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 1153 1154 pxa2xx_rtc_alarm_update(s, s->rtsr); 1155 1156 return 0; 1157 } 1158 1159 static const VMStateDescription vmstate_pxa2xx_rtc_regs = { 1160 .name = "pxa2xx_rtc", 1161 .version_id = 0, 1162 .minimum_version_id = 0, 1163 .minimum_version_id_old = 0, 1164 .pre_save = pxa2xx_rtc_pre_save, 1165 .post_load = pxa2xx_rtc_post_load, 1166 .fields = (VMStateField[]) { 1167 VMSTATE_UINT32(rttr, PXA2xxRTCState), 1168 VMSTATE_UINT32(rtsr, PXA2xxRTCState), 1169 VMSTATE_UINT32(rtar, PXA2xxRTCState), 1170 VMSTATE_UINT32(rdar1, PXA2xxRTCState), 1171 VMSTATE_UINT32(rdar2, PXA2xxRTCState), 1172 VMSTATE_UINT32(ryar1, PXA2xxRTCState), 1173 VMSTATE_UINT32(ryar2, PXA2xxRTCState), 1174 VMSTATE_UINT32(swar1, PXA2xxRTCState), 1175 VMSTATE_UINT32(swar2, PXA2xxRTCState), 1176 VMSTATE_UINT32(piar, PXA2xxRTCState), 1177 VMSTATE_UINT32(last_rcnr, PXA2xxRTCState), 1178 VMSTATE_UINT32(last_rdcr, PXA2xxRTCState), 1179 VMSTATE_UINT32(last_rycr, PXA2xxRTCState), 1180 VMSTATE_UINT32(last_swcr, PXA2xxRTCState), 1181 VMSTATE_UINT32(last_rtcpicr, PXA2xxRTCState), 1182 VMSTATE_INT64(last_hz, PXA2xxRTCState), 1183 VMSTATE_INT64(last_sw, PXA2xxRTCState), 1184 VMSTATE_INT64(last_pi, PXA2xxRTCState), 1185 VMSTATE_END_OF_LIST(), 1186 }, 1187 }; 1188 1189 static void pxa2xx_rtc_sysbus_class_init(ObjectClass *klass, void *data) 1190 { 1191 DeviceClass *dc = DEVICE_CLASS(klass); 1192 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 1193 1194 k->init = pxa2xx_rtc_init; 1195 dc->desc = "PXA2xx RTC Controller"; 1196 dc->vmsd = &vmstate_pxa2xx_rtc_regs; 1197 } 1198 1199 static const TypeInfo pxa2xx_rtc_sysbus_info = { 1200 .name = "pxa2xx_rtc", 1201 .parent = TYPE_SYS_BUS_DEVICE, 1202 .instance_size = sizeof(PXA2xxRTCState), 1203 .class_init = pxa2xx_rtc_sysbus_class_init, 1204 }; 1205 1206 /* I2C Interface */ 1207 typedef struct { 1208 I2CSlave i2c; 1209 PXA2xxI2CState *host; 1210 } PXA2xxI2CSlaveState; 1211 1212 struct PXA2xxI2CState { 1213 SysBusDevice busdev; 1214 MemoryRegion iomem; 1215 PXA2xxI2CSlaveState *slave; 1216 i2c_bus *bus; 1217 qemu_irq irq; 1218 uint32_t offset; 1219 uint32_t region_size; 1220 1221 uint16_t control; 1222 uint16_t status; 1223 uint8_t ibmr; 1224 uint8_t data; 1225 }; 1226 1227 #define IBMR 0x80 /* I2C Bus Monitor register */ 1228 #define IDBR 0x88 /* I2C Data Buffer register */ 1229 #define ICR 0x90 /* I2C Control register */ 1230 #define ISR 0x98 /* I2C Status register */ 1231 #define ISAR 0xa0 /* I2C Slave Address register */ 1232 1233 static void pxa2xx_i2c_update(PXA2xxI2CState *s) 1234 { 1235 uint16_t level = 0; 1236 level |= s->status & s->control & (1 << 10); /* BED */ 1237 level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */ 1238 level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */ 1239 level |= s->status & (1 << 9); /* SAD */ 1240 qemu_set_irq(s->irq, !!level); 1241 } 1242 1243 /* These are only stubs now. */ 1244 static void pxa2xx_i2c_event(I2CSlave *i2c, enum i2c_event event) 1245 { 1246 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c); 1247 PXA2xxI2CState *s = slave->host; 1248 1249 switch (event) { 1250 case I2C_START_SEND: 1251 s->status |= (1 << 9); /* set SAD */ 1252 s->status &= ~(1 << 0); /* clear RWM */ 1253 break; 1254 case I2C_START_RECV: 1255 s->status |= (1 << 9); /* set SAD */ 1256 s->status |= 1 << 0; /* set RWM */ 1257 break; 1258 case I2C_FINISH: 1259 s->status |= (1 << 4); /* set SSD */ 1260 break; 1261 case I2C_NACK: 1262 s->status |= 1 << 1; /* set ACKNAK */ 1263 break; 1264 } 1265 pxa2xx_i2c_update(s); 1266 } 1267 1268 static int pxa2xx_i2c_rx(I2CSlave *i2c) 1269 { 1270 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c); 1271 PXA2xxI2CState *s = slave->host; 1272 if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) 1273 return 0; 1274 1275 if (s->status & (1 << 0)) { /* RWM */ 1276 s->status |= 1 << 6; /* set ITE */ 1277 } 1278 pxa2xx_i2c_update(s); 1279 1280 return s->data; 1281 } 1282 1283 static int pxa2xx_i2c_tx(I2CSlave *i2c, uint8_t data) 1284 { 1285 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c); 1286 PXA2xxI2CState *s = slave->host; 1287 if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) 1288 return 1; 1289 1290 if (!(s->status & (1 << 0))) { /* RWM */ 1291 s->status |= 1 << 7; /* set IRF */ 1292 s->data = data; 1293 } 1294 pxa2xx_i2c_update(s); 1295 1296 return 1; 1297 } 1298 1299 static uint64_t pxa2xx_i2c_read(void *opaque, hwaddr addr, 1300 unsigned size) 1301 { 1302 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; 1303 1304 addr -= s->offset; 1305 switch (addr) { 1306 case ICR: 1307 return s->control; 1308 case ISR: 1309 return s->status | (i2c_bus_busy(s->bus) << 2); 1310 case ISAR: 1311 return s->slave->i2c.address; 1312 case IDBR: 1313 return s->data; 1314 case IBMR: 1315 if (s->status & (1 << 2)) 1316 s->ibmr ^= 3; /* Fake SCL and SDA pin changes */ 1317 else 1318 s->ibmr = 0; 1319 return s->ibmr; 1320 default: 1321 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1322 break; 1323 } 1324 return 0; 1325 } 1326 1327 static void pxa2xx_i2c_write(void *opaque, hwaddr addr, 1328 uint64_t value64, unsigned size) 1329 { 1330 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; 1331 uint32_t value = value64; 1332 int ack; 1333 1334 addr -= s->offset; 1335 switch (addr) { 1336 case ICR: 1337 s->control = value & 0xfff7; 1338 if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */ 1339 /* TODO: slave mode */ 1340 if (value & (1 << 0)) { /* START condition */ 1341 if (s->data & 1) 1342 s->status |= 1 << 0; /* set RWM */ 1343 else 1344 s->status &= ~(1 << 0); /* clear RWM */ 1345 ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1); 1346 } else { 1347 if (s->status & (1 << 0)) { /* RWM */ 1348 s->data = i2c_recv(s->bus); 1349 if (value & (1 << 2)) /* ACKNAK */ 1350 i2c_nack(s->bus); 1351 ack = 1; 1352 } else 1353 ack = !i2c_send(s->bus, s->data); 1354 } 1355 1356 if (value & (1 << 1)) /* STOP condition */ 1357 i2c_end_transfer(s->bus); 1358 1359 if (ack) { 1360 if (value & (1 << 0)) /* START condition */ 1361 s->status |= 1 << 6; /* set ITE */ 1362 else 1363 if (s->status & (1 << 0)) /* RWM */ 1364 s->status |= 1 << 7; /* set IRF */ 1365 else 1366 s->status |= 1 << 6; /* set ITE */ 1367 s->status &= ~(1 << 1); /* clear ACKNAK */ 1368 } else { 1369 s->status |= 1 << 6; /* set ITE */ 1370 s->status |= 1 << 10; /* set BED */ 1371 s->status |= 1 << 1; /* set ACKNAK */ 1372 } 1373 } 1374 if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */ 1375 if (value & (1 << 4)) /* MA */ 1376 i2c_end_transfer(s->bus); 1377 pxa2xx_i2c_update(s); 1378 break; 1379 1380 case ISR: 1381 s->status &= ~(value & 0x07f0); 1382 pxa2xx_i2c_update(s); 1383 break; 1384 1385 case ISAR: 1386 i2c_set_slave_address(&s->slave->i2c, value & 0x7f); 1387 break; 1388 1389 case IDBR: 1390 s->data = value & 0xff; 1391 break; 1392 1393 default: 1394 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1395 } 1396 } 1397 1398 static const MemoryRegionOps pxa2xx_i2c_ops = { 1399 .read = pxa2xx_i2c_read, 1400 .write = pxa2xx_i2c_write, 1401 .endianness = DEVICE_NATIVE_ENDIAN, 1402 }; 1403 1404 static const VMStateDescription vmstate_pxa2xx_i2c_slave = { 1405 .name = "pxa2xx_i2c_slave", 1406 .version_id = 1, 1407 .minimum_version_id = 1, 1408 .minimum_version_id_old = 1, 1409 .fields = (VMStateField []) { 1410 VMSTATE_I2C_SLAVE(i2c, PXA2xxI2CSlaveState), 1411 VMSTATE_END_OF_LIST() 1412 } 1413 }; 1414 1415 static const VMStateDescription vmstate_pxa2xx_i2c = { 1416 .name = "pxa2xx_i2c", 1417 .version_id = 1, 1418 .minimum_version_id = 1, 1419 .minimum_version_id_old = 1, 1420 .fields = (VMStateField []) { 1421 VMSTATE_UINT16(control, PXA2xxI2CState), 1422 VMSTATE_UINT16(status, PXA2xxI2CState), 1423 VMSTATE_UINT8(ibmr, PXA2xxI2CState), 1424 VMSTATE_UINT8(data, PXA2xxI2CState), 1425 VMSTATE_STRUCT_POINTER(slave, PXA2xxI2CState, 1426 vmstate_pxa2xx_i2c_slave, PXA2xxI2CSlaveState *), 1427 VMSTATE_END_OF_LIST() 1428 } 1429 }; 1430 1431 static int pxa2xx_i2c_slave_init(I2CSlave *i2c) 1432 { 1433 /* Nothing to do. */ 1434 return 0; 1435 } 1436 1437 static void pxa2xx_i2c_slave_class_init(ObjectClass *klass, void *data) 1438 { 1439 I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); 1440 1441 k->init = pxa2xx_i2c_slave_init; 1442 k->event = pxa2xx_i2c_event; 1443 k->recv = pxa2xx_i2c_rx; 1444 k->send = pxa2xx_i2c_tx; 1445 } 1446 1447 static const TypeInfo pxa2xx_i2c_slave_info = { 1448 .name = "pxa2xx-i2c-slave", 1449 .parent = TYPE_I2C_SLAVE, 1450 .instance_size = sizeof(PXA2xxI2CSlaveState), 1451 .class_init = pxa2xx_i2c_slave_class_init, 1452 }; 1453 1454 PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base, 1455 qemu_irq irq, uint32_t region_size) 1456 { 1457 DeviceState *dev; 1458 SysBusDevice *i2c_dev; 1459 PXA2xxI2CState *s; 1460 1461 i2c_dev = SYS_BUS_DEVICE(qdev_create(NULL, "pxa2xx_i2c")); 1462 qdev_prop_set_uint32(&i2c_dev->qdev, "size", region_size + 1); 1463 qdev_prop_set_uint32(&i2c_dev->qdev, "offset", base & region_size); 1464 1465 qdev_init_nofail(&i2c_dev->qdev); 1466 1467 sysbus_mmio_map(i2c_dev, 0, base & ~region_size); 1468 sysbus_connect_irq(i2c_dev, 0, irq); 1469 1470 s = FROM_SYSBUS(PXA2xxI2CState, i2c_dev); 1471 /* FIXME: Should the slave device really be on a separate bus? */ 1472 dev = i2c_create_slave(i2c_init_bus(NULL, "dummy"), "pxa2xx-i2c-slave", 0); 1473 s->slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, I2C_SLAVE(dev)); 1474 s->slave->host = s; 1475 1476 return s; 1477 } 1478 1479 static int pxa2xx_i2c_initfn(SysBusDevice *dev) 1480 { 1481 PXA2xxI2CState *s = FROM_SYSBUS(PXA2xxI2CState, dev); 1482 1483 s->bus = i2c_init_bus(&dev->qdev, "i2c"); 1484 1485 memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_i2c_ops, s, 1486 "pxa2xx-i2c", s->region_size); 1487 sysbus_init_mmio(dev, &s->iomem); 1488 sysbus_init_irq(dev, &s->irq); 1489 1490 return 0; 1491 } 1492 1493 i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s) 1494 { 1495 return s->bus; 1496 } 1497 1498 static Property pxa2xx_i2c_properties[] = { 1499 DEFINE_PROP_UINT32("size", PXA2xxI2CState, region_size, 0x10000), 1500 DEFINE_PROP_UINT32("offset", PXA2xxI2CState, offset, 0), 1501 DEFINE_PROP_END_OF_LIST(), 1502 }; 1503 1504 static void pxa2xx_i2c_class_init(ObjectClass *klass, void *data) 1505 { 1506 DeviceClass *dc = DEVICE_CLASS(klass); 1507 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 1508 1509 k->init = pxa2xx_i2c_initfn; 1510 dc->desc = "PXA2xx I2C Bus Controller"; 1511 dc->vmsd = &vmstate_pxa2xx_i2c; 1512 dc->props = pxa2xx_i2c_properties; 1513 } 1514 1515 static const TypeInfo pxa2xx_i2c_info = { 1516 .name = "pxa2xx_i2c", 1517 .parent = TYPE_SYS_BUS_DEVICE, 1518 .instance_size = sizeof(PXA2xxI2CState), 1519 .class_init = pxa2xx_i2c_class_init, 1520 }; 1521 1522 /* PXA Inter-IC Sound Controller */ 1523 static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s) 1524 { 1525 i2s->rx_len = 0; 1526 i2s->tx_len = 0; 1527 i2s->fifo_len = 0; 1528 i2s->clk = 0x1a; 1529 i2s->control[0] = 0x00; 1530 i2s->control[1] = 0x00; 1531 i2s->status = 0x00; 1532 i2s->mask = 0x00; 1533 } 1534 1535 #define SACR_TFTH(val) ((val >> 8) & 0xf) 1536 #define SACR_RFTH(val) ((val >> 12) & 0xf) 1537 #define SACR_DREC(val) (val & (1 << 3)) 1538 #define SACR_DPRL(val) (val & (1 << 4)) 1539 1540 static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s) 1541 { 1542 int rfs, tfs; 1543 rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len && 1544 !SACR_DREC(i2s->control[1]); 1545 tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) && 1546 i2s->enable && !SACR_DPRL(i2s->control[1]); 1547 1548 qemu_set_irq(i2s->rx_dma, rfs); 1549 qemu_set_irq(i2s->tx_dma, tfs); 1550 1551 i2s->status &= 0xe0; 1552 if (i2s->fifo_len < 16 || !i2s->enable) 1553 i2s->status |= 1 << 0; /* TNF */ 1554 if (i2s->rx_len) 1555 i2s->status |= 1 << 1; /* RNE */ 1556 if (i2s->enable) 1557 i2s->status |= 1 << 2; /* BSY */ 1558 if (tfs) 1559 i2s->status |= 1 << 3; /* TFS */ 1560 if (rfs) 1561 i2s->status |= 1 << 4; /* RFS */ 1562 if (!(i2s->tx_len && i2s->enable)) 1563 i2s->status |= i2s->fifo_len << 8; /* TFL */ 1564 i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */ 1565 1566 qemu_set_irq(i2s->irq, i2s->status & i2s->mask); 1567 } 1568 1569 #define SACR0 0x00 /* Serial Audio Global Control register */ 1570 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */ 1571 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */ 1572 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */ 1573 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */ 1574 #define SADIV 0x60 /* Serial Audio Clock Divider register */ 1575 #define SADR 0x80 /* Serial Audio Data register */ 1576 1577 static uint64_t pxa2xx_i2s_read(void *opaque, hwaddr addr, 1578 unsigned size) 1579 { 1580 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; 1581 1582 switch (addr) { 1583 case SACR0: 1584 return s->control[0]; 1585 case SACR1: 1586 return s->control[1]; 1587 case SASR0: 1588 return s->status; 1589 case SAIMR: 1590 return s->mask; 1591 case SAICR: 1592 return 0; 1593 case SADIV: 1594 return s->clk; 1595 case SADR: 1596 if (s->rx_len > 0) { 1597 s->rx_len --; 1598 pxa2xx_i2s_update(s); 1599 return s->codec_in(s->opaque); 1600 } 1601 return 0; 1602 default: 1603 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1604 break; 1605 } 1606 return 0; 1607 } 1608 1609 static void pxa2xx_i2s_write(void *opaque, hwaddr addr, 1610 uint64_t value, unsigned size) 1611 { 1612 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; 1613 uint32_t *sample; 1614 1615 switch (addr) { 1616 case SACR0: 1617 if (value & (1 << 3)) /* RST */ 1618 pxa2xx_i2s_reset(s); 1619 s->control[0] = value & 0xff3d; 1620 if (!s->enable && (value & 1) && s->tx_len) { /* ENB */ 1621 for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++) 1622 s->codec_out(s->opaque, *sample); 1623 s->status &= ~(1 << 7); /* I2SOFF */ 1624 } 1625 if (value & (1 << 4)) /* EFWR */ 1626 printf("%s: Attempt to use special function\n", __FUNCTION__); 1627 s->enable = (value & 9) == 1; /* ENB && !RST*/ 1628 pxa2xx_i2s_update(s); 1629 break; 1630 case SACR1: 1631 s->control[1] = value & 0x0039; 1632 if (value & (1 << 5)) /* ENLBF */ 1633 printf("%s: Attempt to use loopback function\n", __FUNCTION__); 1634 if (value & (1 << 4)) /* DPRL */ 1635 s->fifo_len = 0; 1636 pxa2xx_i2s_update(s); 1637 break; 1638 case SAIMR: 1639 s->mask = value & 0x0078; 1640 pxa2xx_i2s_update(s); 1641 break; 1642 case SAICR: 1643 s->status &= ~(value & (3 << 5)); 1644 pxa2xx_i2s_update(s); 1645 break; 1646 case SADIV: 1647 s->clk = value & 0x007f; 1648 break; 1649 case SADR: 1650 if (s->tx_len && s->enable) { 1651 s->tx_len --; 1652 pxa2xx_i2s_update(s); 1653 s->codec_out(s->opaque, value); 1654 } else if (s->fifo_len < 16) { 1655 s->fifo[s->fifo_len ++] = value; 1656 pxa2xx_i2s_update(s); 1657 } 1658 break; 1659 default: 1660 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1661 } 1662 } 1663 1664 static const MemoryRegionOps pxa2xx_i2s_ops = { 1665 .read = pxa2xx_i2s_read, 1666 .write = pxa2xx_i2s_write, 1667 .endianness = DEVICE_NATIVE_ENDIAN, 1668 }; 1669 1670 static const VMStateDescription vmstate_pxa2xx_i2s = { 1671 .name = "pxa2xx_i2s", 1672 .version_id = 0, 1673 .minimum_version_id = 0, 1674 .minimum_version_id_old = 0, 1675 .fields = (VMStateField[]) { 1676 VMSTATE_UINT32_ARRAY(control, PXA2xxI2SState, 2), 1677 VMSTATE_UINT32(status, PXA2xxI2SState), 1678 VMSTATE_UINT32(mask, PXA2xxI2SState), 1679 VMSTATE_UINT32(clk, PXA2xxI2SState), 1680 VMSTATE_INT32(enable, PXA2xxI2SState), 1681 VMSTATE_INT32(rx_len, PXA2xxI2SState), 1682 VMSTATE_INT32(tx_len, PXA2xxI2SState), 1683 VMSTATE_INT32(fifo_len, PXA2xxI2SState), 1684 VMSTATE_END_OF_LIST() 1685 } 1686 }; 1687 1688 static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx) 1689 { 1690 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; 1691 uint32_t *sample; 1692 1693 /* Signal FIFO errors */ 1694 if (s->enable && s->tx_len) 1695 s->status |= 1 << 5; /* TUR */ 1696 if (s->enable && s->rx_len) 1697 s->status |= 1 << 6; /* ROR */ 1698 1699 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to 1700 * handle the cases where it makes a difference. */ 1701 s->tx_len = tx - s->fifo_len; 1702 s->rx_len = rx; 1703 /* Note that is s->codec_out wasn't set, we wouldn't get called. */ 1704 if (s->enable) 1705 for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++) 1706 s->codec_out(s->opaque, *sample); 1707 pxa2xx_i2s_update(s); 1708 } 1709 1710 static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem, 1711 hwaddr base, 1712 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma) 1713 { 1714 PXA2xxI2SState *s = (PXA2xxI2SState *) 1715 g_malloc0(sizeof(PXA2xxI2SState)); 1716 1717 s->irq = irq; 1718 s->rx_dma = rx_dma; 1719 s->tx_dma = tx_dma; 1720 s->data_req = pxa2xx_i2s_data_req; 1721 1722 pxa2xx_i2s_reset(s); 1723 1724 memory_region_init_io(&s->iomem, NULL, &pxa2xx_i2s_ops, s, 1725 "pxa2xx-i2s", 0x100000); 1726 memory_region_add_subregion(sysmem, base, &s->iomem); 1727 1728 vmstate_register(NULL, base, &vmstate_pxa2xx_i2s, s); 1729 1730 return s; 1731 } 1732 1733 /* PXA Fast Infra-red Communications Port */ 1734 struct PXA2xxFIrState { 1735 MemoryRegion iomem; 1736 qemu_irq irq; 1737 qemu_irq rx_dma; 1738 qemu_irq tx_dma; 1739 int enable; 1740 CharDriverState *chr; 1741 1742 uint8_t control[3]; 1743 uint8_t status[2]; 1744 1745 int rx_len; 1746 int rx_start; 1747 uint8_t rx_fifo[64]; 1748 }; 1749 1750 static void pxa2xx_fir_reset(PXA2xxFIrState *s) 1751 { 1752 s->control[0] = 0x00; 1753 s->control[1] = 0x00; 1754 s->control[2] = 0x00; 1755 s->status[0] = 0x00; 1756 s->status[1] = 0x00; 1757 s->enable = 0; 1758 } 1759 1760 static inline void pxa2xx_fir_update(PXA2xxFIrState *s) 1761 { 1762 static const int tresh[4] = { 8, 16, 32, 0 }; 1763 int intr = 0; 1764 if ((s->control[0] & (1 << 4)) && /* RXE */ 1765 s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */ 1766 s->status[0] |= 1 << 4; /* RFS */ 1767 else 1768 s->status[0] &= ~(1 << 4); /* RFS */ 1769 if (s->control[0] & (1 << 3)) /* TXE */ 1770 s->status[0] |= 1 << 3; /* TFS */ 1771 else 1772 s->status[0] &= ~(1 << 3); /* TFS */ 1773 if (s->rx_len) 1774 s->status[1] |= 1 << 2; /* RNE */ 1775 else 1776 s->status[1] &= ~(1 << 2); /* RNE */ 1777 if (s->control[0] & (1 << 4)) /* RXE */ 1778 s->status[1] |= 1 << 0; /* RSY */ 1779 else 1780 s->status[1] &= ~(1 << 0); /* RSY */ 1781 1782 intr |= (s->control[0] & (1 << 5)) && /* RIE */ 1783 (s->status[0] & (1 << 4)); /* RFS */ 1784 intr |= (s->control[0] & (1 << 6)) && /* TIE */ 1785 (s->status[0] & (1 << 3)); /* TFS */ 1786 intr |= (s->control[2] & (1 << 4)) && /* TRAIL */ 1787 (s->status[0] & (1 << 6)); /* EOC */ 1788 intr |= (s->control[0] & (1 << 2)) && /* TUS */ 1789 (s->status[0] & (1 << 1)); /* TUR */ 1790 intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */ 1791 1792 qemu_set_irq(s->rx_dma, (s->status[0] >> 4) & 1); 1793 qemu_set_irq(s->tx_dma, (s->status[0] >> 3) & 1); 1794 1795 qemu_set_irq(s->irq, intr && s->enable); 1796 } 1797 1798 #define ICCR0 0x00 /* FICP Control register 0 */ 1799 #define ICCR1 0x04 /* FICP Control register 1 */ 1800 #define ICCR2 0x08 /* FICP Control register 2 */ 1801 #define ICDR 0x0c /* FICP Data register */ 1802 #define ICSR0 0x14 /* FICP Status register 0 */ 1803 #define ICSR1 0x18 /* FICP Status register 1 */ 1804 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */ 1805 1806 static uint64_t pxa2xx_fir_read(void *opaque, hwaddr addr, 1807 unsigned size) 1808 { 1809 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1810 uint8_t ret; 1811 1812 switch (addr) { 1813 case ICCR0: 1814 return s->control[0]; 1815 case ICCR1: 1816 return s->control[1]; 1817 case ICCR2: 1818 return s->control[2]; 1819 case ICDR: 1820 s->status[0] &= ~0x01; 1821 s->status[1] &= ~0x72; 1822 if (s->rx_len) { 1823 s->rx_len --; 1824 ret = s->rx_fifo[s->rx_start ++]; 1825 s->rx_start &= 63; 1826 pxa2xx_fir_update(s); 1827 return ret; 1828 } 1829 printf("%s: Rx FIFO underrun.\n", __FUNCTION__); 1830 break; 1831 case ICSR0: 1832 return s->status[0]; 1833 case ICSR1: 1834 return s->status[1] | (1 << 3); /* TNF */ 1835 case ICFOR: 1836 return s->rx_len; 1837 default: 1838 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1839 break; 1840 } 1841 return 0; 1842 } 1843 1844 static void pxa2xx_fir_write(void *opaque, hwaddr addr, 1845 uint64_t value64, unsigned size) 1846 { 1847 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1848 uint32_t value = value64; 1849 uint8_t ch; 1850 1851 switch (addr) { 1852 case ICCR0: 1853 s->control[0] = value; 1854 if (!(value & (1 << 4))) /* RXE */ 1855 s->rx_len = s->rx_start = 0; 1856 if (!(value & (1 << 3))) { /* TXE */ 1857 /* Nop */ 1858 } 1859 s->enable = value & 1; /* ITR */ 1860 if (!s->enable) 1861 s->status[0] = 0; 1862 pxa2xx_fir_update(s); 1863 break; 1864 case ICCR1: 1865 s->control[1] = value; 1866 break; 1867 case ICCR2: 1868 s->control[2] = value & 0x3f; 1869 pxa2xx_fir_update(s); 1870 break; 1871 case ICDR: 1872 if (s->control[2] & (1 << 2)) /* TXP */ 1873 ch = value; 1874 else 1875 ch = ~value; 1876 if (s->chr && s->enable && (s->control[0] & (1 << 3))) /* TXE */ 1877 qemu_chr_fe_write(s->chr, &ch, 1); 1878 break; 1879 case ICSR0: 1880 s->status[0] &= ~(value & 0x66); 1881 pxa2xx_fir_update(s); 1882 break; 1883 case ICFOR: 1884 break; 1885 default: 1886 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1887 } 1888 } 1889 1890 static const MemoryRegionOps pxa2xx_fir_ops = { 1891 .read = pxa2xx_fir_read, 1892 .write = pxa2xx_fir_write, 1893 .endianness = DEVICE_NATIVE_ENDIAN, 1894 }; 1895 1896 static int pxa2xx_fir_is_empty(void *opaque) 1897 { 1898 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1899 return (s->rx_len < 64); 1900 } 1901 1902 static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size) 1903 { 1904 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1905 if (!(s->control[0] & (1 << 4))) /* RXE */ 1906 return; 1907 1908 while (size --) { 1909 s->status[1] |= 1 << 4; /* EOF */ 1910 if (s->rx_len >= 64) { 1911 s->status[1] |= 1 << 6; /* ROR */ 1912 break; 1913 } 1914 1915 if (s->control[2] & (1 << 3)) /* RXP */ 1916 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++); 1917 else 1918 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++); 1919 } 1920 1921 pxa2xx_fir_update(s); 1922 } 1923 1924 static void pxa2xx_fir_event(void *opaque, int event) 1925 { 1926 } 1927 1928 static void pxa2xx_fir_save(QEMUFile *f, void *opaque) 1929 { 1930 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1931 int i; 1932 1933 qemu_put_be32(f, s->enable); 1934 1935 qemu_put_8s(f, &s->control[0]); 1936 qemu_put_8s(f, &s->control[1]); 1937 qemu_put_8s(f, &s->control[2]); 1938 qemu_put_8s(f, &s->status[0]); 1939 qemu_put_8s(f, &s->status[1]); 1940 1941 qemu_put_byte(f, s->rx_len); 1942 for (i = 0; i < s->rx_len; i ++) 1943 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 63]); 1944 } 1945 1946 static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id) 1947 { 1948 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1949 int i; 1950 1951 s->enable = qemu_get_be32(f); 1952 1953 qemu_get_8s(f, &s->control[0]); 1954 qemu_get_8s(f, &s->control[1]); 1955 qemu_get_8s(f, &s->control[2]); 1956 qemu_get_8s(f, &s->status[0]); 1957 qemu_get_8s(f, &s->status[1]); 1958 1959 s->rx_len = qemu_get_byte(f); 1960 s->rx_start = 0; 1961 for (i = 0; i < s->rx_len; i ++) 1962 s->rx_fifo[i] = qemu_get_byte(f); 1963 1964 return 0; 1965 } 1966 1967 static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem, 1968 hwaddr base, 1969 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma, 1970 CharDriverState *chr) 1971 { 1972 PXA2xxFIrState *s = (PXA2xxFIrState *) 1973 g_malloc0(sizeof(PXA2xxFIrState)); 1974 1975 s->irq = irq; 1976 s->rx_dma = rx_dma; 1977 s->tx_dma = tx_dma; 1978 s->chr = chr; 1979 1980 pxa2xx_fir_reset(s); 1981 1982 memory_region_init_io(&s->iomem, NULL, &pxa2xx_fir_ops, s, "pxa2xx-fir", 0x1000); 1983 memory_region_add_subregion(sysmem, base, &s->iomem); 1984 1985 if (chr) { 1986 qemu_chr_fe_claim_no_fail(chr); 1987 qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty, 1988 pxa2xx_fir_rx, pxa2xx_fir_event, s); 1989 } 1990 1991 register_savevm(NULL, "pxa2xx_fir", 0, 0, pxa2xx_fir_save, 1992 pxa2xx_fir_load, s); 1993 1994 return s; 1995 } 1996 1997 static void pxa2xx_reset(void *opaque, int line, int level) 1998 { 1999 PXA2xxState *s = (PXA2xxState *) opaque; 2000 2001 if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */ 2002 cpu_reset(CPU(s->cpu)); 2003 /* TODO: reset peripherals */ 2004 } 2005 } 2006 2007 /* Initialise a PXA270 integrated chip (ARM based core). */ 2008 PXA2xxState *pxa270_init(MemoryRegion *address_space, 2009 unsigned int sdram_size, const char *revision) 2010 { 2011 PXA2xxState *s; 2012 int i; 2013 DriveInfo *dinfo; 2014 s = (PXA2xxState *) g_malloc0(sizeof(PXA2xxState)); 2015 2016 if (revision && strncmp(revision, "pxa27", 5)) { 2017 fprintf(stderr, "Machine requires a PXA27x processor.\n"); 2018 exit(1); 2019 } 2020 if (!revision) 2021 revision = "pxa270"; 2022 2023 s->cpu = cpu_arm_init(revision); 2024 if (s->cpu == NULL) { 2025 fprintf(stderr, "Unable to find CPU definition\n"); 2026 exit(1); 2027 } 2028 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0]; 2029 2030 /* SDRAM & Internal Memory Storage */ 2031 memory_region_init_ram(&s->sdram, NULL, "pxa270.sdram", sdram_size); 2032 vmstate_register_ram_global(&s->sdram); 2033 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram); 2034 memory_region_init_ram(&s->internal, NULL, "pxa270.internal", 0x40000); 2035 vmstate_register_ram_global(&s->internal); 2036 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE, 2037 &s->internal); 2038 2039 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu); 2040 2041 s->dma = pxa27x_dma_init(0x40000000, 2042 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA)); 2043 2044 sysbus_create_varargs("pxa27x-timer", 0x40a00000, 2045 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0), 2046 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1), 2047 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2), 2048 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3), 2049 qdev_get_gpio_in(s->pic, PXA27X_PIC_OST_4_11), 2050 NULL); 2051 2052 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 121); 2053 2054 dinfo = drive_get(IF_SD, 0, 0); 2055 if (!dinfo) { 2056 fprintf(stderr, "qemu: missing SecureDigital device\n"); 2057 exit(1); 2058 } 2059 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, dinfo->bdrv, 2060 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), 2061 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), 2062 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); 2063 2064 for (i = 0; pxa270_serial[i].io_base; i++) { 2065 if (serial_hds[i]) { 2066 serial_mm_init(address_space, pxa270_serial[i].io_base, 2, 2067 qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn), 2068 14857000 / 16, serial_hds[i], 2069 DEVICE_NATIVE_ENDIAN); 2070 } else { 2071 break; 2072 } 2073 } 2074 if (serial_hds[i]) 2075 s->fir = pxa2xx_fir_init(address_space, 0x40800000, 2076 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), 2077 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), 2078 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), 2079 serial_hds[i]); 2080 2081 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000, 2082 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); 2083 2084 s->cm_base = 0x41300000; 2085 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */ 2086 s->clkcfg = 0x00000009; /* Turbo mode active */ 2087 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000); 2088 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); 2089 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); 2090 2091 pxa2xx_setup_cp14(s); 2092 2093 s->mm_base = 0x48000000; 2094 s->mm_regs[MDMRS >> 2] = 0x00020002; 2095 s->mm_regs[MDREFR >> 2] = 0x03ca4000; 2096 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ 2097 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000); 2098 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem); 2099 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s); 2100 2101 s->pm_base = 0x40f00000; 2102 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100); 2103 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem); 2104 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s); 2105 2106 for (i = 0; pxa27x_ssp[i].io_base; i ++); 2107 s->ssp = (SSIBus **)g_malloc0(sizeof(SSIBus *) * i); 2108 for (i = 0; pxa27x_ssp[i].io_base; i ++) { 2109 DeviceState *dev; 2110 dev = sysbus_create_simple("pxa2xx-ssp", pxa27x_ssp[i].io_base, 2111 qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn)); 2112 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi"); 2113 } 2114 2115 if (usb_enabled(false)) { 2116 sysbus_create_simple("sysbus-ohci", 0x4c000000, 2117 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1)); 2118 } 2119 2120 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000); 2121 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000); 2122 2123 sysbus_create_simple("pxa2xx_rtc", 0x40900000, 2124 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM)); 2125 2126 s->i2c[0] = pxa2xx_i2c_init(0x40301600, 2127 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff); 2128 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, 2129 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff); 2130 2131 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000, 2132 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), 2133 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), 2134 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); 2135 2136 s->kp = pxa27x_keypad_init(address_space, 0x41500000, 2137 qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD)); 2138 2139 /* GPIO1 resets the processor */ 2140 /* The handler can be overridden by board-specific code */ 2141 qdev_connect_gpio_out(s->gpio, 1, s->reset); 2142 return s; 2143 } 2144 2145 /* Initialise a PXA255 integrated chip (ARM based core). */ 2146 PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size) 2147 { 2148 PXA2xxState *s; 2149 int i; 2150 DriveInfo *dinfo; 2151 2152 s = (PXA2xxState *) g_malloc0(sizeof(PXA2xxState)); 2153 2154 s->cpu = cpu_arm_init("pxa255"); 2155 if (s->cpu == NULL) { 2156 fprintf(stderr, "Unable to find CPU definition\n"); 2157 exit(1); 2158 } 2159 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0]; 2160 2161 /* SDRAM & Internal Memory Storage */ 2162 memory_region_init_ram(&s->sdram, NULL, "pxa255.sdram", sdram_size); 2163 vmstate_register_ram_global(&s->sdram); 2164 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram); 2165 memory_region_init_ram(&s->internal, NULL, "pxa255.internal", 2166 PXA2XX_INTERNAL_SIZE); 2167 vmstate_register_ram_global(&s->internal); 2168 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE, 2169 &s->internal); 2170 2171 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu); 2172 2173 s->dma = pxa255_dma_init(0x40000000, 2174 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA)); 2175 2176 sysbus_create_varargs("pxa25x-timer", 0x40a00000, 2177 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0), 2178 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1), 2179 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2), 2180 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3), 2181 NULL); 2182 2183 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 85); 2184 2185 dinfo = drive_get(IF_SD, 0, 0); 2186 if (!dinfo) { 2187 fprintf(stderr, "qemu: missing SecureDigital device\n"); 2188 exit(1); 2189 } 2190 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, dinfo->bdrv, 2191 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), 2192 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), 2193 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); 2194 2195 for (i = 0; pxa255_serial[i].io_base; i++) { 2196 if (serial_hds[i]) { 2197 serial_mm_init(address_space, pxa255_serial[i].io_base, 2, 2198 qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn), 2199 14745600 / 16, serial_hds[i], 2200 DEVICE_NATIVE_ENDIAN); 2201 } else { 2202 break; 2203 } 2204 } 2205 if (serial_hds[i]) 2206 s->fir = pxa2xx_fir_init(address_space, 0x40800000, 2207 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), 2208 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), 2209 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), 2210 serial_hds[i]); 2211 2212 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000, 2213 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); 2214 2215 s->cm_base = 0x41300000; 2216 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */ 2217 s->clkcfg = 0x00000009; /* Turbo mode active */ 2218 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000); 2219 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); 2220 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); 2221 2222 pxa2xx_setup_cp14(s); 2223 2224 s->mm_base = 0x48000000; 2225 s->mm_regs[MDMRS >> 2] = 0x00020002; 2226 s->mm_regs[MDREFR >> 2] = 0x03ca4000; 2227 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ 2228 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000); 2229 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem); 2230 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s); 2231 2232 s->pm_base = 0x40f00000; 2233 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100); 2234 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem); 2235 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s); 2236 2237 for (i = 0; pxa255_ssp[i].io_base; i ++); 2238 s->ssp = (SSIBus **)g_malloc0(sizeof(SSIBus *) * i); 2239 for (i = 0; pxa255_ssp[i].io_base; i ++) { 2240 DeviceState *dev; 2241 dev = sysbus_create_simple("pxa2xx-ssp", pxa255_ssp[i].io_base, 2242 qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn)); 2243 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi"); 2244 } 2245 2246 if (usb_enabled(false)) { 2247 sysbus_create_simple("sysbus-ohci", 0x4c000000, 2248 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1)); 2249 } 2250 2251 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000); 2252 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000); 2253 2254 sysbus_create_simple("pxa2xx_rtc", 0x40900000, 2255 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM)); 2256 2257 s->i2c[0] = pxa2xx_i2c_init(0x40301600, 2258 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff); 2259 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, 2260 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff); 2261 2262 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000, 2263 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), 2264 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), 2265 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); 2266 2267 /* GPIO1 resets the processor */ 2268 /* The handler can be overridden by board-specific code */ 2269 qdev_connect_gpio_out(s->gpio, 1, s->reset); 2270 return s; 2271 } 2272 2273 static void pxa2xx_ssp_class_init(ObjectClass *klass, void *data) 2274 { 2275 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 2276 2277 sdc->init = pxa2xx_ssp_init; 2278 } 2279 2280 static const TypeInfo pxa2xx_ssp_info = { 2281 .name = "pxa2xx-ssp", 2282 .parent = TYPE_SYS_BUS_DEVICE, 2283 .instance_size = sizeof(PXA2xxSSPState), 2284 .class_init = pxa2xx_ssp_class_init, 2285 }; 2286 2287 static void pxa2xx_register_types(void) 2288 { 2289 type_register_static(&pxa2xx_i2c_slave_info); 2290 type_register_static(&pxa2xx_ssp_info); 2291 type_register_static(&pxa2xx_i2c_info); 2292 type_register_static(&pxa2xx_rtc_sysbus_info); 2293 } 2294 2295 type_init(pxa2xx_register_types) 2296