xref: /openbmc/qemu/hw/arm/pxa2xx.c (revision 6a0acfff)
1 /*
2  * Intel XScale PXA255/270 processor support.
3  *
4  * Copyright (c) 2006 Openedhand Ltd.
5  * Written by Andrzej Zaborowski <balrog@zabor.org>
6  *
7  * This code is licensed under the GPL.
8  */
9 
10 #include "qemu/osdep.h"
11 #include "qemu-common.h"
12 #include "qemu/error-report.h"
13 #include "qemu/module.h"
14 #include "qapi/error.h"
15 #include "cpu.h"
16 #include "hw/sysbus.h"
17 #include "hw/arm/pxa.h"
18 #include "sysemu/sysemu.h"
19 #include "hw/char/serial.h"
20 #include "hw/i2c/i2c.h"
21 #include "hw/irq.h"
22 #include "hw/ssi/ssi.h"
23 #include "chardev/char-fe.h"
24 #include "sysemu/blockdev.h"
25 #include "sysemu/qtest.h"
26 #include "qemu/cutils.h"
27 
28 static struct {
29     hwaddr io_base;
30     int irqn;
31 } pxa255_serial[] = {
32     { 0x40100000, PXA2XX_PIC_FFUART },
33     { 0x40200000, PXA2XX_PIC_BTUART },
34     { 0x40700000, PXA2XX_PIC_STUART },
35     { 0x41600000, PXA25X_PIC_HWUART },
36     { 0, 0 }
37 }, pxa270_serial[] = {
38     { 0x40100000, PXA2XX_PIC_FFUART },
39     { 0x40200000, PXA2XX_PIC_BTUART },
40     { 0x40700000, PXA2XX_PIC_STUART },
41     { 0, 0 }
42 };
43 
44 typedef struct PXASSPDef {
45     hwaddr io_base;
46     int irqn;
47 } PXASSPDef;
48 
49 #if 0
50 static PXASSPDef pxa250_ssp[] = {
51     { 0x41000000, PXA2XX_PIC_SSP },
52     { 0, 0 }
53 };
54 #endif
55 
56 static PXASSPDef pxa255_ssp[] = {
57     { 0x41000000, PXA2XX_PIC_SSP },
58     { 0x41400000, PXA25X_PIC_NSSP },
59     { 0, 0 }
60 };
61 
62 #if 0
63 static PXASSPDef pxa26x_ssp[] = {
64     { 0x41000000, PXA2XX_PIC_SSP },
65     { 0x41400000, PXA25X_PIC_NSSP },
66     { 0x41500000, PXA26X_PIC_ASSP },
67     { 0, 0 }
68 };
69 #endif
70 
71 static PXASSPDef pxa27x_ssp[] = {
72     { 0x41000000, PXA2XX_PIC_SSP },
73     { 0x41700000, PXA27X_PIC_SSP2 },
74     { 0x41900000, PXA2XX_PIC_SSP3 },
75     { 0, 0 }
76 };
77 
78 #define PMCR	0x00	/* Power Manager Control register */
79 #define PSSR	0x04	/* Power Manager Sleep Status register */
80 #define PSPR	0x08	/* Power Manager Scratch-Pad register */
81 #define PWER	0x0c	/* Power Manager Wake-Up Enable register */
82 #define PRER	0x10	/* Power Manager Rising-Edge Detect Enable register */
83 #define PFER	0x14	/* Power Manager Falling-Edge Detect Enable register */
84 #define PEDR	0x18	/* Power Manager Edge-Detect Status register */
85 #define PCFR	0x1c	/* Power Manager General Configuration register */
86 #define PGSR0	0x20	/* Power Manager GPIO Sleep-State register 0 */
87 #define PGSR1	0x24	/* Power Manager GPIO Sleep-State register 1 */
88 #define PGSR2	0x28	/* Power Manager GPIO Sleep-State register 2 */
89 #define PGSR3	0x2c	/* Power Manager GPIO Sleep-State register 3 */
90 #define RCSR	0x30	/* Reset Controller Status register */
91 #define PSLR	0x34	/* Power Manager Sleep Configuration register */
92 #define PTSR	0x38	/* Power Manager Standby Configuration register */
93 #define PVCR	0x40	/* Power Manager Voltage Change Control register */
94 #define PUCR	0x4c	/* Power Manager USIM Card Control/Status register */
95 #define PKWR	0x50	/* Power Manager Keyboard Wake-Up Enable register */
96 #define PKSR	0x54	/* Power Manager Keyboard Level-Detect Status */
97 #define PCMD0	0x80	/* Power Manager I2C Command register File 0 */
98 #define PCMD31	0xfc	/* Power Manager I2C Command register File 31 */
99 
100 static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr,
101                                unsigned size)
102 {
103     PXA2xxState *s = (PXA2xxState *) opaque;
104 
105     switch (addr) {
106     case PMCR ... PCMD31:
107         if (addr & 3)
108             goto fail;
109 
110         return s->pm_regs[addr >> 2];
111     default:
112     fail:
113         printf("%s: Bad register " REG_FMT "\n", __func__, addr);
114         break;
115     }
116     return 0;
117 }
118 
119 static void pxa2xx_pm_write(void *opaque, hwaddr addr,
120                             uint64_t value, unsigned size)
121 {
122     PXA2xxState *s = (PXA2xxState *) opaque;
123 
124     switch (addr) {
125     case PMCR:
126         /* Clear the write-one-to-clear bits... */
127         s->pm_regs[addr >> 2] &= ~(value & 0x2a);
128         /* ...and set the plain r/w bits */
129         s->pm_regs[addr >> 2] &= ~0x15;
130         s->pm_regs[addr >> 2] |= value & 0x15;
131         break;
132 
133     case PSSR:	/* Read-clean registers */
134     case RCSR:
135     case PKSR:
136         s->pm_regs[addr >> 2] &= ~value;
137         break;
138 
139     default:	/* Read-write registers */
140         if (!(addr & 3)) {
141             s->pm_regs[addr >> 2] = value;
142             break;
143         }
144 
145         printf("%s: Bad register " REG_FMT "\n", __func__, addr);
146         break;
147     }
148 }
149 
150 static const MemoryRegionOps pxa2xx_pm_ops = {
151     .read = pxa2xx_pm_read,
152     .write = pxa2xx_pm_write,
153     .endianness = DEVICE_NATIVE_ENDIAN,
154 };
155 
156 static const VMStateDescription vmstate_pxa2xx_pm = {
157     .name = "pxa2xx_pm",
158     .version_id = 0,
159     .minimum_version_id = 0,
160     .fields = (VMStateField[]) {
161         VMSTATE_UINT32_ARRAY(pm_regs, PXA2xxState, 0x40),
162         VMSTATE_END_OF_LIST()
163     }
164 };
165 
166 #define CCCR	0x00	/* Core Clock Configuration register */
167 #define CKEN	0x04	/* Clock Enable register */
168 #define OSCC	0x08	/* Oscillator Configuration register */
169 #define CCSR	0x0c	/* Core Clock Status register */
170 
171 static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr,
172                                unsigned size)
173 {
174     PXA2xxState *s = (PXA2xxState *) opaque;
175 
176     switch (addr) {
177     case CCCR:
178     case CKEN:
179     case OSCC:
180         return s->cm_regs[addr >> 2];
181 
182     case CCSR:
183         return s->cm_regs[CCCR >> 2] | (3 << 28);
184 
185     default:
186         printf("%s: Bad register " REG_FMT "\n", __func__, addr);
187         break;
188     }
189     return 0;
190 }
191 
192 static void pxa2xx_cm_write(void *opaque, hwaddr addr,
193                             uint64_t value, unsigned size)
194 {
195     PXA2xxState *s = (PXA2xxState *) opaque;
196 
197     switch (addr) {
198     case CCCR:
199     case CKEN:
200         s->cm_regs[addr >> 2] = value;
201         break;
202 
203     case OSCC:
204         s->cm_regs[addr >> 2] &= ~0x6c;
205         s->cm_regs[addr >> 2] |= value & 0x6e;
206         if ((value >> 1) & 1)			/* OON */
207             s->cm_regs[addr >> 2] |= 1 << 0;	/* Oscillator is now stable */
208         break;
209 
210     default:
211         printf("%s: Bad register " REG_FMT "\n", __func__, addr);
212         break;
213     }
214 }
215 
216 static const MemoryRegionOps pxa2xx_cm_ops = {
217     .read = pxa2xx_cm_read,
218     .write = pxa2xx_cm_write,
219     .endianness = DEVICE_NATIVE_ENDIAN,
220 };
221 
222 static const VMStateDescription vmstate_pxa2xx_cm = {
223     .name = "pxa2xx_cm",
224     .version_id = 0,
225     .minimum_version_id = 0,
226     .fields = (VMStateField[]) {
227         VMSTATE_UINT32_ARRAY(cm_regs, PXA2xxState, 4),
228         VMSTATE_UINT32(clkcfg, PXA2xxState),
229         VMSTATE_UINT32(pmnc, PXA2xxState),
230         VMSTATE_END_OF_LIST()
231     }
232 };
233 
234 static uint64_t pxa2xx_clkcfg_read(CPUARMState *env, const ARMCPRegInfo *ri)
235 {
236     PXA2xxState *s = (PXA2xxState *)ri->opaque;
237     return s->clkcfg;
238 }
239 
240 static void pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri,
241                                 uint64_t value)
242 {
243     PXA2xxState *s = (PXA2xxState *)ri->opaque;
244     s->clkcfg = value & 0xf;
245     if (value & 2) {
246         printf("%s: CPU frequency change attempt\n", __func__);
247     }
248 }
249 
250 static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri,
251                                  uint64_t value)
252 {
253     PXA2xxState *s = (PXA2xxState *)ri->opaque;
254     static const char *pwrmode[8] = {
255         "Normal", "Idle", "Deep-idle", "Standby",
256         "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
257     };
258 
259     if (value & 8) {
260         printf("%s: CPU voltage change attempt\n", __func__);
261     }
262     switch (value & 7) {
263     case 0:
264         /* Do nothing */
265         break;
266 
267     case 1:
268         /* Idle */
269         if (!(s->cm_regs[CCCR >> 2] & (1U << 31))) { /* CPDIS */
270             cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
271             break;
272         }
273         /* Fall through.  */
274 
275     case 2:
276         /* Deep-Idle */
277         cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
278         s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
279         goto message;
280 
281     case 3:
282         s->cpu->env.uncached_cpsr = ARM_CPU_MODE_SVC;
283         s->cpu->env.daif = PSTATE_A | PSTATE_F | PSTATE_I;
284         s->cpu->env.cp15.sctlr_ns = 0;
285         s->cpu->env.cp15.cpacr_el1 = 0;
286         s->cpu->env.cp15.ttbr0_el[1] = 0;
287         s->cpu->env.cp15.dacr_ns = 0;
288         s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
289         s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
290 
291         /*
292          * The scratch-pad register is almost universally used
293          * for storing the return address on suspend.  For the
294          * lack of a resuming bootloader, perform a jump
295          * directly to that address.
296          */
297         memset(s->cpu->env.regs, 0, 4 * 15);
298         s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2];
299 
300 #if 0
301         buffer = 0xe59ff000; /* ldr     pc, [pc, #0] */
302         cpu_physical_memory_write(0, &buffer, 4);
303         buffer = s->pm_regs[PSPR >> 2];
304         cpu_physical_memory_write(8, &buffer, 4);
305 #endif
306 
307         /* Suspend */
308         cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
309 
310         goto message;
311 
312     default:
313     message:
314         printf("%s: machine entered %s mode\n", __func__,
315                pwrmode[value & 7]);
316     }
317 }
318 
319 static uint64_t pxa2xx_cppmnc_read(CPUARMState *env, const ARMCPRegInfo *ri)
320 {
321     PXA2xxState *s = (PXA2xxState *)ri->opaque;
322     return s->pmnc;
323 }
324 
325 static void pxa2xx_cppmnc_write(CPUARMState *env, const ARMCPRegInfo *ri,
326                                 uint64_t value)
327 {
328     PXA2xxState *s = (PXA2xxState *)ri->opaque;
329     s->pmnc = value;
330 }
331 
332 static uint64_t pxa2xx_cpccnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
333 {
334     PXA2xxState *s = (PXA2xxState *)ri->opaque;
335     if (s->pmnc & 1) {
336         return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
337     } else {
338         return 0;
339     }
340 }
341 
342 static const ARMCPRegInfo pxa_cp_reginfo[] = {
343     /* cp14 crm==1: perf registers */
344     { .name = "CPPMNC", .cp = 14, .crn = 0, .crm = 1, .opc1 = 0, .opc2 = 0,
345       .access = PL1_RW, .type = ARM_CP_IO,
346       .readfn = pxa2xx_cppmnc_read, .writefn = pxa2xx_cppmnc_write },
347     { .name = "CPCCNT", .cp = 14, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
348       .access = PL1_RW, .type = ARM_CP_IO,
349       .readfn = pxa2xx_cpccnt_read, .writefn = arm_cp_write_ignore },
350     { .name = "CPINTEN", .cp = 14, .crn = 4, .crm = 1, .opc1 = 0, .opc2 = 0,
351       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
352     { .name = "CPFLAG", .cp = 14, .crn = 5, .crm = 1, .opc1 = 0, .opc2 = 0,
353       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
354     { .name = "CPEVTSEL", .cp = 14, .crn = 8, .crm = 1, .opc1 = 0, .opc2 = 0,
355       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
356     /* cp14 crm==2: performance count registers */
357     { .name = "CPPMN0", .cp = 14, .crn = 0, .crm = 2, .opc1 = 0, .opc2 = 0,
358       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
359     { .name = "CPPMN1", .cp = 14, .crn = 1, .crm = 2, .opc1 = 0, .opc2 = 0,
360       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
361     { .name = "CPPMN2", .cp = 14, .crn = 2, .crm = 2, .opc1 = 0, .opc2 = 0,
362       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
363     { .name = "CPPMN3", .cp = 14, .crn = 2, .crm = 3, .opc1 = 0, .opc2 = 0,
364       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
365     /* cp14 crn==6: CLKCFG */
366     { .name = "CLKCFG", .cp = 14, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
367       .access = PL1_RW, .type = ARM_CP_IO,
368       .readfn = pxa2xx_clkcfg_read, .writefn = pxa2xx_clkcfg_write },
369     /* cp14 crn==7: PWRMODE */
370     { .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0,
371       .access = PL1_RW, .type = ARM_CP_IO,
372       .readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write },
373     REGINFO_SENTINEL
374 };
375 
376 static void pxa2xx_setup_cp14(PXA2xxState *s)
377 {
378     define_arm_cp_regs_with_opaque(s->cpu, pxa_cp_reginfo, s);
379 }
380 
381 #define MDCNFG		0x00	/* SDRAM Configuration register */
382 #define MDREFR		0x04	/* SDRAM Refresh Control register */
383 #define MSC0		0x08	/* Static Memory Control register 0 */
384 #define MSC1		0x0c	/* Static Memory Control register 1 */
385 #define MSC2		0x10	/* Static Memory Control register 2 */
386 #define MECR		0x14	/* Expansion Memory Bus Config register */
387 #define SXCNFG		0x1c	/* Synchronous Static Memory Config register */
388 #define MCMEM0		0x28	/* PC Card Memory Socket 0 Timing register */
389 #define MCMEM1		0x2c	/* PC Card Memory Socket 1 Timing register */
390 #define MCATT0		0x30	/* PC Card Attribute Socket 0 register */
391 #define MCATT1		0x34	/* PC Card Attribute Socket 1 register */
392 #define MCIO0		0x38	/* PC Card I/O Socket 0 Timing register */
393 #define MCIO1		0x3c	/* PC Card I/O Socket 1 Timing register */
394 #define MDMRS		0x40	/* SDRAM Mode Register Set Config register */
395 #define BOOT_DEF	0x44	/* Boot-time Default Configuration register */
396 #define ARB_CNTL	0x48	/* Arbiter Control register */
397 #define BSCNTR0		0x4c	/* Memory Buffer Strength Control register 0 */
398 #define BSCNTR1		0x50	/* Memory Buffer Strength Control register 1 */
399 #define LCDBSCNTR	0x54	/* LCD Buffer Strength Control register */
400 #define MDMRSLP		0x58	/* Low Power SDRAM Mode Set Config register */
401 #define BSCNTR2		0x5c	/* Memory Buffer Strength Control register 2 */
402 #define BSCNTR3		0x60	/* Memory Buffer Strength Control register 3 */
403 #define SA1110		0x64	/* SA-1110 Memory Compatibility register */
404 
405 static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr,
406                                unsigned size)
407 {
408     PXA2xxState *s = (PXA2xxState *) opaque;
409 
410     switch (addr) {
411     case MDCNFG ... SA1110:
412         if ((addr & 3) == 0)
413             return s->mm_regs[addr >> 2];
414         /* fall through */
415     default:
416         printf("%s: Bad register " REG_FMT "\n", __func__, addr);
417         break;
418     }
419     return 0;
420 }
421 
422 static void pxa2xx_mm_write(void *opaque, hwaddr addr,
423                             uint64_t value, unsigned size)
424 {
425     PXA2xxState *s = (PXA2xxState *) opaque;
426 
427     switch (addr) {
428     case MDCNFG ... SA1110:
429         if ((addr & 3) == 0) {
430             s->mm_regs[addr >> 2] = value;
431             break;
432         }
433 
434     default:
435         printf("%s: Bad register " REG_FMT "\n", __func__, addr);
436         break;
437     }
438 }
439 
440 static const MemoryRegionOps pxa2xx_mm_ops = {
441     .read = pxa2xx_mm_read,
442     .write = pxa2xx_mm_write,
443     .endianness = DEVICE_NATIVE_ENDIAN,
444 };
445 
446 static const VMStateDescription vmstate_pxa2xx_mm = {
447     .name = "pxa2xx_mm",
448     .version_id = 0,
449     .minimum_version_id = 0,
450     .fields = (VMStateField[]) {
451         VMSTATE_UINT32_ARRAY(mm_regs, PXA2xxState, 0x1a),
452         VMSTATE_END_OF_LIST()
453     }
454 };
455 
456 #define TYPE_PXA2XX_SSP "pxa2xx-ssp"
457 #define PXA2XX_SSP(obj) \
458     OBJECT_CHECK(PXA2xxSSPState, (obj), TYPE_PXA2XX_SSP)
459 
460 /* Synchronous Serial Ports */
461 typedef struct {
462     /*< private >*/
463     SysBusDevice parent_obj;
464     /*< public >*/
465 
466     MemoryRegion iomem;
467     qemu_irq irq;
468     uint32_t enable;
469     SSIBus *bus;
470 
471     uint32_t sscr[2];
472     uint32_t sspsp;
473     uint32_t ssto;
474     uint32_t ssitr;
475     uint32_t sssr;
476     uint8_t sstsa;
477     uint8_t ssrsa;
478     uint8_t ssacd;
479 
480     uint32_t rx_fifo[16];
481     uint32_t rx_level;
482     uint32_t rx_start;
483 } PXA2xxSSPState;
484 
485 static bool pxa2xx_ssp_vmstate_validate(void *opaque, int version_id)
486 {
487     PXA2xxSSPState *s = opaque;
488 
489     return s->rx_start < sizeof(s->rx_fifo);
490 }
491 
492 static const VMStateDescription vmstate_pxa2xx_ssp = {
493     .name = "pxa2xx-ssp",
494     .version_id = 1,
495     .minimum_version_id = 1,
496     .fields = (VMStateField[]) {
497         VMSTATE_UINT32(enable, PXA2xxSSPState),
498         VMSTATE_UINT32_ARRAY(sscr, PXA2xxSSPState, 2),
499         VMSTATE_UINT32(sspsp, PXA2xxSSPState),
500         VMSTATE_UINT32(ssto, PXA2xxSSPState),
501         VMSTATE_UINT32(ssitr, PXA2xxSSPState),
502         VMSTATE_UINT32(sssr, PXA2xxSSPState),
503         VMSTATE_UINT8(sstsa, PXA2xxSSPState),
504         VMSTATE_UINT8(ssrsa, PXA2xxSSPState),
505         VMSTATE_UINT8(ssacd, PXA2xxSSPState),
506         VMSTATE_UINT32(rx_level, PXA2xxSSPState),
507         VMSTATE_UINT32(rx_start, PXA2xxSSPState),
508         VMSTATE_VALIDATE("fifo is 16 bytes", pxa2xx_ssp_vmstate_validate),
509         VMSTATE_UINT32_ARRAY(rx_fifo, PXA2xxSSPState, 16),
510         VMSTATE_END_OF_LIST()
511     }
512 };
513 
514 #define SSCR0	0x00	/* SSP Control register 0 */
515 #define SSCR1	0x04	/* SSP Control register 1 */
516 #define SSSR	0x08	/* SSP Status register */
517 #define SSITR	0x0c	/* SSP Interrupt Test register */
518 #define SSDR	0x10	/* SSP Data register */
519 #define SSTO	0x28	/* SSP Time-Out register */
520 #define SSPSP	0x2c	/* SSP Programmable Serial Protocol register */
521 #define SSTSA	0x30	/* SSP TX Time Slot Active register */
522 #define SSRSA	0x34	/* SSP RX Time Slot Active register */
523 #define SSTSS	0x38	/* SSP Time Slot Status register */
524 #define SSACD	0x3c	/* SSP Audio Clock Divider register */
525 
526 /* Bitfields for above registers */
527 #define SSCR0_SPI(x)	(((x) & 0x30) == 0x00)
528 #define SSCR0_SSP(x)	(((x) & 0x30) == 0x10)
529 #define SSCR0_UWIRE(x)	(((x) & 0x30) == 0x20)
530 #define SSCR0_PSP(x)	(((x) & 0x30) == 0x30)
531 #define SSCR0_SSE	(1 << 7)
532 #define SSCR0_RIM	(1 << 22)
533 #define SSCR0_TIM	(1 << 23)
534 #define SSCR0_MOD       (1U << 31)
535 #define SSCR0_DSS(x)	(((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
536 #define SSCR1_RIE	(1 << 0)
537 #define SSCR1_TIE	(1 << 1)
538 #define SSCR1_LBM	(1 << 2)
539 #define SSCR1_MWDS	(1 << 5)
540 #define SSCR1_TFT(x)	((((x) >> 6) & 0xf) + 1)
541 #define SSCR1_RFT(x)	((((x) >> 10) & 0xf) + 1)
542 #define SSCR1_EFWR	(1 << 14)
543 #define SSCR1_PINTE	(1 << 18)
544 #define SSCR1_TINTE	(1 << 19)
545 #define SSCR1_RSRE	(1 << 20)
546 #define SSCR1_TSRE	(1 << 21)
547 #define SSCR1_EBCEI	(1 << 29)
548 #define SSITR_INT	(7 << 5)
549 #define SSSR_TNF	(1 << 2)
550 #define SSSR_RNE	(1 << 3)
551 #define SSSR_TFS	(1 << 5)
552 #define SSSR_RFS	(1 << 6)
553 #define SSSR_ROR	(1 << 7)
554 #define SSSR_PINT	(1 << 18)
555 #define SSSR_TINT	(1 << 19)
556 #define SSSR_EOC	(1 << 20)
557 #define SSSR_TUR	(1 << 21)
558 #define SSSR_BCE	(1 << 23)
559 #define SSSR_RW		0x00bc0080
560 
561 static void pxa2xx_ssp_int_update(PXA2xxSSPState *s)
562 {
563     int level = 0;
564 
565     level |= s->ssitr & SSITR_INT;
566     level |= (s->sssr & SSSR_BCE)  &&  (s->sscr[1] & SSCR1_EBCEI);
567     level |= (s->sssr & SSSR_TUR)  && !(s->sscr[0] & SSCR0_TIM);
568     level |= (s->sssr & SSSR_EOC)  &&  (s->sssr & (SSSR_TINT | SSSR_PINT));
569     level |= (s->sssr & SSSR_TINT) &&  (s->sscr[1] & SSCR1_TINTE);
570     level |= (s->sssr & SSSR_PINT) &&  (s->sscr[1] & SSCR1_PINTE);
571     level |= (s->sssr & SSSR_ROR)  && !(s->sscr[0] & SSCR0_RIM);
572     level |= (s->sssr & SSSR_RFS)  &&  (s->sscr[1] & SSCR1_RIE);
573     level |= (s->sssr & SSSR_TFS)  &&  (s->sscr[1] & SSCR1_TIE);
574     qemu_set_irq(s->irq, !!level);
575 }
576 
577 static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s)
578 {
579     s->sssr &= ~(0xf << 12);	/* Clear RFL */
580     s->sssr &= ~(0xf << 8);	/* Clear TFL */
581     s->sssr &= ~SSSR_TFS;
582     s->sssr &= ~SSSR_TNF;
583     if (s->enable) {
584         s->sssr |= ((s->rx_level - 1) & 0xf) << 12;
585         if (s->rx_level >= SSCR1_RFT(s->sscr[1]))
586             s->sssr |= SSSR_RFS;
587         else
588             s->sssr &= ~SSSR_RFS;
589         if (s->rx_level)
590             s->sssr |= SSSR_RNE;
591         else
592             s->sssr &= ~SSSR_RNE;
593         /* TX FIFO is never filled, so it is always in underrun
594            condition if SSP is enabled */
595         s->sssr |= SSSR_TFS;
596         s->sssr |= SSSR_TNF;
597     }
598 
599     pxa2xx_ssp_int_update(s);
600 }
601 
602 static uint64_t pxa2xx_ssp_read(void *opaque, hwaddr addr,
603                                 unsigned size)
604 {
605     PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
606     uint32_t retval;
607 
608     switch (addr) {
609     case SSCR0:
610         return s->sscr[0];
611     case SSCR1:
612         return s->sscr[1];
613     case SSPSP:
614         return s->sspsp;
615     case SSTO:
616         return s->ssto;
617     case SSITR:
618         return s->ssitr;
619     case SSSR:
620         return s->sssr | s->ssitr;
621     case SSDR:
622         if (!s->enable)
623             return 0xffffffff;
624         if (s->rx_level < 1) {
625             printf("%s: SSP Rx Underrun\n", __func__);
626             return 0xffffffff;
627         }
628         s->rx_level --;
629         retval = s->rx_fifo[s->rx_start ++];
630         s->rx_start &= 0xf;
631         pxa2xx_ssp_fifo_update(s);
632         return retval;
633     case SSTSA:
634         return s->sstsa;
635     case SSRSA:
636         return s->ssrsa;
637     case SSTSS:
638         return 0;
639     case SSACD:
640         return s->ssacd;
641     default:
642         printf("%s: Bad register " REG_FMT "\n", __func__, addr);
643         break;
644     }
645     return 0;
646 }
647 
648 static void pxa2xx_ssp_write(void *opaque, hwaddr addr,
649                              uint64_t value64, unsigned size)
650 {
651     PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
652     uint32_t value = value64;
653 
654     switch (addr) {
655     case SSCR0:
656         s->sscr[0] = value & 0xc7ffffff;
657         s->enable = value & SSCR0_SSE;
658         if (value & SSCR0_MOD)
659             printf("%s: Attempt to use network mode\n", __func__);
660         if (s->enable && SSCR0_DSS(value) < 4)
661             printf("%s: Wrong data size: %i bits\n", __func__,
662                             SSCR0_DSS(value));
663         if (!(value & SSCR0_SSE)) {
664             s->sssr = 0;
665             s->ssitr = 0;
666             s->rx_level = 0;
667         }
668         pxa2xx_ssp_fifo_update(s);
669         break;
670 
671     case SSCR1:
672         s->sscr[1] = value;
673         if (value & (SSCR1_LBM | SSCR1_EFWR))
674             printf("%s: Attempt to use SSP test mode\n", __func__);
675         pxa2xx_ssp_fifo_update(s);
676         break;
677 
678     case SSPSP:
679         s->sspsp = value;
680         break;
681 
682     case SSTO:
683         s->ssto = value;
684         break;
685 
686     case SSITR:
687         s->ssitr = value & SSITR_INT;
688         pxa2xx_ssp_int_update(s);
689         break;
690 
691     case SSSR:
692         s->sssr &= ~(value & SSSR_RW);
693         pxa2xx_ssp_int_update(s);
694         break;
695 
696     case SSDR:
697         if (SSCR0_UWIRE(s->sscr[0])) {
698             if (s->sscr[1] & SSCR1_MWDS)
699                 value &= 0xffff;
700             else
701                 value &= 0xff;
702         } else
703             /* Note how 32bits overflow does no harm here */
704             value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
705 
706         /* Data goes from here to the Tx FIFO and is shifted out from
707          * there directly to the slave, no need to buffer it.
708          */
709         if (s->enable) {
710             uint32_t readval;
711             readval = ssi_transfer(s->bus, value);
712             if (s->rx_level < 0x10) {
713                 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval;
714             } else {
715                 s->sssr |= SSSR_ROR;
716             }
717         }
718         pxa2xx_ssp_fifo_update(s);
719         break;
720 
721     case SSTSA:
722         s->sstsa = value;
723         break;
724 
725     case SSRSA:
726         s->ssrsa = value;
727         break;
728 
729     case SSACD:
730         s->ssacd = value;
731         break;
732 
733     default:
734         printf("%s: Bad register " REG_FMT "\n", __func__, addr);
735         break;
736     }
737 }
738 
739 static const MemoryRegionOps pxa2xx_ssp_ops = {
740     .read = pxa2xx_ssp_read,
741     .write = pxa2xx_ssp_write,
742     .endianness = DEVICE_NATIVE_ENDIAN,
743 };
744 
745 static void pxa2xx_ssp_reset(DeviceState *d)
746 {
747     PXA2xxSSPState *s = PXA2XX_SSP(d);
748 
749     s->enable = 0;
750     s->sscr[0] = s->sscr[1] = 0;
751     s->sspsp = 0;
752     s->ssto = 0;
753     s->ssitr = 0;
754     s->sssr = 0;
755     s->sstsa = 0;
756     s->ssrsa = 0;
757     s->ssacd = 0;
758     s->rx_start = s->rx_level = 0;
759 }
760 
761 static void pxa2xx_ssp_init(Object *obj)
762 {
763     DeviceState *dev = DEVICE(obj);
764     PXA2xxSSPState *s = PXA2XX_SSP(obj);
765     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
766     sysbus_init_irq(sbd, &s->irq);
767 
768     memory_region_init_io(&s->iomem, obj, &pxa2xx_ssp_ops, s,
769                           "pxa2xx-ssp", 0x1000);
770     sysbus_init_mmio(sbd, &s->iomem);
771 
772     s->bus = ssi_create_bus(dev, "ssi");
773 }
774 
775 /* Real-Time Clock */
776 #define RCNR		0x00	/* RTC Counter register */
777 #define RTAR		0x04	/* RTC Alarm register */
778 #define RTSR		0x08	/* RTC Status register */
779 #define RTTR		0x0c	/* RTC Timer Trim register */
780 #define RDCR		0x10	/* RTC Day Counter register */
781 #define RYCR		0x14	/* RTC Year Counter register */
782 #define RDAR1		0x18	/* RTC Wristwatch Day Alarm register 1 */
783 #define RYAR1		0x1c	/* RTC Wristwatch Year Alarm register 1 */
784 #define RDAR2		0x20	/* RTC Wristwatch Day Alarm register 2 */
785 #define RYAR2		0x24	/* RTC Wristwatch Year Alarm register 2 */
786 #define SWCR		0x28	/* RTC Stopwatch Counter register */
787 #define SWAR1		0x2c	/* RTC Stopwatch Alarm register 1 */
788 #define SWAR2		0x30	/* RTC Stopwatch Alarm register 2 */
789 #define RTCPICR		0x34	/* RTC Periodic Interrupt Counter register */
790 #define PIAR		0x38	/* RTC Periodic Interrupt Alarm register */
791 
792 #define TYPE_PXA2XX_RTC "pxa2xx_rtc"
793 #define PXA2XX_RTC(obj) \
794     OBJECT_CHECK(PXA2xxRTCState, (obj), TYPE_PXA2XX_RTC)
795 
796 typedef struct {
797     /*< private >*/
798     SysBusDevice parent_obj;
799     /*< public >*/
800 
801     MemoryRegion iomem;
802     uint32_t rttr;
803     uint32_t rtsr;
804     uint32_t rtar;
805     uint32_t rdar1;
806     uint32_t rdar2;
807     uint32_t ryar1;
808     uint32_t ryar2;
809     uint32_t swar1;
810     uint32_t swar2;
811     uint32_t piar;
812     uint32_t last_rcnr;
813     uint32_t last_rdcr;
814     uint32_t last_rycr;
815     uint32_t last_swcr;
816     uint32_t last_rtcpicr;
817     int64_t last_hz;
818     int64_t last_sw;
819     int64_t last_pi;
820     QEMUTimer *rtc_hz;
821     QEMUTimer *rtc_rdal1;
822     QEMUTimer *rtc_rdal2;
823     QEMUTimer *rtc_swal1;
824     QEMUTimer *rtc_swal2;
825     QEMUTimer *rtc_pi;
826     qemu_irq rtc_irq;
827 } PXA2xxRTCState;
828 
829 static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s)
830 {
831     qemu_set_irq(s->rtc_irq, !!(s->rtsr & 0x2553));
832 }
833 
834 static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s)
835 {
836     int64_t rt = qemu_clock_get_ms(rtc_clock);
837     s->last_rcnr += ((rt - s->last_hz) << 15) /
838             (1000 * ((s->rttr & 0xffff) + 1));
839     s->last_rdcr += ((rt - s->last_hz) << 15) /
840             (1000 * ((s->rttr & 0xffff) + 1));
841     s->last_hz = rt;
842 }
843 
844 static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s)
845 {
846     int64_t rt = qemu_clock_get_ms(rtc_clock);
847     if (s->rtsr & (1 << 12))
848         s->last_swcr += (rt - s->last_sw) / 10;
849     s->last_sw = rt;
850 }
851 
852 static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s)
853 {
854     int64_t rt = qemu_clock_get_ms(rtc_clock);
855     if (s->rtsr & (1 << 15))
856         s->last_swcr += rt - s->last_pi;
857     s->last_pi = rt;
858 }
859 
860 static inline void pxa2xx_rtc_alarm_update(PXA2xxRTCState *s,
861                 uint32_t rtsr)
862 {
863     if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0)))
864         timer_mod(s->rtc_hz, s->last_hz +
865                 (((s->rtar - s->last_rcnr) * 1000 *
866                   ((s->rttr & 0xffff) + 1)) >> 15));
867     else
868         timer_del(s->rtc_hz);
869 
870     if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4)))
871         timer_mod(s->rtc_rdal1, s->last_hz +
872                 (((s->rdar1 - s->last_rdcr) * 1000 *
873                   ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
874     else
875         timer_del(s->rtc_rdal1);
876 
877     if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6)))
878         timer_mod(s->rtc_rdal2, s->last_hz +
879                 (((s->rdar2 - s->last_rdcr) * 1000 *
880                   ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
881     else
882         timer_del(s->rtc_rdal2);
883 
884     if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8)))
885         timer_mod(s->rtc_swal1, s->last_sw +
886                         (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */
887     else
888         timer_del(s->rtc_swal1);
889 
890     if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10)))
891         timer_mod(s->rtc_swal2, s->last_sw +
892                         (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */
893     else
894         timer_del(s->rtc_swal2);
895 
896     if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13)))
897         timer_mod(s->rtc_pi, s->last_pi +
898                         (s->piar & 0xffff) - s->last_rtcpicr);
899     else
900         timer_del(s->rtc_pi);
901 }
902 
903 static inline void pxa2xx_rtc_hz_tick(void *opaque)
904 {
905     PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
906     s->rtsr |= (1 << 0);
907     pxa2xx_rtc_alarm_update(s, s->rtsr);
908     pxa2xx_rtc_int_update(s);
909 }
910 
911 static inline void pxa2xx_rtc_rdal1_tick(void *opaque)
912 {
913     PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
914     s->rtsr |= (1 << 4);
915     pxa2xx_rtc_alarm_update(s, s->rtsr);
916     pxa2xx_rtc_int_update(s);
917 }
918 
919 static inline void pxa2xx_rtc_rdal2_tick(void *opaque)
920 {
921     PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
922     s->rtsr |= (1 << 6);
923     pxa2xx_rtc_alarm_update(s, s->rtsr);
924     pxa2xx_rtc_int_update(s);
925 }
926 
927 static inline void pxa2xx_rtc_swal1_tick(void *opaque)
928 {
929     PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
930     s->rtsr |= (1 << 8);
931     pxa2xx_rtc_alarm_update(s, s->rtsr);
932     pxa2xx_rtc_int_update(s);
933 }
934 
935 static inline void pxa2xx_rtc_swal2_tick(void *opaque)
936 {
937     PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
938     s->rtsr |= (1 << 10);
939     pxa2xx_rtc_alarm_update(s, s->rtsr);
940     pxa2xx_rtc_int_update(s);
941 }
942 
943 static inline void pxa2xx_rtc_pi_tick(void *opaque)
944 {
945     PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
946     s->rtsr |= (1 << 13);
947     pxa2xx_rtc_piupdate(s);
948     s->last_rtcpicr = 0;
949     pxa2xx_rtc_alarm_update(s, s->rtsr);
950     pxa2xx_rtc_int_update(s);
951 }
952 
953 static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr,
954                                 unsigned size)
955 {
956     PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
957 
958     switch (addr) {
959     case RTTR:
960         return s->rttr;
961     case RTSR:
962         return s->rtsr;
963     case RTAR:
964         return s->rtar;
965     case RDAR1:
966         return s->rdar1;
967     case RDAR2:
968         return s->rdar2;
969     case RYAR1:
970         return s->ryar1;
971     case RYAR2:
972         return s->ryar2;
973     case SWAR1:
974         return s->swar1;
975     case SWAR2:
976         return s->swar2;
977     case PIAR:
978         return s->piar;
979     case RCNR:
980         return s->last_rcnr +
981             ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) /
982             (1000 * ((s->rttr & 0xffff) + 1));
983     case RDCR:
984         return s->last_rdcr +
985             ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) /
986             (1000 * ((s->rttr & 0xffff) + 1));
987     case RYCR:
988         return s->last_rycr;
989     case SWCR:
990         if (s->rtsr & (1 << 12))
991             return s->last_swcr +
992                 (qemu_clock_get_ms(rtc_clock) - s->last_sw) / 10;
993         else
994             return s->last_swcr;
995     default:
996         printf("%s: Bad register " REG_FMT "\n", __func__, addr);
997         break;
998     }
999     return 0;
1000 }
1001 
1002 static void pxa2xx_rtc_write(void *opaque, hwaddr addr,
1003                              uint64_t value64, unsigned size)
1004 {
1005     PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1006     uint32_t value = value64;
1007 
1008     switch (addr) {
1009     case RTTR:
1010         if (!(s->rttr & (1U << 31))) {
1011             pxa2xx_rtc_hzupdate(s);
1012             s->rttr = value;
1013             pxa2xx_rtc_alarm_update(s, s->rtsr);
1014         }
1015         break;
1016 
1017     case RTSR:
1018         if ((s->rtsr ^ value) & (1 << 15))
1019             pxa2xx_rtc_piupdate(s);
1020 
1021         if ((s->rtsr ^ value) & (1 << 12))
1022             pxa2xx_rtc_swupdate(s);
1023 
1024         if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac))
1025             pxa2xx_rtc_alarm_update(s, value);
1026 
1027         s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac));
1028         pxa2xx_rtc_int_update(s);
1029         break;
1030 
1031     case RTAR:
1032         s->rtar = value;
1033         pxa2xx_rtc_alarm_update(s, s->rtsr);
1034         break;
1035 
1036     case RDAR1:
1037         s->rdar1 = value;
1038         pxa2xx_rtc_alarm_update(s, s->rtsr);
1039         break;
1040 
1041     case RDAR2:
1042         s->rdar2 = value;
1043         pxa2xx_rtc_alarm_update(s, s->rtsr);
1044         break;
1045 
1046     case RYAR1:
1047         s->ryar1 = value;
1048         pxa2xx_rtc_alarm_update(s, s->rtsr);
1049         break;
1050 
1051     case RYAR2:
1052         s->ryar2 = value;
1053         pxa2xx_rtc_alarm_update(s, s->rtsr);
1054         break;
1055 
1056     case SWAR1:
1057         pxa2xx_rtc_swupdate(s);
1058         s->swar1 = value;
1059         s->last_swcr = 0;
1060         pxa2xx_rtc_alarm_update(s, s->rtsr);
1061         break;
1062 
1063     case SWAR2:
1064         s->swar2 = value;
1065         pxa2xx_rtc_alarm_update(s, s->rtsr);
1066         break;
1067 
1068     case PIAR:
1069         s->piar = value;
1070         pxa2xx_rtc_alarm_update(s, s->rtsr);
1071         break;
1072 
1073     case RCNR:
1074         pxa2xx_rtc_hzupdate(s);
1075         s->last_rcnr = value;
1076         pxa2xx_rtc_alarm_update(s, s->rtsr);
1077         break;
1078 
1079     case RDCR:
1080         pxa2xx_rtc_hzupdate(s);
1081         s->last_rdcr = value;
1082         pxa2xx_rtc_alarm_update(s, s->rtsr);
1083         break;
1084 
1085     case RYCR:
1086         s->last_rycr = value;
1087         break;
1088 
1089     case SWCR:
1090         pxa2xx_rtc_swupdate(s);
1091         s->last_swcr = value;
1092         pxa2xx_rtc_alarm_update(s, s->rtsr);
1093         break;
1094 
1095     case RTCPICR:
1096         pxa2xx_rtc_piupdate(s);
1097         s->last_rtcpicr = value & 0xffff;
1098         pxa2xx_rtc_alarm_update(s, s->rtsr);
1099         break;
1100 
1101     default:
1102         printf("%s: Bad register " REG_FMT "\n", __func__, addr);
1103     }
1104 }
1105 
1106 static const MemoryRegionOps pxa2xx_rtc_ops = {
1107     .read = pxa2xx_rtc_read,
1108     .write = pxa2xx_rtc_write,
1109     .endianness = DEVICE_NATIVE_ENDIAN,
1110 };
1111 
1112 static void pxa2xx_rtc_init(Object *obj)
1113 {
1114     PXA2xxRTCState *s = PXA2XX_RTC(obj);
1115     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
1116     struct tm tm;
1117     int wom;
1118 
1119     s->rttr = 0x7fff;
1120     s->rtsr = 0;
1121 
1122     qemu_get_timedate(&tm, 0);
1123     wom = ((tm.tm_mday - 1) / 7) + 1;
1124 
1125     s->last_rcnr = (uint32_t) mktimegm(&tm);
1126     s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) |
1127             (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec;
1128     s->last_rycr = ((tm.tm_year + 1900) << 9) |
1129             ((tm.tm_mon + 1) << 5) | tm.tm_mday;
1130     s->last_swcr = (tm.tm_hour << 19) |
1131             (tm.tm_min << 13) | (tm.tm_sec << 7);
1132     s->last_rtcpicr = 0;
1133     s->last_hz = s->last_sw = s->last_pi = qemu_clock_get_ms(rtc_clock);
1134 
1135     s->rtc_hz    = timer_new_ms(rtc_clock, pxa2xx_rtc_hz_tick,    s);
1136     s->rtc_rdal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal1_tick, s);
1137     s->rtc_rdal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal2_tick, s);
1138     s->rtc_swal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal1_tick, s);
1139     s->rtc_swal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal2_tick, s);
1140     s->rtc_pi    = timer_new_ms(rtc_clock, pxa2xx_rtc_pi_tick,    s);
1141 
1142     sysbus_init_irq(dev, &s->rtc_irq);
1143 
1144     memory_region_init_io(&s->iomem, obj, &pxa2xx_rtc_ops, s,
1145                           "pxa2xx-rtc", 0x10000);
1146     sysbus_init_mmio(dev, &s->iomem);
1147 }
1148 
1149 static int pxa2xx_rtc_pre_save(void *opaque)
1150 {
1151     PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1152 
1153     pxa2xx_rtc_hzupdate(s);
1154     pxa2xx_rtc_piupdate(s);
1155     pxa2xx_rtc_swupdate(s);
1156 
1157     return 0;
1158 }
1159 
1160 static int pxa2xx_rtc_post_load(void *opaque, int version_id)
1161 {
1162     PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1163 
1164     pxa2xx_rtc_alarm_update(s, s->rtsr);
1165 
1166     return 0;
1167 }
1168 
1169 static const VMStateDescription vmstate_pxa2xx_rtc_regs = {
1170     .name = "pxa2xx_rtc",
1171     .version_id = 0,
1172     .minimum_version_id = 0,
1173     .pre_save = pxa2xx_rtc_pre_save,
1174     .post_load = pxa2xx_rtc_post_load,
1175     .fields = (VMStateField[]) {
1176         VMSTATE_UINT32(rttr, PXA2xxRTCState),
1177         VMSTATE_UINT32(rtsr, PXA2xxRTCState),
1178         VMSTATE_UINT32(rtar, PXA2xxRTCState),
1179         VMSTATE_UINT32(rdar1, PXA2xxRTCState),
1180         VMSTATE_UINT32(rdar2, PXA2xxRTCState),
1181         VMSTATE_UINT32(ryar1, PXA2xxRTCState),
1182         VMSTATE_UINT32(ryar2, PXA2xxRTCState),
1183         VMSTATE_UINT32(swar1, PXA2xxRTCState),
1184         VMSTATE_UINT32(swar2, PXA2xxRTCState),
1185         VMSTATE_UINT32(piar, PXA2xxRTCState),
1186         VMSTATE_UINT32(last_rcnr, PXA2xxRTCState),
1187         VMSTATE_UINT32(last_rdcr, PXA2xxRTCState),
1188         VMSTATE_UINT32(last_rycr, PXA2xxRTCState),
1189         VMSTATE_UINT32(last_swcr, PXA2xxRTCState),
1190         VMSTATE_UINT32(last_rtcpicr, PXA2xxRTCState),
1191         VMSTATE_INT64(last_hz, PXA2xxRTCState),
1192         VMSTATE_INT64(last_sw, PXA2xxRTCState),
1193         VMSTATE_INT64(last_pi, PXA2xxRTCState),
1194         VMSTATE_END_OF_LIST(),
1195     },
1196 };
1197 
1198 static void pxa2xx_rtc_sysbus_class_init(ObjectClass *klass, void *data)
1199 {
1200     DeviceClass *dc = DEVICE_CLASS(klass);
1201 
1202     dc->desc = "PXA2xx RTC Controller";
1203     dc->vmsd = &vmstate_pxa2xx_rtc_regs;
1204 }
1205 
1206 static const TypeInfo pxa2xx_rtc_sysbus_info = {
1207     .name          = TYPE_PXA2XX_RTC,
1208     .parent        = TYPE_SYS_BUS_DEVICE,
1209     .instance_size = sizeof(PXA2xxRTCState),
1210     .instance_init = pxa2xx_rtc_init,
1211     .class_init    = pxa2xx_rtc_sysbus_class_init,
1212 };
1213 
1214 /* I2C Interface */
1215 
1216 #define TYPE_PXA2XX_I2C_SLAVE "pxa2xx-i2c-slave"
1217 #define PXA2XX_I2C_SLAVE(obj) \
1218     OBJECT_CHECK(PXA2xxI2CSlaveState, (obj), TYPE_PXA2XX_I2C_SLAVE)
1219 
1220 typedef struct PXA2xxI2CSlaveState {
1221     I2CSlave parent_obj;
1222 
1223     PXA2xxI2CState *host;
1224 } PXA2xxI2CSlaveState;
1225 
1226 #define TYPE_PXA2XX_I2C "pxa2xx_i2c"
1227 #define PXA2XX_I2C(obj) \
1228     OBJECT_CHECK(PXA2xxI2CState, (obj), TYPE_PXA2XX_I2C)
1229 
1230 struct PXA2xxI2CState {
1231     /*< private >*/
1232     SysBusDevice parent_obj;
1233     /*< public >*/
1234 
1235     MemoryRegion iomem;
1236     PXA2xxI2CSlaveState *slave;
1237     I2CBus *bus;
1238     qemu_irq irq;
1239     uint32_t offset;
1240     uint32_t region_size;
1241 
1242     uint16_t control;
1243     uint16_t status;
1244     uint8_t ibmr;
1245     uint8_t data;
1246 };
1247 
1248 #define IBMR	0x80	/* I2C Bus Monitor register */
1249 #define IDBR	0x88	/* I2C Data Buffer register */
1250 #define ICR	0x90	/* I2C Control register */
1251 #define ISR	0x98	/* I2C Status register */
1252 #define ISAR	0xa0	/* I2C Slave Address register */
1253 
1254 static void pxa2xx_i2c_update(PXA2xxI2CState *s)
1255 {
1256     uint16_t level = 0;
1257     level |= s->status & s->control & (1 << 10);		/* BED */
1258     level |= (s->status & (1 << 7)) && (s->control & (1 << 9));	/* IRF */
1259     level |= (s->status & (1 << 6)) && (s->control & (1 << 8));	/* ITE */
1260     level |= s->status & (1 << 9);				/* SAD */
1261     qemu_set_irq(s->irq, !!level);
1262 }
1263 
1264 /* These are only stubs now.  */
1265 static int pxa2xx_i2c_event(I2CSlave *i2c, enum i2c_event event)
1266 {
1267     PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c);
1268     PXA2xxI2CState *s = slave->host;
1269 
1270     switch (event) {
1271     case I2C_START_SEND:
1272         s->status |= (1 << 9);				/* set SAD */
1273         s->status &= ~(1 << 0);				/* clear RWM */
1274         break;
1275     case I2C_START_RECV:
1276         s->status |= (1 << 9);				/* set SAD */
1277         s->status |= 1 << 0;				/* set RWM */
1278         break;
1279     case I2C_FINISH:
1280         s->status |= (1 << 4);				/* set SSD */
1281         break;
1282     case I2C_NACK:
1283         s->status |= 1 << 1;				/* set ACKNAK */
1284         break;
1285     }
1286     pxa2xx_i2c_update(s);
1287 
1288     return 0;
1289 }
1290 
1291 static uint8_t pxa2xx_i2c_rx(I2CSlave *i2c)
1292 {
1293     PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c);
1294     PXA2xxI2CState *s = slave->host;
1295 
1296     if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) {
1297         return 0;
1298     }
1299 
1300     if (s->status & (1 << 0)) {			/* RWM */
1301         s->status |= 1 << 6;			/* set ITE */
1302     }
1303     pxa2xx_i2c_update(s);
1304 
1305     return s->data;
1306 }
1307 
1308 static int pxa2xx_i2c_tx(I2CSlave *i2c, uint8_t data)
1309 {
1310     PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c);
1311     PXA2xxI2CState *s = slave->host;
1312 
1313     if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) {
1314         return 1;
1315     }
1316 
1317     if (!(s->status & (1 << 0))) {		/* RWM */
1318         s->status |= 1 << 7;			/* set IRF */
1319         s->data = data;
1320     }
1321     pxa2xx_i2c_update(s);
1322 
1323     return 1;
1324 }
1325 
1326 static uint64_t pxa2xx_i2c_read(void *opaque, hwaddr addr,
1327                                 unsigned size)
1328 {
1329     PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1330     I2CSlave *slave;
1331 
1332     addr -= s->offset;
1333     switch (addr) {
1334     case ICR:
1335         return s->control;
1336     case ISR:
1337         return s->status | (i2c_bus_busy(s->bus) << 2);
1338     case ISAR:
1339         slave = I2C_SLAVE(s->slave);
1340         return slave->address;
1341     case IDBR:
1342         return s->data;
1343     case IBMR:
1344         if (s->status & (1 << 2))
1345             s->ibmr ^= 3;	/* Fake SCL and SDA pin changes */
1346         else
1347             s->ibmr = 0;
1348         return s->ibmr;
1349     default:
1350         printf("%s: Bad register " REG_FMT "\n", __func__, addr);
1351         break;
1352     }
1353     return 0;
1354 }
1355 
1356 static void pxa2xx_i2c_write(void *opaque, hwaddr addr,
1357                              uint64_t value64, unsigned size)
1358 {
1359     PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1360     uint32_t value = value64;
1361     int ack;
1362 
1363     addr -= s->offset;
1364     switch (addr) {
1365     case ICR:
1366         s->control = value & 0xfff7;
1367         if ((value & (1 << 3)) && (value & (1 << 6))) {	/* TB and IUE */
1368             /* TODO: slave mode */
1369             if (value & (1 << 0)) {			/* START condition */
1370                 if (s->data & 1)
1371                     s->status |= 1 << 0;		/* set RWM */
1372                 else
1373                     s->status &= ~(1 << 0);		/* clear RWM */
1374                 ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1);
1375             } else {
1376                 if (s->status & (1 << 0)) {		/* RWM */
1377                     s->data = i2c_recv(s->bus);
1378                     if (value & (1 << 2))		/* ACKNAK */
1379                         i2c_nack(s->bus);
1380                     ack = 1;
1381                 } else
1382                     ack = !i2c_send(s->bus, s->data);
1383             }
1384 
1385             if (value & (1 << 1))			/* STOP condition */
1386                 i2c_end_transfer(s->bus);
1387 
1388             if (ack) {
1389                 if (value & (1 << 0))			/* START condition */
1390                     s->status |= 1 << 6;		/* set ITE */
1391                 else
1392                     if (s->status & (1 << 0))		/* RWM */
1393                         s->status |= 1 << 7;		/* set IRF */
1394                     else
1395                         s->status |= 1 << 6;		/* set ITE */
1396                 s->status &= ~(1 << 1);			/* clear ACKNAK */
1397             } else {
1398                 s->status |= 1 << 6;			/* set ITE */
1399                 s->status |= 1 << 10;			/* set BED */
1400                 s->status |= 1 << 1;			/* set ACKNAK */
1401             }
1402         }
1403         if (!(value & (1 << 3)) && (value & (1 << 6)))	/* !TB and IUE */
1404             if (value & (1 << 4))			/* MA */
1405                 i2c_end_transfer(s->bus);
1406         pxa2xx_i2c_update(s);
1407         break;
1408 
1409     case ISR:
1410         s->status &= ~(value & 0x07f0);
1411         pxa2xx_i2c_update(s);
1412         break;
1413 
1414     case ISAR:
1415         i2c_set_slave_address(I2C_SLAVE(s->slave), value & 0x7f);
1416         break;
1417 
1418     case IDBR:
1419         s->data = value & 0xff;
1420         break;
1421 
1422     default:
1423         printf("%s: Bad register " REG_FMT "\n", __func__, addr);
1424     }
1425 }
1426 
1427 static const MemoryRegionOps pxa2xx_i2c_ops = {
1428     .read = pxa2xx_i2c_read,
1429     .write = pxa2xx_i2c_write,
1430     .endianness = DEVICE_NATIVE_ENDIAN,
1431 };
1432 
1433 static const VMStateDescription vmstate_pxa2xx_i2c_slave = {
1434     .name = "pxa2xx_i2c_slave",
1435     .version_id = 1,
1436     .minimum_version_id = 1,
1437     .fields = (VMStateField[]) {
1438         VMSTATE_I2C_SLAVE(parent_obj, PXA2xxI2CSlaveState),
1439         VMSTATE_END_OF_LIST()
1440     }
1441 };
1442 
1443 static const VMStateDescription vmstate_pxa2xx_i2c = {
1444     .name = "pxa2xx_i2c",
1445     .version_id = 1,
1446     .minimum_version_id = 1,
1447     .fields = (VMStateField[]) {
1448         VMSTATE_UINT16(control, PXA2xxI2CState),
1449         VMSTATE_UINT16(status, PXA2xxI2CState),
1450         VMSTATE_UINT8(ibmr, PXA2xxI2CState),
1451         VMSTATE_UINT8(data, PXA2xxI2CState),
1452         VMSTATE_STRUCT_POINTER(slave, PXA2xxI2CState,
1453                                vmstate_pxa2xx_i2c_slave, PXA2xxI2CSlaveState),
1454         VMSTATE_END_OF_LIST()
1455     }
1456 };
1457 
1458 static void pxa2xx_i2c_slave_class_init(ObjectClass *klass, void *data)
1459 {
1460     I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
1461 
1462     k->event = pxa2xx_i2c_event;
1463     k->recv = pxa2xx_i2c_rx;
1464     k->send = pxa2xx_i2c_tx;
1465 }
1466 
1467 static const TypeInfo pxa2xx_i2c_slave_info = {
1468     .name          = TYPE_PXA2XX_I2C_SLAVE,
1469     .parent        = TYPE_I2C_SLAVE,
1470     .instance_size = sizeof(PXA2xxI2CSlaveState),
1471     .class_init    = pxa2xx_i2c_slave_class_init,
1472 };
1473 
1474 PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
1475                 qemu_irq irq, uint32_t region_size)
1476 {
1477     DeviceState *dev;
1478     SysBusDevice *i2c_dev;
1479     PXA2xxI2CState *s;
1480     I2CBus *i2cbus;
1481 
1482     dev = qdev_create(NULL, TYPE_PXA2XX_I2C);
1483     qdev_prop_set_uint32(dev, "size", region_size + 1);
1484     qdev_prop_set_uint32(dev, "offset", base & region_size);
1485     qdev_init_nofail(dev);
1486 
1487     i2c_dev = SYS_BUS_DEVICE(dev);
1488     sysbus_mmio_map(i2c_dev, 0, base & ~region_size);
1489     sysbus_connect_irq(i2c_dev, 0, irq);
1490 
1491     s = PXA2XX_I2C(i2c_dev);
1492     /* FIXME: Should the slave device really be on a separate bus?  */
1493     i2cbus = i2c_init_bus(dev, "dummy");
1494     dev = i2c_create_slave(i2cbus, TYPE_PXA2XX_I2C_SLAVE, 0);
1495     s->slave = PXA2XX_I2C_SLAVE(dev);
1496     s->slave->host = s;
1497 
1498     return s;
1499 }
1500 
1501 static void pxa2xx_i2c_initfn(Object *obj)
1502 {
1503     DeviceState *dev = DEVICE(obj);
1504     PXA2xxI2CState *s = PXA2XX_I2C(obj);
1505     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1506 
1507     s->bus = i2c_init_bus(dev, NULL);
1508 
1509     memory_region_init_io(&s->iomem, obj, &pxa2xx_i2c_ops, s,
1510                           "pxa2xx-i2c", s->region_size);
1511     sysbus_init_mmio(sbd, &s->iomem);
1512     sysbus_init_irq(sbd, &s->irq);
1513 }
1514 
1515 I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s)
1516 {
1517     return s->bus;
1518 }
1519 
1520 static Property pxa2xx_i2c_properties[] = {
1521     DEFINE_PROP_UINT32("size", PXA2xxI2CState, region_size, 0x10000),
1522     DEFINE_PROP_UINT32("offset", PXA2xxI2CState, offset, 0),
1523     DEFINE_PROP_END_OF_LIST(),
1524 };
1525 
1526 static void pxa2xx_i2c_class_init(ObjectClass *klass, void *data)
1527 {
1528     DeviceClass *dc = DEVICE_CLASS(klass);
1529 
1530     dc->desc = "PXA2xx I2C Bus Controller";
1531     dc->vmsd = &vmstate_pxa2xx_i2c;
1532     dc->props = pxa2xx_i2c_properties;
1533 }
1534 
1535 static const TypeInfo pxa2xx_i2c_info = {
1536     .name          = TYPE_PXA2XX_I2C,
1537     .parent        = TYPE_SYS_BUS_DEVICE,
1538     .instance_size = sizeof(PXA2xxI2CState),
1539     .instance_init = pxa2xx_i2c_initfn,
1540     .class_init    = pxa2xx_i2c_class_init,
1541 };
1542 
1543 /* PXA Inter-IC Sound Controller */
1544 static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s)
1545 {
1546     i2s->rx_len = 0;
1547     i2s->tx_len = 0;
1548     i2s->fifo_len = 0;
1549     i2s->clk = 0x1a;
1550     i2s->control[0] = 0x00;
1551     i2s->control[1] = 0x00;
1552     i2s->status = 0x00;
1553     i2s->mask = 0x00;
1554 }
1555 
1556 #define SACR_TFTH(val)	((val >> 8) & 0xf)
1557 #define SACR_RFTH(val)	((val >> 12) & 0xf)
1558 #define SACR_DREC(val)	(val & (1 << 3))
1559 #define SACR_DPRL(val)	(val & (1 << 4))
1560 
1561 static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s)
1562 {
1563     int rfs, tfs;
1564     rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len &&
1565             !SACR_DREC(i2s->control[1]);
1566     tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) &&
1567             i2s->enable && !SACR_DPRL(i2s->control[1]);
1568 
1569     qemu_set_irq(i2s->rx_dma, rfs);
1570     qemu_set_irq(i2s->tx_dma, tfs);
1571 
1572     i2s->status &= 0xe0;
1573     if (i2s->fifo_len < 16 || !i2s->enable)
1574         i2s->status |= 1 << 0;			/* TNF */
1575     if (i2s->rx_len)
1576         i2s->status |= 1 << 1;			/* RNE */
1577     if (i2s->enable)
1578         i2s->status |= 1 << 2;			/* BSY */
1579     if (tfs)
1580         i2s->status |= 1 << 3;			/* TFS */
1581     if (rfs)
1582         i2s->status |= 1 << 4;			/* RFS */
1583     if (!(i2s->tx_len && i2s->enable))
1584         i2s->status |= i2s->fifo_len << 8;	/* TFL */
1585     i2s->status |= MAX(i2s->rx_len, 0xf) << 12;	/* RFL */
1586 
1587     qemu_set_irq(i2s->irq, i2s->status & i2s->mask);
1588 }
1589 
1590 #define SACR0	0x00	/* Serial Audio Global Control register */
1591 #define SACR1	0x04	/* Serial Audio I2S/MSB-Justified Control register */
1592 #define SASR0	0x0c	/* Serial Audio Interface and FIFO Status register */
1593 #define SAIMR	0x14	/* Serial Audio Interrupt Mask register */
1594 #define SAICR	0x18	/* Serial Audio Interrupt Clear register */
1595 #define SADIV	0x60	/* Serial Audio Clock Divider register */
1596 #define SADR	0x80	/* Serial Audio Data register */
1597 
1598 static uint64_t pxa2xx_i2s_read(void *opaque, hwaddr addr,
1599                                 unsigned size)
1600 {
1601     PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1602 
1603     switch (addr) {
1604     case SACR0:
1605         return s->control[0];
1606     case SACR1:
1607         return s->control[1];
1608     case SASR0:
1609         return s->status;
1610     case SAIMR:
1611         return s->mask;
1612     case SAICR:
1613         return 0;
1614     case SADIV:
1615         return s->clk;
1616     case SADR:
1617         if (s->rx_len > 0) {
1618             s->rx_len --;
1619             pxa2xx_i2s_update(s);
1620             return s->codec_in(s->opaque);
1621         }
1622         return 0;
1623     default:
1624         printf("%s: Bad register " REG_FMT "\n", __func__, addr);
1625         break;
1626     }
1627     return 0;
1628 }
1629 
1630 static void pxa2xx_i2s_write(void *opaque, hwaddr addr,
1631                              uint64_t value, unsigned size)
1632 {
1633     PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1634     uint32_t *sample;
1635 
1636     switch (addr) {
1637     case SACR0:
1638         if (value & (1 << 3))				/* RST */
1639             pxa2xx_i2s_reset(s);
1640         s->control[0] = value & 0xff3d;
1641         if (!s->enable && (value & 1) && s->tx_len) {	/* ENB */
1642             for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++)
1643                 s->codec_out(s->opaque, *sample);
1644             s->status &= ~(1 << 7);			/* I2SOFF */
1645         }
1646         if (value & (1 << 4))				/* EFWR */
1647             printf("%s: Attempt to use special function\n", __func__);
1648         s->enable = (value & 9) == 1;			/* ENB && !RST*/
1649         pxa2xx_i2s_update(s);
1650         break;
1651     case SACR1:
1652         s->control[1] = value & 0x0039;
1653         if (value & (1 << 5))				/* ENLBF */
1654             printf("%s: Attempt to use loopback function\n", __func__);
1655         if (value & (1 << 4))				/* DPRL */
1656             s->fifo_len = 0;
1657         pxa2xx_i2s_update(s);
1658         break;
1659     case SAIMR:
1660         s->mask = value & 0x0078;
1661         pxa2xx_i2s_update(s);
1662         break;
1663     case SAICR:
1664         s->status &= ~(value & (3 << 5));
1665         pxa2xx_i2s_update(s);
1666         break;
1667     case SADIV:
1668         s->clk = value & 0x007f;
1669         break;
1670     case SADR:
1671         if (s->tx_len && s->enable) {
1672             s->tx_len --;
1673             pxa2xx_i2s_update(s);
1674             s->codec_out(s->opaque, value);
1675         } else if (s->fifo_len < 16) {
1676             s->fifo[s->fifo_len ++] = value;
1677             pxa2xx_i2s_update(s);
1678         }
1679         break;
1680     default:
1681         printf("%s: Bad register " REG_FMT "\n", __func__, addr);
1682     }
1683 }
1684 
1685 static const MemoryRegionOps pxa2xx_i2s_ops = {
1686     .read = pxa2xx_i2s_read,
1687     .write = pxa2xx_i2s_write,
1688     .endianness = DEVICE_NATIVE_ENDIAN,
1689 };
1690 
1691 static const VMStateDescription vmstate_pxa2xx_i2s = {
1692     .name = "pxa2xx_i2s",
1693     .version_id = 0,
1694     .minimum_version_id = 0,
1695     .fields = (VMStateField[]) {
1696         VMSTATE_UINT32_ARRAY(control, PXA2xxI2SState, 2),
1697         VMSTATE_UINT32(status, PXA2xxI2SState),
1698         VMSTATE_UINT32(mask, PXA2xxI2SState),
1699         VMSTATE_UINT32(clk, PXA2xxI2SState),
1700         VMSTATE_INT32(enable, PXA2xxI2SState),
1701         VMSTATE_INT32(rx_len, PXA2xxI2SState),
1702         VMSTATE_INT32(tx_len, PXA2xxI2SState),
1703         VMSTATE_INT32(fifo_len, PXA2xxI2SState),
1704         VMSTATE_END_OF_LIST()
1705     }
1706 };
1707 
1708 static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx)
1709 {
1710     PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1711     uint32_t *sample;
1712 
1713     /* Signal FIFO errors */
1714     if (s->enable && s->tx_len)
1715         s->status |= 1 << 5;		/* TUR */
1716     if (s->enable && s->rx_len)
1717         s->status |= 1 << 6;		/* ROR */
1718 
1719     /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1720      * handle the cases where it makes a difference.  */
1721     s->tx_len = tx - s->fifo_len;
1722     s->rx_len = rx;
1723     /* Note that is s->codec_out wasn't set, we wouldn't get called.  */
1724     if (s->enable)
1725         for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++)
1726             s->codec_out(s->opaque, *sample);
1727     pxa2xx_i2s_update(s);
1728 }
1729 
1730 static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem,
1731                 hwaddr base,
1732                 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma)
1733 {
1734     PXA2xxI2SState *s = g_new0(PXA2xxI2SState, 1);
1735 
1736     s->irq = irq;
1737     s->rx_dma = rx_dma;
1738     s->tx_dma = tx_dma;
1739     s->data_req = pxa2xx_i2s_data_req;
1740 
1741     pxa2xx_i2s_reset(s);
1742 
1743     memory_region_init_io(&s->iomem, NULL, &pxa2xx_i2s_ops, s,
1744                           "pxa2xx-i2s", 0x100000);
1745     memory_region_add_subregion(sysmem, base, &s->iomem);
1746 
1747     vmstate_register(NULL, base, &vmstate_pxa2xx_i2s, s);
1748 
1749     return s;
1750 }
1751 
1752 /* PXA Fast Infra-red Communications Port */
1753 #define TYPE_PXA2XX_FIR "pxa2xx-fir"
1754 #define PXA2XX_FIR(obj) OBJECT_CHECK(PXA2xxFIrState, (obj), TYPE_PXA2XX_FIR)
1755 
1756 struct PXA2xxFIrState {
1757     /*< private >*/
1758     SysBusDevice parent_obj;
1759     /*< public >*/
1760 
1761     MemoryRegion iomem;
1762     qemu_irq irq;
1763     qemu_irq rx_dma;
1764     qemu_irq tx_dma;
1765     uint32_t enable;
1766     CharBackend chr;
1767 
1768     uint8_t control[3];
1769     uint8_t status[2];
1770 
1771     uint32_t rx_len;
1772     uint32_t rx_start;
1773     uint8_t rx_fifo[64];
1774 };
1775 
1776 static void pxa2xx_fir_reset(DeviceState *d)
1777 {
1778     PXA2xxFIrState *s = PXA2XX_FIR(d);
1779 
1780     s->control[0] = 0x00;
1781     s->control[1] = 0x00;
1782     s->control[2] = 0x00;
1783     s->status[0] = 0x00;
1784     s->status[1] = 0x00;
1785     s->enable = 0;
1786 }
1787 
1788 static inline void pxa2xx_fir_update(PXA2xxFIrState *s)
1789 {
1790     static const int tresh[4] = { 8, 16, 32, 0 };
1791     int intr = 0;
1792     if ((s->control[0] & (1 << 4)) &&			/* RXE */
1793                     s->rx_len >= tresh[s->control[2] & 3])	/* TRIG */
1794         s->status[0] |= 1 << 4;				/* RFS */
1795     else
1796         s->status[0] &= ~(1 << 4);			/* RFS */
1797     if (s->control[0] & (1 << 3))			/* TXE */
1798         s->status[0] |= 1 << 3;				/* TFS */
1799     else
1800         s->status[0] &= ~(1 << 3);			/* TFS */
1801     if (s->rx_len)
1802         s->status[1] |= 1 << 2;				/* RNE */
1803     else
1804         s->status[1] &= ~(1 << 2);			/* RNE */
1805     if (s->control[0] & (1 << 4))			/* RXE */
1806         s->status[1] |= 1 << 0;				/* RSY */
1807     else
1808         s->status[1] &= ~(1 << 0);			/* RSY */
1809 
1810     intr |= (s->control[0] & (1 << 5)) &&		/* RIE */
1811             (s->status[0] & (1 << 4));			/* RFS */
1812     intr |= (s->control[0] & (1 << 6)) &&		/* TIE */
1813             (s->status[0] & (1 << 3));			/* TFS */
1814     intr |= (s->control[2] & (1 << 4)) &&		/* TRAIL */
1815             (s->status[0] & (1 << 6));			/* EOC */
1816     intr |= (s->control[0] & (1 << 2)) &&		/* TUS */
1817             (s->status[0] & (1 << 1));			/* TUR */
1818     intr |= s->status[0] & 0x25;			/* FRE, RAB, EIF */
1819 
1820     qemu_set_irq(s->rx_dma, (s->status[0] >> 4) & 1);
1821     qemu_set_irq(s->tx_dma, (s->status[0] >> 3) & 1);
1822 
1823     qemu_set_irq(s->irq, intr && s->enable);
1824 }
1825 
1826 #define ICCR0	0x00	/* FICP Control register 0 */
1827 #define ICCR1	0x04	/* FICP Control register 1 */
1828 #define ICCR2	0x08	/* FICP Control register 2 */
1829 #define ICDR	0x0c	/* FICP Data register */
1830 #define ICSR0	0x14	/* FICP Status register 0 */
1831 #define ICSR1	0x18	/* FICP Status register 1 */
1832 #define ICFOR	0x1c	/* FICP FIFO Occupancy Status register */
1833 
1834 static uint64_t pxa2xx_fir_read(void *opaque, hwaddr addr,
1835                                 unsigned size)
1836 {
1837     PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1838     uint8_t ret;
1839 
1840     switch (addr) {
1841     case ICCR0:
1842         return s->control[0];
1843     case ICCR1:
1844         return s->control[1];
1845     case ICCR2:
1846         return s->control[2];
1847     case ICDR:
1848         s->status[0] &= ~0x01;
1849         s->status[1] &= ~0x72;
1850         if (s->rx_len) {
1851             s->rx_len --;
1852             ret = s->rx_fifo[s->rx_start ++];
1853             s->rx_start &= 63;
1854             pxa2xx_fir_update(s);
1855             return ret;
1856         }
1857         printf("%s: Rx FIFO underrun.\n", __func__);
1858         break;
1859     case ICSR0:
1860         return s->status[0];
1861     case ICSR1:
1862         return s->status[1] | (1 << 3);			/* TNF */
1863     case ICFOR:
1864         return s->rx_len;
1865     default:
1866         printf("%s: Bad register " REG_FMT "\n", __func__, addr);
1867         break;
1868     }
1869     return 0;
1870 }
1871 
1872 static void pxa2xx_fir_write(void *opaque, hwaddr addr,
1873                              uint64_t value64, unsigned size)
1874 {
1875     PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1876     uint32_t value = value64;
1877     uint8_t ch;
1878 
1879     switch (addr) {
1880     case ICCR0:
1881         s->control[0] = value;
1882         if (!(value & (1 << 4)))			/* RXE */
1883             s->rx_len = s->rx_start = 0;
1884         if (!(value & (1 << 3))) {                      /* TXE */
1885             /* Nop */
1886         }
1887         s->enable = value & 1;				/* ITR */
1888         if (!s->enable)
1889             s->status[0] = 0;
1890         pxa2xx_fir_update(s);
1891         break;
1892     case ICCR1:
1893         s->control[1] = value;
1894         break;
1895     case ICCR2:
1896         s->control[2] = value & 0x3f;
1897         pxa2xx_fir_update(s);
1898         break;
1899     case ICDR:
1900         if (s->control[2] & (1 << 2)) { /* TXP */
1901             ch = value;
1902         } else {
1903             ch = ~value;
1904         }
1905         if (s->enable && (s->control[0] & (1 << 3))) { /* TXE */
1906             /* XXX this blocks entire thread. Rewrite to use
1907              * qemu_chr_fe_write and background I/O callbacks */
1908             qemu_chr_fe_write_all(&s->chr, &ch, 1);
1909         }
1910         break;
1911     case ICSR0:
1912         s->status[0] &= ~(value & 0x66);
1913         pxa2xx_fir_update(s);
1914         break;
1915     case ICFOR:
1916         break;
1917     default:
1918         printf("%s: Bad register " REG_FMT "\n", __func__, addr);
1919     }
1920 }
1921 
1922 static const MemoryRegionOps pxa2xx_fir_ops = {
1923     .read = pxa2xx_fir_read,
1924     .write = pxa2xx_fir_write,
1925     .endianness = DEVICE_NATIVE_ENDIAN,
1926 };
1927 
1928 static int pxa2xx_fir_is_empty(void *opaque)
1929 {
1930     PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1931     return (s->rx_len < 64);
1932 }
1933 
1934 static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size)
1935 {
1936     PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1937     if (!(s->control[0] & (1 << 4)))			/* RXE */
1938         return;
1939 
1940     while (size --) {
1941         s->status[1] |= 1 << 4;				/* EOF */
1942         if (s->rx_len >= 64) {
1943             s->status[1] |= 1 << 6;			/* ROR */
1944             break;
1945         }
1946 
1947         if (s->control[2] & (1 << 3))			/* RXP */
1948             s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++);
1949         else
1950             s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++);
1951     }
1952 
1953     pxa2xx_fir_update(s);
1954 }
1955 
1956 static void pxa2xx_fir_event(void *opaque, int event)
1957 {
1958 }
1959 
1960 static void pxa2xx_fir_instance_init(Object *obj)
1961 {
1962     PXA2xxFIrState *s = PXA2XX_FIR(obj);
1963     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1964 
1965     memory_region_init_io(&s->iomem, obj, &pxa2xx_fir_ops, s,
1966                           "pxa2xx-fir", 0x1000);
1967     sysbus_init_mmio(sbd, &s->iomem);
1968     sysbus_init_irq(sbd, &s->irq);
1969     sysbus_init_irq(sbd, &s->rx_dma);
1970     sysbus_init_irq(sbd, &s->tx_dma);
1971 }
1972 
1973 static void pxa2xx_fir_realize(DeviceState *dev, Error **errp)
1974 {
1975     PXA2xxFIrState *s = PXA2XX_FIR(dev);
1976 
1977     qemu_chr_fe_set_handlers(&s->chr, pxa2xx_fir_is_empty,
1978                              pxa2xx_fir_rx, pxa2xx_fir_event, NULL, s, NULL,
1979                              true);
1980 }
1981 
1982 static bool pxa2xx_fir_vmstate_validate(void *opaque, int version_id)
1983 {
1984     PXA2xxFIrState *s = opaque;
1985 
1986     return s->rx_start < ARRAY_SIZE(s->rx_fifo);
1987 }
1988 
1989 static const VMStateDescription pxa2xx_fir_vmsd = {
1990     .name = "pxa2xx-fir",
1991     .version_id = 1,
1992     .minimum_version_id = 1,
1993     .fields = (VMStateField[]) {
1994         VMSTATE_UINT32(enable, PXA2xxFIrState),
1995         VMSTATE_UINT8_ARRAY(control, PXA2xxFIrState, 3),
1996         VMSTATE_UINT8_ARRAY(status, PXA2xxFIrState, 2),
1997         VMSTATE_UINT32(rx_len, PXA2xxFIrState),
1998         VMSTATE_UINT32(rx_start, PXA2xxFIrState),
1999         VMSTATE_VALIDATE("fifo is 64 bytes", pxa2xx_fir_vmstate_validate),
2000         VMSTATE_UINT8_ARRAY(rx_fifo, PXA2xxFIrState, 64),
2001         VMSTATE_END_OF_LIST()
2002     }
2003 };
2004 
2005 static Property pxa2xx_fir_properties[] = {
2006     DEFINE_PROP_CHR("chardev", PXA2xxFIrState, chr),
2007     DEFINE_PROP_END_OF_LIST(),
2008 };
2009 
2010 static void pxa2xx_fir_class_init(ObjectClass *klass, void *data)
2011 {
2012     DeviceClass *dc = DEVICE_CLASS(klass);
2013 
2014     dc->realize = pxa2xx_fir_realize;
2015     dc->vmsd = &pxa2xx_fir_vmsd;
2016     dc->props = pxa2xx_fir_properties;
2017     dc->reset = pxa2xx_fir_reset;
2018 }
2019 
2020 static const TypeInfo pxa2xx_fir_info = {
2021     .name = TYPE_PXA2XX_FIR,
2022     .parent = TYPE_SYS_BUS_DEVICE,
2023     .instance_size = sizeof(PXA2xxFIrState),
2024     .class_init = pxa2xx_fir_class_init,
2025     .instance_init = pxa2xx_fir_instance_init,
2026 };
2027 
2028 static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem,
2029                                        hwaddr base,
2030                                        qemu_irq irq, qemu_irq rx_dma,
2031                                        qemu_irq tx_dma,
2032                                        Chardev *chr)
2033 {
2034     DeviceState *dev;
2035     SysBusDevice *sbd;
2036 
2037     dev = qdev_create(NULL, TYPE_PXA2XX_FIR);
2038     qdev_prop_set_chr(dev, "chardev", chr);
2039     qdev_init_nofail(dev);
2040     sbd = SYS_BUS_DEVICE(dev);
2041     sysbus_mmio_map(sbd, 0, base);
2042     sysbus_connect_irq(sbd, 0, irq);
2043     sysbus_connect_irq(sbd, 1, rx_dma);
2044     sysbus_connect_irq(sbd, 2, tx_dma);
2045     return PXA2XX_FIR(dev);
2046 }
2047 
2048 static void pxa2xx_reset(void *opaque, int line, int level)
2049 {
2050     PXA2xxState *s = (PXA2xxState *) opaque;
2051 
2052     if (level && (s->pm_regs[PCFR >> 2] & 0x10)) {	/* GPR_EN */
2053         cpu_reset(CPU(s->cpu));
2054         /* TODO: reset peripherals */
2055     }
2056 }
2057 
2058 /* Initialise a PXA270 integrated chip (ARM based core).  */
2059 PXA2xxState *pxa270_init(MemoryRegion *address_space,
2060                          unsigned int sdram_size, const char *cpu_type)
2061 {
2062     PXA2xxState *s;
2063     int i;
2064     DriveInfo *dinfo;
2065     s = g_new0(PXA2xxState, 1);
2066 
2067     if (strncmp(cpu_type, "pxa27", 5)) {
2068         error_report("Machine requires a PXA27x processor");
2069         exit(1);
2070     }
2071 
2072     s->cpu = ARM_CPU(cpu_create(cpu_type));
2073     s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0);
2074 
2075     /* SDRAM & Internal Memory Storage */
2076     memory_region_init_ram(&s->sdram, NULL, "pxa270.sdram", sdram_size,
2077                            &error_fatal);
2078     memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram);
2079     memory_region_init_ram(&s->internal, NULL, "pxa270.internal", 0x40000,
2080                            &error_fatal);
2081     memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE,
2082                                 &s->internal);
2083 
2084     s->pic = pxa2xx_pic_init(0x40d00000, s->cpu);
2085 
2086     s->dma = pxa27x_dma_init(0x40000000,
2087                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
2088 
2089     sysbus_create_varargs("pxa27x-timer", 0x40a00000,
2090                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
2091                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
2092                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
2093                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
2094                     qdev_get_gpio_in(s->pic, PXA27X_PIC_OST_4_11),
2095                     NULL);
2096 
2097     s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 121);
2098 
2099     dinfo = drive_get(IF_SD, 0, 0);
2100     if (!dinfo && !qtest_enabled()) {
2101         warn_report("missing SecureDigital device");
2102     }
2103     s->mmc = pxa2xx_mmci_init(address_space, 0x41100000,
2104                     dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
2105                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),
2106                     qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
2107                     qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
2108 
2109     for (i = 0; pxa270_serial[i].io_base; i++) {
2110         if (serial_hd(i)) {
2111             serial_mm_init(address_space, pxa270_serial[i].io_base, 2,
2112                            qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn),
2113                            14857000 / 16, serial_hd(i),
2114                            DEVICE_NATIVE_ENDIAN);
2115         } else {
2116             break;
2117         }
2118     }
2119     if (serial_hd(i))
2120         s->fir = pxa2xx_fir_init(address_space, 0x40800000,
2121                         qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
2122                         qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP),
2123                         qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP),
2124                         serial_hd(i));
2125 
2126     s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000,
2127                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
2128 
2129     s->cm_base = 0x41300000;
2130     s->cm_regs[CCCR >> 2] = 0x02000210;	/* 416.0 MHz */
2131     s->clkcfg = 0x00000009;		/* Turbo mode active */
2132     memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000);
2133     memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem);
2134     vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
2135 
2136     pxa2xx_setup_cp14(s);
2137 
2138     s->mm_base = 0x48000000;
2139     s->mm_regs[MDMRS >> 2] = 0x00020002;
2140     s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2141     s->mm_regs[MECR >> 2] = 0x00000001;	/* Two PC Card sockets */
2142     memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000);
2143     memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem);
2144     vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s);
2145 
2146     s->pm_base = 0x40f00000;
2147     memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100);
2148     memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem);
2149     vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s);
2150 
2151     for (i = 0; pxa27x_ssp[i].io_base; i ++);
2152     s->ssp = g_new0(SSIBus *, i);
2153     for (i = 0; pxa27x_ssp[i].io_base; i ++) {
2154         DeviceState *dev;
2155         dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa27x_ssp[i].io_base,
2156                         qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn));
2157         s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2158     }
2159 
2160     sysbus_create_simple("sysbus-ohci", 0x4c000000,
2161                          qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
2162 
2163     s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000);
2164     s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000);
2165 
2166     sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000,
2167                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
2168 
2169     s->i2c[0] = pxa2xx_i2c_init(0x40301600,
2170                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
2171     s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
2172                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
2173 
2174     s->i2s = pxa2xx_i2s_init(address_space, 0x40400000,
2175                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S),
2176                     qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S),
2177                     qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S));
2178 
2179     s->kp = pxa27x_keypad_init(address_space, 0x41500000,
2180                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD));
2181 
2182     /* GPIO1 resets the processor */
2183     /* The handler can be overridden by board-specific code */
2184     qdev_connect_gpio_out(s->gpio, 1, s->reset);
2185     return s;
2186 }
2187 
2188 /* Initialise a PXA255 integrated chip (ARM based core).  */
2189 PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
2190 {
2191     PXA2xxState *s;
2192     int i;
2193     DriveInfo *dinfo;
2194 
2195     s = g_new0(PXA2xxState, 1);
2196 
2197     s->cpu = ARM_CPU(cpu_create(ARM_CPU_TYPE_NAME("pxa255")));
2198     s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0);
2199 
2200     /* SDRAM & Internal Memory Storage */
2201     memory_region_init_ram(&s->sdram, NULL, "pxa255.sdram", sdram_size,
2202                            &error_fatal);
2203     memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram);
2204     memory_region_init_ram(&s->internal, NULL, "pxa255.internal",
2205                            PXA2XX_INTERNAL_SIZE, &error_fatal);
2206     memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE,
2207                                 &s->internal);
2208 
2209     s->pic = pxa2xx_pic_init(0x40d00000, s->cpu);
2210 
2211     s->dma = pxa255_dma_init(0x40000000,
2212                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
2213 
2214     sysbus_create_varargs("pxa25x-timer", 0x40a00000,
2215                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
2216                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
2217                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
2218                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
2219                     NULL);
2220 
2221     s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 85);
2222 
2223     dinfo = drive_get(IF_SD, 0, 0);
2224     if (!dinfo && !qtest_enabled()) {
2225         warn_report("missing SecureDigital device");
2226     }
2227     s->mmc = pxa2xx_mmci_init(address_space, 0x41100000,
2228                     dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
2229                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),
2230                     qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
2231                     qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
2232 
2233     for (i = 0; pxa255_serial[i].io_base; i++) {
2234         if (serial_hd(i)) {
2235             serial_mm_init(address_space, pxa255_serial[i].io_base, 2,
2236                            qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn),
2237                            14745600 / 16, serial_hd(i),
2238                            DEVICE_NATIVE_ENDIAN);
2239         } else {
2240             break;
2241         }
2242     }
2243     if (serial_hd(i))
2244         s->fir = pxa2xx_fir_init(address_space, 0x40800000,
2245                         qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
2246                         qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP),
2247                         qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP),
2248                         serial_hd(i));
2249 
2250     s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000,
2251                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
2252 
2253     s->cm_base = 0x41300000;
2254     s->cm_regs[CCCR >> 2] = 0x00000121;         /* from datasheet */
2255     s->cm_regs[CKEN >> 2] = 0x00017def;         /* from datasheet */
2256 
2257     s->clkcfg = 0x00000009;		/* Turbo mode active */
2258     memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000);
2259     memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem);
2260     vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
2261 
2262     pxa2xx_setup_cp14(s);
2263 
2264     s->mm_base = 0x48000000;
2265     s->mm_regs[MDMRS >> 2] = 0x00020002;
2266     s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2267     s->mm_regs[MECR >> 2] = 0x00000001;	/* Two PC Card sockets */
2268     memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000);
2269     memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem);
2270     vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s);
2271 
2272     s->pm_base = 0x40f00000;
2273     memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100);
2274     memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem);
2275     vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s);
2276 
2277     for (i = 0; pxa255_ssp[i].io_base; i ++);
2278     s->ssp = g_new0(SSIBus *, i);
2279     for (i = 0; pxa255_ssp[i].io_base; i ++) {
2280         DeviceState *dev;
2281         dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa255_ssp[i].io_base,
2282                         qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn));
2283         s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2284     }
2285 
2286     sysbus_create_simple("sysbus-ohci", 0x4c000000,
2287                          qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
2288 
2289     s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000);
2290     s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000);
2291 
2292     sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000,
2293                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
2294 
2295     s->i2c[0] = pxa2xx_i2c_init(0x40301600,
2296                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
2297     s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
2298                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
2299 
2300     s->i2s = pxa2xx_i2s_init(address_space, 0x40400000,
2301                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S),
2302                     qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S),
2303                     qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S));
2304 
2305     /* GPIO1 resets the processor */
2306     /* The handler can be overridden by board-specific code */
2307     qdev_connect_gpio_out(s->gpio, 1, s->reset);
2308     return s;
2309 }
2310 
2311 static void pxa2xx_ssp_class_init(ObjectClass *klass, void *data)
2312 {
2313     DeviceClass *dc = DEVICE_CLASS(klass);
2314 
2315     dc->reset = pxa2xx_ssp_reset;
2316     dc->vmsd = &vmstate_pxa2xx_ssp;
2317 }
2318 
2319 static const TypeInfo pxa2xx_ssp_info = {
2320     .name          = TYPE_PXA2XX_SSP,
2321     .parent        = TYPE_SYS_BUS_DEVICE,
2322     .instance_size = sizeof(PXA2xxSSPState),
2323     .instance_init = pxa2xx_ssp_init,
2324     .class_init    = pxa2xx_ssp_class_init,
2325 };
2326 
2327 static void pxa2xx_register_types(void)
2328 {
2329     type_register_static(&pxa2xx_i2c_slave_info);
2330     type_register_static(&pxa2xx_ssp_info);
2331     type_register_static(&pxa2xx_i2c_info);
2332     type_register_static(&pxa2xx_rtc_sysbus_info);
2333     type_register_static(&pxa2xx_fir_info);
2334 }
2335 
2336 type_init(pxa2xx_register_types)
2337