1 /* 2 * Intel XScale PXA255/270 processor support. 3 * 4 * Copyright (c) 2006 Openedhand Ltd. 5 * Written by Andrzej Zaborowski <balrog@zabor.org> 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "hw/sysbus.h" 11 #include "hw/arm/pxa.h" 12 #include "sysemu/sysemu.h" 13 #include "hw/char/serial.h" 14 #include "hw/i2c/i2c.h" 15 #include "hw/ssi.h" 16 #include "sysemu/char.h" 17 #include "sysemu/blockdev.h" 18 19 static struct { 20 hwaddr io_base; 21 int irqn; 22 } pxa255_serial[] = { 23 { 0x40100000, PXA2XX_PIC_FFUART }, 24 { 0x40200000, PXA2XX_PIC_BTUART }, 25 { 0x40700000, PXA2XX_PIC_STUART }, 26 { 0x41600000, PXA25X_PIC_HWUART }, 27 { 0, 0 } 28 }, pxa270_serial[] = { 29 { 0x40100000, PXA2XX_PIC_FFUART }, 30 { 0x40200000, PXA2XX_PIC_BTUART }, 31 { 0x40700000, PXA2XX_PIC_STUART }, 32 { 0, 0 } 33 }; 34 35 typedef struct PXASSPDef { 36 hwaddr io_base; 37 int irqn; 38 } PXASSPDef; 39 40 #if 0 41 static PXASSPDef pxa250_ssp[] = { 42 { 0x41000000, PXA2XX_PIC_SSP }, 43 { 0, 0 } 44 }; 45 #endif 46 47 static PXASSPDef pxa255_ssp[] = { 48 { 0x41000000, PXA2XX_PIC_SSP }, 49 { 0x41400000, PXA25X_PIC_NSSP }, 50 { 0, 0 } 51 }; 52 53 #if 0 54 static PXASSPDef pxa26x_ssp[] = { 55 { 0x41000000, PXA2XX_PIC_SSP }, 56 { 0x41400000, PXA25X_PIC_NSSP }, 57 { 0x41500000, PXA26X_PIC_ASSP }, 58 { 0, 0 } 59 }; 60 #endif 61 62 static PXASSPDef pxa27x_ssp[] = { 63 { 0x41000000, PXA2XX_PIC_SSP }, 64 { 0x41700000, PXA27X_PIC_SSP2 }, 65 { 0x41900000, PXA2XX_PIC_SSP3 }, 66 { 0, 0 } 67 }; 68 69 #define PMCR 0x00 /* Power Manager Control register */ 70 #define PSSR 0x04 /* Power Manager Sleep Status register */ 71 #define PSPR 0x08 /* Power Manager Scratch-Pad register */ 72 #define PWER 0x0c /* Power Manager Wake-Up Enable register */ 73 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */ 74 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */ 75 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */ 76 #define PCFR 0x1c /* Power Manager General Configuration register */ 77 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */ 78 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */ 79 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */ 80 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */ 81 #define RCSR 0x30 /* Reset Controller Status register */ 82 #define PSLR 0x34 /* Power Manager Sleep Configuration register */ 83 #define PTSR 0x38 /* Power Manager Standby Configuration register */ 84 #define PVCR 0x40 /* Power Manager Voltage Change Control register */ 85 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */ 86 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */ 87 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */ 88 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */ 89 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */ 90 91 static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr, 92 unsigned size) 93 { 94 PXA2xxState *s = (PXA2xxState *) opaque; 95 96 switch (addr) { 97 case PMCR ... PCMD31: 98 if (addr & 3) 99 goto fail; 100 101 return s->pm_regs[addr >> 2]; 102 default: 103 fail: 104 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 105 break; 106 } 107 return 0; 108 } 109 110 static void pxa2xx_pm_write(void *opaque, hwaddr addr, 111 uint64_t value, unsigned size) 112 { 113 PXA2xxState *s = (PXA2xxState *) opaque; 114 115 switch (addr) { 116 case PMCR: 117 /* Clear the write-one-to-clear bits... */ 118 s->pm_regs[addr >> 2] &= ~(value & 0x2a); 119 /* ...and set the plain r/w bits */ 120 s->pm_regs[addr >> 2] &= ~0x15; 121 s->pm_regs[addr >> 2] |= value & 0x15; 122 break; 123 124 case PSSR: /* Read-clean registers */ 125 case RCSR: 126 case PKSR: 127 s->pm_regs[addr >> 2] &= ~value; 128 break; 129 130 default: /* Read-write registers */ 131 if (!(addr & 3)) { 132 s->pm_regs[addr >> 2] = value; 133 break; 134 } 135 136 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 137 break; 138 } 139 } 140 141 static const MemoryRegionOps pxa2xx_pm_ops = { 142 .read = pxa2xx_pm_read, 143 .write = pxa2xx_pm_write, 144 .endianness = DEVICE_NATIVE_ENDIAN, 145 }; 146 147 static const VMStateDescription vmstate_pxa2xx_pm = { 148 .name = "pxa2xx_pm", 149 .version_id = 0, 150 .minimum_version_id = 0, 151 .minimum_version_id_old = 0, 152 .fields = (VMStateField[]) { 153 VMSTATE_UINT32_ARRAY(pm_regs, PXA2xxState, 0x40), 154 VMSTATE_END_OF_LIST() 155 } 156 }; 157 158 #define CCCR 0x00 /* Core Clock Configuration register */ 159 #define CKEN 0x04 /* Clock Enable register */ 160 #define OSCC 0x08 /* Oscillator Configuration register */ 161 #define CCSR 0x0c /* Core Clock Status register */ 162 163 static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr, 164 unsigned size) 165 { 166 PXA2xxState *s = (PXA2xxState *) opaque; 167 168 switch (addr) { 169 case CCCR: 170 case CKEN: 171 case OSCC: 172 return s->cm_regs[addr >> 2]; 173 174 case CCSR: 175 return s->cm_regs[CCCR >> 2] | (3 << 28); 176 177 default: 178 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 179 break; 180 } 181 return 0; 182 } 183 184 static void pxa2xx_cm_write(void *opaque, hwaddr addr, 185 uint64_t value, unsigned size) 186 { 187 PXA2xxState *s = (PXA2xxState *) opaque; 188 189 switch (addr) { 190 case CCCR: 191 case CKEN: 192 s->cm_regs[addr >> 2] = value; 193 break; 194 195 case OSCC: 196 s->cm_regs[addr >> 2] &= ~0x6c; 197 s->cm_regs[addr >> 2] |= value & 0x6e; 198 if ((value >> 1) & 1) /* OON */ 199 s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */ 200 break; 201 202 default: 203 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 204 break; 205 } 206 } 207 208 static const MemoryRegionOps pxa2xx_cm_ops = { 209 .read = pxa2xx_cm_read, 210 .write = pxa2xx_cm_write, 211 .endianness = DEVICE_NATIVE_ENDIAN, 212 }; 213 214 static const VMStateDescription vmstate_pxa2xx_cm = { 215 .name = "pxa2xx_cm", 216 .version_id = 0, 217 .minimum_version_id = 0, 218 .minimum_version_id_old = 0, 219 .fields = (VMStateField[]) { 220 VMSTATE_UINT32_ARRAY(cm_regs, PXA2xxState, 4), 221 VMSTATE_UINT32(clkcfg, PXA2xxState), 222 VMSTATE_UINT32(pmnc, PXA2xxState), 223 VMSTATE_END_OF_LIST() 224 } 225 }; 226 227 static int pxa2xx_clkcfg_read(CPUARMState *env, const ARMCPRegInfo *ri, 228 uint64_t *value) 229 { 230 PXA2xxState *s = (PXA2xxState *)ri->opaque; 231 *value = s->clkcfg; 232 return 0; 233 } 234 235 static int pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri, 236 uint64_t value) 237 { 238 PXA2xxState *s = (PXA2xxState *)ri->opaque; 239 s->clkcfg = value & 0xf; 240 if (value & 2) { 241 printf("%s: CPU frequency change attempt\n", __func__); 242 } 243 return 0; 244 } 245 246 static int pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri, 247 uint64_t value) 248 { 249 PXA2xxState *s = (PXA2xxState *)ri->opaque; 250 static const char *pwrmode[8] = { 251 "Normal", "Idle", "Deep-idle", "Standby", 252 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep", 253 }; 254 255 if (value & 8) { 256 printf("%s: CPU voltage change attempt\n", __func__); 257 } 258 switch (value & 7) { 259 case 0: 260 /* Do nothing */ 261 break; 262 263 case 1: 264 /* Idle */ 265 if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) { /* CPDIS */ 266 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); 267 break; 268 } 269 /* Fall through. */ 270 271 case 2: 272 /* Deep-Idle */ 273 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); 274 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ 275 goto message; 276 277 case 3: 278 s->cpu->env.uncached_cpsr = 279 ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I; 280 s->cpu->env.cp15.c1_sys = 0; 281 s->cpu->env.cp15.c1_coproc = 0; 282 s->cpu->env.cp15.c2_base0 = 0; 283 s->cpu->env.cp15.c3 = 0; 284 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ 285 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ 286 287 /* 288 * The scratch-pad register is almost universally used 289 * for storing the return address on suspend. For the 290 * lack of a resuming bootloader, perform a jump 291 * directly to that address. 292 */ 293 memset(s->cpu->env.regs, 0, 4 * 15); 294 s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2]; 295 296 #if 0 297 buffer = 0xe59ff000; /* ldr pc, [pc, #0] */ 298 cpu_physical_memory_write(0, &buffer, 4); 299 buffer = s->pm_regs[PSPR >> 2]; 300 cpu_physical_memory_write(8, &buffer, 4); 301 #endif 302 303 /* Suspend */ 304 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); 305 306 goto message; 307 308 default: 309 message: 310 printf("%s: machine entered %s mode\n", __func__, 311 pwrmode[value & 7]); 312 } 313 314 return 0; 315 } 316 317 static int pxa2xx_cppmnc_read(CPUARMState *env, const ARMCPRegInfo *ri, 318 uint64_t *value) 319 { 320 PXA2xxState *s = (PXA2xxState *)ri->opaque; 321 *value = s->pmnc; 322 return 0; 323 } 324 325 static int pxa2xx_cppmnc_write(CPUARMState *env, const ARMCPRegInfo *ri, 326 uint64_t value) 327 { 328 PXA2xxState *s = (PXA2xxState *)ri->opaque; 329 s->pmnc = value; 330 return 0; 331 } 332 333 static int pxa2xx_cpccnt_read(CPUARMState *env, const ARMCPRegInfo *ri, 334 uint64_t *value) 335 { 336 PXA2xxState *s = (PXA2xxState *)ri->opaque; 337 if (s->pmnc & 1) { 338 *value = qemu_get_clock_ns(vm_clock); 339 } else { 340 *value = 0; 341 } 342 return 0; 343 } 344 345 static const ARMCPRegInfo pxa_cp_reginfo[] = { 346 /* cp14 crm==1: perf registers */ 347 { .name = "CPPMNC", .cp = 14, .crn = 0, .crm = 1, .opc1 = 0, .opc2 = 0, 348 .access = PL1_RW, 349 .readfn = pxa2xx_cppmnc_read, .writefn = pxa2xx_cppmnc_write }, 350 { .name = "CPCCNT", .cp = 14, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, 351 .access = PL1_RW, 352 .readfn = pxa2xx_cpccnt_read, .writefn = arm_cp_write_ignore }, 353 { .name = "CPINTEN", .cp = 14, .crn = 4, .crm = 1, .opc1 = 0, .opc2 = 0, 354 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 355 { .name = "CPFLAG", .cp = 14, .crn = 5, .crm = 1, .opc1 = 0, .opc2 = 0, 356 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 357 { .name = "CPEVTSEL", .cp = 14, .crn = 8, .crm = 1, .opc1 = 0, .opc2 = 0, 358 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 359 /* cp14 crm==2: performance count registers */ 360 { .name = "CPPMN0", .cp = 14, .crn = 0, .crm = 2, .opc1 = 0, .opc2 = 0, 361 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 362 { .name = "CPPMN1", .cp = 14, .crn = 1, .crm = 2, .opc1 = 0, .opc2 = 0, 363 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 364 { .name = "CPPMN2", .cp = 14, .crn = 2, .crm = 2, .opc1 = 0, .opc2 = 0, 365 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 366 { .name = "CPPMN3", .cp = 14, .crn = 2, .crm = 3, .opc1 = 0, .opc2 = 0, 367 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 368 /* cp14 crn==6: CLKCFG */ 369 { .name = "CLKCFG", .cp = 14, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, 370 .access = PL1_RW, 371 .readfn = pxa2xx_clkcfg_read, .writefn = pxa2xx_clkcfg_write }, 372 /* cp14 crn==7: PWRMODE */ 373 { .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0, 374 .access = PL1_RW, 375 .readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write }, 376 REGINFO_SENTINEL 377 }; 378 379 static void pxa2xx_setup_cp14(PXA2xxState *s) 380 { 381 define_arm_cp_regs_with_opaque(s->cpu, pxa_cp_reginfo, s); 382 } 383 384 #define MDCNFG 0x00 /* SDRAM Configuration register */ 385 #define MDREFR 0x04 /* SDRAM Refresh Control register */ 386 #define MSC0 0x08 /* Static Memory Control register 0 */ 387 #define MSC1 0x0c /* Static Memory Control register 1 */ 388 #define MSC2 0x10 /* Static Memory Control register 2 */ 389 #define MECR 0x14 /* Expansion Memory Bus Config register */ 390 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */ 391 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */ 392 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */ 393 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */ 394 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */ 395 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */ 396 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */ 397 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */ 398 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */ 399 #define ARB_CNTL 0x48 /* Arbiter Control register */ 400 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */ 401 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */ 402 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */ 403 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */ 404 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */ 405 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */ 406 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */ 407 408 static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr, 409 unsigned size) 410 { 411 PXA2xxState *s = (PXA2xxState *) opaque; 412 413 switch (addr) { 414 case MDCNFG ... SA1110: 415 if ((addr & 3) == 0) 416 return s->mm_regs[addr >> 2]; 417 418 default: 419 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 420 break; 421 } 422 return 0; 423 } 424 425 static void pxa2xx_mm_write(void *opaque, hwaddr addr, 426 uint64_t value, unsigned size) 427 { 428 PXA2xxState *s = (PXA2xxState *) opaque; 429 430 switch (addr) { 431 case MDCNFG ... SA1110: 432 if ((addr & 3) == 0) { 433 s->mm_regs[addr >> 2] = value; 434 break; 435 } 436 437 default: 438 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 439 break; 440 } 441 } 442 443 static const MemoryRegionOps pxa2xx_mm_ops = { 444 .read = pxa2xx_mm_read, 445 .write = pxa2xx_mm_write, 446 .endianness = DEVICE_NATIVE_ENDIAN, 447 }; 448 449 static const VMStateDescription vmstate_pxa2xx_mm = { 450 .name = "pxa2xx_mm", 451 .version_id = 0, 452 .minimum_version_id = 0, 453 .minimum_version_id_old = 0, 454 .fields = (VMStateField[]) { 455 VMSTATE_UINT32_ARRAY(mm_regs, PXA2xxState, 0x1a), 456 VMSTATE_END_OF_LIST() 457 } 458 }; 459 460 #define TYPE_PXA2XX_SSP "pxa2xx-ssp" 461 #define PXA2XX_SSP(obj) \ 462 OBJECT_CHECK(PXA2xxSSPState, (obj), TYPE_PXA2XX_SSP) 463 464 /* Synchronous Serial Ports */ 465 typedef struct { 466 /*< private >*/ 467 SysBusDevice parent_obj; 468 /*< public >*/ 469 470 MemoryRegion iomem; 471 qemu_irq irq; 472 int enable; 473 SSIBus *bus; 474 475 uint32_t sscr[2]; 476 uint32_t sspsp; 477 uint32_t ssto; 478 uint32_t ssitr; 479 uint32_t sssr; 480 uint8_t sstsa; 481 uint8_t ssrsa; 482 uint8_t ssacd; 483 484 uint32_t rx_fifo[16]; 485 int rx_level; 486 int rx_start; 487 } PXA2xxSSPState; 488 489 #define SSCR0 0x00 /* SSP Control register 0 */ 490 #define SSCR1 0x04 /* SSP Control register 1 */ 491 #define SSSR 0x08 /* SSP Status register */ 492 #define SSITR 0x0c /* SSP Interrupt Test register */ 493 #define SSDR 0x10 /* SSP Data register */ 494 #define SSTO 0x28 /* SSP Time-Out register */ 495 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */ 496 #define SSTSA 0x30 /* SSP TX Time Slot Active register */ 497 #define SSRSA 0x34 /* SSP RX Time Slot Active register */ 498 #define SSTSS 0x38 /* SSP Time Slot Status register */ 499 #define SSACD 0x3c /* SSP Audio Clock Divider register */ 500 501 /* Bitfields for above registers */ 502 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00) 503 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10) 504 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20) 505 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30) 506 #define SSCR0_SSE (1 << 7) 507 #define SSCR0_RIM (1 << 22) 508 #define SSCR0_TIM (1 << 23) 509 #define SSCR0_MOD (1 << 31) 510 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1) 511 #define SSCR1_RIE (1 << 0) 512 #define SSCR1_TIE (1 << 1) 513 #define SSCR1_LBM (1 << 2) 514 #define SSCR1_MWDS (1 << 5) 515 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1) 516 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1) 517 #define SSCR1_EFWR (1 << 14) 518 #define SSCR1_PINTE (1 << 18) 519 #define SSCR1_TINTE (1 << 19) 520 #define SSCR1_RSRE (1 << 20) 521 #define SSCR1_TSRE (1 << 21) 522 #define SSCR1_EBCEI (1 << 29) 523 #define SSITR_INT (7 << 5) 524 #define SSSR_TNF (1 << 2) 525 #define SSSR_RNE (1 << 3) 526 #define SSSR_TFS (1 << 5) 527 #define SSSR_RFS (1 << 6) 528 #define SSSR_ROR (1 << 7) 529 #define SSSR_PINT (1 << 18) 530 #define SSSR_TINT (1 << 19) 531 #define SSSR_EOC (1 << 20) 532 #define SSSR_TUR (1 << 21) 533 #define SSSR_BCE (1 << 23) 534 #define SSSR_RW 0x00bc0080 535 536 static void pxa2xx_ssp_int_update(PXA2xxSSPState *s) 537 { 538 int level = 0; 539 540 level |= s->ssitr & SSITR_INT; 541 level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI); 542 level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM); 543 level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT)); 544 level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE); 545 level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE); 546 level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM); 547 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE); 548 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE); 549 qemu_set_irq(s->irq, !!level); 550 } 551 552 static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s) 553 { 554 s->sssr &= ~(0xf << 12); /* Clear RFL */ 555 s->sssr &= ~(0xf << 8); /* Clear TFL */ 556 s->sssr &= ~SSSR_TFS; 557 s->sssr &= ~SSSR_TNF; 558 if (s->enable) { 559 s->sssr |= ((s->rx_level - 1) & 0xf) << 12; 560 if (s->rx_level >= SSCR1_RFT(s->sscr[1])) 561 s->sssr |= SSSR_RFS; 562 else 563 s->sssr &= ~SSSR_RFS; 564 if (s->rx_level) 565 s->sssr |= SSSR_RNE; 566 else 567 s->sssr &= ~SSSR_RNE; 568 /* TX FIFO is never filled, so it is always in underrun 569 condition if SSP is enabled */ 570 s->sssr |= SSSR_TFS; 571 s->sssr |= SSSR_TNF; 572 } 573 574 pxa2xx_ssp_int_update(s); 575 } 576 577 static uint64_t pxa2xx_ssp_read(void *opaque, hwaddr addr, 578 unsigned size) 579 { 580 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; 581 uint32_t retval; 582 583 switch (addr) { 584 case SSCR0: 585 return s->sscr[0]; 586 case SSCR1: 587 return s->sscr[1]; 588 case SSPSP: 589 return s->sspsp; 590 case SSTO: 591 return s->ssto; 592 case SSITR: 593 return s->ssitr; 594 case SSSR: 595 return s->sssr | s->ssitr; 596 case SSDR: 597 if (!s->enable) 598 return 0xffffffff; 599 if (s->rx_level < 1) { 600 printf("%s: SSP Rx Underrun\n", __FUNCTION__); 601 return 0xffffffff; 602 } 603 s->rx_level --; 604 retval = s->rx_fifo[s->rx_start ++]; 605 s->rx_start &= 0xf; 606 pxa2xx_ssp_fifo_update(s); 607 return retval; 608 case SSTSA: 609 return s->sstsa; 610 case SSRSA: 611 return s->ssrsa; 612 case SSTSS: 613 return 0; 614 case SSACD: 615 return s->ssacd; 616 default: 617 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 618 break; 619 } 620 return 0; 621 } 622 623 static void pxa2xx_ssp_write(void *opaque, hwaddr addr, 624 uint64_t value64, unsigned size) 625 { 626 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; 627 uint32_t value = value64; 628 629 switch (addr) { 630 case SSCR0: 631 s->sscr[0] = value & 0xc7ffffff; 632 s->enable = value & SSCR0_SSE; 633 if (value & SSCR0_MOD) 634 printf("%s: Attempt to use network mode\n", __FUNCTION__); 635 if (s->enable && SSCR0_DSS(value) < 4) 636 printf("%s: Wrong data size: %i bits\n", __FUNCTION__, 637 SSCR0_DSS(value)); 638 if (!(value & SSCR0_SSE)) { 639 s->sssr = 0; 640 s->ssitr = 0; 641 s->rx_level = 0; 642 } 643 pxa2xx_ssp_fifo_update(s); 644 break; 645 646 case SSCR1: 647 s->sscr[1] = value; 648 if (value & (SSCR1_LBM | SSCR1_EFWR)) 649 printf("%s: Attempt to use SSP test mode\n", __FUNCTION__); 650 pxa2xx_ssp_fifo_update(s); 651 break; 652 653 case SSPSP: 654 s->sspsp = value; 655 break; 656 657 case SSTO: 658 s->ssto = value; 659 break; 660 661 case SSITR: 662 s->ssitr = value & SSITR_INT; 663 pxa2xx_ssp_int_update(s); 664 break; 665 666 case SSSR: 667 s->sssr &= ~(value & SSSR_RW); 668 pxa2xx_ssp_int_update(s); 669 break; 670 671 case SSDR: 672 if (SSCR0_UWIRE(s->sscr[0])) { 673 if (s->sscr[1] & SSCR1_MWDS) 674 value &= 0xffff; 675 else 676 value &= 0xff; 677 } else 678 /* Note how 32bits overflow does no harm here */ 679 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1; 680 681 /* Data goes from here to the Tx FIFO and is shifted out from 682 * there directly to the slave, no need to buffer it. 683 */ 684 if (s->enable) { 685 uint32_t readval; 686 readval = ssi_transfer(s->bus, value); 687 if (s->rx_level < 0x10) { 688 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval; 689 } else { 690 s->sssr |= SSSR_ROR; 691 } 692 } 693 pxa2xx_ssp_fifo_update(s); 694 break; 695 696 case SSTSA: 697 s->sstsa = value; 698 break; 699 700 case SSRSA: 701 s->ssrsa = value; 702 break; 703 704 case SSACD: 705 s->ssacd = value; 706 break; 707 708 default: 709 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 710 break; 711 } 712 } 713 714 static const MemoryRegionOps pxa2xx_ssp_ops = { 715 .read = pxa2xx_ssp_read, 716 .write = pxa2xx_ssp_write, 717 .endianness = DEVICE_NATIVE_ENDIAN, 718 }; 719 720 static void pxa2xx_ssp_save(QEMUFile *f, void *opaque) 721 { 722 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; 723 int i; 724 725 qemu_put_be32(f, s->enable); 726 727 qemu_put_be32s(f, &s->sscr[0]); 728 qemu_put_be32s(f, &s->sscr[1]); 729 qemu_put_be32s(f, &s->sspsp); 730 qemu_put_be32s(f, &s->ssto); 731 qemu_put_be32s(f, &s->ssitr); 732 qemu_put_be32s(f, &s->sssr); 733 qemu_put_8s(f, &s->sstsa); 734 qemu_put_8s(f, &s->ssrsa); 735 qemu_put_8s(f, &s->ssacd); 736 737 qemu_put_byte(f, s->rx_level); 738 for (i = 0; i < s->rx_level; i ++) 739 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 0xf]); 740 } 741 742 static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id) 743 { 744 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; 745 int i; 746 747 s->enable = qemu_get_be32(f); 748 749 qemu_get_be32s(f, &s->sscr[0]); 750 qemu_get_be32s(f, &s->sscr[1]); 751 qemu_get_be32s(f, &s->sspsp); 752 qemu_get_be32s(f, &s->ssto); 753 qemu_get_be32s(f, &s->ssitr); 754 qemu_get_be32s(f, &s->sssr); 755 qemu_get_8s(f, &s->sstsa); 756 qemu_get_8s(f, &s->ssrsa); 757 qemu_get_8s(f, &s->ssacd); 758 759 s->rx_level = qemu_get_byte(f); 760 s->rx_start = 0; 761 for (i = 0; i < s->rx_level; i ++) 762 s->rx_fifo[i] = qemu_get_byte(f); 763 764 return 0; 765 } 766 767 static int pxa2xx_ssp_init(SysBusDevice *sbd) 768 { 769 DeviceState *dev = DEVICE(sbd); 770 PXA2xxSSPState *s = PXA2XX_SSP(dev); 771 772 sysbus_init_irq(sbd, &s->irq); 773 774 memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_ssp_ops, s, 775 "pxa2xx-ssp", 0x1000); 776 sysbus_init_mmio(sbd, &s->iomem); 777 register_savevm(dev, "pxa2xx_ssp", -1, 0, 778 pxa2xx_ssp_save, pxa2xx_ssp_load, s); 779 780 s->bus = ssi_create_bus(dev, "ssi"); 781 return 0; 782 } 783 784 /* Real-Time Clock */ 785 #define RCNR 0x00 /* RTC Counter register */ 786 #define RTAR 0x04 /* RTC Alarm register */ 787 #define RTSR 0x08 /* RTC Status register */ 788 #define RTTR 0x0c /* RTC Timer Trim register */ 789 #define RDCR 0x10 /* RTC Day Counter register */ 790 #define RYCR 0x14 /* RTC Year Counter register */ 791 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */ 792 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */ 793 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */ 794 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */ 795 #define SWCR 0x28 /* RTC Stopwatch Counter register */ 796 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */ 797 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */ 798 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */ 799 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */ 800 801 #define TYPE_PXA2XX_RTC "pxa2xx_rtc" 802 #define PXA2XX_RTC(obj) \ 803 OBJECT_CHECK(PXA2xxRTCState, (obj), TYPE_PXA2XX_RTC) 804 805 typedef struct { 806 /*< private >*/ 807 SysBusDevice parent_obj; 808 /*< public >*/ 809 810 MemoryRegion iomem; 811 uint32_t rttr; 812 uint32_t rtsr; 813 uint32_t rtar; 814 uint32_t rdar1; 815 uint32_t rdar2; 816 uint32_t ryar1; 817 uint32_t ryar2; 818 uint32_t swar1; 819 uint32_t swar2; 820 uint32_t piar; 821 uint32_t last_rcnr; 822 uint32_t last_rdcr; 823 uint32_t last_rycr; 824 uint32_t last_swcr; 825 uint32_t last_rtcpicr; 826 int64_t last_hz; 827 int64_t last_sw; 828 int64_t last_pi; 829 QEMUTimer *rtc_hz; 830 QEMUTimer *rtc_rdal1; 831 QEMUTimer *rtc_rdal2; 832 QEMUTimer *rtc_swal1; 833 QEMUTimer *rtc_swal2; 834 QEMUTimer *rtc_pi; 835 qemu_irq rtc_irq; 836 } PXA2xxRTCState; 837 838 static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s) 839 { 840 qemu_set_irq(s->rtc_irq, !!(s->rtsr & 0x2553)); 841 } 842 843 static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s) 844 { 845 int64_t rt = qemu_get_clock_ms(rtc_clock); 846 s->last_rcnr += ((rt - s->last_hz) << 15) / 847 (1000 * ((s->rttr & 0xffff) + 1)); 848 s->last_rdcr += ((rt - s->last_hz) << 15) / 849 (1000 * ((s->rttr & 0xffff) + 1)); 850 s->last_hz = rt; 851 } 852 853 static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s) 854 { 855 int64_t rt = qemu_get_clock_ms(rtc_clock); 856 if (s->rtsr & (1 << 12)) 857 s->last_swcr += (rt - s->last_sw) / 10; 858 s->last_sw = rt; 859 } 860 861 static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s) 862 { 863 int64_t rt = qemu_get_clock_ms(rtc_clock); 864 if (s->rtsr & (1 << 15)) 865 s->last_swcr += rt - s->last_pi; 866 s->last_pi = rt; 867 } 868 869 static inline void pxa2xx_rtc_alarm_update(PXA2xxRTCState *s, 870 uint32_t rtsr) 871 { 872 if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0))) 873 qemu_mod_timer(s->rtc_hz, s->last_hz + 874 (((s->rtar - s->last_rcnr) * 1000 * 875 ((s->rttr & 0xffff) + 1)) >> 15)); 876 else 877 qemu_del_timer(s->rtc_hz); 878 879 if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4))) 880 qemu_mod_timer(s->rtc_rdal1, s->last_hz + 881 (((s->rdar1 - s->last_rdcr) * 1000 * 882 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */ 883 else 884 qemu_del_timer(s->rtc_rdal1); 885 886 if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6))) 887 qemu_mod_timer(s->rtc_rdal2, s->last_hz + 888 (((s->rdar2 - s->last_rdcr) * 1000 * 889 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */ 890 else 891 qemu_del_timer(s->rtc_rdal2); 892 893 if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8))) 894 qemu_mod_timer(s->rtc_swal1, s->last_sw + 895 (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */ 896 else 897 qemu_del_timer(s->rtc_swal1); 898 899 if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10))) 900 qemu_mod_timer(s->rtc_swal2, s->last_sw + 901 (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */ 902 else 903 qemu_del_timer(s->rtc_swal2); 904 905 if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13))) 906 qemu_mod_timer(s->rtc_pi, s->last_pi + 907 (s->piar & 0xffff) - s->last_rtcpicr); 908 else 909 qemu_del_timer(s->rtc_pi); 910 } 911 912 static inline void pxa2xx_rtc_hz_tick(void *opaque) 913 { 914 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 915 s->rtsr |= (1 << 0); 916 pxa2xx_rtc_alarm_update(s, s->rtsr); 917 pxa2xx_rtc_int_update(s); 918 } 919 920 static inline void pxa2xx_rtc_rdal1_tick(void *opaque) 921 { 922 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 923 s->rtsr |= (1 << 4); 924 pxa2xx_rtc_alarm_update(s, s->rtsr); 925 pxa2xx_rtc_int_update(s); 926 } 927 928 static inline void pxa2xx_rtc_rdal2_tick(void *opaque) 929 { 930 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 931 s->rtsr |= (1 << 6); 932 pxa2xx_rtc_alarm_update(s, s->rtsr); 933 pxa2xx_rtc_int_update(s); 934 } 935 936 static inline void pxa2xx_rtc_swal1_tick(void *opaque) 937 { 938 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 939 s->rtsr |= (1 << 8); 940 pxa2xx_rtc_alarm_update(s, s->rtsr); 941 pxa2xx_rtc_int_update(s); 942 } 943 944 static inline void pxa2xx_rtc_swal2_tick(void *opaque) 945 { 946 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 947 s->rtsr |= (1 << 10); 948 pxa2xx_rtc_alarm_update(s, s->rtsr); 949 pxa2xx_rtc_int_update(s); 950 } 951 952 static inline void pxa2xx_rtc_pi_tick(void *opaque) 953 { 954 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 955 s->rtsr |= (1 << 13); 956 pxa2xx_rtc_piupdate(s); 957 s->last_rtcpicr = 0; 958 pxa2xx_rtc_alarm_update(s, s->rtsr); 959 pxa2xx_rtc_int_update(s); 960 } 961 962 static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr, 963 unsigned size) 964 { 965 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 966 967 switch (addr) { 968 case RTTR: 969 return s->rttr; 970 case RTSR: 971 return s->rtsr; 972 case RTAR: 973 return s->rtar; 974 case RDAR1: 975 return s->rdar1; 976 case RDAR2: 977 return s->rdar2; 978 case RYAR1: 979 return s->ryar1; 980 case RYAR2: 981 return s->ryar2; 982 case SWAR1: 983 return s->swar1; 984 case SWAR2: 985 return s->swar2; 986 case PIAR: 987 return s->piar; 988 case RCNR: 989 return s->last_rcnr + ((qemu_get_clock_ms(rtc_clock) - s->last_hz) << 15) / 990 (1000 * ((s->rttr & 0xffff) + 1)); 991 case RDCR: 992 return s->last_rdcr + ((qemu_get_clock_ms(rtc_clock) - s->last_hz) << 15) / 993 (1000 * ((s->rttr & 0xffff) + 1)); 994 case RYCR: 995 return s->last_rycr; 996 case SWCR: 997 if (s->rtsr & (1 << 12)) 998 return s->last_swcr + (qemu_get_clock_ms(rtc_clock) - s->last_sw) / 10; 999 else 1000 return s->last_swcr; 1001 default: 1002 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1003 break; 1004 } 1005 return 0; 1006 } 1007 1008 static void pxa2xx_rtc_write(void *opaque, hwaddr addr, 1009 uint64_t value64, unsigned size) 1010 { 1011 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 1012 uint32_t value = value64; 1013 1014 switch (addr) { 1015 case RTTR: 1016 if (!(s->rttr & (1 << 31))) { 1017 pxa2xx_rtc_hzupdate(s); 1018 s->rttr = value; 1019 pxa2xx_rtc_alarm_update(s, s->rtsr); 1020 } 1021 break; 1022 1023 case RTSR: 1024 if ((s->rtsr ^ value) & (1 << 15)) 1025 pxa2xx_rtc_piupdate(s); 1026 1027 if ((s->rtsr ^ value) & (1 << 12)) 1028 pxa2xx_rtc_swupdate(s); 1029 1030 if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac)) 1031 pxa2xx_rtc_alarm_update(s, value); 1032 1033 s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac)); 1034 pxa2xx_rtc_int_update(s); 1035 break; 1036 1037 case RTAR: 1038 s->rtar = value; 1039 pxa2xx_rtc_alarm_update(s, s->rtsr); 1040 break; 1041 1042 case RDAR1: 1043 s->rdar1 = value; 1044 pxa2xx_rtc_alarm_update(s, s->rtsr); 1045 break; 1046 1047 case RDAR2: 1048 s->rdar2 = value; 1049 pxa2xx_rtc_alarm_update(s, s->rtsr); 1050 break; 1051 1052 case RYAR1: 1053 s->ryar1 = value; 1054 pxa2xx_rtc_alarm_update(s, s->rtsr); 1055 break; 1056 1057 case RYAR2: 1058 s->ryar2 = value; 1059 pxa2xx_rtc_alarm_update(s, s->rtsr); 1060 break; 1061 1062 case SWAR1: 1063 pxa2xx_rtc_swupdate(s); 1064 s->swar1 = value; 1065 s->last_swcr = 0; 1066 pxa2xx_rtc_alarm_update(s, s->rtsr); 1067 break; 1068 1069 case SWAR2: 1070 s->swar2 = value; 1071 pxa2xx_rtc_alarm_update(s, s->rtsr); 1072 break; 1073 1074 case PIAR: 1075 s->piar = value; 1076 pxa2xx_rtc_alarm_update(s, s->rtsr); 1077 break; 1078 1079 case RCNR: 1080 pxa2xx_rtc_hzupdate(s); 1081 s->last_rcnr = value; 1082 pxa2xx_rtc_alarm_update(s, s->rtsr); 1083 break; 1084 1085 case RDCR: 1086 pxa2xx_rtc_hzupdate(s); 1087 s->last_rdcr = value; 1088 pxa2xx_rtc_alarm_update(s, s->rtsr); 1089 break; 1090 1091 case RYCR: 1092 s->last_rycr = value; 1093 break; 1094 1095 case SWCR: 1096 pxa2xx_rtc_swupdate(s); 1097 s->last_swcr = value; 1098 pxa2xx_rtc_alarm_update(s, s->rtsr); 1099 break; 1100 1101 case RTCPICR: 1102 pxa2xx_rtc_piupdate(s); 1103 s->last_rtcpicr = value & 0xffff; 1104 pxa2xx_rtc_alarm_update(s, s->rtsr); 1105 break; 1106 1107 default: 1108 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1109 } 1110 } 1111 1112 static const MemoryRegionOps pxa2xx_rtc_ops = { 1113 .read = pxa2xx_rtc_read, 1114 .write = pxa2xx_rtc_write, 1115 .endianness = DEVICE_NATIVE_ENDIAN, 1116 }; 1117 1118 static int pxa2xx_rtc_init(SysBusDevice *dev) 1119 { 1120 PXA2xxRTCState *s = PXA2XX_RTC(dev); 1121 struct tm tm; 1122 int wom; 1123 1124 s->rttr = 0x7fff; 1125 s->rtsr = 0; 1126 1127 qemu_get_timedate(&tm, 0); 1128 wom = ((tm.tm_mday - 1) / 7) + 1; 1129 1130 s->last_rcnr = (uint32_t) mktimegm(&tm); 1131 s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) | 1132 (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec; 1133 s->last_rycr = ((tm.tm_year + 1900) << 9) | 1134 ((tm.tm_mon + 1) << 5) | tm.tm_mday; 1135 s->last_swcr = (tm.tm_hour << 19) | 1136 (tm.tm_min << 13) | (tm.tm_sec << 7); 1137 s->last_rtcpicr = 0; 1138 s->last_hz = s->last_sw = s->last_pi = qemu_get_clock_ms(rtc_clock); 1139 1140 s->rtc_hz = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_hz_tick, s); 1141 s->rtc_rdal1 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_rdal1_tick, s); 1142 s->rtc_rdal2 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_rdal2_tick, s); 1143 s->rtc_swal1 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_swal1_tick, s); 1144 s->rtc_swal2 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_swal2_tick, s); 1145 s->rtc_pi = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_pi_tick, s); 1146 1147 sysbus_init_irq(dev, &s->rtc_irq); 1148 1149 memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_rtc_ops, s, 1150 "pxa2xx-rtc", 0x10000); 1151 sysbus_init_mmio(dev, &s->iomem); 1152 1153 return 0; 1154 } 1155 1156 static void pxa2xx_rtc_pre_save(void *opaque) 1157 { 1158 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 1159 1160 pxa2xx_rtc_hzupdate(s); 1161 pxa2xx_rtc_piupdate(s); 1162 pxa2xx_rtc_swupdate(s); 1163 } 1164 1165 static int pxa2xx_rtc_post_load(void *opaque, int version_id) 1166 { 1167 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 1168 1169 pxa2xx_rtc_alarm_update(s, s->rtsr); 1170 1171 return 0; 1172 } 1173 1174 static const VMStateDescription vmstate_pxa2xx_rtc_regs = { 1175 .name = "pxa2xx_rtc", 1176 .version_id = 0, 1177 .minimum_version_id = 0, 1178 .minimum_version_id_old = 0, 1179 .pre_save = pxa2xx_rtc_pre_save, 1180 .post_load = pxa2xx_rtc_post_load, 1181 .fields = (VMStateField[]) { 1182 VMSTATE_UINT32(rttr, PXA2xxRTCState), 1183 VMSTATE_UINT32(rtsr, PXA2xxRTCState), 1184 VMSTATE_UINT32(rtar, PXA2xxRTCState), 1185 VMSTATE_UINT32(rdar1, PXA2xxRTCState), 1186 VMSTATE_UINT32(rdar2, PXA2xxRTCState), 1187 VMSTATE_UINT32(ryar1, PXA2xxRTCState), 1188 VMSTATE_UINT32(ryar2, PXA2xxRTCState), 1189 VMSTATE_UINT32(swar1, PXA2xxRTCState), 1190 VMSTATE_UINT32(swar2, PXA2xxRTCState), 1191 VMSTATE_UINT32(piar, PXA2xxRTCState), 1192 VMSTATE_UINT32(last_rcnr, PXA2xxRTCState), 1193 VMSTATE_UINT32(last_rdcr, PXA2xxRTCState), 1194 VMSTATE_UINT32(last_rycr, PXA2xxRTCState), 1195 VMSTATE_UINT32(last_swcr, PXA2xxRTCState), 1196 VMSTATE_UINT32(last_rtcpicr, PXA2xxRTCState), 1197 VMSTATE_INT64(last_hz, PXA2xxRTCState), 1198 VMSTATE_INT64(last_sw, PXA2xxRTCState), 1199 VMSTATE_INT64(last_pi, PXA2xxRTCState), 1200 VMSTATE_END_OF_LIST(), 1201 }, 1202 }; 1203 1204 static void pxa2xx_rtc_sysbus_class_init(ObjectClass *klass, void *data) 1205 { 1206 DeviceClass *dc = DEVICE_CLASS(klass); 1207 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 1208 1209 k->init = pxa2xx_rtc_init; 1210 dc->desc = "PXA2xx RTC Controller"; 1211 dc->vmsd = &vmstate_pxa2xx_rtc_regs; 1212 } 1213 1214 static const TypeInfo pxa2xx_rtc_sysbus_info = { 1215 .name = TYPE_PXA2XX_RTC, 1216 .parent = TYPE_SYS_BUS_DEVICE, 1217 .instance_size = sizeof(PXA2xxRTCState), 1218 .class_init = pxa2xx_rtc_sysbus_class_init, 1219 }; 1220 1221 /* I2C Interface */ 1222 typedef struct { 1223 I2CSlave i2c; 1224 PXA2xxI2CState *host; 1225 } PXA2xxI2CSlaveState; 1226 1227 #define TYPE_PXA2XX_I2C "pxa2xx_i2c" 1228 #define PXA2XX_I2C(obj) \ 1229 OBJECT_CHECK(PXA2xxI2CState, (obj), TYPE_PXA2XX_I2C) 1230 1231 struct PXA2xxI2CState { 1232 /*< private >*/ 1233 SysBusDevice parent_obj; 1234 /*< public >*/ 1235 1236 MemoryRegion iomem; 1237 PXA2xxI2CSlaveState *slave; 1238 i2c_bus *bus; 1239 qemu_irq irq; 1240 uint32_t offset; 1241 uint32_t region_size; 1242 1243 uint16_t control; 1244 uint16_t status; 1245 uint8_t ibmr; 1246 uint8_t data; 1247 }; 1248 1249 #define IBMR 0x80 /* I2C Bus Monitor register */ 1250 #define IDBR 0x88 /* I2C Data Buffer register */ 1251 #define ICR 0x90 /* I2C Control register */ 1252 #define ISR 0x98 /* I2C Status register */ 1253 #define ISAR 0xa0 /* I2C Slave Address register */ 1254 1255 static void pxa2xx_i2c_update(PXA2xxI2CState *s) 1256 { 1257 uint16_t level = 0; 1258 level |= s->status & s->control & (1 << 10); /* BED */ 1259 level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */ 1260 level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */ 1261 level |= s->status & (1 << 9); /* SAD */ 1262 qemu_set_irq(s->irq, !!level); 1263 } 1264 1265 /* These are only stubs now. */ 1266 static void pxa2xx_i2c_event(I2CSlave *i2c, enum i2c_event event) 1267 { 1268 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c); 1269 PXA2xxI2CState *s = slave->host; 1270 1271 switch (event) { 1272 case I2C_START_SEND: 1273 s->status |= (1 << 9); /* set SAD */ 1274 s->status &= ~(1 << 0); /* clear RWM */ 1275 break; 1276 case I2C_START_RECV: 1277 s->status |= (1 << 9); /* set SAD */ 1278 s->status |= 1 << 0; /* set RWM */ 1279 break; 1280 case I2C_FINISH: 1281 s->status |= (1 << 4); /* set SSD */ 1282 break; 1283 case I2C_NACK: 1284 s->status |= 1 << 1; /* set ACKNAK */ 1285 break; 1286 } 1287 pxa2xx_i2c_update(s); 1288 } 1289 1290 static int pxa2xx_i2c_rx(I2CSlave *i2c) 1291 { 1292 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c); 1293 PXA2xxI2CState *s = slave->host; 1294 if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) 1295 return 0; 1296 1297 if (s->status & (1 << 0)) { /* RWM */ 1298 s->status |= 1 << 6; /* set ITE */ 1299 } 1300 pxa2xx_i2c_update(s); 1301 1302 return s->data; 1303 } 1304 1305 static int pxa2xx_i2c_tx(I2CSlave *i2c, uint8_t data) 1306 { 1307 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c); 1308 PXA2xxI2CState *s = slave->host; 1309 if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) 1310 return 1; 1311 1312 if (!(s->status & (1 << 0))) { /* RWM */ 1313 s->status |= 1 << 7; /* set IRF */ 1314 s->data = data; 1315 } 1316 pxa2xx_i2c_update(s); 1317 1318 return 1; 1319 } 1320 1321 static uint64_t pxa2xx_i2c_read(void *opaque, hwaddr addr, 1322 unsigned size) 1323 { 1324 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; 1325 1326 addr -= s->offset; 1327 switch (addr) { 1328 case ICR: 1329 return s->control; 1330 case ISR: 1331 return s->status | (i2c_bus_busy(s->bus) << 2); 1332 case ISAR: 1333 return s->slave->i2c.address; 1334 case IDBR: 1335 return s->data; 1336 case IBMR: 1337 if (s->status & (1 << 2)) 1338 s->ibmr ^= 3; /* Fake SCL and SDA pin changes */ 1339 else 1340 s->ibmr = 0; 1341 return s->ibmr; 1342 default: 1343 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1344 break; 1345 } 1346 return 0; 1347 } 1348 1349 static void pxa2xx_i2c_write(void *opaque, hwaddr addr, 1350 uint64_t value64, unsigned size) 1351 { 1352 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; 1353 uint32_t value = value64; 1354 int ack; 1355 1356 addr -= s->offset; 1357 switch (addr) { 1358 case ICR: 1359 s->control = value & 0xfff7; 1360 if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */ 1361 /* TODO: slave mode */ 1362 if (value & (1 << 0)) { /* START condition */ 1363 if (s->data & 1) 1364 s->status |= 1 << 0; /* set RWM */ 1365 else 1366 s->status &= ~(1 << 0); /* clear RWM */ 1367 ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1); 1368 } else { 1369 if (s->status & (1 << 0)) { /* RWM */ 1370 s->data = i2c_recv(s->bus); 1371 if (value & (1 << 2)) /* ACKNAK */ 1372 i2c_nack(s->bus); 1373 ack = 1; 1374 } else 1375 ack = !i2c_send(s->bus, s->data); 1376 } 1377 1378 if (value & (1 << 1)) /* STOP condition */ 1379 i2c_end_transfer(s->bus); 1380 1381 if (ack) { 1382 if (value & (1 << 0)) /* START condition */ 1383 s->status |= 1 << 6; /* set ITE */ 1384 else 1385 if (s->status & (1 << 0)) /* RWM */ 1386 s->status |= 1 << 7; /* set IRF */ 1387 else 1388 s->status |= 1 << 6; /* set ITE */ 1389 s->status &= ~(1 << 1); /* clear ACKNAK */ 1390 } else { 1391 s->status |= 1 << 6; /* set ITE */ 1392 s->status |= 1 << 10; /* set BED */ 1393 s->status |= 1 << 1; /* set ACKNAK */ 1394 } 1395 } 1396 if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */ 1397 if (value & (1 << 4)) /* MA */ 1398 i2c_end_transfer(s->bus); 1399 pxa2xx_i2c_update(s); 1400 break; 1401 1402 case ISR: 1403 s->status &= ~(value & 0x07f0); 1404 pxa2xx_i2c_update(s); 1405 break; 1406 1407 case ISAR: 1408 i2c_set_slave_address(&s->slave->i2c, value & 0x7f); 1409 break; 1410 1411 case IDBR: 1412 s->data = value & 0xff; 1413 break; 1414 1415 default: 1416 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1417 } 1418 } 1419 1420 static const MemoryRegionOps pxa2xx_i2c_ops = { 1421 .read = pxa2xx_i2c_read, 1422 .write = pxa2xx_i2c_write, 1423 .endianness = DEVICE_NATIVE_ENDIAN, 1424 }; 1425 1426 static const VMStateDescription vmstate_pxa2xx_i2c_slave = { 1427 .name = "pxa2xx_i2c_slave", 1428 .version_id = 1, 1429 .minimum_version_id = 1, 1430 .minimum_version_id_old = 1, 1431 .fields = (VMStateField []) { 1432 VMSTATE_I2C_SLAVE(i2c, PXA2xxI2CSlaveState), 1433 VMSTATE_END_OF_LIST() 1434 } 1435 }; 1436 1437 static const VMStateDescription vmstate_pxa2xx_i2c = { 1438 .name = "pxa2xx_i2c", 1439 .version_id = 1, 1440 .minimum_version_id = 1, 1441 .minimum_version_id_old = 1, 1442 .fields = (VMStateField []) { 1443 VMSTATE_UINT16(control, PXA2xxI2CState), 1444 VMSTATE_UINT16(status, PXA2xxI2CState), 1445 VMSTATE_UINT8(ibmr, PXA2xxI2CState), 1446 VMSTATE_UINT8(data, PXA2xxI2CState), 1447 VMSTATE_STRUCT_POINTER(slave, PXA2xxI2CState, 1448 vmstate_pxa2xx_i2c_slave, PXA2xxI2CSlaveState *), 1449 VMSTATE_END_OF_LIST() 1450 } 1451 }; 1452 1453 static int pxa2xx_i2c_slave_init(I2CSlave *i2c) 1454 { 1455 /* Nothing to do. */ 1456 return 0; 1457 } 1458 1459 static void pxa2xx_i2c_slave_class_init(ObjectClass *klass, void *data) 1460 { 1461 I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); 1462 1463 k->init = pxa2xx_i2c_slave_init; 1464 k->event = pxa2xx_i2c_event; 1465 k->recv = pxa2xx_i2c_rx; 1466 k->send = pxa2xx_i2c_tx; 1467 } 1468 1469 static const TypeInfo pxa2xx_i2c_slave_info = { 1470 .name = "pxa2xx-i2c-slave", 1471 .parent = TYPE_I2C_SLAVE, 1472 .instance_size = sizeof(PXA2xxI2CSlaveState), 1473 .class_init = pxa2xx_i2c_slave_class_init, 1474 }; 1475 1476 PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base, 1477 qemu_irq irq, uint32_t region_size) 1478 { 1479 DeviceState *dev; 1480 SysBusDevice *i2c_dev; 1481 PXA2xxI2CState *s; 1482 1483 dev = qdev_create(NULL, TYPE_PXA2XX_I2C); 1484 qdev_prop_set_uint32(dev, "size", region_size + 1); 1485 qdev_prop_set_uint32(dev, "offset", base & region_size); 1486 qdev_init_nofail(dev); 1487 1488 i2c_dev = SYS_BUS_DEVICE(dev); 1489 sysbus_mmio_map(i2c_dev, 0, base & ~region_size); 1490 sysbus_connect_irq(i2c_dev, 0, irq); 1491 1492 s = PXA2XX_I2C(i2c_dev); 1493 /* FIXME: Should the slave device really be on a separate bus? */ 1494 dev = i2c_create_slave(i2c_init_bus(NULL, "dummy"), "pxa2xx-i2c-slave", 0); 1495 s->slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, I2C_SLAVE(dev)); 1496 s->slave->host = s; 1497 1498 return s; 1499 } 1500 1501 static int pxa2xx_i2c_initfn(SysBusDevice *sbd) 1502 { 1503 DeviceState *dev = DEVICE(sbd); 1504 PXA2xxI2CState *s = PXA2XX_I2C(dev); 1505 1506 s->bus = i2c_init_bus(dev, "i2c"); 1507 1508 memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_i2c_ops, s, 1509 "pxa2xx-i2c", s->region_size); 1510 sysbus_init_mmio(sbd, &s->iomem); 1511 sysbus_init_irq(sbd, &s->irq); 1512 1513 return 0; 1514 } 1515 1516 i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s) 1517 { 1518 return s->bus; 1519 } 1520 1521 static Property pxa2xx_i2c_properties[] = { 1522 DEFINE_PROP_UINT32("size", PXA2xxI2CState, region_size, 0x10000), 1523 DEFINE_PROP_UINT32("offset", PXA2xxI2CState, offset, 0), 1524 DEFINE_PROP_END_OF_LIST(), 1525 }; 1526 1527 static void pxa2xx_i2c_class_init(ObjectClass *klass, void *data) 1528 { 1529 DeviceClass *dc = DEVICE_CLASS(klass); 1530 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 1531 1532 k->init = pxa2xx_i2c_initfn; 1533 dc->desc = "PXA2xx I2C Bus Controller"; 1534 dc->vmsd = &vmstate_pxa2xx_i2c; 1535 dc->props = pxa2xx_i2c_properties; 1536 } 1537 1538 static const TypeInfo pxa2xx_i2c_info = { 1539 .name = TYPE_PXA2XX_I2C, 1540 .parent = TYPE_SYS_BUS_DEVICE, 1541 .instance_size = sizeof(PXA2xxI2CState), 1542 .class_init = pxa2xx_i2c_class_init, 1543 }; 1544 1545 /* PXA Inter-IC Sound Controller */ 1546 static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s) 1547 { 1548 i2s->rx_len = 0; 1549 i2s->tx_len = 0; 1550 i2s->fifo_len = 0; 1551 i2s->clk = 0x1a; 1552 i2s->control[0] = 0x00; 1553 i2s->control[1] = 0x00; 1554 i2s->status = 0x00; 1555 i2s->mask = 0x00; 1556 } 1557 1558 #define SACR_TFTH(val) ((val >> 8) & 0xf) 1559 #define SACR_RFTH(val) ((val >> 12) & 0xf) 1560 #define SACR_DREC(val) (val & (1 << 3)) 1561 #define SACR_DPRL(val) (val & (1 << 4)) 1562 1563 static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s) 1564 { 1565 int rfs, tfs; 1566 rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len && 1567 !SACR_DREC(i2s->control[1]); 1568 tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) && 1569 i2s->enable && !SACR_DPRL(i2s->control[1]); 1570 1571 qemu_set_irq(i2s->rx_dma, rfs); 1572 qemu_set_irq(i2s->tx_dma, tfs); 1573 1574 i2s->status &= 0xe0; 1575 if (i2s->fifo_len < 16 || !i2s->enable) 1576 i2s->status |= 1 << 0; /* TNF */ 1577 if (i2s->rx_len) 1578 i2s->status |= 1 << 1; /* RNE */ 1579 if (i2s->enable) 1580 i2s->status |= 1 << 2; /* BSY */ 1581 if (tfs) 1582 i2s->status |= 1 << 3; /* TFS */ 1583 if (rfs) 1584 i2s->status |= 1 << 4; /* RFS */ 1585 if (!(i2s->tx_len && i2s->enable)) 1586 i2s->status |= i2s->fifo_len << 8; /* TFL */ 1587 i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */ 1588 1589 qemu_set_irq(i2s->irq, i2s->status & i2s->mask); 1590 } 1591 1592 #define SACR0 0x00 /* Serial Audio Global Control register */ 1593 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */ 1594 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */ 1595 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */ 1596 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */ 1597 #define SADIV 0x60 /* Serial Audio Clock Divider register */ 1598 #define SADR 0x80 /* Serial Audio Data register */ 1599 1600 static uint64_t pxa2xx_i2s_read(void *opaque, hwaddr addr, 1601 unsigned size) 1602 { 1603 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; 1604 1605 switch (addr) { 1606 case SACR0: 1607 return s->control[0]; 1608 case SACR1: 1609 return s->control[1]; 1610 case SASR0: 1611 return s->status; 1612 case SAIMR: 1613 return s->mask; 1614 case SAICR: 1615 return 0; 1616 case SADIV: 1617 return s->clk; 1618 case SADR: 1619 if (s->rx_len > 0) { 1620 s->rx_len --; 1621 pxa2xx_i2s_update(s); 1622 return s->codec_in(s->opaque); 1623 } 1624 return 0; 1625 default: 1626 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1627 break; 1628 } 1629 return 0; 1630 } 1631 1632 static void pxa2xx_i2s_write(void *opaque, hwaddr addr, 1633 uint64_t value, unsigned size) 1634 { 1635 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; 1636 uint32_t *sample; 1637 1638 switch (addr) { 1639 case SACR0: 1640 if (value & (1 << 3)) /* RST */ 1641 pxa2xx_i2s_reset(s); 1642 s->control[0] = value & 0xff3d; 1643 if (!s->enable && (value & 1) && s->tx_len) { /* ENB */ 1644 for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++) 1645 s->codec_out(s->opaque, *sample); 1646 s->status &= ~(1 << 7); /* I2SOFF */ 1647 } 1648 if (value & (1 << 4)) /* EFWR */ 1649 printf("%s: Attempt to use special function\n", __FUNCTION__); 1650 s->enable = (value & 9) == 1; /* ENB && !RST*/ 1651 pxa2xx_i2s_update(s); 1652 break; 1653 case SACR1: 1654 s->control[1] = value & 0x0039; 1655 if (value & (1 << 5)) /* ENLBF */ 1656 printf("%s: Attempt to use loopback function\n", __FUNCTION__); 1657 if (value & (1 << 4)) /* DPRL */ 1658 s->fifo_len = 0; 1659 pxa2xx_i2s_update(s); 1660 break; 1661 case SAIMR: 1662 s->mask = value & 0x0078; 1663 pxa2xx_i2s_update(s); 1664 break; 1665 case SAICR: 1666 s->status &= ~(value & (3 << 5)); 1667 pxa2xx_i2s_update(s); 1668 break; 1669 case SADIV: 1670 s->clk = value & 0x007f; 1671 break; 1672 case SADR: 1673 if (s->tx_len && s->enable) { 1674 s->tx_len --; 1675 pxa2xx_i2s_update(s); 1676 s->codec_out(s->opaque, value); 1677 } else if (s->fifo_len < 16) { 1678 s->fifo[s->fifo_len ++] = value; 1679 pxa2xx_i2s_update(s); 1680 } 1681 break; 1682 default: 1683 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1684 } 1685 } 1686 1687 static const MemoryRegionOps pxa2xx_i2s_ops = { 1688 .read = pxa2xx_i2s_read, 1689 .write = pxa2xx_i2s_write, 1690 .endianness = DEVICE_NATIVE_ENDIAN, 1691 }; 1692 1693 static const VMStateDescription vmstate_pxa2xx_i2s = { 1694 .name = "pxa2xx_i2s", 1695 .version_id = 0, 1696 .minimum_version_id = 0, 1697 .minimum_version_id_old = 0, 1698 .fields = (VMStateField[]) { 1699 VMSTATE_UINT32_ARRAY(control, PXA2xxI2SState, 2), 1700 VMSTATE_UINT32(status, PXA2xxI2SState), 1701 VMSTATE_UINT32(mask, PXA2xxI2SState), 1702 VMSTATE_UINT32(clk, PXA2xxI2SState), 1703 VMSTATE_INT32(enable, PXA2xxI2SState), 1704 VMSTATE_INT32(rx_len, PXA2xxI2SState), 1705 VMSTATE_INT32(tx_len, PXA2xxI2SState), 1706 VMSTATE_INT32(fifo_len, PXA2xxI2SState), 1707 VMSTATE_END_OF_LIST() 1708 } 1709 }; 1710 1711 static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx) 1712 { 1713 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; 1714 uint32_t *sample; 1715 1716 /* Signal FIFO errors */ 1717 if (s->enable && s->tx_len) 1718 s->status |= 1 << 5; /* TUR */ 1719 if (s->enable && s->rx_len) 1720 s->status |= 1 << 6; /* ROR */ 1721 1722 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to 1723 * handle the cases where it makes a difference. */ 1724 s->tx_len = tx - s->fifo_len; 1725 s->rx_len = rx; 1726 /* Note that is s->codec_out wasn't set, we wouldn't get called. */ 1727 if (s->enable) 1728 for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++) 1729 s->codec_out(s->opaque, *sample); 1730 pxa2xx_i2s_update(s); 1731 } 1732 1733 static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem, 1734 hwaddr base, 1735 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma) 1736 { 1737 PXA2xxI2SState *s = (PXA2xxI2SState *) 1738 g_malloc0(sizeof(PXA2xxI2SState)); 1739 1740 s->irq = irq; 1741 s->rx_dma = rx_dma; 1742 s->tx_dma = tx_dma; 1743 s->data_req = pxa2xx_i2s_data_req; 1744 1745 pxa2xx_i2s_reset(s); 1746 1747 memory_region_init_io(&s->iomem, NULL, &pxa2xx_i2s_ops, s, 1748 "pxa2xx-i2s", 0x100000); 1749 memory_region_add_subregion(sysmem, base, &s->iomem); 1750 1751 vmstate_register(NULL, base, &vmstate_pxa2xx_i2s, s); 1752 1753 return s; 1754 } 1755 1756 /* PXA Fast Infra-red Communications Port */ 1757 struct PXA2xxFIrState { 1758 MemoryRegion iomem; 1759 qemu_irq irq; 1760 qemu_irq rx_dma; 1761 qemu_irq tx_dma; 1762 int enable; 1763 CharDriverState *chr; 1764 1765 uint8_t control[3]; 1766 uint8_t status[2]; 1767 1768 int rx_len; 1769 int rx_start; 1770 uint8_t rx_fifo[64]; 1771 }; 1772 1773 static void pxa2xx_fir_reset(PXA2xxFIrState *s) 1774 { 1775 s->control[0] = 0x00; 1776 s->control[1] = 0x00; 1777 s->control[2] = 0x00; 1778 s->status[0] = 0x00; 1779 s->status[1] = 0x00; 1780 s->enable = 0; 1781 } 1782 1783 static inline void pxa2xx_fir_update(PXA2xxFIrState *s) 1784 { 1785 static const int tresh[4] = { 8, 16, 32, 0 }; 1786 int intr = 0; 1787 if ((s->control[0] & (1 << 4)) && /* RXE */ 1788 s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */ 1789 s->status[0] |= 1 << 4; /* RFS */ 1790 else 1791 s->status[0] &= ~(1 << 4); /* RFS */ 1792 if (s->control[0] & (1 << 3)) /* TXE */ 1793 s->status[0] |= 1 << 3; /* TFS */ 1794 else 1795 s->status[0] &= ~(1 << 3); /* TFS */ 1796 if (s->rx_len) 1797 s->status[1] |= 1 << 2; /* RNE */ 1798 else 1799 s->status[1] &= ~(1 << 2); /* RNE */ 1800 if (s->control[0] & (1 << 4)) /* RXE */ 1801 s->status[1] |= 1 << 0; /* RSY */ 1802 else 1803 s->status[1] &= ~(1 << 0); /* RSY */ 1804 1805 intr |= (s->control[0] & (1 << 5)) && /* RIE */ 1806 (s->status[0] & (1 << 4)); /* RFS */ 1807 intr |= (s->control[0] & (1 << 6)) && /* TIE */ 1808 (s->status[0] & (1 << 3)); /* TFS */ 1809 intr |= (s->control[2] & (1 << 4)) && /* TRAIL */ 1810 (s->status[0] & (1 << 6)); /* EOC */ 1811 intr |= (s->control[0] & (1 << 2)) && /* TUS */ 1812 (s->status[0] & (1 << 1)); /* TUR */ 1813 intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */ 1814 1815 qemu_set_irq(s->rx_dma, (s->status[0] >> 4) & 1); 1816 qemu_set_irq(s->tx_dma, (s->status[0] >> 3) & 1); 1817 1818 qemu_set_irq(s->irq, intr && s->enable); 1819 } 1820 1821 #define ICCR0 0x00 /* FICP Control register 0 */ 1822 #define ICCR1 0x04 /* FICP Control register 1 */ 1823 #define ICCR2 0x08 /* FICP Control register 2 */ 1824 #define ICDR 0x0c /* FICP Data register */ 1825 #define ICSR0 0x14 /* FICP Status register 0 */ 1826 #define ICSR1 0x18 /* FICP Status register 1 */ 1827 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */ 1828 1829 static uint64_t pxa2xx_fir_read(void *opaque, hwaddr addr, 1830 unsigned size) 1831 { 1832 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1833 uint8_t ret; 1834 1835 switch (addr) { 1836 case ICCR0: 1837 return s->control[0]; 1838 case ICCR1: 1839 return s->control[1]; 1840 case ICCR2: 1841 return s->control[2]; 1842 case ICDR: 1843 s->status[0] &= ~0x01; 1844 s->status[1] &= ~0x72; 1845 if (s->rx_len) { 1846 s->rx_len --; 1847 ret = s->rx_fifo[s->rx_start ++]; 1848 s->rx_start &= 63; 1849 pxa2xx_fir_update(s); 1850 return ret; 1851 } 1852 printf("%s: Rx FIFO underrun.\n", __FUNCTION__); 1853 break; 1854 case ICSR0: 1855 return s->status[0]; 1856 case ICSR1: 1857 return s->status[1] | (1 << 3); /* TNF */ 1858 case ICFOR: 1859 return s->rx_len; 1860 default: 1861 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1862 break; 1863 } 1864 return 0; 1865 } 1866 1867 static void pxa2xx_fir_write(void *opaque, hwaddr addr, 1868 uint64_t value64, unsigned size) 1869 { 1870 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1871 uint32_t value = value64; 1872 uint8_t ch; 1873 1874 switch (addr) { 1875 case ICCR0: 1876 s->control[0] = value; 1877 if (!(value & (1 << 4))) /* RXE */ 1878 s->rx_len = s->rx_start = 0; 1879 if (!(value & (1 << 3))) { /* TXE */ 1880 /* Nop */ 1881 } 1882 s->enable = value & 1; /* ITR */ 1883 if (!s->enable) 1884 s->status[0] = 0; 1885 pxa2xx_fir_update(s); 1886 break; 1887 case ICCR1: 1888 s->control[1] = value; 1889 break; 1890 case ICCR2: 1891 s->control[2] = value & 0x3f; 1892 pxa2xx_fir_update(s); 1893 break; 1894 case ICDR: 1895 if (s->control[2] & (1 << 2)) /* TXP */ 1896 ch = value; 1897 else 1898 ch = ~value; 1899 if (s->chr && s->enable && (s->control[0] & (1 << 3))) /* TXE */ 1900 qemu_chr_fe_write(s->chr, &ch, 1); 1901 break; 1902 case ICSR0: 1903 s->status[0] &= ~(value & 0x66); 1904 pxa2xx_fir_update(s); 1905 break; 1906 case ICFOR: 1907 break; 1908 default: 1909 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1910 } 1911 } 1912 1913 static const MemoryRegionOps pxa2xx_fir_ops = { 1914 .read = pxa2xx_fir_read, 1915 .write = pxa2xx_fir_write, 1916 .endianness = DEVICE_NATIVE_ENDIAN, 1917 }; 1918 1919 static int pxa2xx_fir_is_empty(void *opaque) 1920 { 1921 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1922 return (s->rx_len < 64); 1923 } 1924 1925 static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size) 1926 { 1927 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1928 if (!(s->control[0] & (1 << 4))) /* RXE */ 1929 return; 1930 1931 while (size --) { 1932 s->status[1] |= 1 << 4; /* EOF */ 1933 if (s->rx_len >= 64) { 1934 s->status[1] |= 1 << 6; /* ROR */ 1935 break; 1936 } 1937 1938 if (s->control[2] & (1 << 3)) /* RXP */ 1939 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++); 1940 else 1941 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++); 1942 } 1943 1944 pxa2xx_fir_update(s); 1945 } 1946 1947 static void pxa2xx_fir_event(void *opaque, int event) 1948 { 1949 } 1950 1951 static void pxa2xx_fir_save(QEMUFile *f, void *opaque) 1952 { 1953 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1954 int i; 1955 1956 qemu_put_be32(f, s->enable); 1957 1958 qemu_put_8s(f, &s->control[0]); 1959 qemu_put_8s(f, &s->control[1]); 1960 qemu_put_8s(f, &s->control[2]); 1961 qemu_put_8s(f, &s->status[0]); 1962 qemu_put_8s(f, &s->status[1]); 1963 1964 qemu_put_byte(f, s->rx_len); 1965 for (i = 0; i < s->rx_len; i ++) 1966 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 63]); 1967 } 1968 1969 static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id) 1970 { 1971 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1972 int i; 1973 1974 s->enable = qemu_get_be32(f); 1975 1976 qemu_get_8s(f, &s->control[0]); 1977 qemu_get_8s(f, &s->control[1]); 1978 qemu_get_8s(f, &s->control[2]); 1979 qemu_get_8s(f, &s->status[0]); 1980 qemu_get_8s(f, &s->status[1]); 1981 1982 s->rx_len = qemu_get_byte(f); 1983 s->rx_start = 0; 1984 for (i = 0; i < s->rx_len; i ++) 1985 s->rx_fifo[i] = qemu_get_byte(f); 1986 1987 return 0; 1988 } 1989 1990 static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem, 1991 hwaddr base, 1992 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma, 1993 CharDriverState *chr) 1994 { 1995 PXA2xxFIrState *s = (PXA2xxFIrState *) 1996 g_malloc0(sizeof(PXA2xxFIrState)); 1997 1998 s->irq = irq; 1999 s->rx_dma = rx_dma; 2000 s->tx_dma = tx_dma; 2001 s->chr = chr; 2002 2003 pxa2xx_fir_reset(s); 2004 2005 memory_region_init_io(&s->iomem, NULL, &pxa2xx_fir_ops, s, "pxa2xx-fir", 0x1000); 2006 memory_region_add_subregion(sysmem, base, &s->iomem); 2007 2008 if (chr) { 2009 qemu_chr_fe_claim_no_fail(chr); 2010 qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty, 2011 pxa2xx_fir_rx, pxa2xx_fir_event, s); 2012 } 2013 2014 register_savevm(NULL, "pxa2xx_fir", 0, 0, pxa2xx_fir_save, 2015 pxa2xx_fir_load, s); 2016 2017 return s; 2018 } 2019 2020 static void pxa2xx_reset(void *opaque, int line, int level) 2021 { 2022 PXA2xxState *s = (PXA2xxState *) opaque; 2023 2024 if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */ 2025 cpu_reset(CPU(s->cpu)); 2026 /* TODO: reset peripherals */ 2027 } 2028 } 2029 2030 /* Initialise a PXA270 integrated chip (ARM based core). */ 2031 PXA2xxState *pxa270_init(MemoryRegion *address_space, 2032 unsigned int sdram_size, const char *revision) 2033 { 2034 PXA2xxState *s; 2035 int i; 2036 DriveInfo *dinfo; 2037 s = (PXA2xxState *) g_malloc0(sizeof(PXA2xxState)); 2038 2039 if (revision && strncmp(revision, "pxa27", 5)) { 2040 fprintf(stderr, "Machine requires a PXA27x processor.\n"); 2041 exit(1); 2042 } 2043 if (!revision) 2044 revision = "pxa270"; 2045 2046 s->cpu = cpu_arm_init(revision); 2047 if (s->cpu == NULL) { 2048 fprintf(stderr, "Unable to find CPU definition\n"); 2049 exit(1); 2050 } 2051 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0]; 2052 2053 /* SDRAM & Internal Memory Storage */ 2054 memory_region_init_ram(&s->sdram, NULL, "pxa270.sdram", sdram_size); 2055 vmstate_register_ram_global(&s->sdram); 2056 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram); 2057 memory_region_init_ram(&s->internal, NULL, "pxa270.internal", 0x40000); 2058 vmstate_register_ram_global(&s->internal); 2059 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE, 2060 &s->internal); 2061 2062 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu); 2063 2064 s->dma = pxa27x_dma_init(0x40000000, 2065 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA)); 2066 2067 sysbus_create_varargs("pxa27x-timer", 0x40a00000, 2068 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0), 2069 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1), 2070 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2), 2071 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3), 2072 qdev_get_gpio_in(s->pic, PXA27X_PIC_OST_4_11), 2073 NULL); 2074 2075 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 121); 2076 2077 dinfo = drive_get(IF_SD, 0, 0); 2078 if (!dinfo) { 2079 fprintf(stderr, "qemu: missing SecureDigital device\n"); 2080 exit(1); 2081 } 2082 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, dinfo->bdrv, 2083 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), 2084 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), 2085 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); 2086 2087 for (i = 0; pxa270_serial[i].io_base; i++) { 2088 if (serial_hds[i]) { 2089 serial_mm_init(address_space, pxa270_serial[i].io_base, 2, 2090 qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn), 2091 14857000 / 16, serial_hds[i], 2092 DEVICE_NATIVE_ENDIAN); 2093 } else { 2094 break; 2095 } 2096 } 2097 if (serial_hds[i]) 2098 s->fir = pxa2xx_fir_init(address_space, 0x40800000, 2099 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), 2100 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), 2101 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), 2102 serial_hds[i]); 2103 2104 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000, 2105 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); 2106 2107 s->cm_base = 0x41300000; 2108 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */ 2109 s->clkcfg = 0x00000009; /* Turbo mode active */ 2110 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000); 2111 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); 2112 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); 2113 2114 pxa2xx_setup_cp14(s); 2115 2116 s->mm_base = 0x48000000; 2117 s->mm_regs[MDMRS >> 2] = 0x00020002; 2118 s->mm_regs[MDREFR >> 2] = 0x03ca4000; 2119 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ 2120 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000); 2121 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem); 2122 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s); 2123 2124 s->pm_base = 0x40f00000; 2125 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100); 2126 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem); 2127 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s); 2128 2129 for (i = 0; pxa27x_ssp[i].io_base; i ++); 2130 s->ssp = (SSIBus **)g_malloc0(sizeof(SSIBus *) * i); 2131 for (i = 0; pxa27x_ssp[i].io_base; i ++) { 2132 DeviceState *dev; 2133 dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa27x_ssp[i].io_base, 2134 qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn)); 2135 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi"); 2136 } 2137 2138 if (usb_enabled(false)) { 2139 sysbus_create_simple("sysbus-ohci", 0x4c000000, 2140 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1)); 2141 } 2142 2143 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000); 2144 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000); 2145 2146 sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000, 2147 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM)); 2148 2149 s->i2c[0] = pxa2xx_i2c_init(0x40301600, 2150 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff); 2151 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, 2152 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff); 2153 2154 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000, 2155 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), 2156 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), 2157 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); 2158 2159 s->kp = pxa27x_keypad_init(address_space, 0x41500000, 2160 qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD)); 2161 2162 /* GPIO1 resets the processor */ 2163 /* The handler can be overridden by board-specific code */ 2164 qdev_connect_gpio_out(s->gpio, 1, s->reset); 2165 return s; 2166 } 2167 2168 /* Initialise a PXA255 integrated chip (ARM based core). */ 2169 PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size) 2170 { 2171 PXA2xxState *s; 2172 int i; 2173 DriveInfo *dinfo; 2174 2175 s = (PXA2xxState *) g_malloc0(sizeof(PXA2xxState)); 2176 2177 s->cpu = cpu_arm_init("pxa255"); 2178 if (s->cpu == NULL) { 2179 fprintf(stderr, "Unable to find CPU definition\n"); 2180 exit(1); 2181 } 2182 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0]; 2183 2184 /* SDRAM & Internal Memory Storage */ 2185 memory_region_init_ram(&s->sdram, NULL, "pxa255.sdram", sdram_size); 2186 vmstate_register_ram_global(&s->sdram); 2187 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram); 2188 memory_region_init_ram(&s->internal, NULL, "pxa255.internal", 2189 PXA2XX_INTERNAL_SIZE); 2190 vmstate_register_ram_global(&s->internal); 2191 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE, 2192 &s->internal); 2193 2194 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu); 2195 2196 s->dma = pxa255_dma_init(0x40000000, 2197 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA)); 2198 2199 sysbus_create_varargs("pxa25x-timer", 0x40a00000, 2200 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0), 2201 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1), 2202 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2), 2203 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3), 2204 NULL); 2205 2206 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 85); 2207 2208 dinfo = drive_get(IF_SD, 0, 0); 2209 if (!dinfo) { 2210 fprintf(stderr, "qemu: missing SecureDigital device\n"); 2211 exit(1); 2212 } 2213 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, dinfo->bdrv, 2214 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), 2215 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), 2216 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); 2217 2218 for (i = 0; pxa255_serial[i].io_base; i++) { 2219 if (serial_hds[i]) { 2220 serial_mm_init(address_space, pxa255_serial[i].io_base, 2, 2221 qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn), 2222 14745600 / 16, serial_hds[i], 2223 DEVICE_NATIVE_ENDIAN); 2224 } else { 2225 break; 2226 } 2227 } 2228 if (serial_hds[i]) 2229 s->fir = pxa2xx_fir_init(address_space, 0x40800000, 2230 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), 2231 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), 2232 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), 2233 serial_hds[i]); 2234 2235 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000, 2236 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); 2237 2238 s->cm_base = 0x41300000; 2239 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */ 2240 s->clkcfg = 0x00000009; /* Turbo mode active */ 2241 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000); 2242 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); 2243 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); 2244 2245 pxa2xx_setup_cp14(s); 2246 2247 s->mm_base = 0x48000000; 2248 s->mm_regs[MDMRS >> 2] = 0x00020002; 2249 s->mm_regs[MDREFR >> 2] = 0x03ca4000; 2250 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ 2251 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000); 2252 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem); 2253 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s); 2254 2255 s->pm_base = 0x40f00000; 2256 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100); 2257 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem); 2258 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s); 2259 2260 for (i = 0; pxa255_ssp[i].io_base; i ++); 2261 s->ssp = (SSIBus **)g_malloc0(sizeof(SSIBus *) * i); 2262 for (i = 0; pxa255_ssp[i].io_base; i ++) { 2263 DeviceState *dev; 2264 dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa255_ssp[i].io_base, 2265 qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn)); 2266 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi"); 2267 } 2268 2269 if (usb_enabled(false)) { 2270 sysbus_create_simple("sysbus-ohci", 0x4c000000, 2271 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1)); 2272 } 2273 2274 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000); 2275 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000); 2276 2277 sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000, 2278 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM)); 2279 2280 s->i2c[0] = pxa2xx_i2c_init(0x40301600, 2281 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff); 2282 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, 2283 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff); 2284 2285 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000, 2286 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), 2287 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), 2288 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); 2289 2290 /* GPIO1 resets the processor */ 2291 /* The handler can be overridden by board-specific code */ 2292 qdev_connect_gpio_out(s->gpio, 1, s->reset); 2293 return s; 2294 } 2295 2296 static void pxa2xx_ssp_class_init(ObjectClass *klass, void *data) 2297 { 2298 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 2299 2300 sdc->init = pxa2xx_ssp_init; 2301 } 2302 2303 static const TypeInfo pxa2xx_ssp_info = { 2304 .name = TYPE_PXA2XX_SSP, 2305 .parent = TYPE_SYS_BUS_DEVICE, 2306 .instance_size = sizeof(PXA2xxSSPState), 2307 .class_init = pxa2xx_ssp_class_init, 2308 }; 2309 2310 static void pxa2xx_register_types(void) 2311 { 2312 type_register_static(&pxa2xx_i2c_slave_info); 2313 type_register_static(&pxa2xx_ssp_info); 2314 type_register_static(&pxa2xx_i2c_info); 2315 type_register_static(&pxa2xx_rtc_sysbus_info); 2316 } 2317 2318 type_init(pxa2xx_register_types) 2319