1 /* 2 * Intel XScale PXA255/270 processor support. 3 * 4 * Copyright (c) 2006 Openedhand Ltd. 5 * Written by Andrzej Zaborowski <balrog@zabor.org> 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "hw/sysbus.h" 11 #include "hw/arm/pxa.h" 12 #include "sysemu/sysemu.h" 13 #include "hw/char/serial.h" 14 #include "hw/i2c/i2c.h" 15 #include "hw/ssi.h" 16 #include "sysemu/char.h" 17 #include "sysemu/blockdev.h" 18 19 static struct { 20 hwaddr io_base; 21 int irqn; 22 } pxa255_serial[] = { 23 { 0x40100000, PXA2XX_PIC_FFUART }, 24 { 0x40200000, PXA2XX_PIC_BTUART }, 25 { 0x40700000, PXA2XX_PIC_STUART }, 26 { 0x41600000, PXA25X_PIC_HWUART }, 27 { 0, 0 } 28 }, pxa270_serial[] = { 29 { 0x40100000, PXA2XX_PIC_FFUART }, 30 { 0x40200000, PXA2XX_PIC_BTUART }, 31 { 0x40700000, PXA2XX_PIC_STUART }, 32 { 0, 0 } 33 }; 34 35 typedef struct PXASSPDef { 36 hwaddr io_base; 37 int irqn; 38 } PXASSPDef; 39 40 #if 0 41 static PXASSPDef pxa250_ssp[] = { 42 { 0x41000000, PXA2XX_PIC_SSP }, 43 { 0, 0 } 44 }; 45 #endif 46 47 static PXASSPDef pxa255_ssp[] = { 48 { 0x41000000, PXA2XX_PIC_SSP }, 49 { 0x41400000, PXA25X_PIC_NSSP }, 50 { 0, 0 } 51 }; 52 53 #if 0 54 static PXASSPDef pxa26x_ssp[] = { 55 { 0x41000000, PXA2XX_PIC_SSP }, 56 { 0x41400000, PXA25X_PIC_NSSP }, 57 { 0x41500000, PXA26X_PIC_ASSP }, 58 { 0, 0 } 59 }; 60 #endif 61 62 static PXASSPDef pxa27x_ssp[] = { 63 { 0x41000000, PXA2XX_PIC_SSP }, 64 { 0x41700000, PXA27X_PIC_SSP2 }, 65 { 0x41900000, PXA2XX_PIC_SSP3 }, 66 { 0, 0 } 67 }; 68 69 #define PMCR 0x00 /* Power Manager Control register */ 70 #define PSSR 0x04 /* Power Manager Sleep Status register */ 71 #define PSPR 0x08 /* Power Manager Scratch-Pad register */ 72 #define PWER 0x0c /* Power Manager Wake-Up Enable register */ 73 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */ 74 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */ 75 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */ 76 #define PCFR 0x1c /* Power Manager General Configuration register */ 77 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */ 78 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */ 79 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */ 80 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */ 81 #define RCSR 0x30 /* Reset Controller Status register */ 82 #define PSLR 0x34 /* Power Manager Sleep Configuration register */ 83 #define PTSR 0x38 /* Power Manager Standby Configuration register */ 84 #define PVCR 0x40 /* Power Manager Voltage Change Control register */ 85 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */ 86 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */ 87 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */ 88 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */ 89 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */ 90 91 static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr, 92 unsigned size) 93 { 94 PXA2xxState *s = (PXA2xxState *) opaque; 95 96 switch (addr) { 97 case PMCR ... PCMD31: 98 if (addr & 3) 99 goto fail; 100 101 return s->pm_regs[addr >> 2]; 102 default: 103 fail: 104 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 105 break; 106 } 107 return 0; 108 } 109 110 static void pxa2xx_pm_write(void *opaque, hwaddr addr, 111 uint64_t value, unsigned size) 112 { 113 PXA2xxState *s = (PXA2xxState *) opaque; 114 115 switch (addr) { 116 case PMCR: 117 /* Clear the write-one-to-clear bits... */ 118 s->pm_regs[addr >> 2] &= ~(value & 0x2a); 119 /* ...and set the plain r/w bits */ 120 s->pm_regs[addr >> 2] &= ~0x15; 121 s->pm_regs[addr >> 2] |= value & 0x15; 122 break; 123 124 case PSSR: /* Read-clean registers */ 125 case RCSR: 126 case PKSR: 127 s->pm_regs[addr >> 2] &= ~value; 128 break; 129 130 default: /* Read-write registers */ 131 if (!(addr & 3)) { 132 s->pm_regs[addr >> 2] = value; 133 break; 134 } 135 136 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 137 break; 138 } 139 } 140 141 static const MemoryRegionOps pxa2xx_pm_ops = { 142 .read = pxa2xx_pm_read, 143 .write = pxa2xx_pm_write, 144 .endianness = DEVICE_NATIVE_ENDIAN, 145 }; 146 147 static const VMStateDescription vmstate_pxa2xx_pm = { 148 .name = "pxa2xx_pm", 149 .version_id = 0, 150 .minimum_version_id = 0, 151 .minimum_version_id_old = 0, 152 .fields = (VMStateField[]) { 153 VMSTATE_UINT32_ARRAY(pm_regs, PXA2xxState, 0x40), 154 VMSTATE_END_OF_LIST() 155 } 156 }; 157 158 #define CCCR 0x00 /* Core Clock Configuration register */ 159 #define CKEN 0x04 /* Clock Enable register */ 160 #define OSCC 0x08 /* Oscillator Configuration register */ 161 #define CCSR 0x0c /* Core Clock Status register */ 162 163 static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr, 164 unsigned size) 165 { 166 PXA2xxState *s = (PXA2xxState *) opaque; 167 168 switch (addr) { 169 case CCCR: 170 case CKEN: 171 case OSCC: 172 return s->cm_regs[addr >> 2]; 173 174 case CCSR: 175 return s->cm_regs[CCCR >> 2] | (3 << 28); 176 177 default: 178 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 179 break; 180 } 181 return 0; 182 } 183 184 static void pxa2xx_cm_write(void *opaque, hwaddr addr, 185 uint64_t value, unsigned size) 186 { 187 PXA2xxState *s = (PXA2xxState *) opaque; 188 189 switch (addr) { 190 case CCCR: 191 case CKEN: 192 s->cm_regs[addr >> 2] = value; 193 break; 194 195 case OSCC: 196 s->cm_regs[addr >> 2] &= ~0x6c; 197 s->cm_regs[addr >> 2] |= value & 0x6e; 198 if ((value >> 1) & 1) /* OON */ 199 s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */ 200 break; 201 202 default: 203 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 204 break; 205 } 206 } 207 208 static const MemoryRegionOps pxa2xx_cm_ops = { 209 .read = pxa2xx_cm_read, 210 .write = pxa2xx_cm_write, 211 .endianness = DEVICE_NATIVE_ENDIAN, 212 }; 213 214 static const VMStateDescription vmstate_pxa2xx_cm = { 215 .name = "pxa2xx_cm", 216 .version_id = 0, 217 .minimum_version_id = 0, 218 .minimum_version_id_old = 0, 219 .fields = (VMStateField[]) { 220 VMSTATE_UINT32_ARRAY(cm_regs, PXA2xxState, 4), 221 VMSTATE_UINT32(clkcfg, PXA2xxState), 222 VMSTATE_UINT32(pmnc, PXA2xxState), 223 VMSTATE_END_OF_LIST() 224 } 225 }; 226 227 static int pxa2xx_clkcfg_read(CPUARMState *env, const ARMCPRegInfo *ri, 228 uint64_t *value) 229 { 230 PXA2xxState *s = (PXA2xxState *)ri->opaque; 231 *value = s->clkcfg; 232 return 0; 233 } 234 235 static int pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri, 236 uint64_t value) 237 { 238 PXA2xxState *s = (PXA2xxState *)ri->opaque; 239 s->clkcfg = value & 0xf; 240 if (value & 2) { 241 printf("%s: CPU frequency change attempt\n", __func__); 242 } 243 return 0; 244 } 245 246 static int pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri, 247 uint64_t value) 248 { 249 PXA2xxState *s = (PXA2xxState *)ri->opaque; 250 static const char *pwrmode[8] = { 251 "Normal", "Idle", "Deep-idle", "Standby", 252 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep", 253 }; 254 255 if (value & 8) { 256 printf("%s: CPU voltage change attempt\n", __func__); 257 } 258 switch (value & 7) { 259 case 0: 260 /* Do nothing */ 261 break; 262 263 case 1: 264 /* Idle */ 265 if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) { /* CPDIS */ 266 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); 267 break; 268 } 269 /* Fall through. */ 270 271 case 2: 272 /* Deep-Idle */ 273 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); 274 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ 275 goto message; 276 277 case 3: 278 s->cpu->env.uncached_cpsr = 279 ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I; 280 s->cpu->env.cp15.c1_sys = 0; 281 s->cpu->env.cp15.c1_coproc = 0; 282 s->cpu->env.cp15.c2_base0 = 0; 283 s->cpu->env.cp15.c3 = 0; 284 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ 285 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ 286 287 /* 288 * The scratch-pad register is almost universally used 289 * for storing the return address on suspend. For the 290 * lack of a resuming bootloader, perform a jump 291 * directly to that address. 292 */ 293 memset(s->cpu->env.regs, 0, 4 * 15); 294 s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2]; 295 296 #if 0 297 buffer = 0xe59ff000; /* ldr pc, [pc, #0] */ 298 cpu_physical_memory_write(0, &buffer, 4); 299 buffer = s->pm_regs[PSPR >> 2]; 300 cpu_physical_memory_write(8, &buffer, 4); 301 #endif 302 303 /* Suspend */ 304 cpu_interrupt(CPU(arm_env_get_cpu(cpu_single_env)), 305 CPU_INTERRUPT_HALT); 306 307 goto message; 308 309 default: 310 message: 311 printf("%s: machine entered %s mode\n", __func__, 312 pwrmode[value & 7]); 313 } 314 315 return 0; 316 } 317 318 static int pxa2xx_cppmnc_read(CPUARMState *env, const ARMCPRegInfo *ri, 319 uint64_t *value) 320 { 321 PXA2xxState *s = (PXA2xxState *)ri->opaque; 322 *value = s->pmnc; 323 return 0; 324 } 325 326 static int pxa2xx_cppmnc_write(CPUARMState *env, const ARMCPRegInfo *ri, 327 uint64_t value) 328 { 329 PXA2xxState *s = (PXA2xxState *)ri->opaque; 330 s->pmnc = value; 331 return 0; 332 } 333 334 static int pxa2xx_cpccnt_read(CPUARMState *env, const ARMCPRegInfo *ri, 335 uint64_t *value) 336 { 337 PXA2xxState *s = (PXA2xxState *)ri->opaque; 338 if (s->pmnc & 1) { 339 *value = qemu_get_clock_ns(vm_clock); 340 } else { 341 *value = 0; 342 } 343 return 0; 344 } 345 346 static const ARMCPRegInfo pxa_cp_reginfo[] = { 347 /* cp14 crm==1: perf registers */ 348 { .name = "CPPMNC", .cp = 14, .crn = 0, .crm = 1, .opc1 = 0, .opc2 = 0, 349 .access = PL1_RW, 350 .readfn = pxa2xx_cppmnc_read, .writefn = pxa2xx_cppmnc_write }, 351 { .name = "CPCCNT", .cp = 14, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, 352 .access = PL1_RW, 353 .readfn = pxa2xx_cpccnt_read, .writefn = arm_cp_write_ignore }, 354 { .name = "CPINTEN", .cp = 14, .crn = 4, .crm = 1, .opc1 = 0, .opc2 = 0, 355 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 356 { .name = "CPFLAG", .cp = 14, .crn = 5, .crm = 1, .opc1 = 0, .opc2 = 0, 357 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 358 { .name = "CPEVTSEL", .cp = 14, .crn = 8, .crm = 1, .opc1 = 0, .opc2 = 0, 359 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 360 /* cp14 crm==2: performance count registers */ 361 { .name = "CPPMN0", .cp = 14, .crn = 0, .crm = 2, .opc1 = 0, .opc2 = 0, 362 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 363 { .name = "CPPMN1", .cp = 14, .crn = 1, .crm = 2, .opc1 = 0, .opc2 = 0, 364 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 365 { .name = "CPPMN2", .cp = 14, .crn = 2, .crm = 2, .opc1 = 0, .opc2 = 0, 366 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 367 { .name = "CPPMN3", .cp = 14, .crn = 2, .crm = 3, .opc1 = 0, .opc2 = 0, 368 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 369 /* cp14 crn==6: CLKCFG */ 370 { .name = "CLKCFG", .cp = 14, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, 371 .access = PL1_RW, 372 .readfn = pxa2xx_clkcfg_read, .writefn = pxa2xx_clkcfg_write }, 373 /* cp14 crn==7: PWRMODE */ 374 { .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0, 375 .access = PL1_RW, 376 .readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write }, 377 REGINFO_SENTINEL 378 }; 379 380 static void pxa2xx_setup_cp14(PXA2xxState *s) 381 { 382 define_arm_cp_regs_with_opaque(s->cpu, pxa_cp_reginfo, s); 383 } 384 385 #define MDCNFG 0x00 /* SDRAM Configuration register */ 386 #define MDREFR 0x04 /* SDRAM Refresh Control register */ 387 #define MSC0 0x08 /* Static Memory Control register 0 */ 388 #define MSC1 0x0c /* Static Memory Control register 1 */ 389 #define MSC2 0x10 /* Static Memory Control register 2 */ 390 #define MECR 0x14 /* Expansion Memory Bus Config register */ 391 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */ 392 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */ 393 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */ 394 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */ 395 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */ 396 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */ 397 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */ 398 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */ 399 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */ 400 #define ARB_CNTL 0x48 /* Arbiter Control register */ 401 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */ 402 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */ 403 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */ 404 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */ 405 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */ 406 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */ 407 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */ 408 409 static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr, 410 unsigned size) 411 { 412 PXA2xxState *s = (PXA2xxState *) opaque; 413 414 switch (addr) { 415 case MDCNFG ... SA1110: 416 if ((addr & 3) == 0) 417 return s->mm_regs[addr >> 2]; 418 419 default: 420 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 421 break; 422 } 423 return 0; 424 } 425 426 static void pxa2xx_mm_write(void *opaque, hwaddr addr, 427 uint64_t value, unsigned size) 428 { 429 PXA2xxState *s = (PXA2xxState *) opaque; 430 431 switch (addr) { 432 case MDCNFG ... SA1110: 433 if ((addr & 3) == 0) { 434 s->mm_regs[addr >> 2] = value; 435 break; 436 } 437 438 default: 439 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 440 break; 441 } 442 } 443 444 static const MemoryRegionOps pxa2xx_mm_ops = { 445 .read = pxa2xx_mm_read, 446 .write = pxa2xx_mm_write, 447 .endianness = DEVICE_NATIVE_ENDIAN, 448 }; 449 450 static const VMStateDescription vmstate_pxa2xx_mm = { 451 .name = "pxa2xx_mm", 452 .version_id = 0, 453 .minimum_version_id = 0, 454 .minimum_version_id_old = 0, 455 .fields = (VMStateField[]) { 456 VMSTATE_UINT32_ARRAY(mm_regs, PXA2xxState, 0x1a), 457 VMSTATE_END_OF_LIST() 458 } 459 }; 460 461 /* Synchronous Serial Ports */ 462 typedef struct { 463 SysBusDevice busdev; 464 MemoryRegion iomem; 465 qemu_irq irq; 466 int enable; 467 SSIBus *bus; 468 469 uint32_t sscr[2]; 470 uint32_t sspsp; 471 uint32_t ssto; 472 uint32_t ssitr; 473 uint32_t sssr; 474 uint8_t sstsa; 475 uint8_t ssrsa; 476 uint8_t ssacd; 477 478 uint32_t rx_fifo[16]; 479 int rx_level; 480 int rx_start; 481 } PXA2xxSSPState; 482 483 #define SSCR0 0x00 /* SSP Control register 0 */ 484 #define SSCR1 0x04 /* SSP Control register 1 */ 485 #define SSSR 0x08 /* SSP Status register */ 486 #define SSITR 0x0c /* SSP Interrupt Test register */ 487 #define SSDR 0x10 /* SSP Data register */ 488 #define SSTO 0x28 /* SSP Time-Out register */ 489 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */ 490 #define SSTSA 0x30 /* SSP TX Time Slot Active register */ 491 #define SSRSA 0x34 /* SSP RX Time Slot Active register */ 492 #define SSTSS 0x38 /* SSP Time Slot Status register */ 493 #define SSACD 0x3c /* SSP Audio Clock Divider register */ 494 495 /* Bitfields for above registers */ 496 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00) 497 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10) 498 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20) 499 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30) 500 #define SSCR0_SSE (1 << 7) 501 #define SSCR0_RIM (1 << 22) 502 #define SSCR0_TIM (1 << 23) 503 #define SSCR0_MOD (1 << 31) 504 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1) 505 #define SSCR1_RIE (1 << 0) 506 #define SSCR1_TIE (1 << 1) 507 #define SSCR1_LBM (1 << 2) 508 #define SSCR1_MWDS (1 << 5) 509 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1) 510 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1) 511 #define SSCR1_EFWR (1 << 14) 512 #define SSCR1_PINTE (1 << 18) 513 #define SSCR1_TINTE (1 << 19) 514 #define SSCR1_RSRE (1 << 20) 515 #define SSCR1_TSRE (1 << 21) 516 #define SSCR1_EBCEI (1 << 29) 517 #define SSITR_INT (7 << 5) 518 #define SSSR_TNF (1 << 2) 519 #define SSSR_RNE (1 << 3) 520 #define SSSR_TFS (1 << 5) 521 #define SSSR_RFS (1 << 6) 522 #define SSSR_ROR (1 << 7) 523 #define SSSR_PINT (1 << 18) 524 #define SSSR_TINT (1 << 19) 525 #define SSSR_EOC (1 << 20) 526 #define SSSR_TUR (1 << 21) 527 #define SSSR_BCE (1 << 23) 528 #define SSSR_RW 0x00bc0080 529 530 static void pxa2xx_ssp_int_update(PXA2xxSSPState *s) 531 { 532 int level = 0; 533 534 level |= s->ssitr & SSITR_INT; 535 level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI); 536 level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM); 537 level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT)); 538 level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE); 539 level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE); 540 level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM); 541 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE); 542 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE); 543 qemu_set_irq(s->irq, !!level); 544 } 545 546 static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s) 547 { 548 s->sssr &= ~(0xf << 12); /* Clear RFL */ 549 s->sssr &= ~(0xf << 8); /* Clear TFL */ 550 s->sssr &= ~SSSR_TFS; 551 s->sssr &= ~SSSR_TNF; 552 if (s->enable) { 553 s->sssr |= ((s->rx_level - 1) & 0xf) << 12; 554 if (s->rx_level >= SSCR1_RFT(s->sscr[1])) 555 s->sssr |= SSSR_RFS; 556 else 557 s->sssr &= ~SSSR_RFS; 558 if (s->rx_level) 559 s->sssr |= SSSR_RNE; 560 else 561 s->sssr &= ~SSSR_RNE; 562 /* TX FIFO is never filled, so it is always in underrun 563 condition if SSP is enabled */ 564 s->sssr |= SSSR_TFS; 565 s->sssr |= SSSR_TNF; 566 } 567 568 pxa2xx_ssp_int_update(s); 569 } 570 571 static uint64_t pxa2xx_ssp_read(void *opaque, hwaddr addr, 572 unsigned size) 573 { 574 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; 575 uint32_t retval; 576 577 switch (addr) { 578 case SSCR0: 579 return s->sscr[0]; 580 case SSCR1: 581 return s->sscr[1]; 582 case SSPSP: 583 return s->sspsp; 584 case SSTO: 585 return s->ssto; 586 case SSITR: 587 return s->ssitr; 588 case SSSR: 589 return s->sssr | s->ssitr; 590 case SSDR: 591 if (!s->enable) 592 return 0xffffffff; 593 if (s->rx_level < 1) { 594 printf("%s: SSP Rx Underrun\n", __FUNCTION__); 595 return 0xffffffff; 596 } 597 s->rx_level --; 598 retval = s->rx_fifo[s->rx_start ++]; 599 s->rx_start &= 0xf; 600 pxa2xx_ssp_fifo_update(s); 601 return retval; 602 case SSTSA: 603 return s->sstsa; 604 case SSRSA: 605 return s->ssrsa; 606 case SSTSS: 607 return 0; 608 case SSACD: 609 return s->ssacd; 610 default: 611 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 612 break; 613 } 614 return 0; 615 } 616 617 static void pxa2xx_ssp_write(void *opaque, hwaddr addr, 618 uint64_t value64, unsigned size) 619 { 620 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; 621 uint32_t value = value64; 622 623 switch (addr) { 624 case SSCR0: 625 s->sscr[0] = value & 0xc7ffffff; 626 s->enable = value & SSCR0_SSE; 627 if (value & SSCR0_MOD) 628 printf("%s: Attempt to use network mode\n", __FUNCTION__); 629 if (s->enable && SSCR0_DSS(value) < 4) 630 printf("%s: Wrong data size: %i bits\n", __FUNCTION__, 631 SSCR0_DSS(value)); 632 if (!(value & SSCR0_SSE)) { 633 s->sssr = 0; 634 s->ssitr = 0; 635 s->rx_level = 0; 636 } 637 pxa2xx_ssp_fifo_update(s); 638 break; 639 640 case SSCR1: 641 s->sscr[1] = value; 642 if (value & (SSCR1_LBM | SSCR1_EFWR)) 643 printf("%s: Attempt to use SSP test mode\n", __FUNCTION__); 644 pxa2xx_ssp_fifo_update(s); 645 break; 646 647 case SSPSP: 648 s->sspsp = value; 649 break; 650 651 case SSTO: 652 s->ssto = value; 653 break; 654 655 case SSITR: 656 s->ssitr = value & SSITR_INT; 657 pxa2xx_ssp_int_update(s); 658 break; 659 660 case SSSR: 661 s->sssr &= ~(value & SSSR_RW); 662 pxa2xx_ssp_int_update(s); 663 break; 664 665 case SSDR: 666 if (SSCR0_UWIRE(s->sscr[0])) { 667 if (s->sscr[1] & SSCR1_MWDS) 668 value &= 0xffff; 669 else 670 value &= 0xff; 671 } else 672 /* Note how 32bits overflow does no harm here */ 673 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1; 674 675 /* Data goes from here to the Tx FIFO and is shifted out from 676 * there directly to the slave, no need to buffer it. 677 */ 678 if (s->enable) { 679 uint32_t readval; 680 readval = ssi_transfer(s->bus, value); 681 if (s->rx_level < 0x10) { 682 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval; 683 } else { 684 s->sssr |= SSSR_ROR; 685 } 686 } 687 pxa2xx_ssp_fifo_update(s); 688 break; 689 690 case SSTSA: 691 s->sstsa = value; 692 break; 693 694 case SSRSA: 695 s->ssrsa = value; 696 break; 697 698 case SSACD: 699 s->ssacd = value; 700 break; 701 702 default: 703 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 704 break; 705 } 706 } 707 708 static const MemoryRegionOps pxa2xx_ssp_ops = { 709 .read = pxa2xx_ssp_read, 710 .write = pxa2xx_ssp_write, 711 .endianness = DEVICE_NATIVE_ENDIAN, 712 }; 713 714 static void pxa2xx_ssp_save(QEMUFile *f, void *opaque) 715 { 716 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; 717 int i; 718 719 qemu_put_be32(f, s->enable); 720 721 qemu_put_be32s(f, &s->sscr[0]); 722 qemu_put_be32s(f, &s->sscr[1]); 723 qemu_put_be32s(f, &s->sspsp); 724 qemu_put_be32s(f, &s->ssto); 725 qemu_put_be32s(f, &s->ssitr); 726 qemu_put_be32s(f, &s->sssr); 727 qemu_put_8s(f, &s->sstsa); 728 qemu_put_8s(f, &s->ssrsa); 729 qemu_put_8s(f, &s->ssacd); 730 731 qemu_put_byte(f, s->rx_level); 732 for (i = 0; i < s->rx_level; i ++) 733 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 0xf]); 734 } 735 736 static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id) 737 { 738 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; 739 int i; 740 741 s->enable = qemu_get_be32(f); 742 743 qemu_get_be32s(f, &s->sscr[0]); 744 qemu_get_be32s(f, &s->sscr[1]); 745 qemu_get_be32s(f, &s->sspsp); 746 qemu_get_be32s(f, &s->ssto); 747 qemu_get_be32s(f, &s->ssitr); 748 qemu_get_be32s(f, &s->sssr); 749 qemu_get_8s(f, &s->sstsa); 750 qemu_get_8s(f, &s->ssrsa); 751 qemu_get_8s(f, &s->ssacd); 752 753 s->rx_level = qemu_get_byte(f); 754 s->rx_start = 0; 755 for (i = 0; i < s->rx_level; i ++) 756 s->rx_fifo[i] = qemu_get_byte(f); 757 758 return 0; 759 } 760 761 static int pxa2xx_ssp_init(SysBusDevice *dev) 762 { 763 PXA2xxSSPState *s = FROM_SYSBUS(PXA2xxSSPState, dev); 764 765 sysbus_init_irq(dev, &s->irq); 766 767 memory_region_init_io(&s->iomem, NULL, &pxa2xx_ssp_ops, s, "pxa2xx-ssp", 0x1000); 768 sysbus_init_mmio(dev, &s->iomem); 769 register_savevm(&dev->qdev, "pxa2xx_ssp", -1, 0, 770 pxa2xx_ssp_save, pxa2xx_ssp_load, s); 771 772 s->bus = ssi_create_bus(&dev->qdev, "ssi"); 773 return 0; 774 } 775 776 /* Real-Time Clock */ 777 #define RCNR 0x00 /* RTC Counter register */ 778 #define RTAR 0x04 /* RTC Alarm register */ 779 #define RTSR 0x08 /* RTC Status register */ 780 #define RTTR 0x0c /* RTC Timer Trim register */ 781 #define RDCR 0x10 /* RTC Day Counter register */ 782 #define RYCR 0x14 /* RTC Year Counter register */ 783 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */ 784 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */ 785 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */ 786 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */ 787 #define SWCR 0x28 /* RTC Stopwatch Counter register */ 788 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */ 789 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */ 790 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */ 791 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */ 792 793 typedef struct { 794 SysBusDevice busdev; 795 MemoryRegion iomem; 796 uint32_t rttr; 797 uint32_t rtsr; 798 uint32_t rtar; 799 uint32_t rdar1; 800 uint32_t rdar2; 801 uint32_t ryar1; 802 uint32_t ryar2; 803 uint32_t swar1; 804 uint32_t swar2; 805 uint32_t piar; 806 uint32_t last_rcnr; 807 uint32_t last_rdcr; 808 uint32_t last_rycr; 809 uint32_t last_swcr; 810 uint32_t last_rtcpicr; 811 int64_t last_hz; 812 int64_t last_sw; 813 int64_t last_pi; 814 QEMUTimer *rtc_hz; 815 QEMUTimer *rtc_rdal1; 816 QEMUTimer *rtc_rdal2; 817 QEMUTimer *rtc_swal1; 818 QEMUTimer *rtc_swal2; 819 QEMUTimer *rtc_pi; 820 qemu_irq rtc_irq; 821 } PXA2xxRTCState; 822 823 static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s) 824 { 825 qemu_set_irq(s->rtc_irq, !!(s->rtsr & 0x2553)); 826 } 827 828 static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s) 829 { 830 int64_t rt = qemu_get_clock_ms(rtc_clock); 831 s->last_rcnr += ((rt - s->last_hz) << 15) / 832 (1000 * ((s->rttr & 0xffff) + 1)); 833 s->last_rdcr += ((rt - s->last_hz) << 15) / 834 (1000 * ((s->rttr & 0xffff) + 1)); 835 s->last_hz = rt; 836 } 837 838 static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s) 839 { 840 int64_t rt = qemu_get_clock_ms(rtc_clock); 841 if (s->rtsr & (1 << 12)) 842 s->last_swcr += (rt - s->last_sw) / 10; 843 s->last_sw = rt; 844 } 845 846 static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s) 847 { 848 int64_t rt = qemu_get_clock_ms(rtc_clock); 849 if (s->rtsr & (1 << 15)) 850 s->last_swcr += rt - s->last_pi; 851 s->last_pi = rt; 852 } 853 854 static inline void pxa2xx_rtc_alarm_update(PXA2xxRTCState *s, 855 uint32_t rtsr) 856 { 857 if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0))) 858 qemu_mod_timer(s->rtc_hz, s->last_hz + 859 (((s->rtar - s->last_rcnr) * 1000 * 860 ((s->rttr & 0xffff) + 1)) >> 15)); 861 else 862 qemu_del_timer(s->rtc_hz); 863 864 if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4))) 865 qemu_mod_timer(s->rtc_rdal1, s->last_hz + 866 (((s->rdar1 - s->last_rdcr) * 1000 * 867 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */ 868 else 869 qemu_del_timer(s->rtc_rdal1); 870 871 if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6))) 872 qemu_mod_timer(s->rtc_rdal2, s->last_hz + 873 (((s->rdar2 - s->last_rdcr) * 1000 * 874 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */ 875 else 876 qemu_del_timer(s->rtc_rdal2); 877 878 if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8))) 879 qemu_mod_timer(s->rtc_swal1, s->last_sw + 880 (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */ 881 else 882 qemu_del_timer(s->rtc_swal1); 883 884 if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10))) 885 qemu_mod_timer(s->rtc_swal2, s->last_sw + 886 (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */ 887 else 888 qemu_del_timer(s->rtc_swal2); 889 890 if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13))) 891 qemu_mod_timer(s->rtc_pi, s->last_pi + 892 (s->piar & 0xffff) - s->last_rtcpicr); 893 else 894 qemu_del_timer(s->rtc_pi); 895 } 896 897 static inline void pxa2xx_rtc_hz_tick(void *opaque) 898 { 899 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 900 s->rtsr |= (1 << 0); 901 pxa2xx_rtc_alarm_update(s, s->rtsr); 902 pxa2xx_rtc_int_update(s); 903 } 904 905 static inline void pxa2xx_rtc_rdal1_tick(void *opaque) 906 { 907 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 908 s->rtsr |= (1 << 4); 909 pxa2xx_rtc_alarm_update(s, s->rtsr); 910 pxa2xx_rtc_int_update(s); 911 } 912 913 static inline void pxa2xx_rtc_rdal2_tick(void *opaque) 914 { 915 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 916 s->rtsr |= (1 << 6); 917 pxa2xx_rtc_alarm_update(s, s->rtsr); 918 pxa2xx_rtc_int_update(s); 919 } 920 921 static inline void pxa2xx_rtc_swal1_tick(void *opaque) 922 { 923 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 924 s->rtsr |= (1 << 8); 925 pxa2xx_rtc_alarm_update(s, s->rtsr); 926 pxa2xx_rtc_int_update(s); 927 } 928 929 static inline void pxa2xx_rtc_swal2_tick(void *opaque) 930 { 931 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 932 s->rtsr |= (1 << 10); 933 pxa2xx_rtc_alarm_update(s, s->rtsr); 934 pxa2xx_rtc_int_update(s); 935 } 936 937 static inline void pxa2xx_rtc_pi_tick(void *opaque) 938 { 939 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 940 s->rtsr |= (1 << 13); 941 pxa2xx_rtc_piupdate(s); 942 s->last_rtcpicr = 0; 943 pxa2xx_rtc_alarm_update(s, s->rtsr); 944 pxa2xx_rtc_int_update(s); 945 } 946 947 static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr, 948 unsigned size) 949 { 950 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 951 952 switch (addr) { 953 case RTTR: 954 return s->rttr; 955 case RTSR: 956 return s->rtsr; 957 case RTAR: 958 return s->rtar; 959 case RDAR1: 960 return s->rdar1; 961 case RDAR2: 962 return s->rdar2; 963 case RYAR1: 964 return s->ryar1; 965 case RYAR2: 966 return s->ryar2; 967 case SWAR1: 968 return s->swar1; 969 case SWAR2: 970 return s->swar2; 971 case PIAR: 972 return s->piar; 973 case RCNR: 974 return s->last_rcnr + ((qemu_get_clock_ms(rtc_clock) - s->last_hz) << 15) / 975 (1000 * ((s->rttr & 0xffff) + 1)); 976 case RDCR: 977 return s->last_rdcr + ((qemu_get_clock_ms(rtc_clock) - s->last_hz) << 15) / 978 (1000 * ((s->rttr & 0xffff) + 1)); 979 case RYCR: 980 return s->last_rycr; 981 case SWCR: 982 if (s->rtsr & (1 << 12)) 983 return s->last_swcr + (qemu_get_clock_ms(rtc_clock) - s->last_sw) / 10; 984 else 985 return s->last_swcr; 986 default: 987 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 988 break; 989 } 990 return 0; 991 } 992 993 static void pxa2xx_rtc_write(void *opaque, hwaddr addr, 994 uint64_t value64, unsigned size) 995 { 996 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 997 uint32_t value = value64; 998 999 switch (addr) { 1000 case RTTR: 1001 if (!(s->rttr & (1 << 31))) { 1002 pxa2xx_rtc_hzupdate(s); 1003 s->rttr = value; 1004 pxa2xx_rtc_alarm_update(s, s->rtsr); 1005 } 1006 break; 1007 1008 case RTSR: 1009 if ((s->rtsr ^ value) & (1 << 15)) 1010 pxa2xx_rtc_piupdate(s); 1011 1012 if ((s->rtsr ^ value) & (1 << 12)) 1013 pxa2xx_rtc_swupdate(s); 1014 1015 if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac)) 1016 pxa2xx_rtc_alarm_update(s, value); 1017 1018 s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac)); 1019 pxa2xx_rtc_int_update(s); 1020 break; 1021 1022 case RTAR: 1023 s->rtar = value; 1024 pxa2xx_rtc_alarm_update(s, s->rtsr); 1025 break; 1026 1027 case RDAR1: 1028 s->rdar1 = value; 1029 pxa2xx_rtc_alarm_update(s, s->rtsr); 1030 break; 1031 1032 case RDAR2: 1033 s->rdar2 = value; 1034 pxa2xx_rtc_alarm_update(s, s->rtsr); 1035 break; 1036 1037 case RYAR1: 1038 s->ryar1 = value; 1039 pxa2xx_rtc_alarm_update(s, s->rtsr); 1040 break; 1041 1042 case RYAR2: 1043 s->ryar2 = value; 1044 pxa2xx_rtc_alarm_update(s, s->rtsr); 1045 break; 1046 1047 case SWAR1: 1048 pxa2xx_rtc_swupdate(s); 1049 s->swar1 = value; 1050 s->last_swcr = 0; 1051 pxa2xx_rtc_alarm_update(s, s->rtsr); 1052 break; 1053 1054 case SWAR2: 1055 s->swar2 = value; 1056 pxa2xx_rtc_alarm_update(s, s->rtsr); 1057 break; 1058 1059 case PIAR: 1060 s->piar = value; 1061 pxa2xx_rtc_alarm_update(s, s->rtsr); 1062 break; 1063 1064 case RCNR: 1065 pxa2xx_rtc_hzupdate(s); 1066 s->last_rcnr = value; 1067 pxa2xx_rtc_alarm_update(s, s->rtsr); 1068 break; 1069 1070 case RDCR: 1071 pxa2xx_rtc_hzupdate(s); 1072 s->last_rdcr = value; 1073 pxa2xx_rtc_alarm_update(s, s->rtsr); 1074 break; 1075 1076 case RYCR: 1077 s->last_rycr = value; 1078 break; 1079 1080 case SWCR: 1081 pxa2xx_rtc_swupdate(s); 1082 s->last_swcr = value; 1083 pxa2xx_rtc_alarm_update(s, s->rtsr); 1084 break; 1085 1086 case RTCPICR: 1087 pxa2xx_rtc_piupdate(s); 1088 s->last_rtcpicr = value & 0xffff; 1089 pxa2xx_rtc_alarm_update(s, s->rtsr); 1090 break; 1091 1092 default: 1093 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1094 } 1095 } 1096 1097 static const MemoryRegionOps pxa2xx_rtc_ops = { 1098 .read = pxa2xx_rtc_read, 1099 .write = pxa2xx_rtc_write, 1100 .endianness = DEVICE_NATIVE_ENDIAN, 1101 }; 1102 1103 static int pxa2xx_rtc_init(SysBusDevice *dev) 1104 { 1105 PXA2xxRTCState *s = FROM_SYSBUS(PXA2xxRTCState, dev); 1106 struct tm tm; 1107 int wom; 1108 1109 s->rttr = 0x7fff; 1110 s->rtsr = 0; 1111 1112 qemu_get_timedate(&tm, 0); 1113 wom = ((tm.tm_mday - 1) / 7) + 1; 1114 1115 s->last_rcnr = (uint32_t) mktimegm(&tm); 1116 s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) | 1117 (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec; 1118 s->last_rycr = ((tm.tm_year + 1900) << 9) | 1119 ((tm.tm_mon + 1) << 5) | tm.tm_mday; 1120 s->last_swcr = (tm.tm_hour << 19) | 1121 (tm.tm_min << 13) | (tm.tm_sec << 7); 1122 s->last_rtcpicr = 0; 1123 s->last_hz = s->last_sw = s->last_pi = qemu_get_clock_ms(rtc_clock); 1124 1125 s->rtc_hz = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_hz_tick, s); 1126 s->rtc_rdal1 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_rdal1_tick, s); 1127 s->rtc_rdal2 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_rdal2_tick, s); 1128 s->rtc_swal1 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_swal1_tick, s); 1129 s->rtc_swal2 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_swal2_tick, s); 1130 s->rtc_pi = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_pi_tick, s); 1131 1132 sysbus_init_irq(dev, &s->rtc_irq); 1133 1134 memory_region_init_io(&s->iomem, NULL, &pxa2xx_rtc_ops, s, "pxa2xx-rtc", 0x10000); 1135 sysbus_init_mmio(dev, &s->iomem); 1136 1137 return 0; 1138 } 1139 1140 static void pxa2xx_rtc_pre_save(void *opaque) 1141 { 1142 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 1143 1144 pxa2xx_rtc_hzupdate(s); 1145 pxa2xx_rtc_piupdate(s); 1146 pxa2xx_rtc_swupdate(s); 1147 } 1148 1149 static int pxa2xx_rtc_post_load(void *opaque, int version_id) 1150 { 1151 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 1152 1153 pxa2xx_rtc_alarm_update(s, s->rtsr); 1154 1155 return 0; 1156 } 1157 1158 static const VMStateDescription vmstate_pxa2xx_rtc_regs = { 1159 .name = "pxa2xx_rtc", 1160 .version_id = 0, 1161 .minimum_version_id = 0, 1162 .minimum_version_id_old = 0, 1163 .pre_save = pxa2xx_rtc_pre_save, 1164 .post_load = pxa2xx_rtc_post_load, 1165 .fields = (VMStateField[]) { 1166 VMSTATE_UINT32(rttr, PXA2xxRTCState), 1167 VMSTATE_UINT32(rtsr, PXA2xxRTCState), 1168 VMSTATE_UINT32(rtar, PXA2xxRTCState), 1169 VMSTATE_UINT32(rdar1, PXA2xxRTCState), 1170 VMSTATE_UINT32(rdar2, PXA2xxRTCState), 1171 VMSTATE_UINT32(ryar1, PXA2xxRTCState), 1172 VMSTATE_UINT32(ryar2, PXA2xxRTCState), 1173 VMSTATE_UINT32(swar1, PXA2xxRTCState), 1174 VMSTATE_UINT32(swar2, PXA2xxRTCState), 1175 VMSTATE_UINT32(piar, PXA2xxRTCState), 1176 VMSTATE_UINT32(last_rcnr, PXA2xxRTCState), 1177 VMSTATE_UINT32(last_rdcr, PXA2xxRTCState), 1178 VMSTATE_UINT32(last_rycr, PXA2xxRTCState), 1179 VMSTATE_UINT32(last_swcr, PXA2xxRTCState), 1180 VMSTATE_UINT32(last_rtcpicr, PXA2xxRTCState), 1181 VMSTATE_INT64(last_hz, PXA2xxRTCState), 1182 VMSTATE_INT64(last_sw, PXA2xxRTCState), 1183 VMSTATE_INT64(last_pi, PXA2xxRTCState), 1184 VMSTATE_END_OF_LIST(), 1185 }, 1186 }; 1187 1188 static void pxa2xx_rtc_sysbus_class_init(ObjectClass *klass, void *data) 1189 { 1190 DeviceClass *dc = DEVICE_CLASS(klass); 1191 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 1192 1193 k->init = pxa2xx_rtc_init; 1194 dc->desc = "PXA2xx RTC Controller"; 1195 dc->vmsd = &vmstate_pxa2xx_rtc_regs; 1196 } 1197 1198 static const TypeInfo pxa2xx_rtc_sysbus_info = { 1199 .name = "pxa2xx_rtc", 1200 .parent = TYPE_SYS_BUS_DEVICE, 1201 .instance_size = sizeof(PXA2xxRTCState), 1202 .class_init = pxa2xx_rtc_sysbus_class_init, 1203 }; 1204 1205 /* I2C Interface */ 1206 typedef struct { 1207 I2CSlave i2c; 1208 PXA2xxI2CState *host; 1209 } PXA2xxI2CSlaveState; 1210 1211 struct PXA2xxI2CState { 1212 SysBusDevice busdev; 1213 MemoryRegion iomem; 1214 PXA2xxI2CSlaveState *slave; 1215 i2c_bus *bus; 1216 qemu_irq irq; 1217 uint32_t offset; 1218 uint32_t region_size; 1219 1220 uint16_t control; 1221 uint16_t status; 1222 uint8_t ibmr; 1223 uint8_t data; 1224 }; 1225 1226 #define IBMR 0x80 /* I2C Bus Monitor register */ 1227 #define IDBR 0x88 /* I2C Data Buffer register */ 1228 #define ICR 0x90 /* I2C Control register */ 1229 #define ISR 0x98 /* I2C Status register */ 1230 #define ISAR 0xa0 /* I2C Slave Address register */ 1231 1232 static void pxa2xx_i2c_update(PXA2xxI2CState *s) 1233 { 1234 uint16_t level = 0; 1235 level |= s->status & s->control & (1 << 10); /* BED */ 1236 level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */ 1237 level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */ 1238 level |= s->status & (1 << 9); /* SAD */ 1239 qemu_set_irq(s->irq, !!level); 1240 } 1241 1242 /* These are only stubs now. */ 1243 static void pxa2xx_i2c_event(I2CSlave *i2c, enum i2c_event event) 1244 { 1245 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c); 1246 PXA2xxI2CState *s = slave->host; 1247 1248 switch (event) { 1249 case I2C_START_SEND: 1250 s->status |= (1 << 9); /* set SAD */ 1251 s->status &= ~(1 << 0); /* clear RWM */ 1252 break; 1253 case I2C_START_RECV: 1254 s->status |= (1 << 9); /* set SAD */ 1255 s->status |= 1 << 0; /* set RWM */ 1256 break; 1257 case I2C_FINISH: 1258 s->status |= (1 << 4); /* set SSD */ 1259 break; 1260 case I2C_NACK: 1261 s->status |= 1 << 1; /* set ACKNAK */ 1262 break; 1263 } 1264 pxa2xx_i2c_update(s); 1265 } 1266 1267 static int pxa2xx_i2c_rx(I2CSlave *i2c) 1268 { 1269 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c); 1270 PXA2xxI2CState *s = slave->host; 1271 if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) 1272 return 0; 1273 1274 if (s->status & (1 << 0)) { /* RWM */ 1275 s->status |= 1 << 6; /* set ITE */ 1276 } 1277 pxa2xx_i2c_update(s); 1278 1279 return s->data; 1280 } 1281 1282 static int pxa2xx_i2c_tx(I2CSlave *i2c, uint8_t data) 1283 { 1284 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c); 1285 PXA2xxI2CState *s = slave->host; 1286 if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) 1287 return 1; 1288 1289 if (!(s->status & (1 << 0))) { /* RWM */ 1290 s->status |= 1 << 7; /* set IRF */ 1291 s->data = data; 1292 } 1293 pxa2xx_i2c_update(s); 1294 1295 return 1; 1296 } 1297 1298 static uint64_t pxa2xx_i2c_read(void *opaque, hwaddr addr, 1299 unsigned size) 1300 { 1301 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; 1302 1303 addr -= s->offset; 1304 switch (addr) { 1305 case ICR: 1306 return s->control; 1307 case ISR: 1308 return s->status | (i2c_bus_busy(s->bus) << 2); 1309 case ISAR: 1310 return s->slave->i2c.address; 1311 case IDBR: 1312 return s->data; 1313 case IBMR: 1314 if (s->status & (1 << 2)) 1315 s->ibmr ^= 3; /* Fake SCL and SDA pin changes */ 1316 else 1317 s->ibmr = 0; 1318 return s->ibmr; 1319 default: 1320 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1321 break; 1322 } 1323 return 0; 1324 } 1325 1326 static void pxa2xx_i2c_write(void *opaque, hwaddr addr, 1327 uint64_t value64, unsigned size) 1328 { 1329 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; 1330 uint32_t value = value64; 1331 int ack; 1332 1333 addr -= s->offset; 1334 switch (addr) { 1335 case ICR: 1336 s->control = value & 0xfff7; 1337 if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */ 1338 /* TODO: slave mode */ 1339 if (value & (1 << 0)) { /* START condition */ 1340 if (s->data & 1) 1341 s->status |= 1 << 0; /* set RWM */ 1342 else 1343 s->status &= ~(1 << 0); /* clear RWM */ 1344 ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1); 1345 } else { 1346 if (s->status & (1 << 0)) { /* RWM */ 1347 s->data = i2c_recv(s->bus); 1348 if (value & (1 << 2)) /* ACKNAK */ 1349 i2c_nack(s->bus); 1350 ack = 1; 1351 } else 1352 ack = !i2c_send(s->bus, s->data); 1353 } 1354 1355 if (value & (1 << 1)) /* STOP condition */ 1356 i2c_end_transfer(s->bus); 1357 1358 if (ack) { 1359 if (value & (1 << 0)) /* START condition */ 1360 s->status |= 1 << 6; /* set ITE */ 1361 else 1362 if (s->status & (1 << 0)) /* RWM */ 1363 s->status |= 1 << 7; /* set IRF */ 1364 else 1365 s->status |= 1 << 6; /* set ITE */ 1366 s->status &= ~(1 << 1); /* clear ACKNAK */ 1367 } else { 1368 s->status |= 1 << 6; /* set ITE */ 1369 s->status |= 1 << 10; /* set BED */ 1370 s->status |= 1 << 1; /* set ACKNAK */ 1371 } 1372 } 1373 if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */ 1374 if (value & (1 << 4)) /* MA */ 1375 i2c_end_transfer(s->bus); 1376 pxa2xx_i2c_update(s); 1377 break; 1378 1379 case ISR: 1380 s->status &= ~(value & 0x07f0); 1381 pxa2xx_i2c_update(s); 1382 break; 1383 1384 case ISAR: 1385 i2c_set_slave_address(&s->slave->i2c, value & 0x7f); 1386 break; 1387 1388 case IDBR: 1389 s->data = value & 0xff; 1390 break; 1391 1392 default: 1393 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1394 } 1395 } 1396 1397 static const MemoryRegionOps pxa2xx_i2c_ops = { 1398 .read = pxa2xx_i2c_read, 1399 .write = pxa2xx_i2c_write, 1400 .endianness = DEVICE_NATIVE_ENDIAN, 1401 }; 1402 1403 static const VMStateDescription vmstate_pxa2xx_i2c_slave = { 1404 .name = "pxa2xx_i2c_slave", 1405 .version_id = 1, 1406 .minimum_version_id = 1, 1407 .minimum_version_id_old = 1, 1408 .fields = (VMStateField []) { 1409 VMSTATE_I2C_SLAVE(i2c, PXA2xxI2CSlaveState), 1410 VMSTATE_END_OF_LIST() 1411 } 1412 }; 1413 1414 static const VMStateDescription vmstate_pxa2xx_i2c = { 1415 .name = "pxa2xx_i2c", 1416 .version_id = 1, 1417 .minimum_version_id = 1, 1418 .minimum_version_id_old = 1, 1419 .fields = (VMStateField []) { 1420 VMSTATE_UINT16(control, PXA2xxI2CState), 1421 VMSTATE_UINT16(status, PXA2xxI2CState), 1422 VMSTATE_UINT8(ibmr, PXA2xxI2CState), 1423 VMSTATE_UINT8(data, PXA2xxI2CState), 1424 VMSTATE_STRUCT_POINTER(slave, PXA2xxI2CState, 1425 vmstate_pxa2xx_i2c_slave, PXA2xxI2CSlaveState *), 1426 VMSTATE_END_OF_LIST() 1427 } 1428 }; 1429 1430 static int pxa2xx_i2c_slave_init(I2CSlave *i2c) 1431 { 1432 /* Nothing to do. */ 1433 return 0; 1434 } 1435 1436 static void pxa2xx_i2c_slave_class_init(ObjectClass *klass, void *data) 1437 { 1438 I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); 1439 1440 k->init = pxa2xx_i2c_slave_init; 1441 k->event = pxa2xx_i2c_event; 1442 k->recv = pxa2xx_i2c_rx; 1443 k->send = pxa2xx_i2c_tx; 1444 } 1445 1446 static const TypeInfo pxa2xx_i2c_slave_info = { 1447 .name = "pxa2xx-i2c-slave", 1448 .parent = TYPE_I2C_SLAVE, 1449 .instance_size = sizeof(PXA2xxI2CSlaveState), 1450 .class_init = pxa2xx_i2c_slave_class_init, 1451 }; 1452 1453 PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base, 1454 qemu_irq irq, uint32_t region_size) 1455 { 1456 DeviceState *dev; 1457 SysBusDevice *i2c_dev; 1458 PXA2xxI2CState *s; 1459 1460 i2c_dev = SYS_BUS_DEVICE(qdev_create(NULL, "pxa2xx_i2c")); 1461 qdev_prop_set_uint32(&i2c_dev->qdev, "size", region_size + 1); 1462 qdev_prop_set_uint32(&i2c_dev->qdev, "offset", base & region_size); 1463 1464 qdev_init_nofail(&i2c_dev->qdev); 1465 1466 sysbus_mmio_map(i2c_dev, 0, base & ~region_size); 1467 sysbus_connect_irq(i2c_dev, 0, irq); 1468 1469 s = FROM_SYSBUS(PXA2xxI2CState, i2c_dev); 1470 /* FIXME: Should the slave device really be on a separate bus? */ 1471 dev = i2c_create_slave(i2c_init_bus(NULL, "dummy"), "pxa2xx-i2c-slave", 0); 1472 s->slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, I2C_SLAVE(dev)); 1473 s->slave->host = s; 1474 1475 return s; 1476 } 1477 1478 static int pxa2xx_i2c_initfn(SysBusDevice *dev) 1479 { 1480 PXA2xxI2CState *s = FROM_SYSBUS(PXA2xxI2CState, dev); 1481 1482 s->bus = i2c_init_bus(&dev->qdev, "i2c"); 1483 1484 memory_region_init_io(&s->iomem, NULL, &pxa2xx_i2c_ops, s, 1485 "pxa2xx-i2x", s->region_size); 1486 sysbus_init_mmio(dev, &s->iomem); 1487 sysbus_init_irq(dev, &s->irq); 1488 1489 return 0; 1490 } 1491 1492 i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s) 1493 { 1494 return s->bus; 1495 } 1496 1497 static Property pxa2xx_i2c_properties[] = { 1498 DEFINE_PROP_UINT32("size", PXA2xxI2CState, region_size, 0x10000), 1499 DEFINE_PROP_UINT32("offset", PXA2xxI2CState, offset, 0), 1500 DEFINE_PROP_END_OF_LIST(), 1501 }; 1502 1503 static void pxa2xx_i2c_class_init(ObjectClass *klass, void *data) 1504 { 1505 DeviceClass *dc = DEVICE_CLASS(klass); 1506 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 1507 1508 k->init = pxa2xx_i2c_initfn; 1509 dc->desc = "PXA2xx I2C Bus Controller"; 1510 dc->vmsd = &vmstate_pxa2xx_i2c; 1511 dc->props = pxa2xx_i2c_properties; 1512 } 1513 1514 static const TypeInfo pxa2xx_i2c_info = { 1515 .name = "pxa2xx_i2c", 1516 .parent = TYPE_SYS_BUS_DEVICE, 1517 .instance_size = sizeof(PXA2xxI2CState), 1518 .class_init = pxa2xx_i2c_class_init, 1519 }; 1520 1521 /* PXA Inter-IC Sound Controller */ 1522 static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s) 1523 { 1524 i2s->rx_len = 0; 1525 i2s->tx_len = 0; 1526 i2s->fifo_len = 0; 1527 i2s->clk = 0x1a; 1528 i2s->control[0] = 0x00; 1529 i2s->control[1] = 0x00; 1530 i2s->status = 0x00; 1531 i2s->mask = 0x00; 1532 } 1533 1534 #define SACR_TFTH(val) ((val >> 8) & 0xf) 1535 #define SACR_RFTH(val) ((val >> 12) & 0xf) 1536 #define SACR_DREC(val) (val & (1 << 3)) 1537 #define SACR_DPRL(val) (val & (1 << 4)) 1538 1539 static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s) 1540 { 1541 int rfs, tfs; 1542 rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len && 1543 !SACR_DREC(i2s->control[1]); 1544 tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) && 1545 i2s->enable && !SACR_DPRL(i2s->control[1]); 1546 1547 qemu_set_irq(i2s->rx_dma, rfs); 1548 qemu_set_irq(i2s->tx_dma, tfs); 1549 1550 i2s->status &= 0xe0; 1551 if (i2s->fifo_len < 16 || !i2s->enable) 1552 i2s->status |= 1 << 0; /* TNF */ 1553 if (i2s->rx_len) 1554 i2s->status |= 1 << 1; /* RNE */ 1555 if (i2s->enable) 1556 i2s->status |= 1 << 2; /* BSY */ 1557 if (tfs) 1558 i2s->status |= 1 << 3; /* TFS */ 1559 if (rfs) 1560 i2s->status |= 1 << 4; /* RFS */ 1561 if (!(i2s->tx_len && i2s->enable)) 1562 i2s->status |= i2s->fifo_len << 8; /* TFL */ 1563 i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */ 1564 1565 qemu_set_irq(i2s->irq, i2s->status & i2s->mask); 1566 } 1567 1568 #define SACR0 0x00 /* Serial Audio Global Control register */ 1569 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */ 1570 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */ 1571 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */ 1572 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */ 1573 #define SADIV 0x60 /* Serial Audio Clock Divider register */ 1574 #define SADR 0x80 /* Serial Audio Data register */ 1575 1576 static uint64_t pxa2xx_i2s_read(void *opaque, hwaddr addr, 1577 unsigned size) 1578 { 1579 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; 1580 1581 switch (addr) { 1582 case SACR0: 1583 return s->control[0]; 1584 case SACR1: 1585 return s->control[1]; 1586 case SASR0: 1587 return s->status; 1588 case SAIMR: 1589 return s->mask; 1590 case SAICR: 1591 return 0; 1592 case SADIV: 1593 return s->clk; 1594 case SADR: 1595 if (s->rx_len > 0) { 1596 s->rx_len --; 1597 pxa2xx_i2s_update(s); 1598 return s->codec_in(s->opaque); 1599 } 1600 return 0; 1601 default: 1602 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1603 break; 1604 } 1605 return 0; 1606 } 1607 1608 static void pxa2xx_i2s_write(void *opaque, hwaddr addr, 1609 uint64_t value, unsigned size) 1610 { 1611 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; 1612 uint32_t *sample; 1613 1614 switch (addr) { 1615 case SACR0: 1616 if (value & (1 << 3)) /* RST */ 1617 pxa2xx_i2s_reset(s); 1618 s->control[0] = value & 0xff3d; 1619 if (!s->enable && (value & 1) && s->tx_len) { /* ENB */ 1620 for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++) 1621 s->codec_out(s->opaque, *sample); 1622 s->status &= ~(1 << 7); /* I2SOFF */ 1623 } 1624 if (value & (1 << 4)) /* EFWR */ 1625 printf("%s: Attempt to use special function\n", __FUNCTION__); 1626 s->enable = (value & 9) == 1; /* ENB && !RST*/ 1627 pxa2xx_i2s_update(s); 1628 break; 1629 case SACR1: 1630 s->control[1] = value & 0x0039; 1631 if (value & (1 << 5)) /* ENLBF */ 1632 printf("%s: Attempt to use loopback function\n", __FUNCTION__); 1633 if (value & (1 << 4)) /* DPRL */ 1634 s->fifo_len = 0; 1635 pxa2xx_i2s_update(s); 1636 break; 1637 case SAIMR: 1638 s->mask = value & 0x0078; 1639 pxa2xx_i2s_update(s); 1640 break; 1641 case SAICR: 1642 s->status &= ~(value & (3 << 5)); 1643 pxa2xx_i2s_update(s); 1644 break; 1645 case SADIV: 1646 s->clk = value & 0x007f; 1647 break; 1648 case SADR: 1649 if (s->tx_len && s->enable) { 1650 s->tx_len --; 1651 pxa2xx_i2s_update(s); 1652 s->codec_out(s->opaque, value); 1653 } else if (s->fifo_len < 16) { 1654 s->fifo[s->fifo_len ++] = value; 1655 pxa2xx_i2s_update(s); 1656 } 1657 break; 1658 default: 1659 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1660 } 1661 } 1662 1663 static const MemoryRegionOps pxa2xx_i2s_ops = { 1664 .read = pxa2xx_i2s_read, 1665 .write = pxa2xx_i2s_write, 1666 .endianness = DEVICE_NATIVE_ENDIAN, 1667 }; 1668 1669 static const VMStateDescription vmstate_pxa2xx_i2s = { 1670 .name = "pxa2xx_i2s", 1671 .version_id = 0, 1672 .minimum_version_id = 0, 1673 .minimum_version_id_old = 0, 1674 .fields = (VMStateField[]) { 1675 VMSTATE_UINT32_ARRAY(control, PXA2xxI2SState, 2), 1676 VMSTATE_UINT32(status, PXA2xxI2SState), 1677 VMSTATE_UINT32(mask, PXA2xxI2SState), 1678 VMSTATE_UINT32(clk, PXA2xxI2SState), 1679 VMSTATE_INT32(enable, PXA2xxI2SState), 1680 VMSTATE_INT32(rx_len, PXA2xxI2SState), 1681 VMSTATE_INT32(tx_len, PXA2xxI2SState), 1682 VMSTATE_INT32(fifo_len, PXA2xxI2SState), 1683 VMSTATE_END_OF_LIST() 1684 } 1685 }; 1686 1687 static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx) 1688 { 1689 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; 1690 uint32_t *sample; 1691 1692 /* Signal FIFO errors */ 1693 if (s->enable && s->tx_len) 1694 s->status |= 1 << 5; /* TUR */ 1695 if (s->enable && s->rx_len) 1696 s->status |= 1 << 6; /* ROR */ 1697 1698 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to 1699 * handle the cases where it makes a difference. */ 1700 s->tx_len = tx - s->fifo_len; 1701 s->rx_len = rx; 1702 /* Note that is s->codec_out wasn't set, we wouldn't get called. */ 1703 if (s->enable) 1704 for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++) 1705 s->codec_out(s->opaque, *sample); 1706 pxa2xx_i2s_update(s); 1707 } 1708 1709 static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem, 1710 hwaddr base, 1711 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma) 1712 { 1713 PXA2xxI2SState *s = (PXA2xxI2SState *) 1714 g_malloc0(sizeof(PXA2xxI2SState)); 1715 1716 s->irq = irq; 1717 s->rx_dma = rx_dma; 1718 s->tx_dma = tx_dma; 1719 s->data_req = pxa2xx_i2s_data_req; 1720 1721 pxa2xx_i2s_reset(s); 1722 1723 memory_region_init_io(&s->iomem, NULL, &pxa2xx_i2s_ops, s, 1724 "pxa2xx-i2s", 0x100000); 1725 memory_region_add_subregion(sysmem, base, &s->iomem); 1726 1727 vmstate_register(NULL, base, &vmstate_pxa2xx_i2s, s); 1728 1729 return s; 1730 } 1731 1732 /* PXA Fast Infra-red Communications Port */ 1733 struct PXA2xxFIrState { 1734 MemoryRegion iomem; 1735 qemu_irq irq; 1736 qemu_irq rx_dma; 1737 qemu_irq tx_dma; 1738 int enable; 1739 CharDriverState *chr; 1740 1741 uint8_t control[3]; 1742 uint8_t status[2]; 1743 1744 int rx_len; 1745 int rx_start; 1746 uint8_t rx_fifo[64]; 1747 }; 1748 1749 static void pxa2xx_fir_reset(PXA2xxFIrState *s) 1750 { 1751 s->control[0] = 0x00; 1752 s->control[1] = 0x00; 1753 s->control[2] = 0x00; 1754 s->status[0] = 0x00; 1755 s->status[1] = 0x00; 1756 s->enable = 0; 1757 } 1758 1759 static inline void pxa2xx_fir_update(PXA2xxFIrState *s) 1760 { 1761 static const int tresh[4] = { 8, 16, 32, 0 }; 1762 int intr = 0; 1763 if ((s->control[0] & (1 << 4)) && /* RXE */ 1764 s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */ 1765 s->status[0] |= 1 << 4; /* RFS */ 1766 else 1767 s->status[0] &= ~(1 << 4); /* RFS */ 1768 if (s->control[0] & (1 << 3)) /* TXE */ 1769 s->status[0] |= 1 << 3; /* TFS */ 1770 else 1771 s->status[0] &= ~(1 << 3); /* TFS */ 1772 if (s->rx_len) 1773 s->status[1] |= 1 << 2; /* RNE */ 1774 else 1775 s->status[1] &= ~(1 << 2); /* RNE */ 1776 if (s->control[0] & (1 << 4)) /* RXE */ 1777 s->status[1] |= 1 << 0; /* RSY */ 1778 else 1779 s->status[1] &= ~(1 << 0); /* RSY */ 1780 1781 intr |= (s->control[0] & (1 << 5)) && /* RIE */ 1782 (s->status[0] & (1 << 4)); /* RFS */ 1783 intr |= (s->control[0] & (1 << 6)) && /* TIE */ 1784 (s->status[0] & (1 << 3)); /* TFS */ 1785 intr |= (s->control[2] & (1 << 4)) && /* TRAIL */ 1786 (s->status[0] & (1 << 6)); /* EOC */ 1787 intr |= (s->control[0] & (1 << 2)) && /* TUS */ 1788 (s->status[0] & (1 << 1)); /* TUR */ 1789 intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */ 1790 1791 qemu_set_irq(s->rx_dma, (s->status[0] >> 4) & 1); 1792 qemu_set_irq(s->tx_dma, (s->status[0] >> 3) & 1); 1793 1794 qemu_set_irq(s->irq, intr && s->enable); 1795 } 1796 1797 #define ICCR0 0x00 /* FICP Control register 0 */ 1798 #define ICCR1 0x04 /* FICP Control register 1 */ 1799 #define ICCR2 0x08 /* FICP Control register 2 */ 1800 #define ICDR 0x0c /* FICP Data register */ 1801 #define ICSR0 0x14 /* FICP Status register 0 */ 1802 #define ICSR1 0x18 /* FICP Status register 1 */ 1803 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */ 1804 1805 static uint64_t pxa2xx_fir_read(void *opaque, hwaddr addr, 1806 unsigned size) 1807 { 1808 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1809 uint8_t ret; 1810 1811 switch (addr) { 1812 case ICCR0: 1813 return s->control[0]; 1814 case ICCR1: 1815 return s->control[1]; 1816 case ICCR2: 1817 return s->control[2]; 1818 case ICDR: 1819 s->status[0] &= ~0x01; 1820 s->status[1] &= ~0x72; 1821 if (s->rx_len) { 1822 s->rx_len --; 1823 ret = s->rx_fifo[s->rx_start ++]; 1824 s->rx_start &= 63; 1825 pxa2xx_fir_update(s); 1826 return ret; 1827 } 1828 printf("%s: Rx FIFO underrun.\n", __FUNCTION__); 1829 break; 1830 case ICSR0: 1831 return s->status[0]; 1832 case ICSR1: 1833 return s->status[1] | (1 << 3); /* TNF */ 1834 case ICFOR: 1835 return s->rx_len; 1836 default: 1837 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1838 break; 1839 } 1840 return 0; 1841 } 1842 1843 static void pxa2xx_fir_write(void *opaque, hwaddr addr, 1844 uint64_t value64, unsigned size) 1845 { 1846 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1847 uint32_t value = value64; 1848 uint8_t ch; 1849 1850 switch (addr) { 1851 case ICCR0: 1852 s->control[0] = value; 1853 if (!(value & (1 << 4))) /* RXE */ 1854 s->rx_len = s->rx_start = 0; 1855 if (!(value & (1 << 3))) { /* TXE */ 1856 /* Nop */ 1857 } 1858 s->enable = value & 1; /* ITR */ 1859 if (!s->enable) 1860 s->status[0] = 0; 1861 pxa2xx_fir_update(s); 1862 break; 1863 case ICCR1: 1864 s->control[1] = value; 1865 break; 1866 case ICCR2: 1867 s->control[2] = value & 0x3f; 1868 pxa2xx_fir_update(s); 1869 break; 1870 case ICDR: 1871 if (s->control[2] & (1 << 2)) /* TXP */ 1872 ch = value; 1873 else 1874 ch = ~value; 1875 if (s->chr && s->enable && (s->control[0] & (1 << 3))) /* TXE */ 1876 qemu_chr_fe_write(s->chr, &ch, 1); 1877 break; 1878 case ICSR0: 1879 s->status[0] &= ~(value & 0x66); 1880 pxa2xx_fir_update(s); 1881 break; 1882 case ICFOR: 1883 break; 1884 default: 1885 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1886 } 1887 } 1888 1889 static const MemoryRegionOps pxa2xx_fir_ops = { 1890 .read = pxa2xx_fir_read, 1891 .write = pxa2xx_fir_write, 1892 .endianness = DEVICE_NATIVE_ENDIAN, 1893 }; 1894 1895 static int pxa2xx_fir_is_empty(void *opaque) 1896 { 1897 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1898 return (s->rx_len < 64); 1899 } 1900 1901 static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size) 1902 { 1903 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1904 if (!(s->control[0] & (1 << 4))) /* RXE */ 1905 return; 1906 1907 while (size --) { 1908 s->status[1] |= 1 << 4; /* EOF */ 1909 if (s->rx_len >= 64) { 1910 s->status[1] |= 1 << 6; /* ROR */ 1911 break; 1912 } 1913 1914 if (s->control[2] & (1 << 3)) /* RXP */ 1915 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++); 1916 else 1917 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++); 1918 } 1919 1920 pxa2xx_fir_update(s); 1921 } 1922 1923 static void pxa2xx_fir_event(void *opaque, int event) 1924 { 1925 } 1926 1927 static void pxa2xx_fir_save(QEMUFile *f, void *opaque) 1928 { 1929 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1930 int i; 1931 1932 qemu_put_be32(f, s->enable); 1933 1934 qemu_put_8s(f, &s->control[0]); 1935 qemu_put_8s(f, &s->control[1]); 1936 qemu_put_8s(f, &s->control[2]); 1937 qemu_put_8s(f, &s->status[0]); 1938 qemu_put_8s(f, &s->status[1]); 1939 1940 qemu_put_byte(f, s->rx_len); 1941 for (i = 0; i < s->rx_len; i ++) 1942 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 63]); 1943 } 1944 1945 static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id) 1946 { 1947 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1948 int i; 1949 1950 s->enable = qemu_get_be32(f); 1951 1952 qemu_get_8s(f, &s->control[0]); 1953 qemu_get_8s(f, &s->control[1]); 1954 qemu_get_8s(f, &s->control[2]); 1955 qemu_get_8s(f, &s->status[0]); 1956 qemu_get_8s(f, &s->status[1]); 1957 1958 s->rx_len = qemu_get_byte(f); 1959 s->rx_start = 0; 1960 for (i = 0; i < s->rx_len; i ++) 1961 s->rx_fifo[i] = qemu_get_byte(f); 1962 1963 return 0; 1964 } 1965 1966 static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem, 1967 hwaddr base, 1968 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma, 1969 CharDriverState *chr) 1970 { 1971 PXA2xxFIrState *s = (PXA2xxFIrState *) 1972 g_malloc0(sizeof(PXA2xxFIrState)); 1973 1974 s->irq = irq; 1975 s->rx_dma = rx_dma; 1976 s->tx_dma = tx_dma; 1977 s->chr = chr; 1978 1979 pxa2xx_fir_reset(s); 1980 1981 memory_region_init_io(&s->iomem, NULL, &pxa2xx_fir_ops, s, "pxa2xx-fir", 0x1000); 1982 memory_region_add_subregion(sysmem, base, &s->iomem); 1983 1984 if (chr) { 1985 qemu_chr_fe_claim_no_fail(chr); 1986 qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty, 1987 pxa2xx_fir_rx, pxa2xx_fir_event, s); 1988 } 1989 1990 register_savevm(NULL, "pxa2xx_fir", 0, 0, pxa2xx_fir_save, 1991 pxa2xx_fir_load, s); 1992 1993 return s; 1994 } 1995 1996 static void pxa2xx_reset(void *opaque, int line, int level) 1997 { 1998 PXA2xxState *s = (PXA2xxState *) opaque; 1999 2000 if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */ 2001 cpu_reset(CPU(s->cpu)); 2002 /* TODO: reset peripherals */ 2003 } 2004 } 2005 2006 /* Initialise a PXA270 integrated chip (ARM based core). */ 2007 PXA2xxState *pxa270_init(MemoryRegion *address_space, 2008 unsigned int sdram_size, const char *revision) 2009 { 2010 PXA2xxState *s; 2011 int i; 2012 DriveInfo *dinfo; 2013 s = (PXA2xxState *) g_malloc0(sizeof(PXA2xxState)); 2014 2015 if (revision && strncmp(revision, "pxa27", 5)) { 2016 fprintf(stderr, "Machine requires a PXA27x processor.\n"); 2017 exit(1); 2018 } 2019 if (!revision) 2020 revision = "pxa270"; 2021 2022 s->cpu = cpu_arm_init(revision); 2023 if (s->cpu == NULL) { 2024 fprintf(stderr, "Unable to find CPU definition\n"); 2025 exit(1); 2026 } 2027 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0]; 2028 2029 /* SDRAM & Internal Memory Storage */ 2030 memory_region_init_ram(&s->sdram, NULL, "pxa270.sdram", sdram_size); 2031 vmstate_register_ram_global(&s->sdram); 2032 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram); 2033 memory_region_init_ram(&s->internal, NULL, "pxa270.internal", 0x40000); 2034 vmstate_register_ram_global(&s->internal); 2035 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE, 2036 &s->internal); 2037 2038 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu); 2039 2040 s->dma = pxa27x_dma_init(0x40000000, 2041 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA)); 2042 2043 sysbus_create_varargs("pxa27x-timer", 0x40a00000, 2044 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0), 2045 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1), 2046 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2), 2047 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3), 2048 qdev_get_gpio_in(s->pic, PXA27X_PIC_OST_4_11), 2049 NULL); 2050 2051 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 121); 2052 2053 dinfo = drive_get(IF_SD, 0, 0); 2054 if (!dinfo) { 2055 fprintf(stderr, "qemu: missing SecureDigital device\n"); 2056 exit(1); 2057 } 2058 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, dinfo->bdrv, 2059 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), 2060 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), 2061 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); 2062 2063 for (i = 0; pxa270_serial[i].io_base; i++) { 2064 if (serial_hds[i]) { 2065 serial_mm_init(address_space, pxa270_serial[i].io_base, 2, 2066 qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn), 2067 14857000 / 16, serial_hds[i], 2068 DEVICE_NATIVE_ENDIAN); 2069 } else { 2070 break; 2071 } 2072 } 2073 if (serial_hds[i]) 2074 s->fir = pxa2xx_fir_init(address_space, 0x40800000, 2075 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), 2076 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), 2077 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), 2078 serial_hds[i]); 2079 2080 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000, 2081 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); 2082 2083 s->cm_base = 0x41300000; 2084 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */ 2085 s->clkcfg = 0x00000009; /* Turbo mode active */ 2086 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000); 2087 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); 2088 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); 2089 2090 pxa2xx_setup_cp14(s); 2091 2092 s->mm_base = 0x48000000; 2093 s->mm_regs[MDMRS >> 2] = 0x00020002; 2094 s->mm_regs[MDREFR >> 2] = 0x03ca4000; 2095 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ 2096 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000); 2097 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem); 2098 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s); 2099 2100 s->pm_base = 0x40f00000; 2101 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100); 2102 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem); 2103 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s); 2104 2105 for (i = 0; pxa27x_ssp[i].io_base; i ++); 2106 s->ssp = (SSIBus **)g_malloc0(sizeof(SSIBus *) * i); 2107 for (i = 0; pxa27x_ssp[i].io_base; i ++) { 2108 DeviceState *dev; 2109 dev = sysbus_create_simple("pxa2xx-ssp", pxa27x_ssp[i].io_base, 2110 qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn)); 2111 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi"); 2112 } 2113 2114 if (usb_enabled(false)) { 2115 sysbus_create_simple("sysbus-ohci", 0x4c000000, 2116 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1)); 2117 } 2118 2119 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000); 2120 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000); 2121 2122 sysbus_create_simple("pxa2xx_rtc", 0x40900000, 2123 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM)); 2124 2125 s->i2c[0] = pxa2xx_i2c_init(0x40301600, 2126 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff); 2127 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, 2128 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff); 2129 2130 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000, 2131 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), 2132 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), 2133 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); 2134 2135 s->kp = pxa27x_keypad_init(address_space, 0x41500000, 2136 qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD)); 2137 2138 /* GPIO1 resets the processor */ 2139 /* The handler can be overridden by board-specific code */ 2140 qdev_connect_gpio_out(s->gpio, 1, s->reset); 2141 return s; 2142 } 2143 2144 /* Initialise a PXA255 integrated chip (ARM based core). */ 2145 PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size) 2146 { 2147 PXA2xxState *s; 2148 int i; 2149 DriveInfo *dinfo; 2150 2151 s = (PXA2xxState *) g_malloc0(sizeof(PXA2xxState)); 2152 2153 s->cpu = cpu_arm_init("pxa255"); 2154 if (s->cpu == NULL) { 2155 fprintf(stderr, "Unable to find CPU definition\n"); 2156 exit(1); 2157 } 2158 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0]; 2159 2160 /* SDRAM & Internal Memory Storage */ 2161 memory_region_init_ram(&s->sdram, NULL, "pxa255.sdram", sdram_size); 2162 vmstate_register_ram_global(&s->sdram); 2163 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram); 2164 memory_region_init_ram(&s->internal, NULL, "pxa255.internal", 2165 PXA2XX_INTERNAL_SIZE); 2166 vmstate_register_ram_global(&s->internal); 2167 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE, 2168 &s->internal); 2169 2170 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu); 2171 2172 s->dma = pxa255_dma_init(0x40000000, 2173 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA)); 2174 2175 sysbus_create_varargs("pxa25x-timer", 0x40a00000, 2176 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0), 2177 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1), 2178 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2), 2179 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3), 2180 NULL); 2181 2182 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 85); 2183 2184 dinfo = drive_get(IF_SD, 0, 0); 2185 if (!dinfo) { 2186 fprintf(stderr, "qemu: missing SecureDigital device\n"); 2187 exit(1); 2188 } 2189 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, dinfo->bdrv, 2190 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), 2191 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), 2192 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); 2193 2194 for (i = 0; pxa255_serial[i].io_base; i++) { 2195 if (serial_hds[i]) { 2196 serial_mm_init(address_space, pxa255_serial[i].io_base, 2, 2197 qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn), 2198 14745600 / 16, serial_hds[i], 2199 DEVICE_NATIVE_ENDIAN); 2200 } else { 2201 break; 2202 } 2203 } 2204 if (serial_hds[i]) 2205 s->fir = pxa2xx_fir_init(address_space, 0x40800000, 2206 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), 2207 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), 2208 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), 2209 serial_hds[i]); 2210 2211 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000, 2212 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); 2213 2214 s->cm_base = 0x41300000; 2215 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */ 2216 s->clkcfg = 0x00000009; /* Turbo mode active */ 2217 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000); 2218 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); 2219 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); 2220 2221 pxa2xx_setup_cp14(s); 2222 2223 s->mm_base = 0x48000000; 2224 s->mm_regs[MDMRS >> 2] = 0x00020002; 2225 s->mm_regs[MDREFR >> 2] = 0x03ca4000; 2226 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ 2227 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000); 2228 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem); 2229 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s); 2230 2231 s->pm_base = 0x40f00000; 2232 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100); 2233 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem); 2234 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s); 2235 2236 for (i = 0; pxa255_ssp[i].io_base; i ++); 2237 s->ssp = (SSIBus **)g_malloc0(sizeof(SSIBus *) * i); 2238 for (i = 0; pxa255_ssp[i].io_base; i ++) { 2239 DeviceState *dev; 2240 dev = sysbus_create_simple("pxa2xx-ssp", pxa255_ssp[i].io_base, 2241 qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn)); 2242 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi"); 2243 } 2244 2245 if (usb_enabled(false)) { 2246 sysbus_create_simple("sysbus-ohci", 0x4c000000, 2247 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1)); 2248 } 2249 2250 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000); 2251 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000); 2252 2253 sysbus_create_simple("pxa2xx_rtc", 0x40900000, 2254 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM)); 2255 2256 s->i2c[0] = pxa2xx_i2c_init(0x40301600, 2257 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff); 2258 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, 2259 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff); 2260 2261 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000, 2262 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), 2263 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), 2264 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); 2265 2266 /* GPIO1 resets the processor */ 2267 /* The handler can be overridden by board-specific code */ 2268 qdev_connect_gpio_out(s->gpio, 1, s->reset); 2269 return s; 2270 } 2271 2272 static void pxa2xx_ssp_class_init(ObjectClass *klass, void *data) 2273 { 2274 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 2275 2276 sdc->init = pxa2xx_ssp_init; 2277 } 2278 2279 static const TypeInfo pxa2xx_ssp_info = { 2280 .name = "pxa2xx-ssp", 2281 .parent = TYPE_SYS_BUS_DEVICE, 2282 .instance_size = sizeof(PXA2xxSSPState), 2283 .class_init = pxa2xx_ssp_class_init, 2284 }; 2285 2286 static void pxa2xx_register_types(void) 2287 { 2288 type_register_static(&pxa2xx_i2c_slave_info); 2289 type_register_static(&pxa2xx_ssp_info); 2290 type_register_static(&pxa2xx_i2c_info); 2291 type_register_static(&pxa2xx_rtc_sysbus_info); 2292 } 2293 2294 type_init(pxa2xx_register_types) 2295