1 /* 2 * Intel XScale PXA255/270 processor support. 3 * 4 * Copyright (c) 2006 Openedhand Ltd. 5 * Written by Andrzej Zaborowski <balrog@zabor.org> 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu-common.h" 12 #include "qemu/error-report.h" 13 #include "qemu/module.h" 14 #include "qapi/error.h" 15 #include "cpu.h" 16 #include "hw/sysbus.h" 17 #include "migration/vmstate.h" 18 #include "hw/arm/pxa.h" 19 #include "sysemu/sysemu.h" 20 #include "hw/char/serial.h" 21 #include "hw/i2c/i2c.h" 22 #include "hw/irq.h" 23 #include "hw/qdev-properties.h" 24 #include "hw/ssi/ssi.h" 25 #include "hw/sd/sd.h" 26 #include "chardev/char-fe.h" 27 #include "sysemu/blockdev.h" 28 #include "sysemu/qtest.h" 29 #include "qemu/cutils.h" 30 #include "qemu/log.h" 31 #include "qom/object.h" 32 33 static struct { 34 hwaddr io_base; 35 int irqn; 36 } pxa255_serial[] = { 37 { 0x40100000, PXA2XX_PIC_FFUART }, 38 { 0x40200000, PXA2XX_PIC_BTUART }, 39 { 0x40700000, PXA2XX_PIC_STUART }, 40 { 0x41600000, PXA25X_PIC_HWUART }, 41 { 0, 0 } 42 }, pxa270_serial[] = { 43 { 0x40100000, PXA2XX_PIC_FFUART }, 44 { 0x40200000, PXA2XX_PIC_BTUART }, 45 { 0x40700000, PXA2XX_PIC_STUART }, 46 { 0, 0 } 47 }; 48 49 typedef struct PXASSPDef { 50 hwaddr io_base; 51 int irqn; 52 } PXASSPDef; 53 54 #if 0 55 static PXASSPDef pxa250_ssp[] = { 56 { 0x41000000, PXA2XX_PIC_SSP }, 57 { 0, 0 } 58 }; 59 #endif 60 61 static PXASSPDef pxa255_ssp[] = { 62 { 0x41000000, PXA2XX_PIC_SSP }, 63 { 0x41400000, PXA25X_PIC_NSSP }, 64 { 0, 0 } 65 }; 66 67 #if 0 68 static PXASSPDef pxa26x_ssp[] = { 69 { 0x41000000, PXA2XX_PIC_SSP }, 70 { 0x41400000, PXA25X_PIC_NSSP }, 71 { 0x41500000, PXA26X_PIC_ASSP }, 72 { 0, 0 } 73 }; 74 #endif 75 76 static PXASSPDef pxa27x_ssp[] = { 77 { 0x41000000, PXA2XX_PIC_SSP }, 78 { 0x41700000, PXA27X_PIC_SSP2 }, 79 { 0x41900000, PXA2XX_PIC_SSP3 }, 80 { 0, 0 } 81 }; 82 83 #define PMCR 0x00 /* Power Manager Control register */ 84 #define PSSR 0x04 /* Power Manager Sleep Status register */ 85 #define PSPR 0x08 /* Power Manager Scratch-Pad register */ 86 #define PWER 0x0c /* Power Manager Wake-Up Enable register */ 87 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */ 88 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */ 89 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */ 90 #define PCFR 0x1c /* Power Manager General Configuration register */ 91 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */ 92 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */ 93 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */ 94 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */ 95 #define RCSR 0x30 /* Reset Controller Status register */ 96 #define PSLR 0x34 /* Power Manager Sleep Configuration register */ 97 #define PTSR 0x38 /* Power Manager Standby Configuration register */ 98 #define PVCR 0x40 /* Power Manager Voltage Change Control register */ 99 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */ 100 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */ 101 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */ 102 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */ 103 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */ 104 105 static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr, 106 unsigned size) 107 { 108 PXA2xxState *s = (PXA2xxState *) opaque; 109 110 switch (addr) { 111 case PMCR ... PCMD31: 112 if (addr & 3) 113 goto fail; 114 115 return s->pm_regs[addr >> 2]; 116 default: 117 fail: 118 qemu_log_mask(LOG_GUEST_ERROR, 119 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 120 __func__, addr); 121 break; 122 } 123 return 0; 124 } 125 126 static void pxa2xx_pm_write(void *opaque, hwaddr addr, 127 uint64_t value, unsigned size) 128 { 129 PXA2xxState *s = (PXA2xxState *) opaque; 130 131 switch (addr) { 132 case PMCR: 133 /* Clear the write-one-to-clear bits... */ 134 s->pm_regs[addr >> 2] &= ~(value & 0x2a); 135 /* ...and set the plain r/w bits */ 136 s->pm_regs[addr >> 2] &= ~0x15; 137 s->pm_regs[addr >> 2] |= value & 0x15; 138 break; 139 140 case PSSR: /* Read-clean registers */ 141 case RCSR: 142 case PKSR: 143 s->pm_regs[addr >> 2] &= ~value; 144 break; 145 146 default: /* Read-write registers */ 147 if (!(addr & 3)) { 148 s->pm_regs[addr >> 2] = value; 149 break; 150 } 151 qemu_log_mask(LOG_GUEST_ERROR, 152 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 153 __func__, addr); 154 break; 155 } 156 } 157 158 static const MemoryRegionOps pxa2xx_pm_ops = { 159 .read = pxa2xx_pm_read, 160 .write = pxa2xx_pm_write, 161 .endianness = DEVICE_NATIVE_ENDIAN, 162 }; 163 164 static const VMStateDescription vmstate_pxa2xx_pm = { 165 .name = "pxa2xx_pm", 166 .version_id = 0, 167 .minimum_version_id = 0, 168 .fields = (VMStateField[]) { 169 VMSTATE_UINT32_ARRAY(pm_regs, PXA2xxState, 0x40), 170 VMSTATE_END_OF_LIST() 171 } 172 }; 173 174 #define CCCR 0x00 /* Core Clock Configuration register */ 175 #define CKEN 0x04 /* Clock Enable register */ 176 #define OSCC 0x08 /* Oscillator Configuration register */ 177 #define CCSR 0x0c /* Core Clock Status register */ 178 179 static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr, 180 unsigned size) 181 { 182 PXA2xxState *s = (PXA2xxState *) opaque; 183 184 switch (addr) { 185 case CCCR: 186 case CKEN: 187 case OSCC: 188 return s->cm_regs[addr >> 2]; 189 190 case CCSR: 191 return s->cm_regs[CCCR >> 2] | (3 << 28); 192 193 default: 194 qemu_log_mask(LOG_GUEST_ERROR, 195 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 196 __func__, addr); 197 break; 198 } 199 return 0; 200 } 201 202 static void pxa2xx_cm_write(void *opaque, hwaddr addr, 203 uint64_t value, unsigned size) 204 { 205 PXA2xxState *s = (PXA2xxState *) opaque; 206 207 switch (addr) { 208 case CCCR: 209 case CKEN: 210 s->cm_regs[addr >> 2] = value; 211 break; 212 213 case OSCC: 214 s->cm_regs[addr >> 2] &= ~0x6c; 215 s->cm_regs[addr >> 2] |= value & 0x6e; 216 if ((value >> 1) & 1) /* OON */ 217 s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */ 218 break; 219 220 default: 221 qemu_log_mask(LOG_GUEST_ERROR, 222 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 223 __func__, addr); 224 break; 225 } 226 } 227 228 static const MemoryRegionOps pxa2xx_cm_ops = { 229 .read = pxa2xx_cm_read, 230 .write = pxa2xx_cm_write, 231 .endianness = DEVICE_NATIVE_ENDIAN, 232 }; 233 234 static const VMStateDescription vmstate_pxa2xx_cm = { 235 .name = "pxa2xx_cm", 236 .version_id = 0, 237 .minimum_version_id = 0, 238 .fields = (VMStateField[]) { 239 VMSTATE_UINT32_ARRAY(cm_regs, PXA2xxState, 4), 240 VMSTATE_UINT32(clkcfg, PXA2xxState), 241 VMSTATE_UINT32(pmnc, PXA2xxState), 242 VMSTATE_END_OF_LIST() 243 } 244 }; 245 246 static uint64_t pxa2xx_clkcfg_read(CPUARMState *env, const ARMCPRegInfo *ri) 247 { 248 PXA2xxState *s = (PXA2xxState *)ri->opaque; 249 return s->clkcfg; 250 } 251 252 static void pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri, 253 uint64_t value) 254 { 255 PXA2xxState *s = (PXA2xxState *)ri->opaque; 256 s->clkcfg = value & 0xf; 257 if (value & 2) { 258 printf("%s: CPU frequency change attempt\n", __func__); 259 } 260 } 261 262 static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri, 263 uint64_t value) 264 { 265 PXA2xxState *s = (PXA2xxState *)ri->opaque; 266 static const char *pwrmode[8] = { 267 "Normal", "Idle", "Deep-idle", "Standby", 268 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep", 269 }; 270 271 if (value & 8) { 272 printf("%s: CPU voltage change attempt\n", __func__); 273 } 274 switch (value & 7) { 275 case 0: 276 /* Do nothing */ 277 break; 278 279 case 1: 280 /* Idle */ 281 if (!(s->cm_regs[CCCR >> 2] & (1U << 31))) { /* CPDIS */ 282 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); 283 break; 284 } 285 /* Fall through. */ 286 287 case 2: 288 /* Deep-Idle */ 289 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); 290 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ 291 goto message; 292 293 case 3: 294 s->cpu->env.uncached_cpsr = ARM_CPU_MODE_SVC; 295 s->cpu->env.daif = PSTATE_A | PSTATE_F | PSTATE_I; 296 s->cpu->env.cp15.sctlr_ns = 0; 297 s->cpu->env.cp15.cpacr_el1 = 0; 298 s->cpu->env.cp15.ttbr0_el[1] = 0; 299 s->cpu->env.cp15.dacr_ns = 0; 300 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ 301 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ 302 303 /* 304 * The scratch-pad register is almost universally used 305 * for storing the return address on suspend. For the 306 * lack of a resuming bootloader, perform a jump 307 * directly to that address. 308 */ 309 memset(s->cpu->env.regs, 0, 4 * 15); 310 s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2]; 311 312 #if 0 313 buffer = 0xe59ff000; /* ldr pc, [pc, #0] */ 314 cpu_physical_memory_write(0, &buffer, 4); 315 buffer = s->pm_regs[PSPR >> 2]; 316 cpu_physical_memory_write(8, &buffer, 4); 317 #endif 318 319 /* Suspend */ 320 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); 321 322 goto message; 323 324 default: 325 message: 326 printf("%s: machine entered %s mode\n", __func__, 327 pwrmode[value & 7]); 328 } 329 } 330 331 static uint64_t pxa2xx_cppmnc_read(CPUARMState *env, const ARMCPRegInfo *ri) 332 { 333 PXA2xxState *s = (PXA2xxState *)ri->opaque; 334 return s->pmnc; 335 } 336 337 static void pxa2xx_cppmnc_write(CPUARMState *env, const ARMCPRegInfo *ri, 338 uint64_t value) 339 { 340 PXA2xxState *s = (PXA2xxState *)ri->opaque; 341 s->pmnc = value; 342 } 343 344 static uint64_t pxa2xx_cpccnt_read(CPUARMState *env, const ARMCPRegInfo *ri) 345 { 346 PXA2xxState *s = (PXA2xxState *)ri->opaque; 347 if (s->pmnc & 1) { 348 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 349 } else { 350 return 0; 351 } 352 } 353 354 static const ARMCPRegInfo pxa_cp_reginfo[] = { 355 /* cp14 crm==1: perf registers */ 356 { .name = "CPPMNC", .cp = 14, .crn = 0, .crm = 1, .opc1 = 0, .opc2 = 0, 357 .access = PL1_RW, .type = ARM_CP_IO, 358 .readfn = pxa2xx_cppmnc_read, .writefn = pxa2xx_cppmnc_write }, 359 { .name = "CPCCNT", .cp = 14, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, 360 .access = PL1_RW, .type = ARM_CP_IO, 361 .readfn = pxa2xx_cpccnt_read, .writefn = arm_cp_write_ignore }, 362 { .name = "CPINTEN", .cp = 14, .crn = 4, .crm = 1, .opc1 = 0, .opc2 = 0, 363 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 364 { .name = "CPFLAG", .cp = 14, .crn = 5, .crm = 1, .opc1 = 0, .opc2 = 0, 365 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 366 { .name = "CPEVTSEL", .cp = 14, .crn = 8, .crm = 1, .opc1 = 0, .opc2 = 0, 367 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 368 /* cp14 crm==2: performance count registers */ 369 { .name = "CPPMN0", .cp = 14, .crn = 0, .crm = 2, .opc1 = 0, .opc2 = 0, 370 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 371 { .name = "CPPMN1", .cp = 14, .crn = 1, .crm = 2, .opc1 = 0, .opc2 = 0, 372 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 373 { .name = "CPPMN2", .cp = 14, .crn = 2, .crm = 2, .opc1 = 0, .opc2 = 0, 374 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 375 { .name = "CPPMN3", .cp = 14, .crn = 2, .crm = 3, .opc1 = 0, .opc2 = 0, 376 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 377 /* cp14 crn==6: CLKCFG */ 378 { .name = "CLKCFG", .cp = 14, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, 379 .access = PL1_RW, .type = ARM_CP_IO, 380 .readfn = pxa2xx_clkcfg_read, .writefn = pxa2xx_clkcfg_write }, 381 /* cp14 crn==7: PWRMODE */ 382 { .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0, 383 .access = PL1_RW, .type = ARM_CP_IO, 384 .readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write }, 385 REGINFO_SENTINEL 386 }; 387 388 static void pxa2xx_setup_cp14(PXA2xxState *s) 389 { 390 define_arm_cp_regs_with_opaque(s->cpu, pxa_cp_reginfo, s); 391 } 392 393 #define MDCNFG 0x00 /* SDRAM Configuration register */ 394 #define MDREFR 0x04 /* SDRAM Refresh Control register */ 395 #define MSC0 0x08 /* Static Memory Control register 0 */ 396 #define MSC1 0x0c /* Static Memory Control register 1 */ 397 #define MSC2 0x10 /* Static Memory Control register 2 */ 398 #define MECR 0x14 /* Expansion Memory Bus Config register */ 399 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */ 400 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */ 401 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */ 402 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */ 403 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */ 404 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */ 405 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */ 406 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */ 407 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */ 408 #define ARB_CNTL 0x48 /* Arbiter Control register */ 409 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */ 410 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */ 411 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */ 412 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */ 413 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */ 414 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */ 415 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */ 416 417 static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr, 418 unsigned size) 419 { 420 PXA2xxState *s = (PXA2xxState *) opaque; 421 422 switch (addr) { 423 case MDCNFG ... SA1110: 424 if ((addr & 3) == 0) 425 return s->mm_regs[addr >> 2]; 426 /* fall through */ 427 default: 428 qemu_log_mask(LOG_GUEST_ERROR, 429 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 430 __func__, addr); 431 break; 432 } 433 return 0; 434 } 435 436 static void pxa2xx_mm_write(void *opaque, hwaddr addr, 437 uint64_t value, unsigned size) 438 { 439 PXA2xxState *s = (PXA2xxState *) opaque; 440 441 switch (addr) { 442 case MDCNFG ... SA1110: 443 if ((addr & 3) == 0) { 444 s->mm_regs[addr >> 2] = value; 445 break; 446 } 447 /* fallthrough */ 448 default: 449 qemu_log_mask(LOG_GUEST_ERROR, 450 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 451 __func__, addr); 452 break; 453 } 454 } 455 456 static const MemoryRegionOps pxa2xx_mm_ops = { 457 .read = pxa2xx_mm_read, 458 .write = pxa2xx_mm_write, 459 .endianness = DEVICE_NATIVE_ENDIAN, 460 }; 461 462 static const VMStateDescription vmstate_pxa2xx_mm = { 463 .name = "pxa2xx_mm", 464 .version_id = 0, 465 .minimum_version_id = 0, 466 .fields = (VMStateField[]) { 467 VMSTATE_UINT32_ARRAY(mm_regs, PXA2xxState, 0x1a), 468 VMSTATE_END_OF_LIST() 469 } 470 }; 471 472 #define TYPE_PXA2XX_SSP "pxa2xx-ssp" 473 OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxSSPState, PXA2XX_SSP) 474 475 /* Synchronous Serial Ports */ 476 struct PXA2xxSSPState { 477 /*< private >*/ 478 SysBusDevice parent_obj; 479 /*< public >*/ 480 481 MemoryRegion iomem; 482 qemu_irq irq; 483 uint32_t enable; 484 SSIBus *bus; 485 486 uint32_t sscr[2]; 487 uint32_t sspsp; 488 uint32_t ssto; 489 uint32_t ssitr; 490 uint32_t sssr; 491 uint8_t sstsa; 492 uint8_t ssrsa; 493 uint8_t ssacd; 494 495 uint32_t rx_fifo[16]; 496 uint32_t rx_level; 497 uint32_t rx_start; 498 }; 499 500 static bool pxa2xx_ssp_vmstate_validate(void *opaque, int version_id) 501 { 502 PXA2xxSSPState *s = opaque; 503 504 return s->rx_start < sizeof(s->rx_fifo); 505 } 506 507 static const VMStateDescription vmstate_pxa2xx_ssp = { 508 .name = "pxa2xx-ssp", 509 .version_id = 1, 510 .minimum_version_id = 1, 511 .fields = (VMStateField[]) { 512 VMSTATE_UINT32(enable, PXA2xxSSPState), 513 VMSTATE_UINT32_ARRAY(sscr, PXA2xxSSPState, 2), 514 VMSTATE_UINT32(sspsp, PXA2xxSSPState), 515 VMSTATE_UINT32(ssto, PXA2xxSSPState), 516 VMSTATE_UINT32(ssitr, PXA2xxSSPState), 517 VMSTATE_UINT32(sssr, PXA2xxSSPState), 518 VMSTATE_UINT8(sstsa, PXA2xxSSPState), 519 VMSTATE_UINT8(ssrsa, PXA2xxSSPState), 520 VMSTATE_UINT8(ssacd, PXA2xxSSPState), 521 VMSTATE_UINT32(rx_level, PXA2xxSSPState), 522 VMSTATE_UINT32(rx_start, PXA2xxSSPState), 523 VMSTATE_VALIDATE("fifo is 16 bytes", pxa2xx_ssp_vmstate_validate), 524 VMSTATE_UINT32_ARRAY(rx_fifo, PXA2xxSSPState, 16), 525 VMSTATE_END_OF_LIST() 526 } 527 }; 528 529 #define SSCR0 0x00 /* SSP Control register 0 */ 530 #define SSCR1 0x04 /* SSP Control register 1 */ 531 #define SSSR 0x08 /* SSP Status register */ 532 #define SSITR 0x0c /* SSP Interrupt Test register */ 533 #define SSDR 0x10 /* SSP Data register */ 534 #define SSTO 0x28 /* SSP Time-Out register */ 535 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */ 536 #define SSTSA 0x30 /* SSP TX Time Slot Active register */ 537 #define SSRSA 0x34 /* SSP RX Time Slot Active register */ 538 #define SSTSS 0x38 /* SSP Time Slot Status register */ 539 #define SSACD 0x3c /* SSP Audio Clock Divider register */ 540 541 /* Bitfields for above registers */ 542 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00) 543 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10) 544 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20) 545 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30) 546 #define SSCR0_SSE (1 << 7) 547 #define SSCR0_RIM (1 << 22) 548 #define SSCR0_TIM (1 << 23) 549 #define SSCR0_MOD (1U << 31) 550 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1) 551 #define SSCR1_RIE (1 << 0) 552 #define SSCR1_TIE (1 << 1) 553 #define SSCR1_LBM (1 << 2) 554 #define SSCR1_MWDS (1 << 5) 555 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1) 556 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1) 557 #define SSCR1_EFWR (1 << 14) 558 #define SSCR1_PINTE (1 << 18) 559 #define SSCR1_TINTE (1 << 19) 560 #define SSCR1_RSRE (1 << 20) 561 #define SSCR1_TSRE (1 << 21) 562 #define SSCR1_EBCEI (1 << 29) 563 #define SSITR_INT (7 << 5) 564 #define SSSR_TNF (1 << 2) 565 #define SSSR_RNE (1 << 3) 566 #define SSSR_TFS (1 << 5) 567 #define SSSR_RFS (1 << 6) 568 #define SSSR_ROR (1 << 7) 569 #define SSSR_PINT (1 << 18) 570 #define SSSR_TINT (1 << 19) 571 #define SSSR_EOC (1 << 20) 572 #define SSSR_TUR (1 << 21) 573 #define SSSR_BCE (1 << 23) 574 #define SSSR_RW 0x00bc0080 575 576 static void pxa2xx_ssp_int_update(PXA2xxSSPState *s) 577 { 578 int level = 0; 579 580 level |= s->ssitr & SSITR_INT; 581 level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI); 582 level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM); 583 level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT)); 584 level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE); 585 level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE); 586 level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM); 587 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE); 588 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE); 589 qemu_set_irq(s->irq, !!level); 590 } 591 592 static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s) 593 { 594 s->sssr &= ~(0xf << 12); /* Clear RFL */ 595 s->sssr &= ~(0xf << 8); /* Clear TFL */ 596 s->sssr &= ~SSSR_TFS; 597 s->sssr &= ~SSSR_TNF; 598 if (s->enable) { 599 s->sssr |= ((s->rx_level - 1) & 0xf) << 12; 600 if (s->rx_level >= SSCR1_RFT(s->sscr[1])) 601 s->sssr |= SSSR_RFS; 602 else 603 s->sssr &= ~SSSR_RFS; 604 if (s->rx_level) 605 s->sssr |= SSSR_RNE; 606 else 607 s->sssr &= ~SSSR_RNE; 608 /* TX FIFO is never filled, so it is always in underrun 609 condition if SSP is enabled */ 610 s->sssr |= SSSR_TFS; 611 s->sssr |= SSSR_TNF; 612 } 613 614 pxa2xx_ssp_int_update(s); 615 } 616 617 static uint64_t pxa2xx_ssp_read(void *opaque, hwaddr addr, 618 unsigned size) 619 { 620 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; 621 uint32_t retval; 622 623 switch (addr) { 624 case SSCR0: 625 return s->sscr[0]; 626 case SSCR1: 627 return s->sscr[1]; 628 case SSPSP: 629 return s->sspsp; 630 case SSTO: 631 return s->ssto; 632 case SSITR: 633 return s->ssitr; 634 case SSSR: 635 return s->sssr | s->ssitr; 636 case SSDR: 637 if (!s->enable) 638 return 0xffffffff; 639 if (s->rx_level < 1) { 640 printf("%s: SSP Rx Underrun\n", __func__); 641 return 0xffffffff; 642 } 643 s->rx_level --; 644 retval = s->rx_fifo[s->rx_start ++]; 645 s->rx_start &= 0xf; 646 pxa2xx_ssp_fifo_update(s); 647 return retval; 648 case SSTSA: 649 return s->sstsa; 650 case SSRSA: 651 return s->ssrsa; 652 case SSTSS: 653 return 0; 654 case SSACD: 655 return s->ssacd; 656 default: 657 qemu_log_mask(LOG_GUEST_ERROR, 658 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 659 __func__, addr); 660 break; 661 } 662 return 0; 663 } 664 665 static void pxa2xx_ssp_write(void *opaque, hwaddr addr, 666 uint64_t value64, unsigned size) 667 { 668 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; 669 uint32_t value = value64; 670 671 switch (addr) { 672 case SSCR0: 673 s->sscr[0] = value & 0xc7ffffff; 674 s->enable = value & SSCR0_SSE; 675 if (value & SSCR0_MOD) 676 printf("%s: Attempt to use network mode\n", __func__); 677 if (s->enable && SSCR0_DSS(value) < 4) 678 printf("%s: Wrong data size: %u bits\n", __func__, 679 SSCR0_DSS(value)); 680 if (!(value & SSCR0_SSE)) { 681 s->sssr = 0; 682 s->ssitr = 0; 683 s->rx_level = 0; 684 } 685 pxa2xx_ssp_fifo_update(s); 686 break; 687 688 case SSCR1: 689 s->sscr[1] = value; 690 if (value & (SSCR1_LBM | SSCR1_EFWR)) 691 printf("%s: Attempt to use SSP test mode\n", __func__); 692 pxa2xx_ssp_fifo_update(s); 693 break; 694 695 case SSPSP: 696 s->sspsp = value; 697 break; 698 699 case SSTO: 700 s->ssto = value; 701 break; 702 703 case SSITR: 704 s->ssitr = value & SSITR_INT; 705 pxa2xx_ssp_int_update(s); 706 break; 707 708 case SSSR: 709 s->sssr &= ~(value & SSSR_RW); 710 pxa2xx_ssp_int_update(s); 711 break; 712 713 case SSDR: 714 if (SSCR0_UWIRE(s->sscr[0])) { 715 if (s->sscr[1] & SSCR1_MWDS) 716 value &= 0xffff; 717 else 718 value &= 0xff; 719 } else 720 /* Note how 32bits overflow does no harm here */ 721 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1; 722 723 /* Data goes from here to the Tx FIFO and is shifted out from 724 * there directly to the slave, no need to buffer it. 725 */ 726 if (s->enable) { 727 uint32_t readval; 728 readval = ssi_transfer(s->bus, value); 729 if (s->rx_level < 0x10) { 730 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval; 731 } else { 732 s->sssr |= SSSR_ROR; 733 } 734 } 735 pxa2xx_ssp_fifo_update(s); 736 break; 737 738 case SSTSA: 739 s->sstsa = value; 740 break; 741 742 case SSRSA: 743 s->ssrsa = value; 744 break; 745 746 case SSACD: 747 s->ssacd = value; 748 break; 749 750 default: 751 qemu_log_mask(LOG_GUEST_ERROR, 752 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 753 __func__, addr); 754 break; 755 } 756 } 757 758 static const MemoryRegionOps pxa2xx_ssp_ops = { 759 .read = pxa2xx_ssp_read, 760 .write = pxa2xx_ssp_write, 761 .endianness = DEVICE_NATIVE_ENDIAN, 762 }; 763 764 static void pxa2xx_ssp_reset(DeviceState *d) 765 { 766 PXA2xxSSPState *s = PXA2XX_SSP(d); 767 768 s->enable = 0; 769 s->sscr[0] = s->sscr[1] = 0; 770 s->sspsp = 0; 771 s->ssto = 0; 772 s->ssitr = 0; 773 s->sssr = 0; 774 s->sstsa = 0; 775 s->ssrsa = 0; 776 s->ssacd = 0; 777 s->rx_start = s->rx_level = 0; 778 } 779 780 static void pxa2xx_ssp_init(Object *obj) 781 { 782 DeviceState *dev = DEVICE(obj); 783 PXA2xxSSPState *s = PXA2XX_SSP(obj); 784 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 785 sysbus_init_irq(sbd, &s->irq); 786 787 memory_region_init_io(&s->iomem, obj, &pxa2xx_ssp_ops, s, 788 "pxa2xx-ssp", 0x1000); 789 sysbus_init_mmio(sbd, &s->iomem); 790 791 s->bus = ssi_create_bus(dev, "ssi"); 792 } 793 794 /* Real-Time Clock */ 795 #define RCNR 0x00 /* RTC Counter register */ 796 #define RTAR 0x04 /* RTC Alarm register */ 797 #define RTSR 0x08 /* RTC Status register */ 798 #define RTTR 0x0c /* RTC Timer Trim register */ 799 #define RDCR 0x10 /* RTC Day Counter register */ 800 #define RYCR 0x14 /* RTC Year Counter register */ 801 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */ 802 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */ 803 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */ 804 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */ 805 #define SWCR 0x28 /* RTC Stopwatch Counter register */ 806 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */ 807 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */ 808 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */ 809 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */ 810 811 #define TYPE_PXA2XX_RTC "pxa2xx_rtc" 812 OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxRTCState, PXA2XX_RTC) 813 814 struct PXA2xxRTCState { 815 /*< private >*/ 816 SysBusDevice parent_obj; 817 /*< public >*/ 818 819 MemoryRegion iomem; 820 uint32_t rttr; 821 uint32_t rtsr; 822 uint32_t rtar; 823 uint32_t rdar1; 824 uint32_t rdar2; 825 uint32_t ryar1; 826 uint32_t ryar2; 827 uint32_t swar1; 828 uint32_t swar2; 829 uint32_t piar; 830 uint32_t last_rcnr; 831 uint32_t last_rdcr; 832 uint32_t last_rycr; 833 uint32_t last_swcr; 834 uint32_t last_rtcpicr; 835 int64_t last_hz; 836 int64_t last_sw; 837 int64_t last_pi; 838 QEMUTimer *rtc_hz; 839 QEMUTimer *rtc_rdal1; 840 QEMUTimer *rtc_rdal2; 841 QEMUTimer *rtc_swal1; 842 QEMUTimer *rtc_swal2; 843 QEMUTimer *rtc_pi; 844 qemu_irq rtc_irq; 845 }; 846 847 static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s) 848 { 849 qemu_set_irq(s->rtc_irq, !!(s->rtsr & 0x2553)); 850 } 851 852 static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s) 853 { 854 int64_t rt = qemu_clock_get_ms(rtc_clock); 855 s->last_rcnr += ((rt - s->last_hz) << 15) / 856 (1000 * ((s->rttr & 0xffff) + 1)); 857 s->last_rdcr += ((rt - s->last_hz) << 15) / 858 (1000 * ((s->rttr & 0xffff) + 1)); 859 s->last_hz = rt; 860 } 861 862 static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s) 863 { 864 int64_t rt = qemu_clock_get_ms(rtc_clock); 865 if (s->rtsr & (1 << 12)) 866 s->last_swcr += (rt - s->last_sw) / 10; 867 s->last_sw = rt; 868 } 869 870 static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s) 871 { 872 int64_t rt = qemu_clock_get_ms(rtc_clock); 873 if (s->rtsr & (1 << 15)) 874 s->last_swcr += rt - s->last_pi; 875 s->last_pi = rt; 876 } 877 878 static inline void pxa2xx_rtc_alarm_update(PXA2xxRTCState *s, 879 uint32_t rtsr) 880 { 881 if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0))) 882 timer_mod(s->rtc_hz, s->last_hz + 883 (((s->rtar - s->last_rcnr) * 1000 * 884 ((s->rttr & 0xffff) + 1)) >> 15)); 885 else 886 timer_del(s->rtc_hz); 887 888 if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4))) 889 timer_mod(s->rtc_rdal1, s->last_hz + 890 (((s->rdar1 - s->last_rdcr) * 1000 * 891 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */ 892 else 893 timer_del(s->rtc_rdal1); 894 895 if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6))) 896 timer_mod(s->rtc_rdal2, s->last_hz + 897 (((s->rdar2 - s->last_rdcr) * 1000 * 898 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */ 899 else 900 timer_del(s->rtc_rdal2); 901 902 if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8))) 903 timer_mod(s->rtc_swal1, s->last_sw + 904 (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */ 905 else 906 timer_del(s->rtc_swal1); 907 908 if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10))) 909 timer_mod(s->rtc_swal2, s->last_sw + 910 (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */ 911 else 912 timer_del(s->rtc_swal2); 913 914 if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13))) 915 timer_mod(s->rtc_pi, s->last_pi + 916 (s->piar & 0xffff) - s->last_rtcpicr); 917 else 918 timer_del(s->rtc_pi); 919 } 920 921 static inline void pxa2xx_rtc_hz_tick(void *opaque) 922 { 923 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 924 s->rtsr |= (1 << 0); 925 pxa2xx_rtc_alarm_update(s, s->rtsr); 926 pxa2xx_rtc_int_update(s); 927 } 928 929 static inline void pxa2xx_rtc_rdal1_tick(void *opaque) 930 { 931 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 932 s->rtsr |= (1 << 4); 933 pxa2xx_rtc_alarm_update(s, s->rtsr); 934 pxa2xx_rtc_int_update(s); 935 } 936 937 static inline void pxa2xx_rtc_rdal2_tick(void *opaque) 938 { 939 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 940 s->rtsr |= (1 << 6); 941 pxa2xx_rtc_alarm_update(s, s->rtsr); 942 pxa2xx_rtc_int_update(s); 943 } 944 945 static inline void pxa2xx_rtc_swal1_tick(void *opaque) 946 { 947 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 948 s->rtsr |= (1 << 8); 949 pxa2xx_rtc_alarm_update(s, s->rtsr); 950 pxa2xx_rtc_int_update(s); 951 } 952 953 static inline void pxa2xx_rtc_swal2_tick(void *opaque) 954 { 955 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 956 s->rtsr |= (1 << 10); 957 pxa2xx_rtc_alarm_update(s, s->rtsr); 958 pxa2xx_rtc_int_update(s); 959 } 960 961 static inline void pxa2xx_rtc_pi_tick(void *opaque) 962 { 963 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 964 s->rtsr |= (1 << 13); 965 pxa2xx_rtc_piupdate(s); 966 s->last_rtcpicr = 0; 967 pxa2xx_rtc_alarm_update(s, s->rtsr); 968 pxa2xx_rtc_int_update(s); 969 } 970 971 static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr, 972 unsigned size) 973 { 974 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 975 976 switch (addr) { 977 case RTTR: 978 return s->rttr; 979 case RTSR: 980 return s->rtsr; 981 case RTAR: 982 return s->rtar; 983 case RDAR1: 984 return s->rdar1; 985 case RDAR2: 986 return s->rdar2; 987 case RYAR1: 988 return s->ryar1; 989 case RYAR2: 990 return s->ryar2; 991 case SWAR1: 992 return s->swar1; 993 case SWAR2: 994 return s->swar2; 995 case PIAR: 996 return s->piar; 997 case RCNR: 998 return s->last_rcnr + 999 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / 1000 (1000 * ((s->rttr & 0xffff) + 1)); 1001 case RDCR: 1002 return s->last_rdcr + 1003 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / 1004 (1000 * ((s->rttr & 0xffff) + 1)); 1005 case RYCR: 1006 return s->last_rycr; 1007 case SWCR: 1008 if (s->rtsr & (1 << 12)) 1009 return s->last_swcr + 1010 (qemu_clock_get_ms(rtc_clock) - s->last_sw) / 10; 1011 else 1012 return s->last_swcr; 1013 default: 1014 qemu_log_mask(LOG_GUEST_ERROR, 1015 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 1016 __func__, addr); 1017 break; 1018 } 1019 return 0; 1020 } 1021 1022 static void pxa2xx_rtc_write(void *opaque, hwaddr addr, 1023 uint64_t value64, unsigned size) 1024 { 1025 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 1026 uint32_t value = value64; 1027 1028 switch (addr) { 1029 case RTTR: 1030 if (!(s->rttr & (1U << 31))) { 1031 pxa2xx_rtc_hzupdate(s); 1032 s->rttr = value; 1033 pxa2xx_rtc_alarm_update(s, s->rtsr); 1034 } 1035 break; 1036 1037 case RTSR: 1038 if ((s->rtsr ^ value) & (1 << 15)) 1039 pxa2xx_rtc_piupdate(s); 1040 1041 if ((s->rtsr ^ value) & (1 << 12)) 1042 pxa2xx_rtc_swupdate(s); 1043 1044 if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac)) 1045 pxa2xx_rtc_alarm_update(s, value); 1046 1047 s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac)); 1048 pxa2xx_rtc_int_update(s); 1049 break; 1050 1051 case RTAR: 1052 s->rtar = value; 1053 pxa2xx_rtc_alarm_update(s, s->rtsr); 1054 break; 1055 1056 case RDAR1: 1057 s->rdar1 = value; 1058 pxa2xx_rtc_alarm_update(s, s->rtsr); 1059 break; 1060 1061 case RDAR2: 1062 s->rdar2 = value; 1063 pxa2xx_rtc_alarm_update(s, s->rtsr); 1064 break; 1065 1066 case RYAR1: 1067 s->ryar1 = value; 1068 pxa2xx_rtc_alarm_update(s, s->rtsr); 1069 break; 1070 1071 case RYAR2: 1072 s->ryar2 = value; 1073 pxa2xx_rtc_alarm_update(s, s->rtsr); 1074 break; 1075 1076 case SWAR1: 1077 pxa2xx_rtc_swupdate(s); 1078 s->swar1 = value; 1079 s->last_swcr = 0; 1080 pxa2xx_rtc_alarm_update(s, s->rtsr); 1081 break; 1082 1083 case SWAR2: 1084 s->swar2 = value; 1085 pxa2xx_rtc_alarm_update(s, s->rtsr); 1086 break; 1087 1088 case PIAR: 1089 s->piar = value; 1090 pxa2xx_rtc_alarm_update(s, s->rtsr); 1091 break; 1092 1093 case RCNR: 1094 pxa2xx_rtc_hzupdate(s); 1095 s->last_rcnr = value; 1096 pxa2xx_rtc_alarm_update(s, s->rtsr); 1097 break; 1098 1099 case RDCR: 1100 pxa2xx_rtc_hzupdate(s); 1101 s->last_rdcr = value; 1102 pxa2xx_rtc_alarm_update(s, s->rtsr); 1103 break; 1104 1105 case RYCR: 1106 s->last_rycr = value; 1107 break; 1108 1109 case SWCR: 1110 pxa2xx_rtc_swupdate(s); 1111 s->last_swcr = value; 1112 pxa2xx_rtc_alarm_update(s, s->rtsr); 1113 break; 1114 1115 case RTCPICR: 1116 pxa2xx_rtc_piupdate(s); 1117 s->last_rtcpicr = value & 0xffff; 1118 pxa2xx_rtc_alarm_update(s, s->rtsr); 1119 break; 1120 1121 default: 1122 qemu_log_mask(LOG_GUEST_ERROR, 1123 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 1124 __func__, addr); 1125 } 1126 } 1127 1128 static const MemoryRegionOps pxa2xx_rtc_ops = { 1129 .read = pxa2xx_rtc_read, 1130 .write = pxa2xx_rtc_write, 1131 .endianness = DEVICE_NATIVE_ENDIAN, 1132 }; 1133 1134 static void pxa2xx_rtc_init(Object *obj) 1135 { 1136 PXA2xxRTCState *s = PXA2XX_RTC(obj); 1137 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 1138 struct tm tm; 1139 int wom; 1140 1141 s->rttr = 0x7fff; 1142 s->rtsr = 0; 1143 1144 qemu_get_timedate(&tm, 0); 1145 wom = ((tm.tm_mday - 1) / 7) + 1; 1146 1147 s->last_rcnr = (uint32_t) mktimegm(&tm); 1148 s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) | 1149 (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec; 1150 s->last_rycr = ((tm.tm_year + 1900) << 9) | 1151 ((tm.tm_mon + 1) << 5) | tm.tm_mday; 1152 s->last_swcr = (tm.tm_hour << 19) | 1153 (tm.tm_min << 13) | (tm.tm_sec << 7); 1154 s->last_rtcpicr = 0; 1155 s->last_hz = s->last_sw = s->last_pi = qemu_clock_get_ms(rtc_clock); 1156 1157 sysbus_init_irq(dev, &s->rtc_irq); 1158 1159 memory_region_init_io(&s->iomem, obj, &pxa2xx_rtc_ops, s, 1160 "pxa2xx-rtc", 0x10000); 1161 sysbus_init_mmio(dev, &s->iomem); 1162 } 1163 1164 static void pxa2xx_rtc_realize(DeviceState *dev, Error **errp) 1165 { 1166 PXA2xxRTCState *s = PXA2XX_RTC(dev); 1167 s->rtc_hz = timer_new_ms(rtc_clock, pxa2xx_rtc_hz_tick, s); 1168 s->rtc_rdal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal1_tick, s); 1169 s->rtc_rdal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal2_tick, s); 1170 s->rtc_swal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal1_tick, s); 1171 s->rtc_swal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal2_tick, s); 1172 s->rtc_pi = timer_new_ms(rtc_clock, pxa2xx_rtc_pi_tick, s); 1173 } 1174 1175 static int pxa2xx_rtc_pre_save(void *opaque) 1176 { 1177 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 1178 1179 pxa2xx_rtc_hzupdate(s); 1180 pxa2xx_rtc_piupdate(s); 1181 pxa2xx_rtc_swupdate(s); 1182 1183 return 0; 1184 } 1185 1186 static int pxa2xx_rtc_post_load(void *opaque, int version_id) 1187 { 1188 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 1189 1190 pxa2xx_rtc_alarm_update(s, s->rtsr); 1191 1192 return 0; 1193 } 1194 1195 static const VMStateDescription vmstate_pxa2xx_rtc_regs = { 1196 .name = "pxa2xx_rtc", 1197 .version_id = 0, 1198 .minimum_version_id = 0, 1199 .pre_save = pxa2xx_rtc_pre_save, 1200 .post_load = pxa2xx_rtc_post_load, 1201 .fields = (VMStateField[]) { 1202 VMSTATE_UINT32(rttr, PXA2xxRTCState), 1203 VMSTATE_UINT32(rtsr, PXA2xxRTCState), 1204 VMSTATE_UINT32(rtar, PXA2xxRTCState), 1205 VMSTATE_UINT32(rdar1, PXA2xxRTCState), 1206 VMSTATE_UINT32(rdar2, PXA2xxRTCState), 1207 VMSTATE_UINT32(ryar1, PXA2xxRTCState), 1208 VMSTATE_UINT32(ryar2, PXA2xxRTCState), 1209 VMSTATE_UINT32(swar1, PXA2xxRTCState), 1210 VMSTATE_UINT32(swar2, PXA2xxRTCState), 1211 VMSTATE_UINT32(piar, PXA2xxRTCState), 1212 VMSTATE_UINT32(last_rcnr, PXA2xxRTCState), 1213 VMSTATE_UINT32(last_rdcr, PXA2xxRTCState), 1214 VMSTATE_UINT32(last_rycr, PXA2xxRTCState), 1215 VMSTATE_UINT32(last_swcr, PXA2xxRTCState), 1216 VMSTATE_UINT32(last_rtcpicr, PXA2xxRTCState), 1217 VMSTATE_INT64(last_hz, PXA2xxRTCState), 1218 VMSTATE_INT64(last_sw, PXA2xxRTCState), 1219 VMSTATE_INT64(last_pi, PXA2xxRTCState), 1220 VMSTATE_END_OF_LIST(), 1221 }, 1222 }; 1223 1224 static void pxa2xx_rtc_sysbus_class_init(ObjectClass *klass, void *data) 1225 { 1226 DeviceClass *dc = DEVICE_CLASS(klass); 1227 1228 dc->desc = "PXA2xx RTC Controller"; 1229 dc->vmsd = &vmstate_pxa2xx_rtc_regs; 1230 dc->realize = pxa2xx_rtc_realize; 1231 } 1232 1233 static const TypeInfo pxa2xx_rtc_sysbus_info = { 1234 .name = TYPE_PXA2XX_RTC, 1235 .parent = TYPE_SYS_BUS_DEVICE, 1236 .instance_size = sizeof(PXA2xxRTCState), 1237 .instance_init = pxa2xx_rtc_init, 1238 .class_init = pxa2xx_rtc_sysbus_class_init, 1239 }; 1240 1241 /* I2C Interface */ 1242 1243 #define TYPE_PXA2XX_I2C_SLAVE "pxa2xx-i2c-slave" 1244 OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxI2CSlaveState, PXA2XX_I2C_SLAVE) 1245 1246 struct PXA2xxI2CSlaveState { 1247 I2CSlave parent_obj; 1248 1249 PXA2xxI2CState *host; 1250 }; 1251 1252 struct PXA2xxI2CState { 1253 /*< private >*/ 1254 SysBusDevice parent_obj; 1255 /*< public >*/ 1256 1257 MemoryRegion iomem; 1258 PXA2xxI2CSlaveState *slave; 1259 I2CBus *bus; 1260 qemu_irq irq; 1261 uint32_t offset; 1262 uint32_t region_size; 1263 1264 uint16_t control; 1265 uint16_t status; 1266 uint8_t ibmr; 1267 uint8_t data; 1268 }; 1269 1270 #define IBMR 0x80 /* I2C Bus Monitor register */ 1271 #define IDBR 0x88 /* I2C Data Buffer register */ 1272 #define ICR 0x90 /* I2C Control register */ 1273 #define ISR 0x98 /* I2C Status register */ 1274 #define ISAR 0xa0 /* I2C Slave Address register */ 1275 1276 static void pxa2xx_i2c_update(PXA2xxI2CState *s) 1277 { 1278 uint16_t level = 0; 1279 level |= s->status & s->control & (1 << 10); /* BED */ 1280 level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */ 1281 level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */ 1282 level |= s->status & (1 << 9); /* SAD */ 1283 qemu_set_irq(s->irq, !!level); 1284 } 1285 1286 /* These are only stubs now. */ 1287 static int pxa2xx_i2c_event(I2CSlave *i2c, enum i2c_event event) 1288 { 1289 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c); 1290 PXA2xxI2CState *s = slave->host; 1291 1292 switch (event) { 1293 case I2C_START_SEND: 1294 s->status |= (1 << 9); /* set SAD */ 1295 s->status &= ~(1 << 0); /* clear RWM */ 1296 break; 1297 case I2C_START_RECV: 1298 s->status |= (1 << 9); /* set SAD */ 1299 s->status |= 1 << 0; /* set RWM */ 1300 break; 1301 case I2C_FINISH: 1302 s->status |= (1 << 4); /* set SSD */ 1303 break; 1304 case I2C_NACK: 1305 s->status |= 1 << 1; /* set ACKNAK */ 1306 break; 1307 } 1308 pxa2xx_i2c_update(s); 1309 1310 return 0; 1311 } 1312 1313 static uint8_t pxa2xx_i2c_rx(I2CSlave *i2c) 1314 { 1315 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c); 1316 PXA2xxI2CState *s = slave->host; 1317 1318 if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) { 1319 return 0; 1320 } 1321 1322 if (s->status & (1 << 0)) { /* RWM */ 1323 s->status |= 1 << 6; /* set ITE */ 1324 } 1325 pxa2xx_i2c_update(s); 1326 1327 return s->data; 1328 } 1329 1330 static int pxa2xx_i2c_tx(I2CSlave *i2c, uint8_t data) 1331 { 1332 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c); 1333 PXA2xxI2CState *s = slave->host; 1334 1335 if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) { 1336 return 1; 1337 } 1338 1339 if (!(s->status & (1 << 0))) { /* RWM */ 1340 s->status |= 1 << 7; /* set IRF */ 1341 s->data = data; 1342 } 1343 pxa2xx_i2c_update(s); 1344 1345 return 1; 1346 } 1347 1348 static uint64_t pxa2xx_i2c_read(void *opaque, hwaddr addr, 1349 unsigned size) 1350 { 1351 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; 1352 I2CSlave *slave; 1353 1354 addr -= s->offset; 1355 switch (addr) { 1356 case ICR: 1357 return s->control; 1358 case ISR: 1359 return s->status | (i2c_bus_busy(s->bus) << 2); 1360 case ISAR: 1361 slave = I2C_SLAVE(s->slave); 1362 return slave->address; 1363 case IDBR: 1364 return s->data; 1365 case IBMR: 1366 if (s->status & (1 << 2)) 1367 s->ibmr ^= 3; /* Fake SCL and SDA pin changes */ 1368 else 1369 s->ibmr = 0; 1370 return s->ibmr; 1371 default: 1372 qemu_log_mask(LOG_GUEST_ERROR, 1373 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 1374 __func__, addr); 1375 break; 1376 } 1377 return 0; 1378 } 1379 1380 static void pxa2xx_i2c_write(void *opaque, hwaddr addr, 1381 uint64_t value64, unsigned size) 1382 { 1383 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; 1384 uint32_t value = value64; 1385 int ack; 1386 1387 addr -= s->offset; 1388 switch (addr) { 1389 case ICR: 1390 s->control = value & 0xfff7; 1391 if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */ 1392 /* TODO: slave mode */ 1393 if (value & (1 << 0)) { /* START condition */ 1394 if (s->data & 1) 1395 s->status |= 1 << 0; /* set RWM */ 1396 else 1397 s->status &= ~(1 << 0); /* clear RWM */ 1398 ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1); 1399 } else { 1400 if (s->status & (1 << 0)) { /* RWM */ 1401 s->data = i2c_recv(s->bus); 1402 if (value & (1 << 2)) /* ACKNAK */ 1403 i2c_nack(s->bus); 1404 ack = 1; 1405 } else 1406 ack = !i2c_send(s->bus, s->data); 1407 } 1408 1409 if (value & (1 << 1)) /* STOP condition */ 1410 i2c_end_transfer(s->bus); 1411 1412 if (ack) { 1413 if (value & (1 << 0)) /* START condition */ 1414 s->status |= 1 << 6; /* set ITE */ 1415 else 1416 if (s->status & (1 << 0)) /* RWM */ 1417 s->status |= 1 << 7; /* set IRF */ 1418 else 1419 s->status |= 1 << 6; /* set ITE */ 1420 s->status &= ~(1 << 1); /* clear ACKNAK */ 1421 } else { 1422 s->status |= 1 << 6; /* set ITE */ 1423 s->status |= 1 << 10; /* set BED */ 1424 s->status |= 1 << 1; /* set ACKNAK */ 1425 } 1426 } 1427 if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */ 1428 if (value & (1 << 4)) /* MA */ 1429 i2c_end_transfer(s->bus); 1430 pxa2xx_i2c_update(s); 1431 break; 1432 1433 case ISR: 1434 s->status &= ~(value & 0x07f0); 1435 pxa2xx_i2c_update(s); 1436 break; 1437 1438 case ISAR: 1439 i2c_set_slave_address(I2C_SLAVE(s->slave), value & 0x7f); 1440 break; 1441 1442 case IDBR: 1443 s->data = value & 0xff; 1444 break; 1445 1446 default: 1447 qemu_log_mask(LOG_GUEST_ERROR, 1448 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 1449 __func__, addr); 1450 } 1451 } 1452 1453 static const MemoryRegionOps pxa2xx_i2c_ops = { 1454 .read = pxa2xx_i2c_read, 1455 .write = pxa2xx_i2c_write, 1456 .endianness = DEVICE_NATIVE_ENDIAN, 1457 }; 1458 1459 static const VMStateDescription vmstate_pxa2xx_i2c_slave = { 1460 .name = "pxa2xx_i2c_slave", 1461 .version_id = 1, 1462 .minimum_version_id = 1, 1463 .fields = (VMStateField[]) { 1464 VMSTATE_I2C_SLAVE(parent_obj, PXA2xxI2CSlaveState), 1465 VMSTATE_END_OF_LIST() 1466 } 1467 }; 1468 1469 static const VMStateDescription vmstate_pxa2xx_i2c = { 1470 .name = "pxa2xx_i2c", 1471 .version_id = 1, 1472 .minimum_version_id = 1, 1473 .fields = (VMStateField[]) { 1474 VMSTATE_UINT16(control, PXA2xxI2CState), 1475 VMSTATE_UINT16(status, PXA2xxI2CState), 1476 VMSTATE_UINT8(ibmr, PXA2xxI2CState), 1477 VMSTATE_UINT8(data, PXA2xxI2CState), 1478 VMSTATE_STRUCT_POINTER(slave, PXA2xxI2CState, 1479 vmstate_pxa2xx_i2c_slave, PXA2xxI2CSlaveState), 1480 VMSTATE_END_OF_LIST() 1481 } 1482 }; 1483 1484 static void pxa2xx_i2c_slave_class_init(ObjectClass *klass, void *data) 1485 { 1486 I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); 1487 1488 k->event = pxa2xx_i2c_event; 1489 k->recv = pxa2xx_i2c_rx; 1490 k->send = pxa2xx_i2c_tx; 1491 } 1492 1493 static const TypeInfo pxa2xx_i2c_slave_info = { 1494 .name = TYPE_PXA2XX_I2C_SLAVE, 1495 .parent = TYPE_I2C_SLAVE, 1496 .instance_size = sizeof(PXA2xxI2CSlaveState), 1497 .class_init = pxa2xx_i2c_slave_class_init, 1498 }; 1499 1500 PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base, 1501 qemu_irq irq, uint32_t region_size) 1502 { 1503 DeviceState *dev; 1504 SysBusDevice *i2c_dev; 1505 PXA2xxI2CState *s; 1506 I2CBus *i2cbus; 1507 1508 dev = qdev_new(TYPE_PXA2XX_I2C); 1509 qdev_prop_set_uint32(dev, "size", region_size + 1); 1510 qdev_prop_set_uint32(dev, "offset", base & region_size); 1511 1512 i2c_dev = SYS_BUS_DEVICE(dev); 1513 sysbus_realize_and_unref(i2c_dev, &error_fatal); 1514 sysbus_mmio_map(i2c_dev, 0, base & ~region_size); 1515 sysbus_connect_irq(i2c_dev, 0, irq); 1516 1517 s = PXA2XX_I2C(i2c_dev); 1518 /* FIXME: Should the slave device really be on a separate bus? */ 1519 i2cbus = i2c_init_bus(dev, "dummy"); 1520 s->slave = PXA2XX_I2C_SLAVE(i2c_slave_create_simple(i2cbus, 1521 TYPE_PXA2XX_I2C_SLAVE, 1522 0)); 1523 s->slave->host = s; 1524 1525 return s; 1526 } 1527 1528 static void pxa2xx_i2c_initfn(Object *obj) 1529 { 1530 DeviceState *dev = DEVICE(obj); 1531 PXA2xxI2CState *s = PXA2XX_I2C(obj); 1532 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1533 1534 s->bus = i2c_init_bus(dev, NULL); 1535 1536 memory_region_init_io(&s->iomem, obj, &pxa2xx_i2c_ops, s, 1537 "pxa2xx-i2c", s->region_size); 1538 sysbus_init_mmio(sbd, &s->iomem); 1539 sysbus_init_irq(sbd, &s->irq); 1540 } 1541 1542 I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s) 1543 { 1544 return s->bus; 1545 } 1546 1547 static Property pxa2xx_i2c_properties[] = { 1548 DEFINE_PROP_UINT32("size", PXA2xxI2CState, region_size, 0x10000), 1549 DEFINE_PROP_UINT32("offset", PXA2xxI2CState, offset, 0), 1550 DEFINE_PROP_END_OF_LIST(), 1551 }; 1552 1553 static void pxa2xx_i2c_class_init(ObjectClass *klass, void *data) 1554 { 1555 DeviceClass *dc = DEVICE_CLASS(klass); 1556 1557 dc->desc = "PXA2xx I2C Bus Controller"; 1558 dc->vmsd = &vmstate_pxa2xx_i2c; 1559 device_class_set_props(dc, pxa2xx_i2c_properties); 1560 } 1561 1562 static const TypeInfo pxa2xx_i2c_info = { 1563 .name = TYPE_PXA2XX_I2C, 1564 .parent = TYPE_SYS_BUS_DEVICE, 1565 .instance_size = sizeof(PXA2xxI2CState), 1566 .instance_init = pxa2xx_i2c_initfn, 1567 .class_init = pxa2xx_i2c_class_init, 1568 }; 1569 1570 /* PXA Inter-IC Sound Controller */ 1571 static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s) 1572 { 1573 i2s->rx_len = 0; 1574 i2s->tx_len = 0; 1575 i2s->fifo_len = 0; 1576 i2s->clk = 0x1a; 1577 i2s->control[0] = 0x00; 1578 i2s->control[1] = 0x00; 1579 i2s->status = 0x00; 1580 i2s->mask = 0x00; 1581 } 1582 1583 #define SACR_TFTH(val) ((val >> 8) & 0xf) 1584 #define SACR_RFTH(val) ((val >> 12) & 0xf) 1585 #define SACR_DREC(val) (val & (1 << 3)) 1586 #define SACR_DPRL(val) (val & (1 << 4)) 1587 1588 static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s) 1589 { 1590 int rfs, tfs; 1591 rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len && 1592 !SACR_DREC(i2s->control[1]); 1593 tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) && 1594 i2s->enable && !SACR_DPRL(i2s->control[1]); 1595 1596 qemu_set_irq(i2s->rx_dma, rfs); 1597 qemu_set_irq(i2s->tx_dma, tfs); 1598 1599 i2s->status &= 0xe0; 1600 if (i2s->fifo_len < 16 || !i2s->enable) 1601 i2s->status |= 1 << 0; /* TNF */ 1602 if (i2s->rx_len) 1603 i2s->status |= 1 << 1; /* RNE */ 1604 if (i2s->enable) 1605 i2s->status |= 1 << 2; /* BSY */ 1606 if (tfs) 1607 i2s->status |= 1 << 3; /* TFS */ 1608 if (rfs) 1609 i2s->status |= 1 << 4; /* RFS */ 1610 if (!(i2s->tx_len && i2s->enable)) 1611 i2s->status |= i2s->fifo_len << 8; /* TFL */ 1612 i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */ 1613 1614 qemu_set_irq(i2s->irq, i2s->status & i2s->mask); 1615 } 1616 1617 #define SACR0 0x00 /* Serial Audio Global Control register */ 1618 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */ 1619 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */ 1620 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */ 1621 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */ 1622 #define SADIV 0x60 /* Serial Audio Clock Divider register */ 1623 #define SADR 0x80 /* Serial Audio Data register */ 1624 1625 static uint64_t pxa2xx_i2s_read(void *opaque, hwaddr addr, 1626 unsigned size) 1627 { 1628 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; 1629 1630 switch (addr) { 1631 case SACR0: 1632 return s->control[0]; 1633 case SACR1: 1634 return s->control[1]; 1635 case SASR0: 1636 return s->status; 1637 case SAIMR: 1638 return s->mask; 1639 case SAICR: 1640 return 0; 1641 case SADIV: 1642 return s->clk; 1643 case SADR: 1644 if (s->rx_len > 0) { 1645 s->rx_len --; 1646 pxa2xx_i2s_update(s); 1647 return s->codec_in(s->opaque); 1648 } 1649 return 0; 1650 default: 1651 qemu_log_mask(LOG_GUEST_ERROR, 1652 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 1653 __func__, addr); 1654 break; 1655 } 1656 return 0; 1657 } 1658 1659 static void pxa2xx_i2s_write(void *opaque, hwaddr addr, 1660 uint64_t value, unsigned size) 1661 { 1662 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; 1663 uint32_t *sample; 1664 1665 switch (addr) { 1666 case SACR0: 1667 if (value & (1 << 3)) /* RST */ 1668 pxa2xx_i2s_reset(s); 1669 s->control[0] = value & 0xff3d; 1670 if (!s->enable && (value & 1) && s->tx_len) { /* ENB */ 1671 for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++) 1672 s->codec_out(s->opaque, *sample); 1673 s->status &= ~(1 << 7); /* I2SOFF */ 1674 } 1675 if (value & (1 << 4)) /* EFWR */ 1676 printf("%s: Attempt to use special function\n", __func__); 1677 s->enable = (value & 9) == 1; /* ENB && !RST*/ 1678 pxa2xx_i2s_update(s); 1679 break; 1680 case SACR1: 1681 s->control[1] = value & 0x0039; 1682 if (value & (1 << 5)) /* ENLBF */ 1683 printf("%s: Attempt to use loopback function\n", __func__); 1684 if (value & (1 << 4)) /* DPRL */ 1685 s->fifo_len = 0; 1686 pxa2xx_i2s_update(s); 1687 break; 1688 case SAIMR: 1689 s->mask = value & 0x0078; 1690 pxa2xx_i2s_update(s); 1691 break; 1692 case SAICR: 1693 s->status &= ~(value & (3 << 5)); 1694 pxa2xx_i2s_update(s); 1695 break; 1696 case SADIV: 1697 s->clk = value & 0x007f; 1698 break; 1699 case SADR: 1700 if (s->tx_len && s->enable) { 1701 s->tx_len --; 1702 pxa2xx_i2s_update(s); 1703 s->codec_out(s->opaque, value); 1704 } else if (s->fifo_len < 16) { 1705 s->fifo[s->fifo_len ++] = value; 1706 pxa2xx_i2s_update(s); 1707 } 1708 break; 1709 default: 1710 qemu_log_mask(LOG_GUEST_ERROR, 1711 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 1712 __func__, addr); 1713 } 1714 } 1715 1716 static const MemoryRegionOps pxa2xx_i2s_ops = { 1717 .read = pxa2xx_i2s_read, 1718 .write = pxa2xx_i2s_write, 1719 .endianness = DEVICE_NATIVE_ENDIAN, 1720 }; 1721 1722 static const VMStateDescription vmstate_pxa2xx_i2s = { 1723 .name = "pxa2xx_i2s", 1724 .version_id = 0, 1725 .minimum_version_id = 0, 1726 .fields = (VMStateField[]) { 1727 VMSTATE_UINT32_ARRAY(control, PXA2xxI2SState, 2), 1728 VMSTATE_UINT32(status, PXA2xxI2SState), 1729 VMSTATE_UINT32(mask, PXA2xxI2SState), 1730 VMSTATE_UINT32(clk, PXA2xxI2SState), 1731 VMSTATE_INT32(enable, PXA2xxI2SState), 1732 VMSTATE_INT32(rx_len, PXA2xxI2SState), 1733 VMSTATE_INT32(tx_len, PXA2xxI2SState), 1734 VMSTATE_INT32(fifo_len, PXA2xxI2SState), 1735 VMSTATE_END_OF_LIST() 1736 } 1737 }; 1738 1739 static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx) 1740 { 1741 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; 1742 uint32_t *sample; 1743 1744 /* Signal FIFO errors */ 1745 if (s->enable && s->tx_len) 1746 s->status |= 1 << 5; /* TUR */ 1747 if (s->enable && s->rx_len) 1748 s->status |= 1 << 6; /* ROR */ 1749 1750 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to 1751 * handle the cases where it makes a difference. */ 1752 s->tx_len = tx - s->fifo_len; 1753 s->rx_len = rx; 1754 /* Note that is s->codec_out wasn't set, we wouldn't get called. */ 1755 if (s->enable) 1756 for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++) 1757 s->codec_out(s->opaque, *sample); 1758 pxa2xx_i2s_update(s); 1759 } 1760 1761 static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem, 1762 hwaddr base, 1763 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma) 1764 { 1765 PXA2xxI2SState *s = g_new0(PXA2xxI2SState, 1); 1766 1767 s->irq = irq; 1768 s->rx_dma = rx_dma; 1769 s->tx_dma = tx_dma; 1770 s->data_req = pxa2xx_i2s_data_req; 1771 1772 pxa2xx_i2s_reset(s); 1773 1774 memory_region_init_io(&s->iomem, NULL, &pxa2xx_i2s_ops, s, 1775 "pxa2xx-i2s", 0x100000); 1776 memory_region_add_subregion(sysmem, base, &s->iomem); 1777 1778 vmstate_register(NULL, base, &vmstate_pxa2xx_i2s, s); 1779 1780 return s; 1781 } 1782 1783 /* PXA Fast Infra-red Communications Port */ 1784 struct PXA2xxFIrState { 1785 /*< private >*/ 1786 SysBusDevice parent_obj; 1787 /*< public >*/ 1788 1789 MemoryRegion iomem; 1790 qemu_irq irq; 1791 qemu_irq rx_dma; 1792 qemu_irq tx_dma; 1793 uint32_t enable; 1794 CharBackend chr; 1795 1796 uint8_t control[3]; 1797 uint8_t status[2]; 1798 1799 uint32_t rx_len; 1800 uint32_t rx_start; 1801 uint8_t rx_fifo[64]; 1802 }; 1803 1804 static void pxa2xx_fir_reset(DeviceState *d) 1805 { 1806 PXA2xxFIrState *s = PXA2XX_FIR(d); 1807 1808 s->control[0] = 0x00; 1809 s->control[1] = 0x00; 1810 s->control[2] = 0x00; 1811 s->status[0] = 0x00; 1812 s->status[1] = 0x00; 1813 s->enable = 0; 1814 } 1815 1816 static inline void pxa2xx_fir_update(PXA2xxFIrState *s) 1817 { 1818 static const int tresh[4] = { 8, 16, 32, 0 }; 1819 int intr = 0; 1820 if ((s->control[0] & (1 << 4)) && /* RXE */ 1821 s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */ 1822 s->status[0] |= 1 << 4; /* RFS */ 1823 else 1824 s->status[0] &= ~(1 << 4); /* RFS */ 1825 if (s->control[0] & (1 << 3)) /* TXE */ 1826 s->status[0] |= 1 << 3; /* TFS */ 1827 else 1828 s->status[0] &= ~(1 << 3); /* TFS */ 1829 if (s->rx_len) 1830 s->status[1] |= 1 << 2; /* RNE */ 1831 else 1832 s->status[1] &= ~(1 << 2); /* RNE */ 1833 if (s->control[0] & (1 << 4)) /* RXE */ 1834 s->status[1] |= 1 << 0; /* RSY */ 1835 else 1836 s->status[1] &= ~(1 << 0); /* RSY */ 1837 1838 intr |= (s->control[0] & (1 << 5)) && /* RIE */ 1839 (s->status[0] & (1 << 4)); /* RFS */ 1840 intr |= (s->control[0] & (1 << 6)) && /* TIE */ 1841 (s->status[0] & (1 << 3)); /* TFS */ 1842 intr |= (s->control[2] & (1 << 4)) && /* TRAIL */ 1843 (s->status[0] & (1 << 6)); /* EOC */ 1844 intr |= (s->control[0] & (1 << 2)) && /* TUS */ 1845 (s->status[0] & (1 << 1)); /* TUR */ 1846 intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */ 1847 1848 qemu_set_irq(s->rx_dma, (s->status[0] >> 4) & 1); 1849 qemu_set_irq(s->tx_dma, (s->status[0] >> 3) & 1); 1850 1851 qemu_set_irq(s->irq, intr && s->enable); 1852 } 1853 1854 #define ICCR0 0x00 /* FICP Control register 0 */ 1855 #define ICCR1 0x04 /* FICP Control register 1 */ 1856 #define ICCR2 0x08 /* FICP Control register 2 */ 1857 #define ICDR 0x0c /* FICP Data register */ 1858 #define ICSR0 0x14 /* FICP Status register 0 */ 1859 #define ICSR1 0x18 /* FICP Status register 1 */ 1860 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */ 1861 1862 static uint64_t pxa2xx_fir_read(void *opaque, hwaddr addr, 1863 unsigned size) 1864 { 1865 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1866 uint8_t ret; 1867 1868 switch (addr) { 1869 case ICCR0: 1870 return s->control[0]; 1871 case ICCR1: 1872 return s->control[1]; 1873 case ICCR2: 1874 return s->control[2]; 1875 case ICDR: 1876 s->status[0] &= ~0x01; 1877 s->status[1] &= ~0x72; 1878 if (s->rx_len) { 1879 s->rx_len --; 1880 ret = s->rx_fifo[s->rx_start ++]; 1881 s->rx_start &= 63; 1882 pxa2xx_fir_update(s); 1883 return ret; 1884 } 1885 printf("%s: Rx FIFO underrun.\n", __func__); 1886 break; 1887 case ICSR0: 1888 return s->status[0]; 1889 case ICSR1: 1890 return s->status[1] | (1 << 3); /* TNF */ 1891 case ICFOR: 1892 return s->rx_len; 1893 default: 1894 qemu_log_mask(LOG_GUEST_ERROR, 1895 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 1896 __func__, addr); 1897 break; 1898 } 1899 return 0; 1900 } 1901 1902 static void pxa2xx_fir_write(void *opaque, hwaddr addr, 1903 uint64_t value64, unsigned size) 1904 { 1905 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1906 uint32_t value = value64; 1907 uint8_t ch; 1908 1909 switch (addr) { 1910 case ICCR0: 1911 s->control[0] = value; 1912 if (!(value & (1 << 4))) /* RXE */ 1913 s->rx_len = s->rx_start = 0; 1914 if (!(value & (1 << 3))) { /* TXE */ 1915 /* Nop */ 1916 } 1917 s->enable = value & 1; /* ITR */ 1918 if (!s->enable) 1919 s->status[0] = 0; 1920 pxa2xx_fir_update(s); 1921 break; 1922 case ICCR1: 1923 s->control[1] = value; 1924 break; 1925 case ICCR2: 1926 s->control[2] = value & 0x3f; 1927 pxa2xx_fir_update(s); 1928 break; 1929 case ICDR: 1930 if (s->control[2] & (1 << 2)) { /* TXP */ 1931 ch = value; 1932 } else { 1933 ch = ~value; 1934 } 1935 if (s->enable && (s->control[0] & (1 << 3))) { /* TXE */ 1936 /* XXX this blocks entire thread. Rewrite to use 1937 * qemu_chr_fe_write and background I/O callbacks */ 1938 qemu_chr_fe_write_all(&s->chr, &ch, 1); 1939 } 1940 break; 1941 case ICSR0: 1942 s->status[0] &= ~(value & 0x66); 1943 pxa2xx_fir_update(s); 1944 break; 1945 case ICFOR: 1946 break; 1947 default: 1948 qemu_log_mask(LOG_GUEST_ERROR, 1949 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 1950 __func__, addr); 1951 } 1952 } 1953 1954 static const MemoryRegionOps pxa2xx_fir_ops = { 1955 .read = pxa2xx_fir_read, 1956 .write = pxa2xx_fir_write, 1957 .endianness = DEVICE_NATIVE_ENDIAN, 1958 }; 1959 1960 static int pxa2xx_fir_is_empty(void *opaque) 1961 { 1962 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1963 return (s->rx_len < 64); 1964 } 1965 1966 static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size) 1967 { 1968 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1969 if (!(s->control[0] & (1 << 4))) /* RXE */ 1970 return; 1971 1972 while (size --) { 1973 s->status[1] |= 1 << 4; /* EOF */ 1974 if (s->rx_len >= 64) { 1975 s->status[1] |= 1 << 6; /* ROR */ 1976 break; 1977 } 1978 1979 if (s->control[2] & (1 << 3)) /* RXP */ 1980 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++); 1981 else 1982 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++); 1983 } 1984 1985 pxa2xx_fir_update(s); 1986 } 1987 1988 static void pxa2xx_fir_event(void *opaque, QEMUChrEvent event) 1989 { 1990 } 1991 1992 static void pxa2xx_fir_instance_init(Object *obj) 1993 { 1994 PXA2xxFIrState *s = PXA2XX_FIR(obj); 1995 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1996 1997 memory_region_init_io(&s->iomem, obj, &pxa2xx_fir_ops, s, 1998 "pxa2xx-fir", 0x1000); 1999 sysbus_init_mmio(sbd, &s->iomem); 2000 sysbus_init_irq(sbd, &s->irq); 2001 sysbus_init_irq(sbd, &s->rx_dma); 2002 sysbus_init_irq(sbd, &s->tx_dma); 2003 } 2004 2005 static void pxa2xx_fir_realize(DeviceState *dev, Error **errp) 2006 { 2007 PXA2xxFIrState *s = PXA2XX_FIR(dev); 2008 2009 qemu_chr_fe_set_handlers(&s->chr, pxa2xx_fir_is_empty, 2010 pxa2xx_fir_rx, pxa2xx_fir_event, NULL, s, NULL, 2011 true); 2012 } 2013 2014 static bool pxa2xx_fir_vmstate_validate(void *opaque, int version_id) 2015 { 2016 PXA2xxFIrState *s = opaque; 2017 2018 return s->rx_start < ARRAY_SIZE(s->rx_fifo); 2019 } 2020 2021 static const VMStateDescription pxa2xx_fir_vmsd = { 2022 .name = "pxa2xx-fir", 2023 .version_id = 1, 2024 .minimum_version_id = 1, 2025 .fields = (VMStateField[]) { 2026 VMSTATE_UINT32(enable, PXA2xxFIrState), 2027 VMSTATE_UINT8_ARRAY(control, PXA2xxFIrState, 3), 2028 VMSTATE_UINT8_ARRAY(status, PXA2xxFIrState, 2), 2029 VMSTATE_UINT32(rx_len, PXA2xxFIrState), 2030 VMSTATE_UINT32(rx_start, PXA2xxFIrState), 2031 VMSTATE_VALIDATE("fifo is 64 bytes", pxa2xx_fir_vmstate_validate), 2032 VMSTATE_UINT8_ARRAY(rx_fifo, PXA2xxFIrState, 64), 2033 VMSTATE_END_OF_LIST() 2034 } 2035 }; 2036 2037 static Property pxa2xx_fir_properties[] = { 2038 DEFINE_PROP_CHR("chardev", PXA2xxFIrState, chr), 2039 DEFINE_PROP_END_OF_LIST(), 2040 }; 2041 2042 static void pxa2xx_fir_class_init(ObjectClass *klass, void *data) 2043 { 2044 DeviceClass *dc = DEVICE_CLASS(klass); 2045 2046 dc->realize = pxa2xx_fir_realize; 2047 dc->vmsd = &pxa2xx_fir_vmsd; 2048 device_class_set_props(dc, pxa2xx_fir_properties); 2049 dc->reset = pxa2xx_fir_reset; 2050 } 2051 2052 static const TypeInfo pxa2xx_fir_info = { 2053 .name = TYPE_PXA2XX_FIR, 2054 .parent = TYPE_SYS_BUS_DEVICE, 2055 .instance_size = sizeof(PXA2xxFIrState), 2056 .class_init = pxa2xx_fir_class_init, 2057 .instance_init = pxa2xx_fir_instance_init, 2058 }; 2059 2060 static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem, 2061 hwaddr base, 2062 qemu_irq irq, qemu_irq rx_dma, 2063 qemu_irq tx_dma, 2064 Chardev *chr) 2065 { 2066 DeviceState *dev; 2067 SysBusDevice *sbd; 2068 2069 dev = qdev_new(TYPE_PXA2XX_FIR); 2070 qdev_prop_set_chr(dev, "chardev", chr); 2071 sbd = SYS_BUS_DEVICE(dev); 2072 sysbus_realize_and_unref(sbd, &error_fatal); 2073 sysbus_mmio_map(sbd, 0, base); 2074 sysbus_connect_irq(sbd, 0, irq); 2075 sysbus_connect_irq(sbd, 1, rx_dma); 2076 sysbus_connect_irq(sbd, 2, tx_dma); 2077 return PXA2XX_FIR(dev); 2078 } 2079 2080 static void pxa2xx_reset(void *opaque, int line, int level) 2081 { 2082 PXA2xxState *s = (PXA2xxState *) opaque; 2083 2084 if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */ 2085 cpu_reset(CPU(s->cpu)); 2086 /* TODO: reset peripherals */ 2087 } 2088 } 2089 2090 /* Initialise a PXA270 integrated chip (ARM based core). */ 2091 PXA2xxState *pxa270_init(MemoryRegion *address_space, 2092 unsigned int sdram_size, const char *cpu_type) 2093 { 2094 PXA2xxState *s; 2095 int i; 2096 DriveInfo *dinfo; 2097 s = g_new0(PXA2xxState, 1); 2098 2099 if (strncmp(cpu_type, "pxa27", 5)) { 2100 error_report("Machine requires a PXA27x processor"); 2101 exit(1); 2102 } 2103 2104 s->cpu = ARM_CPU(cpu_create(cpu_type)); 2105 s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0); 2106 2107 /* SDRAM & Internal Memory Storage */ 2108 memory_region_init_ram(&s->sdram, NULL, "pxa270.sdram", sdram_size, 2109 &error_fatal); 2110 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram); 2111 memory_region_init_ram(&s->internal, NULL, "pxa270.internal", 0x40000, 2112 &error_fatal); 2113 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE, 2114 &s->internal); 2115 2116 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu); 2117 2118 s->dma = pxa27x_dma_init(0x40000000, 2119 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA)); 2120 2121 sysbus_create_varargs("pxa27x-timer", 0x40a00000, 2122 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0), 2123 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1), 2124 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2), 2125 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3), 2126 qdev_get_gpio_in(s->pic, PXA27X_PIC_OST_4_11), 2127 NULL); 2128 2129 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 121); 2130 2131 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, 2132 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), 2133 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), 2134 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); 2135 dinfo = drive_get(IF_SD, 0, 0); 2136 if (dinfo) { 2137 DeviceState *carddev; 2138 2139 /* Create and plug in the sd card */ 2140 carddev = qdev_new(TYPE_SD_CARD); 2141 qdev_prop_set_drive_err(carddev, "drive", 2142 blk_by_legacy_dinfo(dinfo), &error_fatal); 2143 qdev_realize_and_unref(carddev, qdev_get_child_bus(DEVICE(s->mmc), 2144 "sd-bus"), 2145 &error_fatal); 2146 } else if (!qtest_enabled()) { 2147 warn_report("missing SecureDigital device"); 2148 } 2149 2150 for (i = 0; pxa270_serial[i].io_base; i++) { 2151 if (serial_hd(i)) { 2152 serial_mm_init(address_space, pxa270_serial[i].io_base, 2, 2153 qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn), 2154 14857000 / 16, serial_hd(i), 2155 DEVICE_NATIVE_ENDIAN); 2156 } else { 2157 break; 2158 } 2159 } 2160 if (serial_hd(i)) 2161 s->fir = pxa2xx_fir_init(address_space, 0x40800000, 2162 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), 2163 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), 2164 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), 2165 serial_hd(i)); 2166 2167 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000, 2168 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); 2169 2170 s->cm_base = 0x41300000; 2171 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */ 2172 s->clkcfg = 0x00000009; /* Turbo mode active */ 2173 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000); 2174 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); 2175 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); 2176 2177 pxa2xx_setup_cp14(s); 2178 2179 s->mm_base = 0x48000000; 2180 s->mm_regs[MDMRS >> 2] = 0x00020002; 2181 s->mm_regs[MDREFR >> 2] = 0x03ca4000; 2182 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ 2183 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000); 2184 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem); 2185 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s); 2186 2187 s->pm_base = 0x40f00000; 2188 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100); 2189 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem); 2190 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s); 2191 2192 for (i = 0; pxa27x_ssp[i].io_base; i ++); 2193 s->ssp = g_new0(SSIBus *, i); 2194 for (i = 0; pxa27x_ssp[i].io_base; i ++) { 2195 DeviceState *dev; 2196 dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa27x_ssp[i].io_base, 2197 qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn)); 2198 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi"); 2199 } 2200 2201 sysbus_create_simple("sysbus-ohci", 0x4c000000, 2202 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1)); 2203 2204 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000); 2205 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000); 2206 2207 sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000, 2208 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM)); 2209 2210 s->i2c[0] = pxa2xx_i2c_init(0x40301600, 2211 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff); 2212 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, 2213 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff); 2214 2215 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000, 2216 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), 2217 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), 2218 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); 2219 2220 s->kp = pxa27x_keypad_init(address_space, 0x41500000, 2221 qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD)); 2222 2223 /* GPIO1 resets the processor */ 2224 /* The handler can be overridden by board-specific code */ 2225 qdev_connect_gpio_out(s->gpio, 1, s->reset); 2226 return s; 2227 } 2228 2229 /* Initialise a PXA255 integrated chip (ARM based core). */ 2230 PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size) 2231 { 2232 PXA2xxState *s; 2233 int i; 2234 DriveInfo *dinfo; 2235 2236 s = g_new0(PXA2xxState, 1); 2237 2238 s->cpu = ARM_CPU(cpu_create(ARM_CPU_TYPE_NAME("pxa255"))); 2239 s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0); 2240 2241 /* SDRAM & Internal Memory Storage */ 2242 memory_region_init_ram(&s->sdram, NULL, "pxa255.sdram", sdram_size, 2243 &error_fatal); 2244 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram); 2245 memory_region_init_ram(&s->internal, NULL, "pxa255.internal", 2246 PXA2XX_INTERNAL_SIZE, &error_fatal); 2247 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE, 2248 &s->internal); 2249 2250 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu); 2251 2252 s->dma = pxa255_dma_init(0x40000000, 2253 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA)); 2254 2255 sysbus_create_varargs("pxa25x-timer", 0x40a00000, 2256 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0), 2257 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1), 2258 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2), 2259 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3), 2260 NULL); 2261 2262 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 85); 2263 2264 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, 2265 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), 2266 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), 2267 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); 2268 dinfo = drive_get(IF_SD, 0, 0); 2269 if (dinfo) { 2270 DeviceState *carddev; 2271 2272 /* Create and plug in the sd card */ 2273 carddev = qdev_new(TYPE_SD_CARD); 2274 qdev_prop_set_drive_err(carddev, "drive", 2275 blk_by_legacy_dinfo(dinfo), &error_fatal); 2276 qdev_realize_and_unref(carddev, qdev_get_child_bus(DEVICE(s->mmc), 2277 "sd-bus"), 2278 &error_fatal); 2279 } else if (!qtest_enabled()) { 2280 warn_report("missing SecureDigital device"); 2281 } 2282 2283 for (i = 0; pxa255_serial[i].io_base; i++) { 2284 if (serial_hd(i)) { 2285 serial_mm_init(address_space, pxa255_serial[i].io_base, 2, 2286 qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn), 2287 14745600 / 16, serial_hd(i), 2288 DEVICE_NATIVE_ENDIAN); 2289 } else { 2290 break; 2291 } 2292 } 2293 if (serial_hd(i)) 2294 s->fir = pxa2xx_fir_init(address_space, 0x40800000, 2295 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), 2296 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), 2297 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), 2298 serial_hd(i)); 2299 2300 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000, 2301 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); 2302 2303 s->cm_base = 0x41300000; 2304 s->cm_regs[CCCR >> 2] = 0x00000121; /* from datasheet */ 2305 s->cm_regs[CKEN >> 2] = 0x00017def; /* from datasheet */ 2306 2307 s->clkcfg = 0x00000009; /* Turbo mode active */ 2308 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000); 2309 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); 2310 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); 2311 2312 pxa2xx_setup_cp14(s); 2313 2314 s->mm_base = 0x48000000; 2315 s->mm_regs[MDMRS >> 2] = 0x00020002; 2316 s->mm_regs[MDREFR >> 2] = 0x03ca4000; 2317 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ 2318 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000); 2319 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem); 2320 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s); 2321 2322 s->pm_base = 0x40f00000; 2323 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100); 2324 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem); 2325 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s); 2326 2327 for (i = 0; pxa255_ssp[i].io_base; i ++); 2328 s->ssp = g_new0(SSIBus *, i); 2329 for (i = 0; pxa255_ssp[i].io_base; i ++) { 2330 DeviceState *dev; 2331 dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa255_ssp[i].io_base, 2332 qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn)); 2333 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi"); 2334 } 2335 2336 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000); 2337 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000); 2338 2339 sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000, 2340 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM)); 2341 2342 s->i2c[0] = pxa2xx_i2c_init(0x40301600, 2343 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff); 2344 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, 2345 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff); 2346 2347 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000, 2348 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), 2349 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), 2350 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); 2351 2352 /* GPIO1 resets the processor */ 2353 /* The handler can be overridden by board-specific code */ 2354 qdev_connect_gpio_out(s->gpio, 1, s->reset); 2355 return s; 2356 } 2357 2358 static void pxa2xx_ssp_class_init(ObjectClass *klass, void *data) 2359 { 2360 DeviceClass *dc = DEVICE_CLASS(klass); 2361 2362 dc->reset = pxa2xx_ssp_reset; 2363 dc->vmsd = &vmstate_pxa2xx_ssp; 2364 } 2365 2366 static const TypeInfo pxa2xx_ssp_info = { 2367 .name = TYPE_PXA2XX_SSP, 2368 .parent = TYPE_SYS_BUS_DEVICE, 2369 .instance_size = sizeof(PXA2xxSSPState), 2370 .instance_init = pxa2xx_ssp_init, 2371 .class_init = pxa2xx_ssp_class_init, 2372 }; 2373 2374 static void pxa2xx_register_types(void) 2375 { 2376 type_register_static(&pxa2xx_i2c_slave_info); 2377 type_register_static(&pxa2xx_ssp_info); 2378 type_register_static(&pxa2xx_i2c_info); 2379 type_register_static(&pxa2xx_rtc_sysbus_info); 2380 type_register_static(&pxa2xx_fir_info); 2381 } 2382 2383 type_init(pxa2xx_register_types) 2384