1 /* 2 * Intel XScale PXA255/270 processor support. 3 * 4 * Copyright (c) 2006 Openedhand Ltd. 5 * Written by Andrzej Zaborowski <balrog@zabor.org> 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu-common.h" 12 #include "qemu/error-report.h" 13 #include "qemu/module.h" 14 #include "qapi/error.h" 15 #include "cpu.h" 16 #include "hw/sysbus.h" 17 #include "migration/vmstate.h" 18 #include "hw/arm/pxa.h" 19 #include "sysemu/sysemu.h" 20 #include "hw/char/serial.h" 21 #include "hw/i2c/i2c.h" 22 #include "hw/irq.h" 23 #include "hw/qdev-properties.h" 24 #include "hw/ssi/ssi.h" 25 #include "hw/sd/sd.h" 26 #include "chardev/char-fe.h" 27 #include "sysemu/blockdev.h" 28 #include "sysemu/qtest.h" 29 #include "qemu/cutils.h" 30 #include "qemu/log.h" 31 32 static struct { 33 hwaddr io_base; 34 int irqn; 35 } pxa255_serial[] = { 36 { 0x40100000, PXA2XX_PIC_FFUART }, 37 { 0x40200000, PXA2XX_PIC_BTUART }, 38 { 0x40700000, PXA2XX_PIC_STUART }, 39 { 0x41600000, PXA25X_PIC_HWUART }, 40 { 0, 0 } 41 }, pxa270_serial[] = { 42 { 0x40100000, PXA2XX_PIC_FFUART }, 43 { 0x40200000, PXA2XX_PIC_BTUART }, 44 { 0x40700000, PXA2XX_PIC_STUART }, 45 { 0, 0 } 46 }; 47 48 typedef struct PXASSPDef { 49 hwaddr io_base; 50 int irqn; 51 } PXASSPDef; 52 53 #if 0 54 static PXASSPDef pxa250_ssp[] = { 55 { 0x41000000, PXA2XX_PIC_SSP }, 56 { 0, 0 } 57 }; 58 #endif 59 60 static PXASSPDef pxa255_ssp[] = { 61 { 0x41000000, PXA2XX_PIC_SSP }, 62 { 0x41400000, PXA25X_PIC_NSSP }, 63 { 0, 0 } 64 }; 65 66 #if 0 67 static PXASSPDef pxa26x_ssp[] = { 68 { 0x41000000, PXA2XX_PIC_SSP }, 69 { 0x41400000, PXA25X_PIC_NSSP }, 70 { 0x41500000, PXA26X_PIC_ASSP }, 71 { 0, 0 } 72 }; 73 #endif 74 75 static PXASSPDef pxa27x_ssp[] = { 76 { 0x41000000, PXA2XX_PIC_SSP }, 77 { 0x41700000, PXA27X_PIC_SSP2 }, 78 { 0x41900000, PXA2XX_PIC_SSP3 }, 79 { 0, 0 } 80 }; 81 82 #define PMCR 0x00 /* Power Manager Control register */ 83 #define PSSR 0x04 /* Power Manager Sleep Status register */ 84 #define PSPR 0x08 /* Power Manager Scratch-Pad register */ 85 #define PWER 0x0c /* Power Manager Wake-Up Enable register */ 86 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */ 87 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */ 88 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */ 89 #define PCFR 0x1c /* Power Manager General Configuration register */ 90 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */ 91 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */ 92 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */ 93 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */ 94 #define RCSR 0x30 /* Reset Controller Status register */ 95 #define PSLR 0x34 /* Power Manager Sleep Configuration register */ 96 #define PTSR 0x38 /* Power Manager Standby Configuration register */ 97 #define PVCR 0x40 /* Power Manager Voltage Change Control register */ 98 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */ 99 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */ 100 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */ 101 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */ 102 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */ 103 104 static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr, 105 unsigned size) 106 { 107 PXA2xxState *s = (PXA2xxState *) opaque; 108 109 switch (addr) { 110 case PMCR ... PCMD31: 111 if (addr & 3) 112 goto fail; 113 114 return s->pm_regs[addr >> 2]; 115 default: 116 fail: 117 qemu_log_mask(LOG_GUEST_ERROR, 118 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 119 __func__, addr); 120 break; 121 } 122 return 0; 123 } 124 125 static void pxa2xx_pm_write(void *opaque, hwaddr addr, 126 uint64_t value, unsigned size) 127 { 128 PXA2xxState *s = (PXA2xxState *) opaque; 129 130 switch (addr) { 131 case PMCR: 132 /* Clear the write-one-to-clear bits... */ 133 s->pm_regs[addr >> 2] &= ~(value & 0x2a); 134 /* ...and set the plain r/w bits */ 135 s->pm_regs[addr >> 2] &= ~0x15; 136 s->pm_regs[addr >> 2] |= value & 0x15; 137 break; 138 139 case PSSR: /* Read-clean registers */ 140 case RCSR: 141 case PKSR: 142 s->pm_regs[addr >> 2] &= ~value; 143 break; 144 145 default: /* Read-write registers */ 146 if (!(addr & 3)) { 147 s->pm_regs[addr >> 2] = value; 148 break; 149 } 150 qemu_log_mask(LOG_GUEST_ERROR, 151 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 152 __func__, addr); 153 break; 154 } 155 } 156 157 static const MemoryRegionOps pxa2xx_pm_ops = { 158 .read = pxa2xx_pm_read, 159 .write = pxa2xx_pm_write, 160 .endianness = DEVICE_NATIVE_ENDIAN, 161 }; 162 163 static const VMStateDescription vmstate_pxa2xx_pm = { 164 .name = "pxa2xx_pm", 165 .version_id = 0, 166 .minimum_version_id = 0, 167 .fields = (VMStateField[]) { 168 VMSTATE_UINT32_ARRAY(pm_regs, PXA2xxState, 0x40), 169 VMSTATE_END_OF_LIST() 170 } 171 }; 172 173 #define CCCR 0x00 /* Core Clock Configuration register */ 174 #define CKEN 0x04 /* Clock Enable register */ 175 #define OSCC 0x08 /* Oscillator Configuration register */ 176 #define CCSR 0x0c /* Core Clock Status register */ 177 178 static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr, 179 unsigned size) 180 { 181 PXA2xxState *s = (PXA2xxState *) opaque; 182 183 switch (addr) { 184 case CCCR: 185 case CKEN: 186 case OSCC: 187 return s->cm_regs[addr >> 2]; 188 189 case CCSR: 190 return s->cm_regs[CCCR >> 2] | (3 << 28); 191 192 default: 193 qemu_log_mask(LOG_GUEST_ERROR, 194 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 195 __func__, addr); 196 break; 197 } 198 return 0; 199 } 200 201 static void pxa2xx_cm_write(void *opaque, hwaddr addr, 202 uint64_t value, unsigned size) 203 { 204 PXA2xxState *s = (PXA2xxState *) opaque; 205 206 switch (addr) { 207 case CCCR: 208 case CKEN: 209 s->cm_regs[addr >> 2] = value; 210 break; 211 212 case OSCC: 213 s->cm_regs[addr >> 2] &= ~0x6c; 214 s->cm_regs[addr >> 2] |= value & 0x6e; 215 if ((value >> 1) & 1) /* OON */ 216 s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */ 217 break; 218 219 default: 220 qemu_log_mask(LOG_GUEST_ERROR, 221 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 222 __func__, addr); 223 break; 224 } 225 } 226 227 static const MemoryRegionOps pxa2xx_cm_ops = { 228 .read = pxa2xx_cm_read, 229 .write = pxa2xx_cm_write, 230 .endianness = DEVICE_NATIVE_ENDIAN, 231 }; 232 233 static const VMStateDescription vmstate_pxa2xx_cm = { 234 .name = "pxa2xx_cm", 235 .version_id = 0, 236 .minimum_version_id = 0, 237 .fields = (VMStateField[]) { 238 VMSTATE_UINT32_ARRAY(cm_regs, PXA2xxState, 4), 239 VMSTATE_UINT32(clkcfg, PXA2xxState), 240 VMSTATE_UINT32(pmnc, PXA2xxState), 241 VMSTATE_END_OF_LIST() 242 } 243 }; 244 245 static uint64_t pxa2xx_clkcfg_read(CPUARMState *env, const ARMCPRegInfo *ri) 246 { 247 PXA2xxState *s = (PXA2xxState *)ri->opaque; 248 return s->clkcfg; 249 } 250 251 static void pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri, 252 uint64_t value) 253 { 254 PXA2xxState *s = (PXA2xxState *)ri->opaque; 255 s->clkcfg = value & 0xf; 256 if (value & 2) { 257 printf("%s: CPU frequency change attempt\n", __func__); 258 } 259 } 260 261 static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri, 262 uint64_t value) 263 { 264 PXA2xxState *s = (PXA2xxState *)ri->opaque; 265 static const char *pwrmode[8] = { 266 "Normal", "Idle", "Deep-idle", "Standby", 267 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep", 268 }; 269 270 if (value & 8) { 271 printf("%s: CPU voltage change attempt\n", __func__); 272 } 273 switch (value & 7) { 274 case 0: 275 /* Do nothing */ 276 break; 277 278 case 1: 279 /* Idle */ 280 if (!(s->cm_regs[CCCR >> 2] & (1U << 31))) { /* CPDIS */ 281 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); 282 break; 283 } 284 /* Fall through. */ 285 286 case 2: 287 /* Deep-Idle */ 288 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); 289 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ 290 goto message; 291 292 case 3: 293 s->cpu->env.uncached_cpsr = ARM_CPU_MODE_SVC; 294 s->cpu->env.daif = PSTATE_A | PSTATE_F | PSTATE_I; 295 s->cpu->env.cp15.sctlr_ns = 0; 296 s->cpu->env.cp15.cpacr_el1 = 0; 297 s->cpu->env.cp15.ttbr0_el[1] = 0; 298 s->cpu->env.cp15.dacr_ns = 0; 299 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ 300 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ 301 302 /* 303 * The scratch-pad register is almost universally used 304 * for storing the return address on suspend. For the 305 * lack of a resuming bootloader, perform a jump 306 * directly to that address. 307 */ 308 memset(s->cpu->env.regs, 0, 4 * 15); 309 s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2]; 310 311 #if 0 312 buffer = 0xe59ff000; /* ldr pc, [pc, #0] */ 313 cpu_physical_memory_write(0, &buffer, 4); 314 buffer = s->pm_regs[PSPR >> 2]; 315 cpu_physical_memory_write(8, &buffer, 4); 316 #endif 317 318 /* Suspend */ 319 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); 320 321 goto message; 322 323 default: 324 message: 325 printf("%s: machine entered %s mode\n", __func__, 326 pwrmode[value & 7]); 327 } 328 } 329 330 static uint64_t pxa2xx_cppmnc_read(CPUARMState *env, const ARMCPRegInfo *ri) 331 { 332 PXA2xxState *s = (PXA2xxState *)ri->opaque; 333 return s->pmnc; 334 } 335 336 static void pxa2xx_cppmnc_write(CPUARMState *env, const ARMCPRegInfo *ri, 337 uint64_t value) 338 { 339 PXA2xxState *s = (PXA2xxState *)ri->opaque; 340 s->pmnc = value; 341 } 342 343 static uint64_t pxa2xx_cpccnt_read(CPUARMState *env, const ARMCPRegInfo *ri) 344 { 345 PXA2xxState *s = (PXA2xxState *)ri->opaque; 346 if (s->pmnc & 1) { 347 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 348 } else { 349 return 0; 350 } 351 } 352 353 static const ARMCPRegInfo pxa_cp_reginfo[] = { 354 /* cp14 crm==1: perf registers */ 355 { .name = "CPPMNC", .cp = 14, .crn = 0, .crm = 1, .opc1 = 0, .opc2 = 0, 356 .access = PL1_RW, .type = ARM_CP_IO, 357 .readfn = pxa2xx_cppmnc_read, .writefn = pxa2xx_cppmnc_write }, 358 { .name = "CPCCNT", .cp = 14, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, 359 .access = PL1_RW, .type = ARM_CP_IO, 360 .readfn = pxa2xx_cpccnt_read, .writefn = arm_cp_write_ignore }, 361 { .name = "CPINTEN", .cp = 14, .crn = 4, .crm = 1, .opc1 = 0, .opc2 = 0, 362 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 363 { .name = "CPFLAG", .cp = 14, .crn = 5, .crm = 1, .opc1 = 0, .opc2 = 0, 364 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 365 { .name = "CPEVTSEL", .cp = 14, .crn = 8, .crm = 1, .opc1 = 0, .opc2 = 0, 366 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 367 /* cp14 crm==2: performance count registers */ 368 { .name = "CPPMN0", .cp = 14, .crn = 0, .crm = 2, .opc1 = 0, .opc2 = 0, 369 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 370 { .name = "CPPMN1", .cp = 14, .crn = 1, .crm = 2, .opc1 = 0, .opc2 = 0, 371 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 372 { .name = "CPPMN2", .cp = 14, .crn = 2, .crm = 2, .opc1 = 0, .opc2 = 0, 373 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 374 { .name = "CPPMN3", .cp = 14, .crn = 2, .crm = 3, .opc1 = 0, .opc2 = 0, 375 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 376 /* cp14 crn==6: CLKCFG */ 377 { .name = "CLKCFG", .cp = 14, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, 378 .access = PL1_RW, .type = ARM_CP_IO, 379 .readfn = pxa2xx_clkcfg_read, .writefn = pxa2xx_clkcfg_write }, 380 /* cp14 crn==7: PWRMODE */ 381 { .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0, 382 .access = PL1_RW, .type = ARM_CP_IO, 383 .readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write }, 384 REGINFO_SENTINEL 385 }; 386 387 static void pxa2xx_setup_cp14(PXA2xxState *s) 388 { 389 define_arm_cp_regs_with_opaque(s->cpu, pxa_cp_reginfo, s); 390 } 391 392 #define MDCNFG 0x00 /* SDRAM Configuration register */ 393 #define MDREFR 0x04 /* SDRAM Refresh Control register */ 394 #define MSC0 0x08 /* Static Memory Control register 0 */ 395 #define MSC1 0x0c /* Static Memory Control register 1 */ 396 #define MSC2 0x10 /* Static Memory Control register 2 */ 397 #define MECR 0x14 /* Expansion Memory Bus Config register */ 398 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */ 399 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */ 400 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */ 401 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */ 402 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */ 403 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */ 404 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */ 405 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */ 406 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */ 407 #define ARB_CNTL 0x48 /* Arbiter Control register */ 408 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */ 409 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */ 410 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */ 411 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */ 412 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */ 413 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */ 414 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */ 415 416 static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr, 417 unsigned size) 418 { 419 PXA2xxState *s = (PXA2xxState *) opaque; 420 421 switch (addr) { 422 case MDCNFG ... SA1110: 423 if ((addr & 3) == 0) 424 return s->mm_regs[addr >> 2]; 425 /* fall through */ 426 default: 427 qemu_log_mask(LOG_GUEST_ERROR, 428 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 429 __func__, addr); 430 break; 431 } 432 return 0; 433 } 434 435 static void pxa2xx_mm_write(void *opaque, hwaddr addr, 436 uint64_t value, unsigned size) 437 { 438 PXA2xxState *s = (PXA2xxState *) opaque; 439 440 switch (addr) { 441 case MDCNFG ... SA1110: 442 if ((addr & 3) == 0) { 443 s->mm_regs[addr >> 2] = value; 444 break; 445 } 446 447 default: 448 qemu_log_mask(LOG_GUEST_ERROR, 449 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 450 __func__, addr); 451 break; 452 } 453 } 454 455 static const MemoryRegionOps pxa2xx_mm_ops = { 456 .read = pxa2xx_mm_read, 457 .write = pxa2xx_mm_write, 458 .endianness = DEVICE_NATIVE_ENDIAN, 459 }; 460 461 static const VMStateDescription vmstate_pxa2xx_mm = { 462 .name = "pxa2xx_mm", 463 .version_id = 0, 464 .minimum_version_id = 0, 465 .fields = (VMStateField[]) { 466 VMSTATE_UINT32_ARRAY(mm_regs, PXA2xxState, 0x1a), 467 VMSTATE_END_OF_LIST() 468 } 469 }; 470 471 #define TYPE_PXA2XX_SSP "pxa2xx-ssp" 472 #define PXA2XX_SSP(obj) \ 473 OBJECT_CHECK(PXA2xxSSPState, (obj), TYPE_PXA2XX_SSP) 474 475 /* Synchronous Serial Ports */ 476 typedef struct { 477 /*< private >*/ 478 SysBusDevice parent_obj; 479 /*< public >*/ 480 481 MemoryRegion iomem; 482 qemu_irq irq; 483 uint32_t enable; 484 SSIBus *bus; 485 486 uint32_t sscr[2]; 487 uint32_t sspsp; 488 uint32_t ssto; 489 uint32_t ssitr; 490 uint32_t sssr; 491 uint8_t sstsa; 492 uint8_t ssrsa; 493 uint8_t ssacd; 494 495 uint32_t rx_fifo[16]; 496 uint32_t rx_level; 497 uint32_t rx_start; 498 } PXA2xxSSPState; 499 500 static bool pxa2xx_ssp_vmstate_validate(void *opaque, int version_id) 501 { 502 PXA2xxSSPState *s = opaque; 503 504 return s->rx_start < sizeof(s->rx_fifo); 505 } 506 507 static const VMStateDescription vmstate_pxa2xx_ssp = { 508 .name = "pxa2xx-ssp", 509 .version_id = 1, 510 .minimum_version_id = 1, 511 .fields = (VMStateField[]) { 512 VMSTATE_UINT32(enable, PXA2xxSSPState), 513 VMSTATE_UINT32_ARRAY(sscr, PXA2xxSSPState, 2), 514 VMSTATE_UINT32(sspsp, PXA2xxSSPState), 515 VMSTATE_UINT32(ssto, PXA2xxSSPState), 516 VMSTATE_UINT32(ssitr, PXA2xxSSPState), 517 VMSTATE_UINT32(sssr, PXA2xxSSPState), 518 VMSTATE_UINT8(sstsa, PXA2xxSSPState), 519 VMSTATE_UINT8(ssrsa, PXA2xxSSPState), 520 VMSTATE_UINT8(ssacd, PXA2xxSSPState), 521 VMSTATE_UINT32(rx_level, PXA2xxSSPState), 522 VMSTATE_UINT32(rx_start, PXA2xxSSPState), 523 VMSTATE_VALIDATE("fifo is 16 bytes", pxa2xx_ssp_vmstate_validate), 524 VMSTATE_UINT32_ARRAY(rx_fifo, PXA2xxSSPState, 16), 525 VMSTATE_END_OF_LIST() 526 } 527 }; 528 529 #define SSCR0 0x00 /* SSP Control register 0 */ 530 #define SSCR1 0x04 /* SSP Control register 1 */ 531 #define SSSR 0x08 /* SSP Status register */ 532 #define SSITR 0x0c /* SSP Interrupt Test register */ 533 #define SSDR 0x10 /* SSP Data register */ 534 #define SSTO 0x28 /* SSP Time-Out register */ 535 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */ 536 #define SSTSA 0x30 /* SSP TX Time Slot Active register */ 537 #define SSRSA 0x34 /* SSP RX Time Slot Active register */ 538 #define SSTSS 0x38 /* SSP Time Slot Status register */ 539 #define SSACD 0x3c /* SSP Audio Clock Divider register */ 540 541 /* Bitfields for above registers */ 542 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00) 543 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10) 544 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20) 545 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30) 546 #define SSCR0_SSE (1 << 7) 547 #define SSCR0_RIM (1 << 22) 548 #define SSCR0_TIM (1 << 23) 549 #define SSCR0_MOD (1U << 31) 550 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1) 551 #define SSCR1_RIE (1 << 0) 552 #define SSCR1_TIE (1 << 1) 553 #define SSCR1_LBM (1 << 2) 554 #define SSCR1_MWDS (1 << 5) 555 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1) 556 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1) 557 #define SSCR1_EFWR (1 << 14) 558 #define SSCR1_PINTE (1 << 18) 559 #define SSCR1_TINTE (1 << 19) 560 #define SSCR1_RSRE (1 << 20) 561 #define SSCR1_TSRE (1 << 21) 562 #define SSCR1_EBCEI (1 << 29) 563 #define SSITR_INT (7 << 5) 564 #define SSSR_TNF (1 << 2) 565 #define SSSR_RNE (1 << 3) 566 #define SSSR_TFS (1 << 5) 567 #define SSSR_RFS (1 << 6) 568 #define SSSR_ROR (1 << 7) 569 #define SSSR_PINT (1 << 18) 570 #define SSSR_TINT (1 << 19) 571 #define SSSR_EOC (1 << 20) 572 #define SSSR_TUR (1 << 21) 573 #define SSSR_BCE (1 << 23) 574 #define SSSR_RW 0x00bc0080 575 576 static void pxa2xx_ssp_int_update(PXA2xxSSPState *s) 577 { 578 int level = 0; 579 580 level |= s->ssitr & SSITR_INT; 581 level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI); 582 level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM); 583 level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT)); 584 level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE); 585 level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE); 586 level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM); 587 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE); 588 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE); 589 qemu_set_irq(s->irq, !!level); 590 } 591 592 static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s) 593 { 594 s->sssr &= ~(0xf << 12); /* Clear RFL */ 595 s->sssr &= ~(0xf << 8); /* Clear TFL */ 596 s->sssr &= ~SSSR_TFS; 597 s->sssr &= ~SSSR_TNF; 598 if (s->enable) { 599 s->sssr |= ((s->rx_level - 1) & 0xf) << 12; 600 if (s->rx_level >= SSCR1_RFT(s->sscr[1])) 601 s->sssr |= SSSR_RFS; 602 else 603 s->sssr &= ~SSSR_RFS; 604 if (s->rx_level) 605 s->sssr |= SSSR_RNE; 606 else 607 s->sssr &= ~SSSR_RNE; 608 /* TX FIFO is never filled, so it is always in underrun 609 condition if SSP is enabled */ 610 s->sssr |= SSSR_TFS; 611 s->sssr |= SSSR_TNF; 612 } 613 614 pxa2xx_ssp_int_update(s); 615 } 616 617 static uint64_t pxa2xx_ssp_read(void *opaque, hwaddr addr, 618 unsigned size) 619 { 620 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; 621 uint32_t retval; 622 623 switch (addr) { 624 case SSCR0: 625 return s->sscr[0]; 626 case SSCR1: 627 return s->sscr[1]; 628 case SSPSP: 629 return s->sspsp; 630 case SSTO: 631 return s->ssto; 632 case SSITR: 633 return s->ssitr; 634 case SSSR: 635 return s->sssr | s->ssitr; 636 case SSDR: 637 if (!s->enable) 638 return 0xffffffff; 639 if (s->rx_level < 1) { 640 printf("%s: SSP Rx Underrun\n", __func__); 641 return 0xffffffff; 642 } 643 s->rx_level --; 644 retval = s->rx_fifo[s->rx_start ++]; 645 s->rx_start &= 0xf; 646 pxa2xx_ssp_fifo_update(s); 647 return retval; 648 case SSTSA: 649 return s->sstsa; 650 case SSRSA: 651 return s->ssrsa; 652 case SSTSS: 653 return 0; 654 case SSACD: 655 return s->ssacd; 656 default: 657 qemu_log_mask(LOG_GUEST_ERROR, 658 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 659 __func__, addr); 660 break; 661 } 662 return 0; 663 } 664 665 static void pxa2xx_ssp_write(void *opaque, hwaddr addr, 666 uint64_t value64, unsigned size) 667 { 668 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; 669 uint32_t value = value64; 670 671 switch (addr) { 672 case SSCR0: 673 s->sscr[0] = value & 0xc7ffffff; 674 s->enable = value & SSCR0_SSE; 675 if (value & SSCR0_MOD) 676 printf("%s: Attempt to use network mode\n", __func__); 677 if (s->enable && SSCR0_DSS(value) < 4) 678 printf("%s: Wrong data size: %i bits\n", __func__, 679 SSCR0_DSS(value)); 680 if (!(value & SSCR0_SSE)) { 681 s->sssr = 0; 682 s->ssitr = 0; 683 s->rx_level = 0; 684 } 685 pxa2xx_ssp_fifo_update(s); 686 break; 687 688 case SSCR1: 689 s->sscr[1] = value; 690 if (value & (SSCR1_LBM | SSCR1_EFWR)) 691 printf("%s: Attempt to use SSP test mode\n", __func__); 692 pxa2xx_ssp_fifo_update(s); 693 break; 694 695 case SSPSP: 696 s->sspsp = value; 697 break; 698 699 case SSTO: 700 s->ssto = value; 701 break; 702 703 case SSITR: 704 s->ssitr = value & SSITR_INT; 705 pxa2xx_ssp_int_update(s); 706 break; 707 708 case SSSR: 709 s->sssr &= ~(value & SSSR_RW); 710 pxa2xx_ssp_int_update(s); 711 break; 712 713 case SSDR: 714 if (SSCR0_UWIRE(s->sscr[0])) { 715 if (s->sscr[1] & SSCR1_MWDS) 716 value &= 0xffff; 717 else 718 value &= 0xff; 719 } else 720 /* Note how 32bits overflow does no harm here */ 721 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1; 722 723 /* Data goes from here to the Tx FIFO and is shifted out from 724 * there directly to the slave, no need to buffer it. 725 */ 726 if (s->enable) { 727 uint32_t readval; 728 readval = ssi_transfer(s->bus, value); 729 if (s->rx_level < 0x10) { 730 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval; 731 } else { 732 s->sssr |= SSSR_ROR; 733 } 734 } 735 pxa2xx_ssp_fifo_update(s); 736 break; 737 738 case SSTSA: 739 s->sstsa = value; 740 break; 741 742 case SSRSA: 743 s->ssrsa = value; 744 break; 745 746 case SSACD: 747 s->ssacd = value; 748 break; 749 750 default: 751 qemu_log_mask(LOG_GUEST_ERROR, 752 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 753 __func__, addr); 754 break; 755 } 756 } 757 758 static const MemoryRegionOps pxa2xx_ssp_ops = { 759 .read = pxa2xx_ssp_read, 760 .write = pxa2xx_ssp_write, 761 .endianness = DEVICE_NATIVE_ENDIAN, 762 }; 763 764 static void pxa2xx_ssp_reset(DeviceState *d) 765 { 766 PXA2xxSSPState *s = PXA2XX_SSP(d); 767 768 s->enable = 0; 769 s->sscr[0] = s->sscr[1] = 0; 770 s->sspsp = 0; 771 s->ssto = 0; 772 s->ssitr = 0; 773 s->sssr = 0; 774 s->sstsa = 0; 775 s->ssrsa = 0; 776 s->ssacd = 0; 777 s->rx_start = s->rx_level = 0; 778 } 779 780 static void pxa2xx_ssp_init(Object *obj) 781 { 782 DeviceState *dev = DEVICE(obj); 783 PXA2xxSSPState *s = PXA2XX_SSP(obj); 784 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 785 sysbus_init_irq(sbd, &s->irq); 786 787 memory_region_init_io(&s->iomem, obj, &pxa2xx_ssp_ops, s, 788 "pxa2xx-ssp", 0x1000); 789 sysbus_init_mmio(sbd, &s->iomem); 790 791 s->bus = ssi_create_bus(dev, "ssi"); 792 } 793 794 /* Real-Time Clock */ 795 #define RCNR 0x00 /* RTC Counter register */ 796 #define RTAR 0x04 /* RTC Alarm register */ 797 #define RTSR 0x08 /* RTC Status register */ 798 #define RTTR 0x0c /* RTC Timer Trim register */ 799 #define RDCR 0x10 /* RTC Day Counter register */ 800 #define RYCR 0x14 /* RTC Year Counter register */ 801 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */ 802 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */ 803 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */ 804 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */ 805 #define SWCR 0x28 /* RTC Stopwatch Counter register */ 806 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */ 807 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */ 808 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */ 809 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */ 810 811 #define TYPE_PXA2XX_RTC "pxa2xx_rtc" 812 #define PXA2XX_RTC(obj) \ 813 OBJECT_CHECK(PXA2xxRTCState, (obj), TYPE_PXA2XX_RTC) 814 815 typedef struct { 816 /*< private >*/ 817 SysBusDevice parent_obj; 818 /*< public >*/ 819 820 MemoryRegion iomem; 821 uint32_t rttr; 822 uint32_t rtsr; 823 uint32_t rtar; 824 uint32_t rdar1; 825 uint32_t rdar2; 826 uint32_t ryar1; 827 uint32_t ryar2; 828 uint32_t swar1; 829 uint32_t swar2; 830 uint32_t piar; 831 uint32_t last_rcnr; 832 uint32_t last_rdcr; 833 uint32_t last_rycr; 834 uint32_t last_swcr; 835 uint32_t last_rtcpicr; 836 int64_t last_hz; 837 int64_t last_sw; 838 int64_t last_pi; 839 QEMUTimer *rtc_hz; 840 QEMUTimer *rtc_rdal1; 841 QEMUTimer *rtc_rdal2; 842 QEMUTimer *rtc_swal1; 843 QEMUTimer *rtc_swal2; 844 QEMUTimer *rtc_pi; 845 qemu_irq rtc_irq; 846 } PXA2xxRTCState; 847 848 static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s) 849 { 850 qemu_set_irq(s->rtc_irq, !!(s->rtsr & 0x2553)); 851 } 852 853 static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s) 854 { 855 int64_t rt = qemu_clock_get_ms(rtc_clock); 856 s->last_rcnr += ((rt - s->last_hz) << 15) / 857 (1000 * ((s->rttr & 0xffff) + 1)); 858 s->last_rdcr += ((rt - s->last_hz) << 15) / 859 (1000 * ((s->rttr & 0xffff) + 1)); 860 s->last_hz = rt; 861 } 862 863 static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s) 864 { 865 int64_t rt = qemu_clock_get_ms(rtc_clock); 866 if (s->rtsr & (1 << 12)) 867 s->last_swcr += (rt - s->last_sw) / 10; 868 s->last_sw = rt; 869 } 870 871 static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s) 872 { 873 int64_t rt = qemu_clock_get_ms(rtc_clock); 874 if (s->rtsr & (1 << 15)) 875 s->last_swcr += rt - s->last_pi; 876 s->last_pi = rt; 877 } 878 879 static inline void pxa2xx_rtc_alarm_update(PXA2xxRTCState *s, 880 uint32_t rtsr) 881 { 882 if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0))) 883 timer_mod(s->rtc_hz, s->last_hz + 884 (((s->rtar - s->last_rcnr) * 1000 * 885 ((s->rttr & 0xffff) + 1)) >> 15)); 886 else 887 timer_del(s->rtc_hz); 888 889 if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4))) 890 timer_mod(s->rtc_rdal1, s->last_hz + 891 (((s->rdar1 - s->last_rdcr) * 1000 * 892 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */ 893 else 894 timer_del(s->rtc_rdal1); 895 896 if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6))) 897 timer_mod(s->rtc_rdal2, s->last_hz + 898 (((s->rdar2 - s->last_rdcr) * 1000 * 899 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */ 900 else 901 timer_del(s->rtc_rdal2); 902 903 if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8))) 904 timer_mod(s->rtc_swal1, s->last_sw + 905 (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */ 906 else 907 timer_del(s->rtc_swal1); 908 909 if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10))) 910 timer_mod(s->rtc_swal2, s->last_sw + 911 (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */ 912 else 913 timer_del(s->rtc_swal2); 914 915 if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13))) 916 timer_mod(s->rtc_pi, s->last_pi + 917 (s->piar & 0xffff) - s->last_rtcpicr); 918 else 919 timer_del(s->rtc_pi); 920 } 921 922 static inline void pxa2xx_rtc_hz_tick(void *opaque) 923 { 924 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 925 s->rtsr |= (1 << 0); 926 pxa2xx_rtc_alarm_update(s, s->rtsr); 927 pxa2xx_rtc_int_update(s); 928 } 929 930 static inline void pxa2xx_rtc_rdal1_tick(void *opaque) 931 { 932 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 933 s->rtsr |= (1 << 4); 934 pxa2xx_rtc_alarm_update(s, s->rtsr); 935 pxa2xx_rtc_int_update(s); 936 } 937 938 static inline void pxa2xx_rtc_rdal2_tick(void *opaque) 939 { 940 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 941 s->rtsr |= (1 << 6); 942 pxa2xx_rtc_alarm_update(s, s->rtsr); 943 pxa2xx_rtc_int_update(s); 944 } 945 946 static inline void pxa2xx_rtc_swal1_tick(void *opaque) 947 { 948 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 949 s->rtsr |= (1 << 8); 950 pxa2xx_rtc_alarm_update(s, s->rtsr); 951 pxa2xx_rtc_int_update(s); 952 } 953 954 static inline void pxa2xx_rtc_swal2_tick(void *opaque) 955 { 956 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 957 s->rtsr |= (1 << 10); 958 pxa2xx_rtc_alarm_update(s, s->rtsr); 959 pxa2xx_rtc_int_update(s); 960 } 961 962 static inline void pxa2xx_rtc_pi_tick(void *opaque) 963 { 964 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 965 s->rtsr |= (1 << 13); 966 pxa2xx_rtc_piupdate(s); 967 s->last_rtcpicr = 0; 968 pxa2xx_rtc_alarm_update(s, s->rtsr); 969 pxa2xx_rtc_int_update(s); 970 } 971 972 static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr, 973 unsigned size) 974 { 975 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 976 977 switch (addr) { 978 case RTTR: 979 return s->rttr; 980 case RTSR: 981 return s->rtsr; 982 case RTAR: 983 return s->rtar; 984 case RDAR1: 985 return s->rdar1; 986 case RDAR2: 987 return s->rdar2; 988 case RYAR1: 989 return s->ryar1; 990 case RYAR2: 991 return s->ryar2; 992 case SWAR1: 993 return s->swar1; 994 case SWAR2: 995 return s->swar2; 996 case PIAR: 997 return s->piar; 998 case RCNR: 999 return s->last_rcnr + 1000 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / 1001 (1000 * ((s->rttr & 0xffff) + 1)); 1002 case RDCR: 1003 return s->last_rdcr + 1004 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / 1005 (1000 * ((s->rttr & 0xffff) + 1)); 1006 case RYCR: 1007 return s->last_rycr; 1008 case SWCR: 1009 if (s->rtsr & (1 << 12)) 1010 return s->last_swcr + 1011 (qemu_clock_get_ms(rtc_clock) - s->last_sw) / 10; 1012 else 1013 return s->last_swcr; 1014 default: 1015 qemu_log_mask(LOG_GUEST_ERROR, 1016 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 1017 __func__, addr); 1018 break; 1019 } 1020 return 0; 1021 } 1022 1023 static void pxa2xx_rtc_write(void *opaque, hwaddr addr, 1024 uint64_t value64, unsigned size) 1025 { 1026 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 1027 uint32_t value = value64; 1028 1029 switch (addr) { 1030 case RTTR: 1031 if (!(s->rttr & (1U << 31))) { 1032 pxa2xx_rtc_hzupdate(s); 1033 s->rttr = value; 1034 pxa2xx_rtc_alarm_update(s, s->rtsr); 1035 } 1036 break; 1037 1038 case RTSR: 1039 if ((s->rtsr ^ value) & (1 << 15)) 1040 pxa2xx_rtc_piupdate(s); 1041 1042 if ((s->rtsr ^ value) & (1 << 12)) 1043 pxa2xx_rtc_swupdate(s); 1044 1045 if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac)) 1046 pxa2xx_rtc_alarm_update(s, value); 1047 1048 s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac)); 1049 pxa2xx_rtc_int_update(s); 1050 break; 1051 1052 case RTAR: 1053 s->rtar = value; 1054 pxa2xx_rtc_alarm_update(s, s->rtsr); 1055 break; 1056 1057 case RDAR1: 1058 s->rdar1 = value; 1059 pxa2xx_rtc_alarm_update(s, s->rtsr); 1060 break; 1061 1062 case RDAR2: 1063 s->rdar2 = value; 1064 pxa2xx_rtc_alarm_update(s, s->rtsr); 1065 break; 1066 1067 case RYAR1: 1068 s->ryar1 = value; 1069 pxa2xx_rtc_alarm_update(s, s->rtsr); 1070 break; 1071 1072 case RYAR2: 1073 s->ryar2 = value; 1074 pxa2xx_rtc_alarm_update(s, s->rtsr); 1075 break; 1076 1077 case SWAR1: 1078 pxa2xx_rtc_swupdate(s); 1079 s->swar1 = value; 1080 s->last_swcr = 0; 1081 pxa2xx_rtc_alarm_update(s, s->rtsr); 1082 break; 1083 1084 case SWAR2: 1085 s->swar2 = value; 1086 pxa2xx_rtc_alarm_update(s, s->rtsr); 1087 break; 1088 1089 case PIAR: 1090 s->piar = value; 1091 pxa2xx_rtc_alarm_update(s, s->rtsr); 1092 break; 1093 1094 case RCNR: 1095 pxa2xx_rtc_hzupdate(s); 1096 s->last_rcnr = value; 1097 pxa2xx_rtc_alarm_update(s, s->rtsr); 1098 break; 1099 1100 case RDCR: 1101 pxa2xx_rtc_hzupdate(s); 1102 s->last_rdcr = value; 1103 pxa2xx_rtc_alarm_update(s, s->rtsr); 1104 break; 1105 1106 case RYCR: 1107 s->last_rycr = value; 1108 break; 1109 1110 case SWCR: 1111 pxa2xx_rtc_swupdate(s); 1112 s->last_swcr = value; 1113 pxa2xx_rtc_alarm_update(s, s->rtsr); 1114 break; 1115 1116 case RTCPICR: 1117 pxa2xx_rtc_piupdate(s); 1118 s->last_rtcpicr = value & 0xffff; 1119 pxa2xx_rtc_alarm_update(s, s->rtsr); 1120 break; 1121 1122 default: 1123 qemu_log_mask(LOG_GUEST_ERROR, 1124 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 1125 __func__, addr); 1126 } 1127 } 1128 1129 static const MemoryRegionOps pxa2xx_rtc_ops = { 1130 .read = pxa2xx_rtc_read, 1131 .write = pxa2xx_rtc_write, 1132 .endianness = DEVICE_NATIVE_ENDIAN, 1133 }; 1134 1135 static void pxa2xx_rtc_init(Object *obj) 1136 { 1137 PXA2xxRTCState *s = PXA2XX_RTC(obj); 1138 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 1139 struct tm tm; 1140 int wom; 1141 1142 s->rttr = 0x7fff; 1143 s->rtsr = 0; 1144 1145 qemu_get_timedate(&tm, 0); 1146 wom = ((tm.tm_mday - 1) / 7) + 1; 1147 1148 s->last_rcnr = (uint32_t) mktimegm(&tm); 1149 s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) | 1150 (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec; 1151 s->last_rycr = ((tm.tm_year + 1900) << 9) | 1152 ((tm.tm_mon + 1) << 5) | tm.tm_mday; 1153 s->last_swcr = (tm.tm_hour << 19) | 1154 (tm.tm_min << 13) | (tm.tm_sec << 7); 1155 s->last_rtcpicr = 0; 1156 s->last_hz = s->last_sw = s->last_pi = qemu_clock_get_ms(rtc_clock); 1157 1158 sysbus_init_irq(dev, &s->rtc_irq); 1159 1160 memory_region_init_io(&s->iomem, obj, &pxa2xx_rtc_ops, s, 1161 "pxa2xx-rtc", 0x10000); 1162 sysbus_init_mmio(dev, &s->iomem); 1163 } 1164 1165 static void pxa2xx_rtc_realize(DeviceState *dev, Error **errp) 1166 { 1167 PXA2xxRTCState *s = PXA2XX_RTC(dev); 1168 s->rtc_hz = timer_new_ms(rtc_clock, pxa2xx_rtc_hz_tick, s); 1169 s->rtc_rdal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal1_tick, s); 1170 s->rtc_rdal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal2_tick, s); 1171 s->rtc_swal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal1_tick, s); 1172 s->rtc_swal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal2_tick, s); 1173 s->rtc_pi = timer_new_ms(rtc_clock, pxa2xx_rtc_pi_tick, s); 1174 } 1175 1176 static int pxa2xx_rtc_pre_save(void *opaque) 1177 { 1178 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 1179 1180 pxa2xx_rtc_hzupdate(s); 1181 pxa2xx_rtc_piupdate(s); 1182 pxa2xx_rtc_swupdate(s); 1183 1184 return 0; 1185 } 1186 1187 static int pxa2xx_rtc_post_load(void *opaque, int version_id) 1188 { 1189 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 1190 1191 pxa2xx_rtc_alarm_update(s, s->rtsr); 1192 1193 return 0; 1194 } 1195 1196 static const VMStateDescription vmstate_pxa2xx_rtc_regs = { 1197 .name = "pxa2xx_rtc", 1198 .version_id = 0, 1199 .minimum_version_id = 0, 1200 .pre_save = pxa2xx_rtc_pre_save, 1201 .post_load = pxa2xx_rtc_post_load, 1202 .fields = (VMStateField[]) { 1203 VMSTATE_UINT32(rttr, PXA2xxRTCState), 1204 VMSTATE_UINT32(rtsr, PXA2xxRTCState), 1205 VMSTATE_UINT32(rtar, PXA2xxRTCState), 1206 VMSTATE_UINT32(rdar1, PXA2xxRTCState), 1207 VMSTATE_UINT32(rdar2, PXA2xxRTCState), 1208 VMSTATE_UINT32(ryar1, PXA2xxRTCState), 1209 VMSTATE_UINT32(ryar2, PXA2xxRTCState), 1210 VMSTATE_UINT32(swar1, PXA2xxRTCState), 1211 VMSTATE_UINT32(swar2, PXA2xxRTCState), 1212 VMSTATE_UINT32(piar, PXA2xxRTCState), 1213 VMSTATE_UINT32(last_rcnr, PXA2xxRTCState), 1214 VMSTATE_UINT32(last_rdcr, PXA2xxRTCState), 1215 VMSTATE_UINT32(last_rycr, PXA2xxRTCState), 1216 VMSTATE_UINT32(last_swcr, PXA2xxRTCState), 1217 VMSTATE_UINT32(last_rtcpicr, PXA2xxRTCState), 1218 VMSTATE_INT64(last_hz, PXA2xxRTCState), 1219 VMSTATE_INT64(last_sw, PXA2xxRTCState), 1220 VMSTATE_INT64(last_pi, PXA2xxRTCState), 1221 VMSTATE_END_OF_LIST(), 1222 }, 1223 }; 1224 1225 static void pxa2xx_rtc_sysbus_class_init(ObjectClass *klass, void *data) 1226 { 1227 DeviceClass *dc = DEVICE_CLASS(klass); 1228 1229 dc->desc = "PXA2xx RTC Controller"; 1230 dc->vmsd = &vmstate_pxa2xx_rtc_regs; 1231 dc->realize = pxa2xx_rtc_realize; 1232 } 1233 1234 static const TypeInfo pxa2xx_rtc_sysbus_info = { 1235 .name = TYPE_PXA2XX_RTC, 1236 .parent = TYPE_SYS_BUS_DEVICE, 1237 .instance_size = sizeof(PXA2xxRTCState), 1238 .instance_init = pxa2xx_rtc_init, 1239 .class_init = pxa2xx_rtc_sysbus_class_init, 1240 }; 1241 1242 /* I2C Interface */ 1243 1244 #define TYPE_PXA2XX_I2C_SLAVE "pxa2xx-i2c-slave" 1245 #define PXA2XX_I2C_SLAVE(obj) \ 1246 OBJECT_CHECK(PXA2xxI2CSlaveState, (obj), TYPE_PXA2XX_I2C_SLAVE) 1247 1248 typedef struct PXA2xxI2CSlaveState { 1249 I2CSlave parent_obj; 1250 1251 PXA2xxI2CState *host; 1252 } PXA2xxI2CSlaveState; 1253 1254 struct PXA2xxI2CState { 1255 /*< private >*/ 1256 SysBusDevice parent_obj; 1257 /*< public >*/ 1258 1259 MemoryRegion iomem; 1260 PXA2xxI2CSlaveState *slave; 1261 I2CBus *bus; 1262 qemu_irq irq; 1263 uint32_t offset; 1264 uint32_t region_size; 1265 1266 uint16_t control; 1267 uint16_t status; 1268 uint8_t ibmr; 1269 uint8_t data; 1270 }; 1271 1272 #define IBMR 0x80 /* I2C Bus Monitor register */ 1273 #define IDBR 0x88 /* I2C Data Buffer register */ 1274 #define ICR 0x90 /* I2C Control register */ 1275 #define ISR 0x98 /* I2C Status register */ 1276 #define ISAR 0xa0 /* I2C Slave Address register */ 1277 1278 static void pxa2xx_i2c_update(PXA2xxI2CState *s) 1279 { 1280 uint16_t level = 0; 1281 level |= s->status & s->control & (1 << 10); /* BED */ 1282 level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */ 1283 level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */ 1284 level |= s->status & (1 << 9); /* SAD */ 1285 qemu_set_irq(s->irq, !!level); 1286 } 1287 1288 /* These are only stubs now. */ 1289 static int pxa2xx_i2c_event(I2CSlave *i2c, enum i2c_event event) 1290 { 1291 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c); 1292 PXA2xxI2CState *s = slave->host; 1293 1294 switch (event) { 1295 case I2C_START_SEND: 1296 s->status |= (1 << 9); /* set SAD */ 1297 s->status &= ~(1 << 0); /* clear RWM */ 1298 break; 1299 case I2C_START_RECV: 1300 s->status |= (1 << 9); /* set SAD */ 1301 s->status |= 1 << 0; /* set RWM */ 1302 break; 1303 case I2C_FINISH: 1304 s->status |= (1 << 4); /* set SSD */ 1305 break; 1306 case I2C_NACK: 1307 s->status |= 1 << 1; /* set ACKNAK */ 1308 break; 1309 } 1310 pxa2xx_i2c_update(s); 1311 1312 return 0; 1313 } 1314 1315 static uint8_t pxa2xx_i2c_rx(I2CSlave *i2c) 1316 { 1317 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c); 1318 PXA2xxI2CState *s = slave->host; 1319 1320 if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) { 1321 return 0; 1322 } 1323 1324 if (s->status & (1 << 0)) { /* RWM */ 1325 s->status |= 1 << 6; /* set ITE */ 1326 } 1327 pxa2xx_i2c_update(s); 1328 1329 return s->data; 1330 } 1331 1332 static int pxa2xx_i2c_tx(I2CSlave *i2c, uint8_t data) 1333 { 1334 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c); 1335 PXA2xxI2CState *s = slave->host; 1336 1337 if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) { 1338 return 1; 1339 } 1340 1341 if (!(s->status & (1 << 0))) { /* RWM */ 1342 s->status |= 1 << 7; /* set IRF */ 1343 s->data = data; 1344 } 1345 pxa2xx_i2c_update(s); 1346 1347 return 1; 1348 } 1349 1350 static uint64_t pxa2xx_i2c_read(void *opaque, hwaddr addr, 1351 unsigned size) 1352 { 1353 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; 1354 I2CSlave *slave; 1355 1356 addr -= s->offset; 1357 switch (addr) { 1358 case ICR: 1359 return s->control; 1360 case ISR: 1361 return s->status | (i2c_bus_busy(s->bus) << 2); 1362 case ISAR: 1363 slave = I2C_SLAVE(s->slave); 1364 return slave->address; 1365 case IDBR: 1366 return s->data; 1367 case IBMR: 1368 if (s->status & (1 << 2)) 1369 s->ibmr ^= 3; /* Fake SCL and SDA pin changes */ 1370 else 1371 s->ibmr = 0; 1372 return s->ibmr; 1373 default: 1374 qemu_log_mask(LOG_GUEST_ERROR, 1375 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 1376 __func__, addr); 1377 break; 1378 } 1379 return 0; 1380 } 1381 1382 static void pxa2xx_i2c_write(void *opaque, hwaddr addr, 1383 uint64_t value64, unsigned size) 1384 { 1385 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; 1386 uint32_t value = value64; 1387 int ack; 1388 1389 addr -= s->offset; 1390 switch (addr) { 1391 case ICR: 1392 s->control = value & 0xfff7; 1393 if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */ 1394 /* TODO: slave mode */ 1395 if (value & (1 << 0)) { /* START condition */ 1396 if (s->data & 1) 1397 s->status |= 1 << 0; /* set RWM */ 1398 else 1399 s->status &= ~(1 << 0); /* clear RWM */ 1400 ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1); 1401 } else { 1402 if (s->status & (1 << 0)) { /* RWM */ 1403 s->data = i2c_recv(s->bus); 1404 if (value & (1 << 2)) /* ACKNAK */ 1405 i2c_nack(s->bus); 1406 ack = 1; 1407 } else 1408 ack = !i2c_send(s->bus, s->data); 1409 } 1410 1411 if (value & (1 << 1)) /* STOP condition */ 1412 i2c_end_transfer(s->bus); 1413 1414 if (ack) { 1415 if (value & (1 << 0)) /* START condition */ 1416 s->status |= 1 << 6; /* set ITE */ 1417 else 1418 if (s->status & (1 << 0)) /* RWM */ 1419 s->status |= 1 << 7; /* set IRF */ 1420 else 1421 s->status |= 1 << 6; /* set ITE */ 1422 s->status &= ~(1 << 1); /* clear ACKNAK */ 1423 } else { 1424 s->status |= 1 << 6; /* set ITE */ 1425 s->status |= 1 << 10; /* set BED */ 1426 s->status |= 1 << 1; /* set ACKNAK */ 1427 } 1428 } 1429 if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */ 1430 if (value & (1 << 4)) /* MA */ 1431 i2c_end_transfer(s->bus); 1432 pxa2xx_i2c_update(s); 1433 break; 1434 1435 case ISR: 1436 s->status &= ~(value & 0x07f0); 1437 pxa2xx_i2c_update(s); 1438 break; 1439 1440 case ISAR: 1441 i2c_set_slave_address(I2C_SLAVE(s->slave), value & 0x7f); 1442 break; 1443 1444 case IDBR: 1445 s->data = value & 0xff; 1446 break; 1447 1448 default: 1449 qemu_log_mask(LOG_GUEST_ERROR, 1450 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 1451 __func__, addr); 1452 } 1453 } 1454 1455 static const MemoryRegionOps pxa2xx_i2c_ops = { 1456 .read = pxa2xx_i2c_read, 1457 .write = pxa2xx_i2c_write, 1458 .endianness = DEVICE_NATIVE_ENDIAN, 1459 }; 1460 1461 static const VMStateDescription vmstate_pxa2xx_i2c_slave = { 1462 .name = "pxa2xx_i2c_slave", 1463 .version_id = 1, 1464 .minimum_version_id = 1, 1465 .fields = (VMStateField[]) { 1466 VMSTATE_I2C_SLAVE(parent_obj, PXA2xxI2CSlaveState), 1467 VMSTATE_END_OF_LIST() 1468 } 1469 }; 1470 1471 static const VMStateDescription vmstate_pxa2xx_i2c = { 1472 .name = "pxa2xx_i2c", 1473 .version_id = 1, 1474 .minimum_version_id = 1, 1475 .fields = (VMStateField[]) { 1476 VMSTATE_UINT16(control, PXA2xxI2CState), 1477 VMSTATE_UINT16(status, PXA2xxI2CState), 1478 VMSTATE_UINT8(ibmr, PXA2xxI2CState), 1479 VMSTATE_UINT8(data, PXA2xxI2CState), 1480 VMSTATE_STRUCT_POINTER(slave, PXA2xxI2CState, 1481 vmstate_pxa2xx_i2c_slave, PXA2xxI2CSlaveState), 1482 VMSTATE_END_OF_LIST() 1483 } 1484 }; 1485 1486 static void pxa2xx_i2c_slave_class_init(ObjectClass *klass, void *data) 1487 { 1488 I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); 1489 1490 k->event = pxa2xx_i2c_event; 1491 k->recv = pxa2xx_i2c_rx; 1492 k->send = pxa2xx_i2c_tx; 1493 } 1494 1495 static const TypeInfo pxa2xx_i2c_slave_info = { 1496 .name = TYPE_PXA2XX_I2C_SLAVE, 1497 .parent = TYPE_I2C_SLAVE, 1498 .instance_size = sizeof(PXA2xxI2CSlaveState), 1499 .class_init = pxa2xx_i2c_slave_class_init, 1500 }; 1501 1502 PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base, 1503 qemu_irq irq, uint32_t region_size) 1504 { 1505 DeviceState *dev; 1506 SysBusDevice *i2c_dev; 1507 PXA2xxI2CState *s; 1508 I2CBus *i2cbus; 1509 1510 dev = qdev_new(TYPE_PXA2XX_I2C); 1511 qdev_prop_set_uint32(dev, "size", region_size + 1); 1512 qdev_prop_set_uint32(dev, "offset", base & region_size); 1513 1514 i2c_dev = SYS_BUS_DEVICE(dev); 1515 sysbus_realize_and_unref(i2c_dev, &error_fatal); 1516 sysbus_mmio_map(i2c_dev, 0, base & ~region_size); 1517 sysbus_connect_irq(i2c_dev, 0, irq); 1518 1519 s = PXA2XX_I2C(i2c_dev); 1520 /* FIXME: Should the slave device really be on a separate bus? */ 1521 i2cbus = i2c_init_bus(dev, "dummy"); 1522 s->slave = PXA2XX_I2C_SLAVE(i2c_slave_create_simple(i2cbus, 1523 TYPE_PXA2XX_I2C_SLAVE, 1524 0)); 1525 s->slave->host = s; 1526 1527 return s; 1528 } 1529 1530 static void pxa2xx_i2c_initfn(Object *obj) 1531 { 1532 DeviceState *dev = DEVICE(obj); 1533 PXA2xxI2CState *s = PXA2XX_I2C(obj); 1534 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1535 1536 s->bus = i2c_init_bus(dev, NULL); 1537 1538 memory_region_init_io(&s->iomem, obj, &pxa2xx_i2c_ops, s, 1539 "pxa2xx-i2c", s->region_size); 1540 sysbus_init_mmio(sbd, &s->iomem); 1541 sysbus_init_irq(sbd, &s->irq); 1542 } 1543 1544 I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s) 1545 { 1546 return s->bus; 1547 } 1548 1549 static Property pxa2xx_i2c_properties[] = { 1550 DEFINE_PROP_UINT32("size", PXA2xxI2CState, region_size, 0x10000), 1551 DEFINE_PROP_UINT32("offset", PXA2xxI2CState, offset, 0), 1552 DEFINE_PROP_END_OF_LIST(), 1553 }; 1554 1555 static void pxa2xx_i2c_class_init(ObjectClass *klass, void *data) 1556 { 1557 DeviceClass *dc = DEVICE_CLASS(klass); 1558 1559 dc->desc = "PXA2xx I2C Bus Controller"; 1560 dc->vmsd = &vmstate_pxa2xx_i2c; 1561 device_class_set_props(dc, pxa2xx_i2c_properties); 1562 } 1563 1564 static const TypeInfo pxa2xx_i2c_info = { 1565 .name = TYPE_PXA2XX_I2C, 1566 .parent = TYPE_SYS_BUS_DEVICE, 1567 .instance_size = sizeof(PXA2xxI2CState), 1568 .instance_init = pxa2xx_i2c_initfn, 1569 .class_init = pxa2xx_i2c_class_init, 1570 }; 1571 1572 /* PXA Inter-IC Sound Controller */ 1573 static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s) 1574 { 1575 i2s->rx_len = 0; 1576 i2s->tx_len = 0; 1577 i2s->fifo_len = 0; 1578 i2s->clk = 0x1a; 1579 i2s->control[0] = 0x00; 1580 i2s->control[1] = 0x00; 1581 i2s->status = 0x00; 1582 i2s->mask = 0x00; 1583 } 1584 1585 #define SACR_TFTH(val) ((val >> 8) & 0xf) 1586 #define SACR_RFTH(val) ((val >> 12) & 0xf) 1587 #define SACR_DREC(val) (val & (1 << 3)) 1588 #define SACR_DPRL(val) (val & (1 << 4)) 1589 1590 static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s) 1591 { 1592 int rfs, tfs; 1593 rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len && 1594 !SACR_DREC(i2s->control[1]); 1595 tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) && 1596 i2s->enable && !SACR_DPRL(i2s->control[1]); 1597 1598 qemu_set_irq(i2s->rx_dma, rfs); 1599 qemu_set_irq(i2s->tx_dma, tfs); 1600 1601 i2s->status &= 0xe0; 1602 if (i2s->fifo_len < 16 || !i2s->enable) 1603 i2s->status |= 1 << 0; /* TNF */ 1604 if (i2s->rx_len) 1605 i2s->status |= 1 << 1; /* RNE */ 1606 if (i2s->enable) 1607 i2s->status |= 1 << 2; /* BSY */ 1608 if (tfs) 1609 i2s->status |= 1 << 3; /* TFS */ 1610 if (rfs) 1611 i2s->status |= 1 << 4; /* RFS */ 1612 if (!(i2s->tx_len && i2s->enable)) 1613 i2s->status |= i2s->fifo_len << 8; /* TFL */ 1614 i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */ 1615 1616 qemu_set_irq(i2s->irq, i2s->status & i2s->mask); 1617 } 1618 1619 #define SACR0 0x00 /* Serial Audio Global Control register */ 1620 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */ 1621 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */ 1622 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */ 1623 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */ 1624 #define SADIV 0x60 /* Serial Audio Clock Divider register */ 1625 #define SADR 0x80 /* Serial Audio Data register */ 1626 1627 static uint64_t pxa2xx_i2s_read(void *opaque, hwaddr addr, 1628 unsigned size) 1629 { 1630 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; 1631 1632 switch (addr) { 1633 case SACR0: 1634 return s->control[0]; 1635 case SACR1: 1636 return s->control[1]; 1637 case SASR0: 1638 return s->status; 1639 case SAIMR: 1640 return s->mask; 1641 case SAICR: 1642 return 0; 1643 case SADIV: 1644 return s->clk; 1645 case SADR: 1646 if (s->rx_len > 0) { 1647 s->rx_len --; 1648 pxa2xx_i2s_update(s); 1649 return s->codec_in(s->opaque); 1650 } 1651 return 0; 1652 default: 1653 qemu_log_mask(LOG_GUEST_ERROR, 1654 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 1655 __func__, addr); 1656 break; 1657 } 1658 return 0; 1659 } 1660 1661 static void pxa2xx_i2s_write(void *opaque, hwaddr addr, 1662 uint64_t value, unsigned size) 1663 { 1664 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; 1665 uint32_t *sample; 1666 1667 switch (addr) { 1668 case SACR0: 1669 if (value & (1 << 3)) /* RST */ 1670 pxa2xx_i2s_reset(s); 1671 s->control[0] = value & 0xff3d; 1672 if (!s->enable && (value & 1) && s->tx_len) { /* ENB */ 1673 for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++) 1674 s->codec_out(s->opaque, *sample); 1675 s->status &= ~(1 << 7); /* I2SOFF */ 1676 } 1677 if (value & (1 << 4)) /* EFWR */ 1678 printf("%s: Attempt to use special function\n", __func__); 1679 s->enable = (value & 9) == 1; /* ENB && !RST*/ 1680 pxa2xx_i2s_update(s); 1681 break; 1682 case SACR1: 1683 s->control[1] = value & 0x0039; 1684 if (value & (1 << 5)) /* ENLBF */ 1685 printf("%s: Attempt to use loopback function\n", __func__); 1686 if (value & (1 << 4)) /* DPRL */ 1687 s->fifo_len = 0; 1688 pxa2xx_i2s_update(s); 1689 break; 1690 case SAIMR: 1691 s->mask = value & 0x0078; 1692 pxa2xx_i2s_update(s); 1693 break; 1694 case SAICR: 1695 s->status &= ~(value & (3 << 5)); 1696 pxa2xx_i2s_update(s); 1697 break; 1698 case SADIV: 1699 s->clk = value & 0x007f; 1700 break; 1701 case SADR: 1702 if (s->tx_len && s->enable) { 1703 s->tx_len --; 1704 pxa2xx_i2s_update(s); 1705 s->codec_out(s->opaque, value); 1706 } else if (s->fifo_len < 16) { 1707 s->fifo[s->fifo_len ++] = value; 1708 pxa2xx_i2s_update(s); 1709 } 1710 break; 1711 default: 1712 qemu_log_mask(LOG_GUEST_ERROR, 1713 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 1714 __func__, addr); 1715 } 1716 } 1717 1718 static const MemoryRegionOps pxa2xx_i2s_ops = { 1719 .read = pxa2xx_i2s_read, 1720 .write = pxa2xx_i2s_write, 1721 .endianness = DEVICE_NATIVE_ENDIAN, 1722 }; 1723 1724 static const VMStateDescription vmstate_pxa2xx_i2s = { 1725 .name = "pxa2xx_i2s", 1726 .version_id = 0, 1727 .minimum_version_id = 0, 1728 .fields = (VMStateField[]) { 1729 VMSTATE_UINT32_ARRAY(control, PXA2xxI2SState, 2), 1730 VMSTATE_UINT32(status, PXA2xxI2SState), 1731 VMSTATE_UINT32(mask, PXA2xxI2SState), 1732 VMSTATE_UINT32(clk, PXA2xxI2SState), 1733 VMSTATE_INT32(enable, PXA2xxI2SState), 1734 VMSTATE_INT32(rx_len, PXA2xxI2SState), 1735 VMSTATE_INT32(tx_len, PXA2xxI2SState), 1736 VMSTATE_INT32(fifo_len, PXA2xxI2SState), 1737 VMSTATE_END_OF_LIST() 1738 } 1739 }; 1740 1741 static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx) 1742 { 1743 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; 1744 uint32_t *sample; 1745 1746 /* Signal FIFO errors */ 1747 if (s->enable && s->tx_len) 1748 s->status |= 1 << 5; /* TUR */ 1749 if (s->enable && s->rx_len) 1750 s->status |= 1 << 6; /* ROR */ 1751 1752 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to 1753 * handle the cases where it makes a difference. */ 1754 s->tx_len = tx - s->fifo_len; 1755 s->rx_len = rx; 1756 /* Note that is s->codec_out wasn't set, we wouldn't get called. */ 1757 if (s->enable) 1758 for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++) 1759 s->codec_out(s->opaque, *sample); 1760 pxa2xx_i2s_update(s); 1761 } 1762 1763 static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem, 1764 hwaddr base, 1765 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma) 1766 { 1767 PXA2xxI2SState *s = g_new0(PXA2xxI2SState, 1); 1768 1769 s->irq = irq; 1770 s->rx_dma = rx_dma; 1771 s->tx_dma = tx_dma; 1772 s->data_req = pxa2xx_i2s_data_req; 1773 1774 pxa2xx_i2s_reset(s); 1775 1776 memory_region_init_io(&s->iomem, NULL, &pxa2xx_i2s_ops, s, 1777 "pxa2xx-i2s", 0x100000); 1778 memory_region_add_subregion(sysmem, base, &s->iomem); 1779 1780 vmstate_register(NULL, base, &vmstate_pxa2xx_i2s, s); 1781 1782 return s; 1783 } 1784 1785 /* PXA Fast Infra-red Communications Port */ 1786 struct PXA2xxFIrState { 1787 /*< private >*/ 1788 SysBusDevice parent_obj; 1789 /*< public >*/ 1790 1791 MemoryRegion iomem; 1792 qemu_irq irq; 1793 qemu_irq rx_dma; 1794 qemu_irq tx_dma; 1795 uint32_t enable; 1796 CharBackend chr; 1797 1798 uint8_t control[3]; 1799 uint8_t status[2]; 1800 1801 uint32_t rx_len; 1802 uint32_t rx_start; 1803 uint8_t rx_fifo[64]; 1804 }; 1805 1806 static void pxa2xx_fir_reset(DeviceState *d) 1807 { 1808 PXA2xxFIrState *s = PXA2XX_FIR(d); 1809 1810 s->control[0] = 0x00; 1811 s->control[1] = 0x00; 1812 s->control[2] = 0x00; 1813 s->status[0] = 0x00; 1814 s->status[1] = 0x00; 1815 s->enable = 0; 1816 } 1817 1818 static inline void pxa2xx_fir_update(PXA2xxFIrState *s) 1819 { 1820 static const int tresh[4] = { 8, 16, 32, 0 }; 1821 int intr = 0; 1822 if ((s->control[0] & (1 << 4)) && /* RXE */ 1823 s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */ 1824 s->status[0] |= 1 << 4; /* RFS */ 1825 else 1826 s->status[0] &= ~(1 << 4); /* RFS */ 1827 if (s->control[0] & (1 << 3)) /* TXE */ 1828 s->status[0] |= 1 << 3; /* TFS */ 1829 else 1830 s->status[0] &= ~(1 << 3); /* TFS */ 1831 if (s->rx_len) 1832 s->status[1] |= 1 << 2; /* RNE */ 1833 else 1834 s->status[1] &= ~(1 << 2); /* RNE */ 1835 if (s->control[0] & (1 << 4)) /* RXE */ 1836 s->status[1] |= 1 << 0; /* RSY */ 1837 else 1838 s->status[1] &= ~(1 << 0); /* RSY */ 1839 1840 intr |= (s->control[0] & (1 << 5)) && /* RIE */ 1841 (s->status[0] & (1 << 4)); /* RFS */ 1842 intr |= (s->control[0] & (1 << 6)) && /* TIE */ 1843 (s->status[0] & (1 << 3)); /* TFS */ 1844 intr |= (s->control[2] & (1 << 4)) && /* TRAIL */ 1845 (s->status[0] & (1 << 6)); /* EOC */ 1846 intr |= (s->control[0] & (1 << 2)) && /* TUS */ 1847 (s->status[0] & (1 << 1)); /* TUR */ 1848 intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */ 1849 1850 qemu_set_irq(s->rx_dma, (s->status[0] >> 4) & 1); 1851 qemu_set_irq(s->tx_dma, (s->status[0] >> 3) & 1); 1852 1853 qemu_set_irq(s->irq, intr && s->enable); 1854 } 1855 1856 #define ICCR0 0x00 /* FICP Control register 0 */ 1857 #define ICCR1 0x04 /* FICP Control register 1 */ 1858 #define ICCR2 0x08 /* FICP Control register 2 */ 1859 #define ICDR 0x0c /* FICP Data register */ 1860 #define ICSR0 0x14 /* FICP Status register 0 */ 1861 #define ICSR1 0x18 /* FICP Status register 1 */ 1862 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */ 1863 1864 static uint64_t pxa2xx_fir_read(void *opaque, hwaddr addr, 1865 unsigned size) 1866 { 1867 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1868 uint8_t ret; 1869 1870 switch (addr) { 1871 case ICCR0: 1872 return s->control[0]; 1873 case ICCR1: 1874 return s->control[1]; 1875 case ICCR2: 1876 return s->control[2]; 1877 case ICDR: 1878 s->status[0] &= ~0x01; 1879 s->status[1] &= ~0x72; 1880 if (s->rx_len) { 1881 s->rx_len --; 1882 ret = s->rx_fifo[s->rx_start ++]; 1883 s->rx_start &= 63; 1884 pxa2xx_fir_update(s); 1885 return ret; 1886 } 1887 printf("%s: Rx FIFO underrun.\n", __func__); 1888 break; 1889 case ICSR0: 1890 return s->status[0]; 1891 case ICSR1: 1892 return s->status[1] | (1 << 3); /* TNF */ 1893 case ICFOR: 1894 return s->rx_len; 1895 default: 1896 qemu_log_mask(LOG_GUEST_ERROR, 1897 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 1898 __func__, addr); 1899 break; 1900 } 1901 return 0; 1902 } 1903 1904 static void pxa2xx_fir_write(void *opaque, hwaddr addr, 1905 uint64_t value64, unsigned size) 1906 { 1907 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1908 uint32_t value = value64; 1909 uint8_t ch; 1910 1911 switch (addr) { 1912 case ICCR0: 1913 s->control[0] = value; 1914 if (!(value & (1 << 4))) /* RXE */ 1915 s->rx_len = s->rx_start = 0; 1916 if (!(value & (1 << 3))) { /* TXE */ 1917 /* Nop */ 1918 } 1919 s->enable = value & 1; /* ITR */ 1920 if (!s->enable) 1921 s->status[0] = 0; 1922 pxa2xx_fir_update(s); 1923 break; 1924 case ICCR1: 1925 s->control[1] = value; 1926 break; 1927 case ICCR2: 1928 s->control[2] = value & 0x3f; 1929 pxa2xx_fir_update(s); 1930 break; 1931 case ICDR: 1932 if (s->control[2] & (1 << 2)) { /* TXP */ 1933 ch = value; 1934 } else { 1935 ch = ~value; 1936 } 1937 if (s->enable && (s->control[0] & (1 << 3))) { /* TXE */ 1938 /* XXX this blocks entire thread. Rewrite to use 1939 * qemu_chr_fe_write and background I/O callbacks */ 1940 qemu_chr_fe_write_all(&s->chr, &ch, 1); 1941 } 1942 break; 1943 case ICSR0: 1944 s->status[0] &= ~(value & 0x66); 1945 pxa2xx_fir_update(s); 1946 break; 1947 case ICFOR: 1948 break; 1949 default: 1950 qemu_log_mask(LOG_GUEST_ERROR, 1951 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 1952 __func__, addr); 1953 } 1954 } 1955 1956 static const MemoryRegionOps pxa2xx_fir_ops = { 1957 .read = pxa2xx_fir_read, 1958 .write = pxa2xx_fir_write, 1959 .endianness = DEVICE_NATIVE_ENDIAN, 1960 }; 1961 1962 static int pxa2xx_fir_is_empty(void *opaque) 1963 { 1964 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1965 return (s->rx_len < 64); 1966 } 1967 1968 static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size) 1969 { 1970 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1971 if (!(s->control[0] & (1 << 4))) /* RXE */ 1972 return; 1973 1974 while (size --) { 1975 s->status[1] |= 1 << 4; /* EOF */ 1976 if (s->rx_len >= 64) { 1977 s->status[1] |= 1 << 6; /* ROR */ 1978 break; 1979 } 1980 1981 if (s->control[2] & (1 << 3)) /* RXP */ 1982 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++); 1983 else 1984 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++); 1985 } 1986 1987 pxa2xx_fir_update(s); 1988 } 1989 1990 static void pxa2xx_fir_event(void *opaque, QEMUChrEvent event) 1991 { 1992 } 1993 1994 static void pxa2xx_fir_instance_init(Object *obj) 1995 { 1996 PXA2xxFIrState *s = PXA2XX_FIR(obj); 1997 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1998 1999 memory_region_init_io(&s->iomem, obj, &pxa2xx_fir_ops, s, 2000 "pxa2xx-fir", 0x1000); 2001 sysbus_init_mmio(sbd, &s->iomem); 2002 sysbus_init_irq(sbd, &s->irq); 2003 sysbus_init_irq(sbd, &s->rx_dma); 2004 sysbus_init_irq(sbd, &s->tx_dma); 2005 } 2006 2007 static void pxa2xx_fir_realize(DeviceState *dev, Error **errp) 2008 { 2009 PXA2xxFIrState *s = PXA2XX_FIR(dev); 2010 2011 qemu_chr_fe_set_handlers(&s->chr, pxa2xx_fir_is_empty, 2012 pxa2xx_fir_rx, pxa2xx_fir_event, NULL, s, NULL, 2013 true); 2014 } 2015 2016 static bool pxa2xx_fir_vmstate_validate(void *opaque, int version_id) 2017 { 2018 PXA2xxFIrState *s = opaque; 2019 2020 return s->rx_start < ARRAY_SIZE(s->rx_fifo); 2021 } 2022 2023 static const VMStateDescription pxa2xx_fir_vmsd = { 2024 .name = "pxa2xx-fir", 2025 .version_id = 1, 2026 .minimum_version_id = 1, 2027 .fields = (VMStateField[]) { 2028 VMSTATE_UINT32(enable, PXA2xxFIrState), 2029 VMSTATE_UINT8_ARRAY(control, PXA2xxFIrState, 3), 2030 VMSTATE_UINT8_ARRAY(status, PXA2xxFIrState, 2), 2031 VMSTATE_UINT32(rx_len, PXA2xxFIrState), 2032 VMSTATE_UINT32(rx_start, PXA2xxFIrState), 2033 VMSTATE_VALIDATE("fifo is 64 bytes", pxa2xx_fir_vmstate_validate), 2034 VMSTATE_UINT8_ARRAY(rx_fifo, PXA2xxFIrState, 64), 2035 VMSTATE_END_OF_LIST() 2036 } 2037 }; 2038 2039 static Property pxa2xx_fir_properties[] = { 2040 DEFINE_PROP_CHR("chardev", PXA2xxFIrState, chr), 2041 DEFINE_PROP_END_OF_LIST(), 2042 }; 2043 2044 static void pxa2xx_fir_class_init(ObjectClass *klass, void *data) 2045 { 2046 DeviceClass *dc = DEVICE_CLASS(klass); 2047 2048 dc->realize = pxa2xx_fir_realize; 2049 dc->vmsd = &pxa2xx_fir_vmsd; 2050 device_class_set_props(dc, pxa2xx_fir_properties); 2051 dc->reset = pxa2xx_fir_reset; 2052 } 2053 2054 static const TypeInfo pxa2xx_fir_info = { 2055 .name = TYPE_PXA2XX_FIR, 2056 .parent = TYPE_SYS_BUS_DEVICE, 2057 .instance_size = sizeof(PXA2xxFIrState), 2058 .class_init = pxa2xx_fir_class_init, 2059 .instance_init = pxa2xx_fir_instance_init, 2060 }; 2061 2062 static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem, 2063 hwaddr base, 2064 qemu_irq irq, qemu_irq rx_dma, 2065 qemu_irq tx_dma, 2066 Chardev *chr) 2067 { 2068 DeviceState *dev; 2069 SysBusDevice *sbd; 2070 2071 dev = qdev_new(TYPE_PXA2XX_FIR); 2072 qdev_prop_set_chr(dev, "chardev", chr); 2073 sbd = SYS_BUS_DEVICE(dev); 2074 sysbus_realize_and_unref(sbd, &error_fatal); 2075 sysbus_mmio_map(sbd, 0, base); 2076 sysbus_connect_irq(sbd, 0, irq); 2077 sysbus_connect_irq(sbd, 1, rx_dma); 2078 sysbus_connect_irq(sbd, 2, tx_dma); 2079 return PXA2XX_FIR(dev); 2080 } 2081 2082 static void pxa2xx_reset(void *opaque, int line, int level) 2083 { 2084 PXA2xxState *s = (PXA2xxState *) opaque; 2085 2086 if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */ 2087 cpu_reset(CPU(s->cpu)); 2088 /* TODO: reset peripherals */ 2089 } 2090 } 2091 2092 /* Initialise a PXA270 integrated chip (ARM based core). */ 2093 PXA2xxState *pxa270_init(MemoryRegion *address_space, 2094 unsigned int sdram_size, const char *cpu_type) 2095 { 2096 PXA2xxState *s; 2097 int i; 2098 DriveInfo *dinfo; 2099 s = g_new0(PXA2xxState, 1); 2100 2101 if (strncmp(cpu_type, "pxa27", 5)) { 2102 error_report("Machine requires a PXA27x processor"); 2103 exit(1); 2104 } 2105 2106 s->cpu = ARM_CPU(cpu_create(cpu_type)); 2107 s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0); 2108 2109 /* SDRAM & Internal Memory Storage */ 2110 memory_region_init_ram(&s->sdram, NULL, "pxa270.sdram", sdram_size, 2111 &error_fatal); 2112 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram); 2113 memory_region_init_ram(&s->internal, NULL, "pxa270.internal", 0x40000, 2114 &error_fatal); 2115 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE, 2116 &s->internal); 2117 2118 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu); 2119 2120 s->dma = pxa27x_dma_init(0x40000000, 2121 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA)); 2122 2123 sysbus_create_varargs("pxa27x-timer", 0x40a00000, 2124 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0), 2125 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1), 2126 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2), 2127 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3), 2128 qdev_get_gpio_in(s->pic, PXA27X_PIC_OST_4_11), 2129 NULL); 2130 2131 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 121); 2132 2133 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, 2134 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), 2135 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), 2136 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); 2137 dinfo = drive_get(IF_SD, 0, 0); 2138 if (dinfo) { 2139 DeviceState *carddev; 2140 2141 /* Create and plug in the sd card */ 2142 carddev = qdev_new(TYPE_SD_CARD); 2143 qdev_prop_set_drive_err(carddev, "drive", 2144 blk_by_legacy_dinfo(dinfo), &error_fatal); 2145 qdev_realize_and_unref(carddev, qdev_get_child_bus(DEVICE(s->mmc), 2146 "sd-bus"), 2147 &error_fatal); 2148 } else if (!qtest_enabled()) { 2149 warn_report("missing SecureDigital device"); 2150 } 2151 2152 for (i = 0; pxa270_serial[i].io_base; i++) { 2153 if (serial_hd(i)) { 2154 serial_mm_init(address_space, pxa270_serial[i].io_base, 2, 2155 qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn), 2156 14857000 / 16, serial_hd(i), 2157 DEVICE_NATIVE_ENDIAN); 2158 } else { 2159 break; 2160 } 2161 } 2162 if (serial_hd(i)) 2163 s->fir = pxa2xx_fir_init(address_space, 0x40800000, 2164 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), 2165 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), 2166 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), 2167 serial_hd(i)); 2168 2169 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000, 2170 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); 2171 2172 s->cm_base = 0x41300000; 2173 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */ 2174 s->clkcfg = 0x00000009; /* Turbo mode active */ 2175 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000); 2176 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); 2177 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); 2178 2179 pxa2xx_setup_cp14(s); 2180 2181 s->mm_base = 0x48000000; 2182 s->mm_regs[MDMRS >> 2] = 0x00020002; 2183 s->mm_regs[MDREFR >> 2] = 0x03ca4000; 2184 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ 2185 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000); 2186 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem); 2187 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s); 2188 2189 s->pm_base = 0x40f00000; 2190 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100); 2191 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem); 2192 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s); 2193 2194 for (i = 0; pxa27x_ssp[i].io_base; i ++); 2195 s->ssp = g_new0(SSIBus *, i); 2196 for (i = 0; pxa27x_ssp[i].io_base; i ++) { 2197 DeviceState *dev; 2198 dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa27x_ssp[i].io_base, 2199 qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn)); 2200 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi"); 2201 } 2202 2203 sysbus_create_simple("sysbus-ohci", 0x4c000000, 2204 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1)); 2205 2206 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000); 2207 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000); 2208 2209 sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000, 2210 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM)); 2211 2212 s->i2c[0] = pxa2xx_i2c_init(0x40301600, 2213 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff); 2214 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, 2215 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff); 2216 2217 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000, 2218 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), 2219 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), 2220 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); 2221 2222 s->kp = pxa27x_keypad_init(address_space, 0x41500000, 2223 qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD)); 2224 2225 /* GPIO1 resets the processor */ 2226 /* The handler can be overridden by board-specific code */ 2227 qdev_connect_gpio_out(s->gpio, 1, s->reset); 2228 return s; 2229 } 2230 2231 /* Initialise a PXA255 integrated chip (ARM based core). */ 2232 PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size) 2233 { 2234 PXA2xxState *s; 2235 int i; 2236 DriveInfo *dinfo; 2237 2238 s = g_new0(PXA2xxState, 1); 2239 2240 s->cpu = ARM_CPU(cpu_create(ARM_CPU_TYPE_NAME("pxa255"))); 2241 s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0); 2242 2243 /* SDRAM & Internal Memory Storage */ 2244 memory_region_init_ram(&s->sdram, NULL, "pxa255.sdram", sdram_size, 2245 &error_fatal); 2246 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram); 2247 memory_region_init_ram(&s->internal, NULL, "pxa255.internal", 2248 PXA2XX_INTERNAL_SIZE, &error_fatal); 2249 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE, 2250 &s->internal); 2251 2252 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu); 2253 2254 s->dma = pxa255_dma_init(0x40000000, 2255 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA)); 2256 2257 sysbus_create_varargs("pxa25x-timer", 0x40a00000, 2258 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0), 2259 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1), 2260 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2), 2261 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3), 2262 NULL); 2263 2264 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 85); 2265 2266 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, 2267 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), 2268 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), 2269 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); 2270 dinfo = drive_get(IF_SD, 0, 0); 2271 if (dinfo) { 2272 DeviceState *carddev; 2273 2274 /* Create and plug in the sd card */ 2275 carddev = qdev_new(TYPE_SD_CARD); 2276 qdev_prop_set_drive_err(carddev, "drive", 2277 blk_by_legacy_dinfo(dinfo), &error_fatal); 2278 qdev_realize_and_unref(carddev, qdev_get_child_bus(DEVICE(s->mmc), 2279 "sd-bus"), 2280 &error_fatal); 2281 } else if (!qtest_enabled()) { 2282 warn_report("missing SecureDigital device"); 2283 } 2284 2285 for (i = 0; pxa255_serial[i].io_base; i++) { 2286 if (serial_hd(i)) { 2287 serial_mm_init(address_space, pxa255_serial[i].io_base, 2, 2288 qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn), 2289 14745600 / 16, serial_hd(i), 2290 DEVICE_NATIVE_ENDIAN); 2291 } else { 2292 break; 2293 } 2294 } 2295 if (serial_hd(i)) 2296 s->fir = pxa2xx_fir_init(address_space, 0x40800000, 2297 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), 2298 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), 2299 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), 2300 serial_hd(i)); 2301 2302 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000, 2303 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); 2304 2305 s->cm_base = 0x41300000; 2306 s->cm_regs[CCCR >> 2] = 0x00000121; /* from datasheet */ 2307 s->cm_regs[CKEN >> 2] = 0x00017def; /* from datasheet */ 2308 2309 s->clkcfg = 0x00000009; /* Turbo mode active */ 2310 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000); 2311 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); 2312 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); 2313 2314 pxa2xx_setup_cp14(s); 2315 2316 s->mm_base = 0x48000000; 2317 s->mm_regs[MDMRS >> 2] = 0x00020002; 2318 s->mm_regs[MDREFR >> 2] = 0x03ca4000; 2319 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ 2320 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000); 2321 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem); 2322 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s); 2323 2324 s->pm_base = 0x40f00000; 2325 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100); 2326 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem); 2327 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s); 2328 2329 for (i = 0; pxa255_ssp[i].io_base; i ++); 2330 s->ssp = g_new0(SSIBus *, i); 2331 for (i = 0; pxa255_ssp[i].io_base; i ++) { 2332 DeviceState *dev; 2333 dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa255_ssp[i].io_base, 2334 qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn)); 2335 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi"); 2336 } 2337 2338 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000); 2339 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000); 2340 2341 sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000, 2342 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM)); 2343 2344 s->i2c[0] = pxa2xx_i2c_init(0x40301600, 2345 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff); 2346 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, 2347 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff); 2348 2349 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000, 2350 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), 2351 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), 2352 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); 2353 2354 /* GPIO1 resets the processor */ 2355 /* The handler can be overridden by board-specific code */ 2356 qdev_connect_gpio_out(s->gpio, 1, s->reset); 2357 return s; 2358 } 2359 2360 static void pxa2xx_ssp_class_init(ObjectClass *klass, void *data) 2361 { 2362 DeviceClass *dc = DEVICE_CLASS(klass); 2363 2364 dc->reset = pxa2xx_ssp_reset; 2365 dc->vmsd = &vmstate_pxa2xx_ssp; 2366 } 2367 2368 static const TypeInfo pxa2xx_ssp_info = { 2369 .name = TYPE_PXA2XX_SSP, 2370 .parent = TYPE_SYS_BUS_DEVICE, 2371 .instance_size = sizeof(PXA2xxSSPState), 2372 .instance_init = pxa2xx_ssp_init, 2373 .class_init = pxa2xx_ssp_class_init, 2374 }; 2375 2376 static void pxa2xx_register_types(void) 2377 { 2378 type_register_static(&pxa2xx_i2c_slave_info); 2379 type_register_static(&pxa2xx_ssp_info); 2380 type_register_static(&pxa2xx_i2c_info); 2381 type_register_static(&pxa2xx_rtc_sysbus_info); 2382 type_register_static(&pxa2xx_fir_info); 2383 } 2384 2385 type_init(pxa2xx_register_types) 2386