1 /* 2 * Intel XScale PXA255/270 processor support. 3 * 4 * Copyright (c) 2006 Openedhand Ltd. 5 * Written by Andrzej Zaborowski <balrog@zabor.org> 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu-common.h" 12 #include "qemu/error-report.h" 13 #include "qemu/module.h" 14 #include "qapi/error.h" 15 #include "cpu.h" 16 #include "hw/sysbus.h" 17 #include "migration/vmstate.h" 18 #include "hw/arm/pxa.h" 19 #include "sysemu/sysemu.h" 20 #include "hw/char/serial.h" 21 #include "hw/i2c/i2c.h" 22 #include "hw/irq.h" 23 #include "hw/qdev-properties.h" 24 #include "hw/qdev-properties-system.h" 25 #include "hw/ssi/ssi.h" 26 #include "hw/sd/sd.h" 27 #include "chardev/char-fe.h" 28 #include "sysemu/blockdev.h" 29 #include "sysemu/qtest.h" 30 #include "qemu/cutils.h" 31 #include "qemu/log.h" 32 #include "qom/object.h" 33 34 static struct { 35 hwaddr io_base; 36 int irqn; 37 } pxa255_serial[] = { 38 { 0x40100000, PXA2XX_PIC_FFUART }, 39 { 0x40200000, PXA2XX_PIC_BTUART }, 40 { 0x40700000, PXA2XX_PIC_STUART }, 41 { 0x41600000, PXA25X_PIC_HWUART }, 42 { 0, 0 } 43 }, pxa270_serial[] = { 44 { 0x40100000, PXA2XX_PIC_FFUART }, 45 { 0x40200000, PXA2XX_PIC_BTUART }, 46 { 0x40700000, PXA2XX_PIC_STUART }, 47 { 0, 0 } 48 }; 49 50 typedef struct PXASSPDef { 51 hwaddr io_base; 52 int irqn; 53 } PXASSPDef; 54 55 #if 0 56 static PXASSPDef pxa250_ssp[] = { 57 { 0x41000000, PXA2XX_PIC_SSP }, 58 { 0, 0 } 59 }; 60 #endif 61 62 static PXASSPDef pxa255_ssp[] = { 63 { 0x41000000, PXA2XX_PIC_SSP }, 64 { 0x41400000, PXA25X_PIC_NSSP }, 65 { 0, 0 } 66 }; 67 68 #if 0 69 static PXASSPDef pxa26x_ssp[] = { 70 { 0x41000000, PXA2XX_PIC_SSP }, 71 { 0x41400000, PXA25X_PIC_NSSP }, 72 { 0x41500000, PXA26X_PIC_ASSP }, 73 { 0, 0 } 74 }; 75 #endif 76 77 static PXASSPDef pxa27x_ssp[] = { 78 { 0x41000000, PXA2XX_PIC_SSP }, 79 { 0x41700000, PXA27X_PIC_SSP2 }, 80 { 0x41900000, PXA2XX_PIC_SSP3 }, 81 { 0, 0 } 82 }; 83 84 #define PMCR 0x00 /* Power Manager Control register */ 85 #define PSSR 0x04 /* Power Manager Sleep Status register */ 86 #define PSPR 0x08 /* Power Manager Scratch-Pad register */ 87 #define PWER 0x0c /* Power Manager Wake-Up Enable register */ 88 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */ 89 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */ 90 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */ 91 #define PCFR 0x1c /* Power Manager General Configuration register */ 92 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */ 93 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */ 94 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */ 95 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */ 96 #define RCSR 0x30 /* Reset Controller Status register */ 97 #define PSLR 0x34 /* Power Manager Sleep Configuration register */ 98 #define PTSR 0x38 /* Power Manager Standby Configuration register */ 99 #define PVCR 0x40 /* Power Manager Voltage Change Control register */ 100 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */ 101 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */ 102 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */ 103 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */ 104 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */ 105 106 static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr, 107 unsigned size) 108 { 109 PXA2xxState *s = (PXA2xxState *) opaque; 110 111 switch (addr) { 112 case PMCR ... PCMD31: 113 if (addr & 3) 114 goto fail; 115 116 return s->pm_regs[addr >> 2]; 117 default: 118 fail: 119 qemu_log_mask(LOG_GUEST_ERROR, 120 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 121 __func__, addr); 122 break; 123 } 124 return 0; 125 } 126 127 static void pxa2xx_pm_write(void *opaque, hwaddr addr, 128 uint64_t value, unsigned size) 129 { 130 PXA2xxState *s = (PXA2xxState *) opaque; 131 132 switch (addr) { 133 case PMCR: 134 /* Clear the write-one-to-clear bits... */ 135 s->pm_regs[addr >> 2] &= ~(value & 0x2a); 136 /* ...and set the plain r/w bits */ 137 s->pm_regs[addr >> 2] &= ~0x15; 138 s->pm_regs[addr >> 2] |= value & 0x15; 139 break; 140 141 case PSSR: /* Read-clean registers */ 142 case RCSR: 143 case PKSR: 144 s->pm_regs[addr >> 2] &= ~value; 145 break; 146 147 default: /* Read-write registers */ 148 if (!(addr & 3)) { 149 s->pm_regs[addr >> 2] = value; 150 break; 151 } 152 qemu_log_mask(LOG_GUEST_ERROR, 153 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 154 __func__, addr); 155 break; 156 } 157 } 158 159 static const MemoryRegionOps pxa2xx_pm_ops = { 160 .read = pxa2xx_pm_read, 161 .write = pxa2xx_pm_write, 162 .endianness = DEVICE_NATIVE_ENDIAN, 163 }; 164 165 static const VMStateDescription vmstate_pxa2xx_pm = { 166 .name = "pxa2xx_pm", 167 .version_id = 0, 168 .minimum_version_id = 0, 169 .fields = (VMStateField[]) { 170 VMSTATE_UINT32_ARRAY(pm_regs, PXA2xxState, 0x40), 171 VMSTATE_END_OF_LIST() 172 } 173 }; 174 175 #define CCCR 0x00 /* Core Clock Configuration register */ 176 #define CKEN 0x04 /* Clock Enable register */ 177 #define OSCC 0x08 /* Oscillator Configuration register */ 178 #define CCSR 0x0c /* Core Clock Status register */ 179 180 static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr, 181 unsigned size) 182 { 183 PXA2xxState *s = (PXA2xxState *) opaque; 184 185 switch (addr) { 186 case CCCR: 187 case CKEN: 188 case OSCC: 189 return s->cm_regs[addr >> 2]; 190 191 case CCSR: 192 return s->cm_regs[CCCR >> 2] | (3 << 28); 193 194 default: 195 qemu_log_mask(LOG_GUEST_ERROR, 196 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 197 __func__, addr); 198 break; 199 } 200 return 0; 201 } 202 203 static void pxa2xx_cm_write(void *opaque, hwaddr addr, 204 uint64_t value, unsigned size) 205 { 206 PXA2xxState *s = (PXA2xxState *) opaque; 207 208 switch (addr) { 209 case CCCR: 210 case CKEN: 211 s->cm_regs[addr >> 2] = value; 212 break; 213 214 case OSCC: 215 s->cm_regs[addr >> 2] &= ~0x6c; 216 s->cm_regs[addr >> 2] |= value & 0x6e; 217 if ((value >> 1) & 1) /* OON */ 218 s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */ 219 break; 220 221 default: 222 qemu_log_mask(LOG_GUEST_ERROR, 223 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 224 __func__, addr); 225 break; 226 } 227 } 228 229 static const MemoryRegionOps pxa2xx_cm_ops = { 230 .read = pxa2xx_cm_read, 231 .write = pxa2xx_cm_write, 232 .endianness = DEVICE_NATIVE_ENDIAN, 233 }; 234 235 static const VMStateDescription vmstate_pxa2xx_cm = { 236 .name = "pxa2xx_cm", 237 .version_id = 0, 238 .minimum_version_id = 0, 239 .fields = (VMStateField[]) { 240 VMSTATE_UINT32_ARRAY(cm_regs, PXA2xxState, 4), 241 VMSTATE_UINT32(clkcfg, PXA2xxState), 242 VMSTATE_UINT32(pmnc, PXA2xxState), 243 VMSTATE_END_OF_LIST() 244 } 245 }; 246 247 static uint64_t pxa2xx_clkcfg_read(CPUARMState *env, const ARMCPRegInfo *ri) 248 { 249 PXA2xxState *s = (PXA2xxState *)ri->opaque; 250 return s->clkcfg; 251 } 252 253 static void pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri, 254 uint64_t value) 255 { 256 PXA2xxState *s = (PXA2xxState *)ri->opaque; 257 s->clkcfg = value & 0xf; 258 if (value & 2) { 259 printf("%s: CPU frequency change attempt\n", __func__); 260 } 261 } 262 263 static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri, 264 uint64_t value) 265 { 266 PXA2xxState *s = (PXA2xxState *)ri->opaque; 267 static const char *pwrmode[8] = { 268 "Normal", "Idle", "Deep-idle", "Standby", 269 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep", 270 }; 271 272 if (value & 8) { 273 printf("%s: CPU voltage change attempt\n", __func__); 274 } 275 switch (value & 7) { 276 case 0: 277 /* Do nothing */ 278 break; 279 280 case 1: 281 /* Idle */ 282 if (!(s->cm_regs[CCCR >> 2] & (1U << 31))) { /* CPDIS */ 283 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); 284 break; 285 } 286 /* Fall through. */ 287 288 case 2: 289 /* Deep-Idle */ 290 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); 291 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ 292 goto message; 293 294 case 3: 295 s->cpu->env.uncached_cpsr = ARM_CPU_MODE_SVC; 296 s->cpu->env.daif = PSTATE_A | PSTATE_F | PSTATE_I; 297 s->cpu->env.cp15.sctlr_ns = 0; 298 s->cpu->env.cp15.cpacr_el1 = 0; 299 s->cpu->env.cp15.ttbr0_el[1] = 0; 300 s->cpu->env.cp15.dacr_ns = 0; 301 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ 302 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ 303 304 /* 305 * The scratch-pad register is almost universally used 306 * for storing the return address on suspend. For the 307 * lack of a resuming bootloader, perform a jump 308 * directly to that address. 309 */ 310 memset(s->cpu->env.regs, 0, 4 * 15); 311 s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2]; 312 313 #if 0 314 buffer = 0xe59ff000; /* ldr pc, [pc, #0] */ 315 cpu_physical_memory_write(0, &buffer, 4); 316 buffer = s->pm_regs[PSPR >> 2]; 317 cpu_physical_memory_write(8, &buffer, 4); 318 #endif 319 320 /* Suspend */ 321 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); 322 323 goto message; 324 325 default: 326 message: 327 printf("%s: machine entered %s mode\n", __func__, 328 pwrmode[value & 7]); 329 } 330 } 331 332 static uint64_t pxa2xx_cppmnc_read(CPUARMState *env, const ARMCPRegInfo *ri) 333 { 334 PXA2xxState *s = (PXA2xxState *)ri->opaque; 335 return s->pmnc; 336 } 337 338 static void pxa2xx_cppmnc_write(CPUARMState *env, const ARMCPRegInfo *ri, 339 uint64_t value) 340 { 341 PXA2xxState *s = (PXA2xxState *)ri->opaque; 342 s->pmnc = value; 343 } 344 345 static uint64_t pxa2xx_cpccnt_read(CPUARMState *env, const ARMCPRegInfo *ri) 346 { 347 PXA2xxState *s = (PXA2xxState *)ri->opaque; 348 if (s->pmnc & 1) { 349 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 350 } else { 351 return 0; 352 } 353 } 354 355 static const ARMCPRegInfo pxa_cp_reginfo[] = { 356 /* cp14 crm==1: perf registers */ 357 { .name = "CPPMNC", .cp = 14, .crn = 0, .crm = 1, .opc1 = 0, .opc2 = 0, 358 .access = PL1_RW, .type = ARM_CP_IO, 359 .readfn = pxa2xx_cppmnc_read, .writefn = pxa2xx_cppmnc_write }, 360 { .name = "CPCCNT", .cp = 14, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, 361 .access = PL1_RW, .type = ARM_CP_IO, 362 .readfn = pxa2xx_cpccnt_read, .writefn = arm_cp_write_ignore }, 363 { .name = "CPINTEN", .cp = 14, .crn = 4, .crm = 1, .opc1 = 0, .opc2 = 0, 364 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 365 { .name = "CPFLAG", .cp = 14, .crn = 5, .crm = 1, .opc1 = 0, .opc2 = 0, 366 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 367 { .name = "CPEVTSEL", .cp = 14, .crn = 8, .crm = 1, .opc1 = 0, .opc2 = 0, 368 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 369 /* cp14 crm==2: performance count registers */ 370 { .name = "CPPMN0", .cp = 14, .crn = 0, .crm = 2, .opc1 = 0, .opc2 = 0, 371 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 372 { .name = "CPPMN1", .cp = 14, .crn = 1, .crm = 2, .opc1 = 0, .opc2 = 0, 373 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 374 { .name = "CPPMN2", .cp = 14, .crn = 2, .crm = 2, .opc1 = 0, .opc2 = 0, 375 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 376 { .name = "CPPMN3", .cp = 14, .crn = 2, .crm = 3, .opc1 = 0, .opc2 = 0, 377 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 378 /* cp14 crn==6: CLKCFG */ 379 { .name = "CLKCFG", .cp = 14, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, 380 .access = PL1_RW, .type = ARM_CP_IO, 381 .readfn = pxa2xx_clkcfg_read, .writefn = pxa2xx_clkcfg_write }, 382 /* cp14 crn==7: PWRMODE */ 383 { .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0, 384 .access = PL1_RW, .type = ARM_CP_IO, 385 .readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write }, 386 REGINFO_SENTINEL 387 }; 388 389 static void pxa2xx_setup_cp14(PXA2xxState *s) 390 { 391 define_arm_cp_regs_with_opaque(s->cpu, pxa_cp_reginfo, s); 392 } 393 394 #define MDCNFG 0x00 /* SDRAM Configuration register */ 395 #define MDREFR 0x04 /* SDRAM Refresh Control register */ 396 #define MSC0 0x08 /* Static Memory Control register 0 */ 397 #define MSC1 0x0c /* Static Memory Control register 1 */ 398 #define MSC2 0x10 /* Static Memory Control register 2 */ 399 #define MECR 0x14 /* Expansion Memory Bus Config register */ 400 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */ 401 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */ 402 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */ 403 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */ 404 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */ 405 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */ 406 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */ 407 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */ 408 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */ 409 #define ARB_CNTL 0x48 /* Arbiter Control register */ 410 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */ 411 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */ 412 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */ 413 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */ 414 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */ 415 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */ 416 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */ 417 418 static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr, 419 unsigned size) 420 { 421 PXA2xxState *s = (PXA2xxState *) opaque; 422 423 switch (addr) { 424 case MDCNFG ... SA1110: 425 if ((addr & 3) == 0) 426 return s->mm_regs[addr >> 2]; 427 /* fall through */ 428 default: 429 qemu_log_mask(LOG_GUEST_ERROR, 430 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 431 __func__, addr); 432 break; 433 } 434 return 0; 435 } 436 437 static void pxa2xx_mm_write(void *opaque, hwaddr addr, 438 uint64_t value, unsigned size) 439 { 440 PXA2xxState *s = (PXA2xxState *) opaque; 441 442 switch (addr) { 443 case MDCNFG ... SA1110: 444 if ((addr & 3) == 0) { 445 s->mm_regs[addr >> 2] = value; 446 break; 447 } 448 /* fallthrough */ 449 default: 450 qemu_log_mask(LOG_GUEST_ERROR, 451 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 452 __func__, addr); 453 break; 454 } 455 } 456 457 static const MemoryRegionOps pxa2xx_mm_ops = { 458 .read = pxa2xx_mm_read, 459 .write = pxa2xx_mm_write, 460 .endianness = DEVICE_NATIVE_ENDIAN, 461 }; 462 463 static const VMStateDescription vmstate_pxa2xx_mm = { 464 .name = "pxa2xx_mm", 465 .version_id = 0, 466 .minimum_version_id = 0, 467 .fields = (VMStateField[]) { 468 VMSTATE_UINT32_ARRAY(mm_regs, PXA2xxState, 0x1a), 469 VMSTATE_END_OF_LIST() 470 } 471 }; 472 473 #define TYPE_PXA2XX_SSP "pxa2xx-ssp" 474 OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxSSPState, PXA2XX_SSP) 475 476 /* Synchronous Serial Ports */ 477 struct PXA2xxSSPState { 478 /*< private >*/ 479 SysBusDevice parent_obj; 480 /*< public >*/ 481 482 MemoryRegion iomem; 483 qemu_irq irq; 484 uint32_t enable; 485 SSIBus *bus; 486 487 uint32_t sscr[2]; 488 uint32_t sspsp; 489 uint32_t ssto; 490 uint32_t ssitr; 491 uint32_t sssr; 492 uint8_t sstsa; 493 uint8_t ssrsa; 494 uint8_t ssacd; 495 496 uint32_t rx_fifo[16]; 497 uint32_t rx_level; 498 uint32_t rx_start; 499 }; 500 501 static bool pxa2xx_ssp_vmstate_validate(void *opaque, int version_id) 502 { 503 PXA2xxSSPState *s = opaque; 504 505 return s->rx_start < sizeof(s->rx_fifo); 506 } 507 508 static const VMStateDescription vmstate_pxa2xx_ssp = { 509 .name = "pxa2xx-ssp", 510 .version_id = 1, 511 .minimum_version_id = 1, 512 .fields = (VMStateField[]) { 513 VMSTATE_UINT32(enable, PXA2xxSSPState), 514 VMSTATE_UINT32_ARRAY(sscr, PXA2xxSSPState, 2), 515 VMSTATE_UINT32(sspsp, PXA2xxSSPState), 516 VMSTATE_UINT32(ssto, PXA2xxSSPState), 517 VMSTATE_UINT32(ssitr, PXA2xxSSPState), 518 VMSTATE_UINT32(sssr, PXA2xxSSPState), 519 VMSTATE_UINT8(sstsa, PXA2xxSSPState), 520 VMSTATE_UINT8(ssrsa, PXA2xxSSPState), 521 VMSTATE_UINT8(ssacd, PXA2xxSSPState), 522 VMSTATE_UINT32(rx_level, PXA2xxSSPState), 523 VMSTATE_UINT32(rx_start, PXA2xxSSPState), 524 VMSTATE_VALIDATE("fifo is 16 bytes", pxa2xx_ssp_vmstate_validate), 525 VMSTATE_UINT32_ARRAY(rx_fifo, PXA2xxSSPState, 16), 526 VMSTATE_END_OF_LIST() 527 } 528 }; 529 530 #define SSCR0 0x00 /* SSP Control register 0 */ 531 #define SSCR1 0x04 /* SSP Control register 1 */ 532 #define SSSR 0x08 /* SSP Status register */ 533 #define SSITR 0x0c /* SSP Interrupt Test register */ 534 #define SSDR 0x10 /* SSP Data register */ 535 #define SSTO 0x28 /* SSP Time-Out register */ 536 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */ 537 #define SSTSA 0x30 /* SSP TX Time Slot Active register */ 538 #define SSRSA 0x34 /* SSP RX Time Slot Active register */ 539 #define SSTSS 0x38 /* SSP Time Slot Status register */ 540 #define SSACD 0x3c /* SSP Audio Clock Divider register */ 541 542 /* Bitfields for above registers */ 543 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00) 544 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10) 545 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20) 546 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30) 547 #define SSCR0_SSE (1 << 7) 548 #define SSCR0_RIM (1 << 22) 549 #define SSCR0_TIM (1 << 23) 550 #define SSCR0_MOD (1U << 31) 551 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1) 552 #define SSCR1_RIE (1 << 0) 553 #define SSCR1_TIE (1 << 1) 554 #define SSCR1_LBM (1 << 2) 555 #define SSCR1_MWDS (1 << 5) 556 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1) 557 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1) 558 #define SSCR1_EFWR (1 << 14) 559 #define SSCR1_PINTE (1 << 18) 560 #define SSCR1_TINTE (1 << 19) 561 #define SSCR1_RSRE (1 << 20) 562 #define SSCR1_TSRE (1 << 21) 563 #define SSCR1_EBCEI (1 << 29) 564 #define SSITR_INT (7 << 5) 565 #define SSSR_TNF (1 << 2) 566 #define SSSR_RNE (1 << 3) 567 #define SSSR_TFS (1 << 5) 568 #define SSSR_RFS (1 << 6) 569 #define SSSR_ROR (1 << 7) 570 #define SSSR_PINT (1 << 18) 571 #define SSSR_TINT (1 << 19) 572 #define SSSR_EOC (1 << 20) 573 #define SSSR_TUR (1 << 21) 574 #define SSSR_BCE (1 << 23) 575 #define SSSR_RW 0x00bc0080 576 577 static void pxa2xx_ssp_int_update(PXA2xxSSPState *s) 578 { 579 int level = 0; 580 581 level |= s->ssitr & SSITR_INT; 582 level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI); 583 level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM); 584 level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT)); 585 level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE); 586 level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE); 587 level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM); 588 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE); 589 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE); 590 qemu_set_irq(s->irq, !!level); 591 } 592 593 static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s) 594 { 595 s->sssr &= ~(0xf << 12); /* Clear RFL */ 596 s->sssr &= ~(0xf << 8); /* Clear TFL */ 597 s->sssr &= ~SSSR_TFS; 598 s->sssr &= ~SSSR_TNF; 599 if (s->enable) { 600 s->sssr |= ((s->rx_level - 1) & 0xf) << 12; 601 if (s->rx_level >= SSCR1_RFT(s->sscr[1])) 602 s->sssr |= SSSR_RFS; 603 else 604 s->sssr &= ~SSSR_RFS; 605 if (s->rx_level) 606 s->sssr |= SSSR_RNE; 607 else 608 s->sssr &= ~SSSR_RNE; 609 /* TX FIFO is never filled, so it is always in underrun 610 condition if SSP is enabled */ 611 s->sssr |= SSSR_TFS; 612 s->sssr |= SSSR_TNF; 613 } 614 615 pxa2xx_ssp_int_update(s); 616 } 617 618 static uint64_t pxa2xx_ssp_read(void *opaque, hwaddr addr, 619 unsigned size) 620 { 621 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; 622 uint32_t retval; 623 624 switch (addr) { 625 case SSCR0: 626 return s->sscr[0]; 627 case SSCR1: 628 return s->sscr[1]; 629 case SSPSP: 630 return s->sspsp; 631 case SSTO: 632 return s->ssto; 633 case SSITR: 634 return s->ssitr; 635 case SSSR: 636 return s->sssr | s->ssitr; 637 case SSDR: 638 if (!s->enable) 639 return 0xffffffff; 640 if (s->rx_level < 1) { 641 printf("%s: SSP Rx Underrun\n", __func__); 642 return 0xffffffff; 643 } 644 s->rx_level --; 645 retval = s->rx_fifo[s->rx_start ++]; 646 s->rx_start &= 0xf; 647 pxa2xx_ssp_fifo_update(s); 648 return retval; 649 case SSTSA: 650 return s->sstsa; 651 case SSRSA: 652 return s->ssrsa; 653 case SSTSS: 654 return 0; 655 case SSACD: 656 return s->ssacd; 657 default: 658 qemu_log_mask(LOG_GUEST_ERROR, 659 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 660 __func__, addr); 661 break; 662 } 663 return 0; 664 } 665 666 static void pxa2xx_ssp_write(void *opaque, hwaddr addr, 667 uint64_t value64, unsigned size) 668 { 669 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; 670 uint32_t value = value64; 671 672 switch (addr) { 673 case SSCR0: 674 s->sscr[0] = value & 0xc7ffffff; 675 s->enable = value & SSCR0_SSE; 676 if (value & SSCR0_MOD) 677 printf("%s: Attempt to use network mode\n", __func__); 678 if (s->enable && SSCR0_DSS(value) < 4) 679 printf("%s: Wrong data size: %u bits\n", __func__, 680 SSCR0_DSS(value)); 681 if (!(value & SSCR0_SSE)) { 682 s->sssr = 0; 683 s->ssitr = 0; 684 s->rx_level = 0; 685 } 686 pxa2xx_ssp_fifo_update(s); 687 break; 688 689 case SSCR1: 690 s->sscr[1] = value; 691 if (value & (SSCR1_LBM | SSCR1_EFWR)) 692 printf("%s: Attempt to use SSP test mode\n", __func__); 693 pxa2xx_ssp_fifo_update(s); 694 break; 695 696 case SSPSP: 697 s->sspsp = value; 698 break; 699 700 case SSTO: 701 s->ssto = value; 702 break; 703 704 case SSITR: 705 s->ssitr = value & SSITR_INT; 706 pxa2xx_ssp_int_update(s); 707 break; 708 709 case SSSR: 710 s->sssr &= ~(value & SSSR_RW); 711 pxa2xx_ssp_int_update(s); 712 break; 713 714 case SSDR: 715 if (SSCR0_UWIRE(s->sscr[0])) { 716 if (s->sscr[1] & SSCR1_MWDS) 717 value &= 0xffff; 718 else 719 value &= 0xff; 720 } else 721 /* Note how 32bits overflow does no harm here */ 722 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1; 723 724 /* Data goes from here to the Tx FIFO and is shifted out from 725 * there directly to the slave, no need to buffer it. 726 */ 727 if (s->enable) { 728 uint32_t readval; 729 readval = ssi_transfer(s->bus, value); 730 if (s->rx_level < 0x10) { 731 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval; 732 } else { 733 s->sssr |= SSSR_ROR; 734 } 735 } 736 pxa2xx_ssp_fifo_update(s); 737 break; 738 739 case SSTSA: 740 s->sstsa = value; 741 break; 742 743 case SSRSA: 744 s->ssrsa = value; 745 break; 746 747 case SSACD: 748 s->ssacd = value; 749 break; 750 751 default: 752 qemu_log_mask(LOG_GUEST_ERROR, 753 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 754 __func__, addr); 755 break; 756 } 757 } 758 759 static const MemoryRegionOps pxa2xx_ssp_ops = { 760 .read = pxa2xx_ssp_read, 761 .write = pxa2xx_ssp_write, 762 .endianness = DEVICE_NATIVE_ENDIAN, 763 }; 764 765 static void pxa2xx_ssp_reset(DeviceState *d) 766 { 767 PXA2xxSSPState *s = PXA2XX_SSP(d); 768 769 s->enable = 0; 770 s->sscr[0] = s->sscr[1] = 0; 771 s->sspsp = 0; 772 s->ssto = 0; 773 s->ssitr = 0; 774 s->sssr = 0; 775 s->sstsa = 0; 776 s->ssrsa = 0; 777 s->ssacd = 0; 778 s->rx_start = s->rx_level = 0; 779 } 780 781 static void pxa2xx_ssp_init(Object *obj) 782 { 783 DeviceState *dev = DEVICE(obj); 784 PXA2xxSSPState *s = PXA2XX_SSP(obj); 785 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 786 sysbus_init_irq(sbd, &s->irq); 787 788 memory_region_init_io(&s->iomem, obj, &pxa2xx_ssp_ops, s, 789 "pxa2xx-ssp", 0x1000); 790 sysbus_init_mmio(sbd, &s->iomem); 791 792 s->bus = ssi_create_bus(dev, "ssi"); 793 } 794 795 /* Real-Time Clock */ 796 #define RCNR 0x00 /* RTC Counter register */ 797 #define RTAR 0x04 /* RTC Alarm register */ 798 #define RTSR 0x08 /* RTC Status register */ 799 #define RTTR 0x0c /* RTC Timer Trim register */ 800 #define RDCR 0x10 /* RTC Day Counter register */ 801 #define RYCR 0x14 /* RTC Year Counter register */ 802 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */ 803 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */ 804 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */ 805 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */ 806 #define SWCR 0x28 /* RTC Stopwatch Counter register */ 807 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */ 808 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */ 809 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */ 810 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */ 811 812 #define TYPE_PXA2XX_RTC "pxa2xx_rtc" 813 OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxRTCState, PXA2XX_RTC) 814 815 struct PXA2xxRTCState { 816 /*< private >*/ 817 SysBusDevice parent_obj; 818 /*< public >*/ 819 820 MemoryRegion iomem; 821 uint32_t rttr; 822 uint32_t rtsr; 823 uint32_t rtar; 824 uint32_t rdar1; 825 uint32_t rdar2; 826 uint32_t ryar1; 827 uint32_t ryar2; 828 uint32_t swar1; 829 uint32_t swar2; 830 uint32_t piar; 831 uint32_t last_rcnr; 832 uint32_t last_rdcr; 833 uint32_t last_rycr; 834 uint32_t last_swcr; 835 uint32_t last_rtcpicr; 836 int64_t last_hz; 837 int64_t last_sw; 838 int64_t last_pi; 839 QEMUTimer *rtc_hz; 840 QEMUTimer *rtc_rdal1; 841 QEMUTimer *rtc_rdal2; 842 QEMUTimer *rtc_swal1; 843 QEMUTimer *rtc_swal2; 844 QEMUTimer *rtc_pi; 845 qemu_irq rtc_irq; 846 }; 847 848 static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s) 849 { 850 qemu_set_irq(s->rtc_irq, !!(s->rtsr & 0x2553)); 851 } 852 853 static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s) 854 { 855 int64_t rt = qemu_clock_get_ms(rtc_clock); 856 s->last_rcnr += ((rt - s->last_hz) << 15) / 857 (1000 * ((s->rttr & 0xffff) + 1)); 858 s->last_rdcr += ((rt - s->last_hz) << 15) / 859 (1000 * ((s->rttr & 0xffff) + 1)); 860 s->last_hz = rt; 861 } 862 863 static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s) 864 { 865 int64_t rt = qemu_clock_get_ms(rtc_clock); 866 if (s->rtsr & (1 << 12)) 867 s->last_swcr += (rt - s->last_sw) / 10; 868 s->last_sw = rt; 869 } 870 871 static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s) 872 { 873 int64_t rt = qemu_clock_get_ms(rtc_clock); 874 if (s->rtsr & (1 << 15)) 875 s->last_swcr += rt - s->last_pi; 876 s->last_pi = rt; 877 } 878 879 static inline void pxa2xx_rtc_alarm_update(PXA2xxRTCState *s, 880 uint32_t rtsr) 881 { 882 if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0))) 883 timer_mod(s->rtc_hz, s->last_hz + 884 (((s->rtar - s->last_rcnr) * 1000 * 885 ((s->rttr & 0xffff) + 1)) >> 15)); 886 else 887 timer_del(s->rtc_hz); 888 889 if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4))) 890 timer_mod(s->rtc_rdal1, s->last_hz + 891 (((s->rdar1 - s->last_rdcr) * 1000 * 892 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */ 893 else 894 timer_del(s->rtc_rdal1); 895 896 if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6))) 897 timer_mod(s->rtc_rdal2, s->last_hz + 898 (((s->rdar2 - s->last_rdcr) * 1000 * 899 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */ 900 else 901 timer_del(s->rtc_rdal2); 902 903 if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8))) 904 timer_mod(s->rtc_swal1, s->last_sw + 905 (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */ 906 else 907 timer_del(s->rtc_swal1); 908 909 if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10))) 910 timer_mod(s->rtc_swal2, s->last_sw + 911 (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */ 912 else 913 timer_del(s->rtc_swal2); 914 915 if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13))) 916 timer_mod(s->rtc_pi, s->last_pi + 917 (s->piar & 0xffff) - s->last_rtcpicr); 918 else 919 timer_del(s->rtc_pi); 920 } 921 922 static inline void pxa2xx_rtc_hz_tick(void *opaque) 923 { 924 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 925 s->rtsr |= (1 << 0); 926 pxa2xx_rtc_alarm_update(s, s->rtsr); 927 pxa2xx_rtc_int_update(s); 928 } 929 930 static inline void pxa2xx_rtc_rdal1_tick(void *opaque) 931 { 932 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 933 s->rtsr |= (1 << 4); 934 pxa2xx_rtc_alarm_update(s, s->rtsr); 935 pxa2xx_rtc_int_update(s); 936 } 937 938 static inline void pxa2xx_rtc_rdal2_tick(void *opaque) 939 { 940 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 941 s->rtsr |= (1 << 6); 942 pxa2xx_rtc_alarm_update(s, s->rtsr); 943 pxa2xx_rtc_int_update(s); 944 } 945 946 static inline void pxa2xx_rtc_swal1_tick(void *opaque) 947 { 948 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 949 s->rtsr |= (1 << 8); 950 pxa2xx_rtc_alarm_update(s, s->rtsr); 951 pxa2xx_rtc_int_update(s); 952 } 953 954 static inline void pxa2xx_rtc_swal2_tick(void *opaque) 955 { 956 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 957 s->rtsr |= (1 << 10); 958 pxa2xx_rtc_alarm_update(s, s->rtsr); 959 pxa2xx_rtc_int_update(s); 960 } 961 962 static inline void pxa2xx_rtc_pi_tick(void *opaque) 963 { 964 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 965 s->rtsr |= (1 << 13); 966 pxa2xx_rtc_piupdate(s); 967 s->last_rtcpicr = 0; 968 pxa2xx_rtc_alarm_update(s, s->rtsr); 969 pxa2xx_rtc_int_update(s); 970 } 971 972 static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr, 973 unsigned size) 974 { 975 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 976 977 switch (addr) { 978 case RTTR: 979 return s->rttr; 980 case RTSR: 981 return s->rtsr; 982 case RTAR: 983 return s->rtar; 984 case RDAR1: 985 return s->rdar1; 986 case RDAR2: 987 return s->rdar2; 988 case RYAR1: 989 return s->ryar1; 990 case RYAR2: 991 return s->ryar2; 992 case SWAR1: 993 return s->swar1; 994 case SWAR2: 995 return s->swar2; 996 case PIAR: 997 return s->piar; 998 case RCNR: 999 return s->last_rcnr + 1000 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / 1001 (1000 * ((s->rttr & 0xffff) + 1)); 1002 case RDCR: 1003 return s->last_rdcr + 1004 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / 1005 (1000 * ((s->rttr & 0xffff) + 1)); 1006 case RYCR: 1007 return s->last_rycr; 1008 case SWCR: 1009 if (s->rtsr & (1 << 12)) 1010 return s->last_swcr + 1011 (qemu_clock_get_ms(rtc_clock) - s->last_sw) / 10; 1012 else 1013 return s->last_swcr; 1014 default: 1015 qemu_log_mask(LOG_GUEST_ERROR, 1016 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 1017 __func__, addr); 1018 break; 1019 } 1020 return 0; 1021 } 1022 1023 static void pxa2xx_rtc_write(void *opaque, hwaddr addr, 1024 uint64_t value64, unsigned size) 1025 { 1026 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 1027 uint32_t value = value64; 1028 1029 switch (addr) { 1030 case RTTR: 1031 if (!(s->rttr & (1U << 31))) { 1032 pxa2xx_rtc_hzupdate(s); 1033 s->rttr = value; 1034 pxa2xx_rtc_alarm_update(s, s->rtsr); 1035 } 1036 break; 1037 1038 case RTSR: 1039 if ((s->rtsr ^ value) & (1 << 15)) 1040 pxa2xx_rtc_piupdate(s); 1041 1042 if ((s->rtsr ^ value) & (1 << 12)) 1043 pxa2xx_rtc_swupdate(s); 1044 1045 if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac)) 1046 pxa2xx_rtc_alarm_update(s, value); 1047 1048 s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac)); 1049 pxa2xx_rtc_int_update(s); 1050 break; 1051 1052 case RTAR: 1053 s->rtar = value; 1054 pxa2xx_rtc_alarm_update(s, s->rtsr); 1055 break; 1056 1057 case RDAR1: 1058 s->rdar1 = value; 1059 pxa2xx_rtc_alarm_update(s, s->rtsr); 1060 break; 1061 1062 case RDAR2: 1063 s->rdar2 = value; 1064 pxa2xx_rtc_alarm_update(s, s->rtsr); 1065 break; 1066 1067 case RYAR1: 1068 s->ryar1 = value; 1069 pxa2xx_rtc_alarm_update(s, s->rtsr); 1070 break; 1071 1072 case RYAR2: 1073 s->ryar2 = value; 1074 pxa2xx_rtc_alarm_update(s, s->rtsr); 1075 break; 1076 1077 case SWAR1: 1078 pxa2xx_rtc_swupdate(s); 1079 s->swar1 = value; 1080 s->last_swcr = 0; 1081 pxa2xx_rtc_alarm_update(s, s->rtsr); 1082 break; 1083 1084 case SWAR2: 1085 s->swar2 = value; 1086 pxa2xx_rtc_alarm_update(s, s->rtsr); 1087 break; 1088 1089 case PIAR: 1090 s->piar = value; 1091 pxa2xx_rtc_alarm_update(s, s->rtsr); 1092 break; 1093 1094 case RCNR: 1095 pxa2xx_rtc_hzupdate(s); 1096 s->last_rcnr = value; 1097 pxa2xx_rtc_alarm_update(s, s->rtsr); 1098 break; 1099 1100 case RDCR: 1101 pxa2xx_rtc_hzupdate(s); 1102 s->last_rdcr = value; 1103 pxa2xx_rtc_alarm_update(s, s->rtsr); 1104 break; 1105 1106 case RYCR: 1107 s->last_rycr = value; 1108 break; 1109 1110 case SWCR: 1111 pxa2xx_rtc_swupdate(s); 1112 s->last_swcr = value; 1113 pxa2xx_rtc_alarm_update(s, s->rtsr); 1114 break; 1115 1116 case RTCPICR: 1117 pxa2xx_rtc_piupdate(s); 1118 s->last_rtcpicr = value & 0xffff; 1119 pxa2xx_rtc_alarm_update(s, s->rtsr); 1120 break; 1121 1122 default: 1123 qemu_log_mask(LOG_GUEST_ERROR, 1124 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 1125 __func__, addr); 1126 } 1127 } 1128 1129 static const MemoryRegionOps pxa2xx_rtc_ops = { 1130 .read = pxa2xx_rtc_read, 1131 .write = pxa2xx_rtc_write, 1132 .endianness = DEVICE_NATIVE_ENDIAN, 1133 }; 1134 1135 static void pxa2xx_rtc_init(Object *obj) 1136 { 1137 PXA2xxRTCState *s = PXA2XX_RTC(obj); 1138 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 1139 struct tm tm; 1140 int wom; 1141 1142 s->rttr = 0x7fff; 1143 s->rtsr = 0; 1144 1145 qemu_get_timedate(&tm, 0); 1146 wom = ((tm.tm_mday - 1) / 7) + 1; 1147 1148 s->last_rcnr = (uint32_t) mktimegm(&tm); 1149 s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) | 1150 (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec; 1151 s->last_rycr = ((tm.tm_year + 1900) << 9) | 1152 ((tm.tm_mon + 1) << 5) | tm.tm_mday; 1153 s->last_swcr = (tm.tm_hour << 19) | 1154 (tm.tm_min << 13) | (tm.tm_sec << 7); 1155 s->last_rtcpicr = 0; 1156 s->last_hz = s->last_sw = s->last_pi = qemu_clock_get_ms(rtc_clock); 1157 1158 sysbus_init_irq(dev, &s->rtc_irq); 1159 1160 memory_region_init_io(&s->iomem, obj, &pxa2xx_rtc_ops, s, 1161 "pxa2xx-rtc", 0x10000); 1162 sysbus_init_mmio(dev, &s->iomem); 1163 } 1164 1165 static void pxa2xx_rtc_realize(DeviceState *dev, Error **errp) 1166 { 1167 PXA2xxRTCState *s = PXA2XX_RTC(dev); 1168 s->rtc_hz = timer_new_ms(rtc_clock, pxa2xx_rtc_hz_tick, s); 1169 s->rtc_rdal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal1_tick, s); 1170 s->rtc_rdal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal2_tick, s); 1171 s->rtc_swal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal1_tick, s); 1172 s->rtc_swal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal2_tick, s); 1173 s->rtc_pi = timer_new_ms(rtc_clock, pxa2xx_rtc_pi_tick, s); 1174 } 1175 1176 static int pxa2xx_rtc_pre_save(void *opaque) 1177 { 1178 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 1179 1180 pxa2xx_rtc_hzupdate(s); 1181 pxa2xx_rtc_piupdate(s); 1182 pxa2xx_rtc_swupdate(s); 1183 1184 return 0; 1185 } 1186 1187 static int pxa2xx_rtc_post_load(void *opaque, int version_id) 1188 { 1189 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 1190 1191 pxa2xx_rtc_alarm_update(s, s->rtsr); 1192 1193 return 0; 1194 } 1195 1196 static const VMStateDescription vmstate_pxa2xx_rtc_regs = { 1197 .name = "pxa2xx_rtc", 1198 .version_id = 0, 1199 .minimum_version_id = 0, 1200 .pre_save = pxa2xx_rtc_pre_save, 1201 .post_load = pxa2xx_rtc_post_load, 1202 .fields = (VMStateField[]) { 1203 VMSTATE_UINT32(rttr, PXA2xxRTCState), 1204 VMSTATE_UINT32(rtsr, PXA2xxRTCState), 1205 VMSTATE_UINT32(rtar, PXA2xxRTCState), 1206 VMSTATE_UINT32(rdar1, PXA2xxRTCState), 1207 VMSTATE_UINT32(rdar2, PXA2xxRTCState), 1208 VMSTATE_UINT32(ryar1, PXA2xxRTCState), 1209 VMSTATE_UINT32(ryar2, PXA2xxRTCState), 1210 VMSTATE_UINT32(swar1, PXA2xxRTCState), 1211 VMSTATE_UINT32(swar2, PXA2xxRTCState), 1212 VMSTATE_UINT32(piar, PXA2xxRTCState), 1213 VMSTATE_UINT32(last_rcnr, PXA2xxRTCState), 1214 VMSTATE_UINT32(last_rdcr, PXA2xxRTCState), 1215 VMSTATE_UINT32(last_rycr, PXA2xxRTCState), 1216 VMSTATE_UINT32(last_swcr, PXA2xxRTCState), 1217 VMSTATE_UINT32(last_rtcpicr, PXA2xxRTCState), 1218 VMSTATE_INT64(last_hz, PXA2xxRTCState), 1219 VMSTATE_INT64(last_sw, PXA2xxRTCState), 1220 VMSTATE_INT64(last_pi, PXA2xxRTCState), 1221 VMSTATE_END_OF_LIST(), 1222 }, 1223 }; 1224 1225 static void pxa2xx_rtc_sysbus_class_init(ObjectClass *klass, void *data) 1226 { 1227 DeviceClass *dc = DEVICE_CLASS(klass); 1228 1229 dc->desc = "PXA2xx RTC Controller"; 1230 dc->vmsd = &vmstate_pxa2xx_rtc_regs; 1231 dc->realize = pxa2xx_rtc_realize; 1232 } 1233 1234 static const TypeInfo pxa2xx_rtc_sysbus_info = { 1235 .name = TYPE_PXA2XX_RTC, 1236 .parent = TYPE_SYS_BUS_DEVICE, 1237 .instance_size = sizeof(PXA2xxRTCState), 1238 .instance_init = pxa2xx_rtc_init, 1239 .class_init = pxa2xx_rtc_sysbus_class_init, 1240 }; 1241 1242 /* I2C Interface */ 1243 1244 #define TYPE_PXA2XX_I2C_SLAVE "pxa2xx-i2c-slave" 1245 OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxI2CSlaveState, PXA2XX_I2C_SLAVE) 1246 1247 struct PXA2xxI2CSlaveState { 1248 I2CSlave parent_obj; 1249 1250 PXA2xxI2CState *host; 1251 }; 1252 1253 struct PXA2xxI2CState { 1254 /*< private >*/ 1255 SysBusDevice parent_obj; 1256 /*< public >*/ 1257 1258 MemoryRegion iomem; 1259 PXA2xxI2CSlaveState *slave; 1260 I2CBus *bus; 1261 qemu_irq irq; 1262 uint32_t offset; 1263 uint32_t region_size; 1264 1265 uint16_t control; 1266 uint16_t status; 1267 uint8_t ibmr; 1268 uint8_t data; 1269 }; 1270 1271 #define IBMR 0x80 /* I2C Bus Monitor register */ 1272 #define IDBR 0x88 /* I2C Data Buffer register */ 1273 #define ICR 0x90 /* I2C Control register */ 1274 #define ISR 0x98 /* I2C Status register */ 1275 #define ISAR 0xa0 /* I2C Slave Address register */ 1276 1277 static void pxa2xx_i2c_update(PXA2xxI2CState *s) 1278 { 1279 uint16_t level = 0; 1280 level |= s->status & s->control & (1 << 10); /* BED */ 1281 level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */ 1282 level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */ 1283 level |= s->status & (1 << 9); /* SAD */ 1284 qemu_set_irq(s->irq, !!level); 1285 } 1286 1287 /* These are only stubs now. */ 1288 static int pxa2xx_i2c_event(I2CSlave *i2c, enum i2c_event event) 1289 { 1290 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c); 1291 PXA2xxI2CState *s = slave->host; 1292 1293 switch (event) { 1294 case I2C_START_SEND: 1295 s->status |= (1 << 9); /* set SAD */ 1296 s->status &= ~(1 << 0); /* clear RWM */ 1297 break; 1298 case I2C_START_RECV: 1299 s->status |= (1 << 9); /* set SAD */ 1300 s->status |= 1 << 0; /* set RWM */ 1301 break; 1302 case I2C_FINISH: 1303 s->status |= (1 << 4); /* set SSD */ 1304 break; 1305 case I2C_NACK: 1306 s->status |= 1 << 1; /* set ACKNAK */ 1307 break; 1308 } 1309 pxa2xx_i2c_update(s); 1310 1311 return 0; 1312 } 1313 1314 static uint8_t pxa2xx_i2c_rx(I2CSlave *i2c) 1315 { 1316 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c); 1317 PXA2xxI2CState *s = slave->host; 1318 1319 if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) { 1320 return 0; 1321 } 1322 1323 if (s->status & (1 << 0)) { /* RWM */ 1324 s->status |= 1 << 6; /* set ITE */ 1325 } 1326 pxa2xx_i2c_update(s); 1327 1328 return s->data; 1329 } 1330 1331 static int pxa2xx_i2c_tx(I2CSlave *i2c, uint8_t data) 1332 { 1333 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c); 1334 PXA2xxI2CState *s = slave->host; 1335 1336 if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) { 1337 return 1; 1338 } 1339 1340 if (!(s->status & (1 << 0))) { /* RWM */ 1341 s->status |= 1 << 7; /* set IRF */ 1342 s->data = data; 1343 } 1344 pxa2xx_i2c_update(s); 1345 1346 return 1; 1347 } 1348 1349 static uint64_t pxa2xx_i2c_read(void *opaque, hwaddr addr, 1350 unsigned size) 1351 { 1352 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; 1353 I2CSlave *slave; 1354 1355 addr -= s->offset; 1356 switch (addr) { 1357 case ICR: 1358 return s->control; 1359 case ISR: 1360 return s->status | (i2c_bus_busy(s->bus) << 2); 1361 case ISAR: 1362 slave = I2C_SLAVE(s->slave); 1363 return slave->address; 1364 case IDBR: 1365 return s->data; 1366 case IBMR: 1367 if (s->status & (1 << 2)) 1368 s->ibmr ^= 3; /* Fake SCL and SDA pin changes */ 1369 else 1370 s->ibmr = 0; 1371 return s->ibmr; 1372 default: 1373 qemu_log_mask(LOG_GUEST_ERROR, 1374 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 1375 __func__, addr); 1376 break; 1377 } 1378 return 0; 1379 } 1380 1381 static void pxa2xx_i2c_write(void *opaque, hwaddr addr, 1382 uint64_t value64, unsigned size) 1383 { 1384 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; 1385 uint32_t value = value64; 1386 int ack; 1387 1388 addr -= s->offset; 1389 switch (addr) { 1390 case ICR: 1391 s->control = value & 0xfff7; 1392 if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */ 1393 /* TODO: slave mode */ 1394 if (value & (1 << 0)) { /* START condition */ 1395 if (s->data & 1) 1396 s->status |= 1 << 0; /* set RWM */ 1397 else 1398 s->status &= ~(1 << 0); /* clear RWM */ 1399 ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1); 1400 } else { 1401 if (s->status & (1 << 0)) { /* RWM */ 1402 s->data = i2c_recv(s->bus); 1403 if (value & (1 << 2)) /* ACKNAK */ 1404 i2c_nack(s->bus); 1405 ack = 1; 1406 } else 1407 ack = !i2c_send(s->bus, s->data); 1408 } 1409 1410 if (value & (1 << 1)) /* STOP condition */ 1411 i2c_end_transfer(s->bus); 1412 1413 if (ack) { 1414 if (value & (1 << 0)) /* START condition */ 1415 s->status |= 1 << 6; /* set ITE */ 1416 else 1417 if (s->status & (1 << 0)) /* RWM */ 1418 s->status |= 1 << 7; /* set IRF */ 1419 else 1420 s->status |= 1 << 6; /* set ITE */ 1421 s->status &= ~(1 << 1); /* clear ACKNAK */ 1422 } else { 1423 s->status |= 1 << 6; /* set ITE */ 1424 s->status |= 1 << 10; /* set BED */ 1425 s->status |= 1 << 1; /* set ACKNAK */ 1426 } 1427 } 1428 if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */ 1429 if (value & (1 << 4)) /* MA */ 1430 i2c_end_transfer(s->bus); 1431 pxa2xx_i2c_update(s); 1432 break; 1433 1434 case ISR: 1435 s->status &= ~(value & 0x07f0); 1436 pxa2xx_i2c_update(s); 1437 break; 1438 1439 case ISAR: 1440 i2c_set_slave_address(I2C_SLAVE(s->slave), value & 0x7f); 1441 break; 1442 1443 case IDBR: 1444 s->data = value & 0xff; 1445 break; 1446 1447 default: 1448 qemu_log_mask(LOG_GUEST_ERROR, 1449 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 1450 __func__, addr); 1451 } 1452 } 1453 1454 static const MemoryRegionOps pxa2xx_i2c_ops = { 1455 .read = pxa2xx_i2c_read, 1456 .write = pxa2xx_i2c_write, 1457 .endianness = DEVICE_NATIVE_ENDIAN, 1458 }; 1459 1460 static const VMStateDescription vmstate_pxa2xx_i2c_slave = { 1461 .name = "pxa2xx_i2c_slave", 1462 .version_id = 1, 1463 .minimum_version_id = 1, 1464 .fields = (VMStateField[]) { 1465 VMSTATE_I2C_SLAVE(parent_obj, PXA2xxI2CSlaveState), 1466 VMSTATE_END_OF_LIST() 1467 } 1468 }; 1469 1470 static const VMStateDescription vmstate_pxa2xx_i2c = { 1471 .name = "pxa2xx_i2c", 1472 .version_id = 1, 1473 .minimum_version_id = 1, 1474 .fields = (VMStateField[]) { 1475 VMSTATE_UINT16(control, PXA2xxI2CState), 1476 VMSTATE_UINT16(status, PXA2xxI2CState), 1477 VMSTATE_UINT8(ibmr, PXA2xxI2CState), 1478 VMSTATE_UINT8(data, PXA2xxI2CState), 1479 VMSTATE_STRUCT_POINTER(slave, PXA2xxI2CState, 1480 vmstate_pxa2xx_i2c_slave, PXA2xxI2CSlaveState), 1481 VMSTATE_END_OF_LIST() 1482 } 1483 }; 1484 1485 static void pxa2xx_i2c_slave_class_init(ObjectClass *klass, void *data) 1486 { 1487 I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); 1488 1489 k->event = pxa2xx_i2c_event; 1490 k->recv = pxa2xx_i2c_rx; 1491 k->send = pxa2xx_i2c_tx; 1492 } 1493 1494 static const TypeInfo pxa2xx_i2c_slave_info = { 1495 .name = TYPE_PXA2XX_I2C_SLAVE, 1496 .parent = TYPE_I2C_SLAVE, 1497 .instance_size = sizeof(PXA2xxI2CSlaveState), 1498 .class_init = pxa2xx_i2c_slave_class_init, 1499 }; 1500 1501 PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base, 1502 qemu_irq irq, uint32_t region_size) 1503 { 1504 DeviceState *dev; 1505 SysBusDevice *i2c_dev; 1506 PXA2xxI2CState *s; 1507 I2CBus *i2cbus; 1508 1509 dev = qdev_new(TYPE_PXA2XX_I2C); 1510 qdev_prop_set_uint32(dev, "size", region_size + 1); 1511 qdev_prop_set_uint32(dev, "offset", base & region_size); 1512 1513 i2c_dev = SYS_BUS_DEVICE(dev); 1514 sysbus_realize_and_unref(i2c_dev, &error_fatal); 1515 sysbus_mmio_map(i2c_dev, 0, base & ~region_size); 1516 sysbus_connect_irq(i2c_dev, 0, irq); 1517 1518 s = PXA2XX_I2C(i2c_dev); 1519 /* FIXME: Should the slave device really be on a separate bus? */ 1520 i2cbus = i2c_init_bus(dev, "dummy"); 1521 s->slave = PXA2XX_I2C_SLAVE(i2c_slave_create_simple(i2cbus, 1522 TYPE_PXA2XX_I2C_SLAVE, 1523 0)); 1524 s->slave->host = s; 1525 1526 return s; 1527 } 1528 1529 static void pxa2xx_i2c_initfn(Object *obj) 1530 { 1531 DeviceState *dev = DEVICE(obj); 1532 PXA2xxI2CState *s = PXA2XX_I2C(obj); 1533 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1534 1535 s->bus = i2c_init_bus(dev, NULL); 1536 1537 memory_region_init_io(&s->iomem, obj, &pxa2xx_i2c_ops, s, 1538 "pxa2xx-i2c", s->region_size); 1539 sysbus_init_mmio(sbd, &s->iomem); 1540 sysbus_init_irq(sbd, &s->irq); 1541 } 1542 1543 I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s) 1544 { 1545 return s->bus; 1546 } 1547 1548 static Property pxa2xx_i2c_properties[] = { 1549 DEFINE_PROP_UINT32("size", PXA2xxI2CState, region_size, 0x10000), 1550 DEFINE_PROP_UINT32("offset", PXA2xxI2CState, offset, 0), 1551 DEFINE_PROP_END_OF_LIST(), 1552 }; 1553 1554 static void pxa2xx_i2c_class_init(ObjectClass *klass, void *data) 1555 { 1556 DeviceClass *dc = DEVICE_CLASS(klass); 1557 1558 dc->desc = "PXA2xx I2C Bus Controller"; 1559 dc->vmsd = &vmstate_pxa2xx_i2c; 1560 device_class_set_props(dc, pxa2xx_i2c_properties); 1561 } 1562 1563 static const TypeInfo pxa2xx_i2c_info = { 1564 .name = TYPE_PXA2XX_I2C, 1565 .parent = TYPE_SYS_BUS_DEVICE, 1566 .instance_size = sizeof(PXA2xxI2CState), 1567 .instance_init = pxa2xx_i2c_initfn, 1568 .class_init = pxa2xx_i2c_class_init, 1569 }; 1570 1571 /* PXA Inter-IC Sound Controller */ 1572 static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s) 1573 { 1574 i2s->rx_len = 0; 1575 i2s->tx_len = 0; 1576 i2s->fifo_len = 0; 1577 i2s->clk = 0x1a; 1578 i2s->control[0] = 0x00; 1579 i2s->control[1] = 0x00; 1580 i2s->status = 0x00; 1581 i2s->mask = 0x00; 1582 } 1583 1584 #define SACR_TFTH(val) ((val >> 8) & 0xf) 1585 #define SACR_RFTH(val) ((val >> 12) & 0xf) 1586 #define SACR_DREC(val) (val & (1 << 3)) 1587 #define SACR_DPRL(val) (val & (1 << 4)) 1588 1589 static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s) 1590 { 1591 int rfs, tfs; 1592 rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len && 1593 !SACR_DREC(i2s->control[1]); 1594 tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) && 1595 i2s->enable && !SACR_DPRL(i2s->control[1]); 1596 1597 qemu_set_irq(i2s->rx_dma, rfs); 1598 qemu_set_irq(i2s->tx_dma, tfs); 1599 1600 i2s->status &= 0xe0; 1601 if (i2s->fifo_len < 16 || !i2s->enable) 1602 i2s->status |= 1 << 0; /* TNF */ 1603 if (i2s->rx_len) 1604 i2s->status |= 1 << 1; /* RNE */ 1605 if (i2s->enable) 1606 i2s->status |= 1 << 2; /* BSY */ 1607 if (tfs) 1608 i2s->status |= 1 << 3; /* TFS */ 1609 if (rfs) 1610 i2s->status |= 1 << 4; /* RFS */ 1611 if (!(i2s->tx_len && i2s->enable)) 1612 i2s->status |= i2s->fifo_len << 8; /* TFL */ 1613 i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */ 1614 1615 qemu_set_irq(i2s->irq, i2s->status & i2s->mask); 1616 } 1617 1618 #define SACR0 0x00 /* Serial Audio Global Control register */ 1619 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */ 1620 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */ 1621 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */ 1622 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */ 1623 #define SADIV 0x60 /* Serial Audio Clock Divider register */ 1624 #define SADR 0x80 /* Serial Audio Data register */ 1625 1626 static uint64_t pxa2xx_i2s_read(void *opaque, hwaddr addr, 1627 unsigned size) 1628 { 1629 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; 1630 1631 switch (addr) { 1632 case SACR0: 1633 return s->control[0]; 1634 case SACR1: 1635 return s->control[1]; 1636 case SASR0: 1637 return s->status; 1638 case SAIMR: 1639 return s->mask; 1640 case SAICR: 1641 return 0; 1642 case SADIV: 1643 return s->clk; 1644 case SADR: 1645 if (s->rx_len > 0) { 1646 s->rx_len --; 1647 pxa2xx_i2s_update(s); 1648 return s->codec_in(s->opaque); 1649 } 1650 return 0; 1651 default: 1652 qemu_log_mask(LOG_GUEST_ERROR, 1653 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 1654 __func__, addr); 1655 break; 1656 } 1657 return 0; 1658 } 1659 1660 static void pxa2xx_i2s_write(void *opaque, hwaddr addr, 1661 uint64_t value, unsigned size) 1662 { 1663 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; 1664 uint32_t *sample; 1665 1666 switch (addr) { 1667 case SACR0: 1668 if (value & (1 << 3)) /* RST */ 1669 pxa2xx_i2s_reset(s); 1670 s->control[0] = value & 0xff3d; 1671 if (!s->enable && (value & 1) && s->tx_len) { /* ENB */ 1672 for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++) 1673 s->codec_out(s->opaque, *sample); 1674 s->status &= ~(1 << 7); /* I2SOFF */ 1675 } 1676 if (value & (1 << 4)) /* EFWR */ 1677 printf("%s: Attempt to use special function\n", __func__); 1678 s->enable = (value & 9) == 1; /* ENB && !RST*/ 1679 pxa2xx_i2s_update(s); 1680 break; 1681 case SACR1: 1682 s->control[1] = value & 0x0039; 1683 if (value & (1 << 5)) /* ENLBF */ 1684 printf("%s: Attempt to use loopback function\n", __func__); 1685 if (value & (1 << 4)) /* DPRL */ 1686 s->fifo_len = 0; 1687 pxa2xx_i2s_update(s); 1688 break; 1689 case SAIMR: 1690 s->mask = value & 0x0078; 1691 pxa2xx_i2s_update(s); 1692 break; 1693 case SAICR: 1694 s->status &= ~(value & (3 << 5)); 1695 pxa2xx_i2s_update(s); 1696 break; 1697 case SADIV: 1698 s->clk = value & 0x007f; 1699 break; 1700 case SADR: 1701 if (s->tx_len && s->enable) { 1702 s->tx_len --; 1703 pxa2xx_i2s_update(s); 1704 s->codec_out(s->opaque, value); 1705 } else if (s->fifo_len < 16) { 1706 s->fifo[s->fifo_len ++] = value; 1707 pxa2xx_i2s_update(s); 1708 } 1709 break; 1710 default: 1711 qemu_log_mask(LOG_GUEST_ERROR, 1712 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 1713 __func__, addr); 1714 } 1715 } 1716 1717 static const MemoryRegionOps pxa2xx_i2s_ops = { 1718 .read = pxa2xx_i2s_read, 1719 .write = pxa2xx_i2s_write, 1720 .endianness = DEVICE_NATIVE_ENDIAN, 1721 }; 1722 1723 static const VMStateDescription vmstate_pxa2xx_i2s = { 1724 .name = "pxa2xx_i2s", 1725 .version_id = 0, 1726 .minimum_version_id = 0, 1727 .fields = (VMStateField[]) { 1728 VMSTATE_UINT32_ARRAY(control, PXA2xxI2SState, 2), 1729 VMSTATE_UINT32(status, PXA2xxI2SState), 1730 VMSTATE_UINT32(mask, PXA2xxI2SState), 1731 VMSTATE_UINT32(clk, PXA2xxI2SState), 1732 VMSTATE_INT32(enable, PXA2xxI2SState), 1733 VMSTATE_INT32(rx_len, PXA2xxI2SState), 1734 VMSTATE_INT32(tx_len, PXA2xxI2SState), 1735 VMSTATE_INT32(fifo_len, PXA2xxI2SState), 1736 VMSTATE_END_OF_LIST() 1737 } 1738 }; 1739 1740 static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx) 1741 { 1742 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; 1743 uint32_t *sample; 1744 1745 /* Signal FIFO errors */ 1746 if (s->enable && s->tx_len) 1747 s->status |= 1 << 5; /* TUR */ 1748 if (s->enable && s->rx_len) 1749 s->status |= 1 << 6; /* ROR */ 1750 1751 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to 1752 * handle the cases where it makes a difference. */ 1753 s->tx_len = tx - s->fifo_len; 1754 s->rx_len = rx; 1755 /* Note that is s->codec_out wasn't set, we wouldn't get called. */ 1756 if (s->enable) 1757 for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++) 1758 s->codec_out(s->opaque, *sample); 1759 pxa2xx_i2s_update(s); 1760 } 1761 1762 static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem, 1763 hwaddr base, 1764 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma) 1765 { 1766 PXA2xxI2SState *s = g_new0(PXA2xxI2SState, 1); 1767 1768 s->irq = irq; 1769 s->rx_dma = rx_dma; 1770 s->tx_dma = tx_dma; 1771 s->data_req = pxa2xx_i2s_data_req; 1772 1773 pxa2xx_i2s_reset(s); 1774 1775 memory_region_init_io(&s->iomem, NULL, &pxa2xx_i2s_ops, s, 1776 "pxa2xx-i2s", 0x100000); 1777 memory_region_add_subregion(sysmem, base, &s->iomem); 1778 1779 vmstate_register(NULL, base, &vmstate_pxa2xx_i2s, s); 1780 1781 return s; 1782 } 1783 1784 /* PXA Fast Infra-red Communications Port */ 1785 struct PXA2xxFIrState { 1786 /*< private >*/ 1787 SysBusDevice parent_obj; 1788 /*< public >*/ 1789 1790 MemoryRegion iomem; 1791 qemu_irq irq; 1792 qemu_irq rx_dma; 1793 qemu_irq tx_dma; 1794 uint32_t enable; 1795 CharBackend chr; 1796 1797 uint8_t control[3]; 1798 uint8_t status[2]; 1799 1800 uint32_t rx_len; 1801 uint32_t rx_start; 1802 uint8_t rx_fifo[64]; 1803 }; 1804 1805 static void pxa2xx_fir_reset(DeviceState *d) 1806 { 1807 PXA2xxFIrState *s = PXA2XX_FIR(d); 1808 1809 s->control[0] = 0x00; 1810 s->control[1] = 0x00; 1811 s->control[2] = 0x00; 1812 s->status[0] = 0x00; 1813 s->status[1] = 0x00; 1814 s->enable = 0; 1815 } 1816 1817 static inline void pxa2xx_fir_update(PXA2xxFIrState *s) 1818 { 1819 static const int tresh[4] = { 8, 16, 32, 0 }; 1820 int intr = 0; 1821 if ((s->control[0] & (1 << 4)) && /* RXE */ 1822 s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */ 1823 s->status[0] |= 1 << 4; /* RFS */ 1824 else 1825 s->status[0] &= ~(1 << 4); /* RFS */ 1826 if (s->control[0] & (1 << 3)) /* TXE */ 1827 s->status[0] |= 1 << 3; /* TFS */ 1828 else 1829 s->status[0] &= ~(1 << 3); /* TFS */ 1830 if (s->rx_len) 1831 s->status[1] |= 1 << 2; /* RNE */ 1832 else 1833 s->status[1] &= ~(1 << 2); /* RNE */ 1834 if (s->control[0] & (1 << 4)) /* RXE */ 1835 s->status[1] |= 1 << 0; /* RSY */ 1836 else 1837 s->status[1] &= ~(1 << 0); /* RSY */ 1838 1839 intr |= (s->control[0] & (1 << 5)) && /* RIE */ 1840 (s->status[0] & (1 << 4)); /* RFS */ 1841 intr |= (s->control[0] & (1 << 6)) && /* TIE */ 1842 (s->status[0] & (1 << 3)); /* TFS */ 1843 intr |= (s->control[2] & (1 << 4)) && /* TRAIL */ 1844 (s->status[0] & (1 << 6)); /* EOC */ 1845 intr |= (s->control[0] & (1 << 2)) && /* TUS */ 1846 (s->status[0] & (1 << 1)); /* TUR */ 1847 intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */ 1848 1849 qemu_set_irq(s->rx_dma, (s->status[0] >> 4) & 1); 1850 qemu_set_irq(s->tx_dma, (s->status[0] >> 3) & 1); 1851 1852 qemu_set_irq(s->irq, intr && s->enable); 1853 } 1854 1855 #define ICCR0 0x00 /* FICP Control register 0 */ 1856 #define ICCR1 0x04 /* FICP Control register 1 */ 1857 #define ICCR2 0x08 /* FICP Control register 2 */ 1858 #define ICDR 0x0c /* FICP Data register */ 1859 #define ICSR0 0x14 /* FICP Status register 0 */ 1860 #define ICSR1 0x18 /* FICP Status register 1 */ 1861 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */ 1862 1863 static uint64_t pxa2xx_fir_read(void *opaque, hwaddr addr, 1864 unsigned size) 1865 { 1866 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1867 uint8_t ret; 1868 1869 switch (addr) { 1870 case ICCR0: 1871 return s->control[0]; 1872 case ICCR1: 1873 return s->control[1]; 1874 case ICCR2: 1875 return s->control[2]; 1876 case ICDR: 1877 s->status[0] &= ~0x01; 1878 s->status[1] &= ~0x72; 1879 if (s->rx_len) { 1880 s->rx_len --; 1881 ret = s->rx_fifo[s->rx_start ++]; 1882 s->rx_start &= 63; 1883 pxa2xx_fir_update(s); 1884 return ret; 1885 } 1886 printf("%s: Rx FIFO underrun.\n", __func__); 1887 break; 1888 case ICSR0: 1889 return s->status[0]; 1890 case ICSR1: 1891 return s->status[1] | (1 << 3); /* TNF */ 1892 case ICFOR: 1893 return s->rx_len; 1894 default: 1895 qemu_log_mask(LOG_GUEST_ERROR, 1896 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 1897 __func__, addr); 1898 break; 1899 } 1900 return 0; 1901 } 1902 1903 static void pxa2xx_fir_write(void *opaque, hwaddr addr, 1904 uint64_t value64, unsigned size) 1905 { 1906 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1907 uint32_t value = value64; 1908 uint8_t ch; 1909 1910 switch (addr) { 1911 case ICCR0: 1912 s->control[0] = value; 1913 if (!(value & (1 << 4))) /* RXE */ 1914 s->rx_len = s->rx_start = 0; 1915 if (!(value & (1 << 3))) { /* TXE */ 1916 /* Nop */ 1917 } 1918 s->enable = value & 1; /* ITR */ 1919 if (!s->enable) 1920 s->status[0] = 0; 1921 pxa2xx_fir_update(s); 1922 break; 1923 case ICCR1: 1924 s->control[1] = value; 1925 break; 1926 case ICCR2: 1927 s->control[2] = value & 0x3f; 1928 pxa2xx_fir_update(s); 1929 break; 1930 case ICDR: 1931 if (s->control[2] & (1 << 2)) { /* TXP */ 1932 ch = value; 1933 } else { 1934 ch = ~value; 1935 } 1936 if (s->enable && (s->control[0] & (1 << 3))) { /* TXE */ 1937 /* XXX this blocks entire thread. Rewrite to use 1938 * qemu_chr_fe_write and background I/O callbacks */ 1939 qemu_chr_fe_write_all(&s->chr, &ch, 1); 1940 } 1941 break; 1942 case ICSR0: 1943 s->status[0] &= ~(value & 0x66); 1944 pxa2xx_fir_update(s); 1945 break; 1946 case ICFOR: 1947 break; 1948 default: 1949 qemu_log_mask(LOG_GUEST_ERROR, 1950 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 1951 __func__, addr); 1952 } 1953 } 1954 1955 static const MemoryRegionOps pxa2xx_fir_ops = { 1956 .read = pxa2xx_fir_read, 1957 .write = pxa2xx_fir_write, 1958 .endianness = DEVICE_NATIVE_ENDIAN, 1959 }; 1960 1961 static int pxa2xx_fir_is_empty(void *opaque) 1962 { 1963 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1964 return (s->rx_len < 64); 1965 } 1966 1967 static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size) 1968 { 1969 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1970 if (!(s->control[0] & (1 << 4))) /* RXE */ 1971 return; 1972 1973 while (size --) { 1974 s->status[1] |= 1 << 4; /* EOF */ 1975 if (s->rx_len >= 64) { 1976 s->status[1] |= 1 << 6; /* ROR */ 1977 break; 1978 } 1979 1980 if (s->control[2] & (1 << 3)) /* RXP */ 1981 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++); 1982 else 1983 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++); 1984 } 1985 1986 pxa2xx_fir_update(s); 1987 } 1988 1989 static void pxa2xx_fir_event(void *opaque, QEMUChrEvent event) 1990 { 1991 } 1992 1993 static void pxa2xx_fir_instance_init(Object *obj) 1994 { 1995 PXA2xxFIrState *s = PXA2XX_FIR(obj); 1996 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1997 1998 memory_region_init_io(&s->iomem, obj, &pxa2xx_fir_ops, s, 1999 "pxa2xx-fir", 0x1000); 2000 sysbus_init_mmio(sbd, &s->iomem); 2001 sysbus_init_irq(sbd, &s->irq); 2002 sysbus_init_irq(sbd, &s->rx_dma); 2003 sysbus_init_irq(sbd, &s->tx_dma); 2004 } 2005 2006 static void pxa2xx_fir_realize(DeviceState *dev, Error **errp) 2007 { 2008 PXA2xxFIrState *s = PXA2XX_FIR(dev); 2009 2010 qemu_chr_fe_set_handlers(&s->chr, pxa2xx_fir_is_empty, 2011 pxa2xx_fir_rx, pxa2xx_fir_event, NULL, s, NULL, 2012 true); 2013 } 2014 2015 static bool pxa2xx_fir_vmstate_validate(void *opaque, int version_id) 2016 { 2017 PXA2xxFIrState *s = opaque; 2018 2019 return s->rx_start < ARRAY_SIZE(s->rx_fifo); 2020 } 2021 2022 static const VMStateDescription pxa2xx_fir_vmsd = { 2023 .name = "pxa2xx-fir", 2024 .version_id = 1, 2025 .minimum_version_id = 1, 2026 .fields = (VMStateField[]) { 2027 VMSTATE_UINT32(enable, PXA2xxFIrState), 2028 VMSTATE_UINT8_ARRAY(control, PXA2xxFIrState, 3), 2029 VMSTATE_UINT8_ARRAY(status, PXA2xxFIrState, 2), 2030 VMSTATE_UINT32(rx_len, PXA2xxFIrState), 2031 VMSTATE_UINT32(rx_start, PXA2xxFIrState), 2032 VMSTATE_VALIDATE("fifo is 64 bytes", pxa2xx_fir_vmstate_validate), 2033 VMSTATE_UINT8_ARRAY(rx_fifo, PXA2xxFIrState, 64), 2034 VMSTATE_END_OF_LIST() 2035 } 2036 }; 2037 2038 static Property pxa2xx_fir_properties[] = { 2039 DEFINE_PROP_CHR("chardev", PXA2xxFIrState, chr), 2040 DEFINE_PROP_END_OF_LIST(), 2041 }; 2042 2043 static void pxa2xx_fir_class_init(ObjectClass *klass, void *data) 2044 { 2045 DeviceClass *dc = DEVICE_CLASS(klass); 2046 2047 dc->realize = pxa2xx_fir_realize; 2048 dc->vmsd = &pxa2xx_fir_vmsd; 2049 device_class_set_props(dc, pxa2xx_fir_properties); 2050 dc->reset = pxa2xx_fir_reset; 2051 } 2052 2053 static const TypeInfo pxa2xx_fir_info = { 2054 .name = TYPE_PXA2XX_FIR, 2055 .parent = TYPE_SYS_BUS_DEVICE, 2056 .instance_size = sizeof(PXA2xxFIrState), 2057 .class_init = pxa2xx_fir_class_init, 2058 .instance_init = pxa2xx_fir_instance_init, 2059 }; 2060 2061 static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem, 2062 hwaddr base, 2063 qemu_irq irq, qemu_irq rx_dma, 2064 qemu_irq tx_dma, 2065 Chardev *chr) 2066 { 2067 DeviceState *dev; 2068 SysBusDevice *sbd; 2069 2070 dev = qdev_new(TYPE_PXA2XX_FIR); 2071 qdev_prop_set_chr(dev, "chardev", chr); 2072 sbd = SYS_BUS_DEVICE(dev); 2073 sysbus_realize_and_unref(sbd, &error_fatal); 2074 sysbus_mmio_map(sbd, 0, base); 2075 sysbus_connect_irq(sbd, 0, irq); 2076 sysbus_connect_irq(sbd, 1, rx_dma); 2077 sysbus_connect_irq(sbd, 2, tx_dma); 2078 return PXA2XX_FIR(dev); 2079 } 2080 2081 static void pxa2xx_reset(void *opaque, int line, int level) 2082 { 2083 PXA2xxState *s = (PXA2xxState *) opaque; 2084 2085 if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */ 2086 cpu_reset(CPU(s->cpu)); 2087 /* TODO: reset peripherals */ 2088 } 2089 } 2090 2091 /* Initialise a PXA270 integrated chip (ARM based core). */ 2092 PXA2xxState *pxa270_init(MemoryRegion *address_space, 2093 unsigned int sdram_size, const char *cpu_type) 2094 { 2095 PXA2xxState *s; 2096 int i; 2097 DriveInfo *dinfo; 2098 s = g_new0(PXA2xxState, 1); 2099 2100 if (strncmp(cpu_type, "pxa27", 5)) { 2101 error_report("Machine requires a PXA27x processor"); 2102 exit(1); 2103 } 2104 2105 s->cpu = ARM_CPU(cpu_create(cpu_type)); 2106 s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0); 2107 2108 /* SDRAM & Internal Memory Storage */ 2109 memory_region_init_ram(&s->sdram, NULL, "pxa270.sdram", sdram_size, 2110 &error_fatal); 2111 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram); 2112 memory_region_init_ram(&s->internal, NULL, "pxa270.internal", 0x40000, 2113 &error_fatal); 2114 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE, 2115 &s->internal); 2116 2117 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu); 2118 2119 s->dma = pxa27x_dma_init(0x40000000, 2120 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA)); 2121 2122 sysbus_create_varargs("pxa27x-timer", 0x40a00000, 2123 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0), 2124 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1), 2125 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2), 2126 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3), 2127 qdev_get_gpio_in(s->pic, PXA27X_PIC_OST_4_11), 2128 NULL); 2129 2130 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 121); 2131 2132 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, 2133 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), 2134 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), 2135 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); 2136 dinfo = drive_get(IF_SD, 0, 0); 2137 if (dinfo) { 2138 DeviceState *carddev; 2139 2140 /* Create and plug in the sd card */ 2141 carddev = qdev_new(TYPE_SD_CARD); 2142 qdev_prop_set_drive_err(carddev, "drive", 2143 blk_by_legacy_dinfo(dinfo), &error_fatal); 2144 qdev_realize_and_unref(carddev, qdev_get_child_bus(DEVICE(s->mmc), 2145 "sd-bus"), 2146 &error_fatal); 2147 } else if (!qtest_enabled()) { 2148 warn_report("missing SecureDigital device"); 2149 } 2150 2151 for (i = 0; pxa270_serial[i].io_base; i++) { 2152 if (serial_hd(i)) { 2153 serial_mm_init(address_space, pxa270_serial[i].io_base, 2, 2154 qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn), 2155 14857000 / 16, serial_hd(i), 2156 DEVICE_NATIVE_ENDIAN); 2157 } else { 2158 break; 2159 } 2160 } 2161 if (serial_hd(i)) 2162 s->fir = pxa2xx_fir_init(address_space, 0x40800000, 2163 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), 2164 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), 2165 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), 2166 serial_hd(i)); 2167 2168 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000, 2169 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); 2170 2171 s->cm_base = 0x41300000; 2172 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */ 2173 s->clkcfg = 0x00000009; /* Turbo mode active */ 2174 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000); 2175 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); 2176 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); 2177 2178 pxa2xx_setup_cp14(s); 2179 2180 s->mm_base = 0x48000000; 2181 s->mm_regs[MDMRS >> 2] = 0x00020002; 2182 s->mm_regs[MDREFR >> 2] = 0x03ca4000; 2183 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ 2184 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000); 2185 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem); 2186 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s); 2187 2188 s->pm_base = 0x40f00000; 2189 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100); 2190 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem); 2191 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s); 2192 2193 for (i = 0; pxa27x_ssp[i].io_base; i ++); 2194 s->ssp = g_new0(SSIBus *, i); 2195 for (i = 0; pxa27x_ssp[i].io_base; i ++) { 2196 DeviceState *dev; 2197 dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa27x_ssp[i].io_base, 2198 qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn)); 2199 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi"); 2200 } 2201 2202 sysbus_create_simple("sysbus-ohci", 0x4c000000, 2203 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1)); 2204 2205 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000); 2206 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000); 2207 2208 sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000, 2209 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM)); 2210 2211 s->i2c[0] = pxa2xx_i2c_init(0x40301600, 2212 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff); 2213 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, 2214 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff); 2215 2216 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000, 2217 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), 2218 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), 2219 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); 2220 2221 s->kp = pxa27x_keypad_init(address_space, 0x41500000, 2222 qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD)); 2223 2224 /* GPIO1 resets the processor */ 2225 /* The handler can be overridden by board-specific code */ 2226 qdev_connect_gpio_out(s->gpio, 1, s->reset); 2227 return s; 2228 } 2229 2230 /* Initialise a PXA255 integrated chip (ARM based core). */ 2231 PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size) 2232 { 2233 PXA2xxState *s; 2234 int i; 2235 DriveInfo *dinfo; 2236 2237 s = g_new0(PXA2xxState, 1); 2238 2239 s->cpu = ARM_CPU(cpu_create(ARM_CPU_TYPE_NAME("pxa255"))); 2240 s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0); 2241 2242 /* SDRAM & Internal Memory Storage */ 2243 memory_region_init_ram(&s->sdram, NULL, "pxa255.sdram", sdram_size, 2244 &error_fatal); 2245 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram); 2246 memory_region_init_ram(&s->internal, NULL, "pxa255.internal", 2247 PXA2XX_INTERNAL_SIZE, &error_fatal); 2248 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE, 2249 &s->internal); 2250 2251 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu); 2252 2253 s->dma = pxa255_dma_init(0x40000000, 2254 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA)); 2255 2256 sysbus_create_varargs("pxa25x-timer", 0x40a00000, 2257 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0), 2258 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1), 2259 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2), 2260 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3), 2261 NULL); 2262 2263 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 85); 2264 2265 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, 2266 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), 2267 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), 2268 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); 2269 dinfo = drive_get(IF_SD, 0, 0); 2270 if (dinfo) { 2271 DeviceState *carddev; 2272 2273 /* Create and plug in the sd card */ 2274 carddev = qdev_new(TYPE_SD_CARD); 2275 qdev_prop_set_drive_err(carddev, "drive", 2276 blk_by_legacy_dinfo(dinfo), &error_fatal); 2277 qdev_realize_and_unref(carddev, qdev_get_child_bus(DEVICE(s->mmc), 2278 "sd-bus"), 2279 &error_fatal); 2280 } else if (!qtest_enabled()) { 2281 warn_report("missing SecureDigital device"); 2282 } 2283 2284 for (i = 0; pxa255_serial[i].io_base; i++) { 2285 if (serial_hd(i)) { 2286 serial_mm_init(address_space, pxa255_serial[i].io_base, 2, 2287 qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn), 2288 14745600 / 16, serial_hd(i), 2289 DEVICE_NATIVE_ENDIAN); 2290 } else { 2291 break; 2292 } 2293 } 2294 if (serial_hd(i)) 2295 s->fir = pxa2xx_fir_init(address_space, 0x40800000, 2296 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), 2297 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), 2298 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), 2299 serial_hd(i)); 2300 2301 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000, 2302 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); 2303 2304 s->cm_base = 0x41300000; 2305 s->cm_regs[CCCR >> 2] = 0x00000121; /* from datasheet */ 2306 s->cm_regs[CKEN >> 2] = 0x00017def; /* from datasheet */ 2307 2308 s->clkcfg = 0x00000009; /* Turbo mode active */ 2309 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000); 2310 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); 2311 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); 2312 2313 pxa2xx_setup_cp14(s); 2314 2315 s->mm_base = 0x48000000; 2316 s->mm_regs[MDMRS >> 2] = 0x00020002; 2317 s->mm_regs[MDREFR >> 2] = 0x03ca4000; 2318 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ 2319 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000); 2320 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem); 2321 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s); 2322 2323 s->pm_base = 0x40f00000; 2324 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100); 2325 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem); 2326 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s); 2327 2328 for (i = 0; pxa255_ssp[i].io_base; i ++); 2329 s->ssp = g_new0(SSIBus *, i); 2330 for (i = 0; pxa255_ssp[i].io_base; i ++) { 2331 DeviceState *dev; 2332 dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa255_ssp[i].io_base, 2333 qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn)); 2334 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi"); 2335 } 2336 2337 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000); 2338 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000); 2339 2340 sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000, 2341 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM)); 2342 2343 s->i2c[0] = pxa2xx_i2c_init(0x40301600, 2344 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff); 2345 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, 2346 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff); 2347 2348 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000, 2349 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), 2350 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), 2351 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); 2352 2353 /* GPIO1 resets the processor */ 2354 /* The handler can be overridden by board-specific code */ 2355 qdev_connect_gpio_out(s->gpio, 1, s->reset); 2356 return s; 2357 } 2358 2359 static void pxa2xx_ssp_class_init(ObjectClass *klass, void *data) 2360 { 2361 DeviceClass *dc = DEVICE_CLASS(klass); 2362 2363 dc->reset = pxa2xx_ssp_reset; 2364 dc->vmsd = &vmstate_pxa2xx_ssp; 2365 } 2366 2367 static const TypeInfo pxa2xx_ssp_info = { 2368 .name = TYPE_PXA2XX_SSP, 2369 .parent = TYPE_SYS_BUS_DEVICE, 2370 .instance_size = sizeof(PXA2xxSSPState), 2371 .instance_init = pxa2xx_ssp_init, 2372 .class_init = pxa2xx_ssp_class_init, 2373 }; 2374 2375 static void pxa2xx_register_types(void) 2376 { 2377 type_register_static(&pxa2xx_i2c_slave_info); 2378 type_register_static(&pxa2xx_ssp_info); 2379 type_register_static(&pxa2xx_i2c_info); 2380 type_register_static(&pxa2xx_rtc_sysbus_info); 2381 type_register_static(&pxa2xx_fir_info); 2382 } 2383 2384 type_init(pxa2xx_register_types) 2385