1 /* omap_sx1.c Support for the Siemens SX1 smartphone emulation. 2 * 3 * Copyright (C) 2008 4 * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 5 * Copyright (C) 2007 Vladimir Ananiev <vovan888@gmail.com> 6 * 7 * based on PalmOne's (TM) PDAs support (palm.c) 8 */ 9 10 /* 11 * PalmOne's (TM) PDAs. 12 * 13 * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org> 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License along 26 * with this program; if not, see <http://www.gnu.org/licenses/>. 27 */ 28 #include "qemu/osdep.h" 29 #include "qemu/units.h" 30 #include "qapi/error.h" 31 #include "ui/console.h" 32 #include "hw/arm/omap.h" 33 #include "hw/boards.h" 34 #include "hw/arm/boot.h" 35 #include "hw/block/flash.h" 36 #include "sysemu/qtest.h" 37 #include "exec/address-spaces.h" 38 #include "cpu.h" 39 #include "qemu/cutils.h" 40 #include "qemu/error-report.h" 41 42 43 /*****************************************************************************/ 44 /* Siemens SX1 Cellphone V1 */ 45 /* - ARM OMAP310 processor 46 * - SRAM 192 kB 47 * - SDRAM 32 MB at 0x10000000 48 * - Boot flash 16 MB at 0x00000000 49 * - Application flash 8 MB at 0x04000000 50 * - 3 serial ports 51 * - 1 SecureDigital 52 * - 1 LCD display 53 * - 1 RTC 54 */ 55 56 /*****************************************************************************/ 57 /* Siemens SX1 Cellphone V2 */ 58 /* - ARM OMAP310 processor 59 * - SRAM 192 kB 60 * - SDRAM 32 MB at 0x10000000 61 * - Boot flash 32 MB at 0x00000000 62 * - 3 serial ports 63 * - 1 SecureDigital 64 * - 1 LCD display 65 * - 1 RTC 66 */ 67 68 static uint64_t static_read(void *opaque, hwaddr offset, 69 unsigned size) 70 { 71 uint32_t *val = opaque; 72 uint32_t mask = (4 / size) - 1; 73 74 return *val >> ((offset & mask) << 3); 75 } 76 77 static void static_write(void *opaque, hwaddr offset, 78 uint64_t value, unsigned size) 79 { 80 #ifdef SPY 81 printf("%s: value %" PRIx64 " %u bytes written at 0x%x\n", 82 __func__, value, size, (int)offset); 83 #endif 84 } 85 86 static const MemoryRegionOps static_ops = { 87 .read = static_read, 88 .write = static_write, 89 .endianness = DEVICE_NATIVE_ENDIAN, 90 }; 91 92 #define SDRAM_SIZE (32 * MiB) 93 #define SECTOR_SIZE (128 * KiB) 94 #define FLASH0_SIZE (16 * MiB) 95 #define FLASH1_SIZE (8 * MiB) 96 #define FLASH2_SIZE (32 * MiB) 97 98 static struct arm_boot_info sx1_binfo = { 99 .loader_start = OMAP_EMIFF_BASE, 100 .ram_size = SDRAM_SIZE, 101 .board_id = 0x265, 102 }; 103 104 static void sx1_init(MachineState *machine, const int version) 105 { 106 struct omap_mpu_state_s *mpu; 107 MachineClass *mc = MACHINE_GET_CLASS(machine); 108 MemoryRegion *address_space = get_system_memory(); 109 MemoryRegion *flash = g_new(MemoryRegion, 1); 110 MemoryRegion *cs = g_new(MemoryRegion, 4); 111 static uint32_t cs0val = 0x00213090; 112 static uint32_t cs1val = 0x00215070; 113 static uint32_t cs2val = 0x00001139; 114 static uint32_t cs3val = 0x00001139; 115 DriveInfo *dinfo; 116 int fl_idx; 117 uint32_t flash_size = FLASH0_SIZE; 118 119 if (machine->ram_size != mc->default_ram_size) { 120 char *sz = size_to_str(mc->default_ram_size); 121 error_report("Invalid RAM size, should be %s", sz); 122 g_free(sz); 123 exit(EXIT_FAILURE); 124 } 125 126 if (version == 2) { 127 flash_size = FLASH2_SIZE; 128 } 129 130 memory_region_add_subregion(address_space, OMAP_EMIFF_BASE, machine->ram); 131 132 mpu = omap310_mpu_init(machine->ram, machine->cpu_type); 133 134 /* External Flash (EMIFS) */ 135 memory_region_init_rom(flash, NULL, "omap_sx1.flash0-0", flash_size, 136 &error_fatal); 137 memory_region_add_subregion(address_space, OMAP_CS0_BASE, flash); 138 139 memory_region_init_io(&cs[0], NULL, &static_ops, &cs0val, 140 "sx1.cs0", OMAP_CS0_SIZE - flash_size); 141 memory_region_add_subregion(address_space, 142 OMAP_CS0_BASE + flash_size, &cs[0]); 143 144 145 memory_region_init_io(&cs[2], NULL, &static_ops, &cs2val, 146 "sx1.cs2", OMAP_CS2_SIZE); 147 memory_region_add_subregion(address_space, 148 OMAP_CS2_BASE, &cs[2]); 149 150 memory_region_init_io(&cs[3], NULL, &static_ops, &cs3val, 151 "sx1.cs3", OMAP_CS3_SIZE); 152 memory_region_add_subregion(address_space, 153 OMAP_CS2_BASE, &cs[3]); 154 155 fl_idx = 0; 156 if ((dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) { 157 pflash_cfi01_register(OMAP_CS0_BASE, 158 "omap_sx1.flash0-1", flash_size, 159 blk_by_legacy_dinfo(dinfo), 160 SECTOR_SIZE, 4, 0, 0, 0, 0, 0); 161 fl_idx++; 162 } 163 164 if ((version == 1) && 165 (dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) { 166 MemoryRegion *flash_1 = g_new(MemoryRegion, 1); 167 memory_region_init_rom(flash_1, NULL, "omap_sx1.flash1-0", 168 FLASH1_SIZE, &error_fatal); 169 memory_region_add_subregion(address_space, OMAP_CS1_BASE, flash_1); 170 171 memory_region_init_io(&cs[1], NULL, &static_ops, &cs1val, 172 "sx1.cs1", OMAP_CS1_SIZE - FLASH1_SIZE); 173 memory_region_add_subregion(address_space, 174 OMAP_CS1_BASE + FLASH1_SIZE, &cs[1]); 175 176 pflash_cfi01_register(OMAP_CS1_BASE, 177 "omap_sx1.flash1-1", FLASH1_SIZE, 178 blk_by_legacy_dinfo(dinfo), 179 SECTOR_SIZE, 4, 0, 0, 0, 0, 0); 180 fl_idx++; 181 } else { 182 memory_region_init_io(&cs[1], NULL, &static_ops, &cs1val, 183 "sx1.cs1", OMAP_CS1_SIZE); 184 memory_region_add_subregion(address_space, 185 OMAP_CS1_BASE, &cs[1]); 186 } 187 188 if (!machine->kernel_filename && !fl_idx && !qtest_enabled()) { 189 error_report("Kernel or Flash image must be specified"); 190 exit(1); 191 } 192 193 /* Load the kernel. */ 194 arm_load_kernel(mpu->cpu, machine, &sx1_binfo); 195 196 /* TODO: fix next line */ 197 //~ qemu_console_resize(ds, 640, 480); 198 } 199 200 static void sx1_init_v1(MachineState *machine) 201 { 202 sx1_init(machine, 1); 203 } 204 205 static void sx1_init_v2(MachineState *machine) 206 { 207 sx1_init(machine, 2); 208 } 209 210 static void sx1_machine_v2_class_init(ObjectClass *oc, void *data) 211 { 212 MachineClass *mc = MACHINE_CLASS(oc); 213 214 mc->desc = "Siemens SX1 (OMAP310) V2"; 215 mc->init = sx1_init_v2; 216 mc->ignore_memory_transaction_failures = true; 217 mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t"); 218 mc->default_ram_size = SDRAM_SIZE; 219 mc->default_ram_id = "omap1.dram"; 220 } 221 222 static const TypeInfo sx1_machine_v2_type = { 223 .name = MACHINE_TYPE_NAME("sx1"), 224 .parent = TYPE_MACHINE, 225 .class_init = sx1_machine_v2_class_init, 226 }; 227 228 static void sx1_machine_v1_class_init(ObjectClass *oc, void *data) 229 { 230 MachineClass *mc = MACHINE_CLASS(oc); 231 232 mc->desc = "Siemens SX1 (OMAP310) V1"; 233 mc->init = sx1_init_v1; 234 mc->ignore_memory_transaction_failures = true; 235 mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t"); 236 mc->default_ram_size = SDRAM_SIZE; 237 mc->default_ram_id = "omap1.dram"; 238 } 239 240 static const TypeInfo sx1_machine_v1_type = { 241 .name = MACHINE_TYPE_NAME("sx1-v1"), 242 .parent = TYPE_MACHINE, 243 .class_init = sx1_machine_v1_class_init, 244 }; 245 246 static void sx1_machine_init(void) 247 { 248 type_register_static(&sx1_machine_v1_type); 249 type_register_static(&sx1_machine_v2_type); 250 } 251 252 type_init(sx1_machine_init) 253