1 /* omap_sx1.c Support for the Siemens SX1 smartphone emulation.
2 *
3 * Copyright (C) 2008
4 * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 * Copyright (C) 2007 Vladimir Ananiev <vovan888@gmail.com>
6 *
7 * based on PalmOne's (TM) PDAs support (palm.c)
8 */
9
10 /*
11 * PalmOne's (TM) PDAs.
12 *
13 * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, see <http://www.gnu.org/licenses/>.
27 */
28 #include "qemu/osdep.h"
29 #include "qemu/units.h"
30 #include "qapi/error.h"
31 #include "ui/console.h"
32 #include "hw/arm/omap.h"
33 #include "hw/boards.h"
34 #include "hw/arm/boot.h"
35 #include "hw/block/flash.h"
36 #include "sysemu/qtest.h"
37 #include "exec/address-spaces.h"
38 #include "qemu/cutils.h"
39 #include "qemu/error-report.h"
40
41
42 /*****************************************************************************/
43 /* Siemens SX1 Cellphone V1 */
44 /* - ARM OMAP310 processor
45 * - SRAM 192 kB
46 * - SDRAM 32 MB at 0x10000000
47 * - Boot flash 16 MB at 0x00000000
48 * - Application flash 8 MB at 0x04000000
49 * - 3 serial ports
50 * - 1 SecureDigital
51 * - 1 LCD display
52 * - 1 RTC
53 */
54
55 /*****************************************************************************/
56 /* Siemens SX1 Cellphone V2 */
57 /* - ARM OMAP310 processor
58 * - SRAM 192 kB
59 * - SDRAM 32 MB at 0x10000000
60 * - Boot flash 32 MB at 0x00000000
61 * - 3 serial ports
62 * - 1 SecureDigital
63 * - 1 LCD display
64 * - 1 RTC
65 */
66
static_read(void * opaque,hwaddr offset,unsigned size)67 static uint64_t static_read(void *opaque, hwaddr offset,
68 unsigned size)
69 {
70 uint32_t *val = opaque;
71 uint32_t mask = (4 / size) - 1;
72
73 return *val >> ((offset & mask) << 3);
74 }
75
static_write(void * opaque,hwaddr offset,uint64_t value,unsigned size)76 static void static_write(void *opaque, hwaddr offset,
77 uint64_t value, unsigned size)
78 {
79 #ifdef SPY
80 printf("%s: value %" PRIx64 " %u bytes written at 0x%x\n",
81 __func__, value, size, (int)offset);
82 #endif
83 }
84
85 static const MemoryRegionOps static_ops = {
86 .read = static_read,
87 .write = static_write,
88 .endianness = DEVICE_NATIVE_ENDIAN,
89 };
90
91 #define SDRAM_SIZE (32 * MiB)
92 #define SECTOR_SIZE (128 * KiB)
93 #define FLASH0_SIZE (16 * MiB)
94 #define FLASH1_SIZE (8 * MiB)
95 #define FLASH2_SIZE (32 * MiB)
96
97 static struct arm_boot_info sx1_binfo = {
98 .loader_start = OMAP_EMIFF_BASE,
99 .ram_size = SDRAM_SIZE,
100 .board_id = 0x265,
101 };
102
sx1_init(MachineState * machine,const int version)103 static void sx1_init(MachineState *machine, const int version)
104 {
105 struct omap_mpu_state_s *mpu;
106 MachineClass *mc = MACHINE_GET_CLASS(machine);
107 MemoryRegion *address_space = get_system_memory();
108 MemoryRegion *flash = g_new(MemoryRegion, 1);
109 MemoryRegion *cs = g_new(MemoryRegion, 4);
110 static uint32_t cs0val = 0x00213090;
111 static uint32_t cs1val = 0x00215070;
112 static uint32_t cs2val = 0x00001139;
113 static uint32_t cs3val = 0x00001139;
114 DriveInfo *dinfo;
115 int fl_idx;
116 uint32_t flash_size = FLASH0_SIZE;
117
118 if (machine->ram_size != mc->default_ram_size) {
119 char *sz = size_to_str(mc->default_ram_size);
120 error_report("Invalid RAM size, should be %s", sz);
121 g_free(sz);
122 exit(EXIT_FAILURE);
123 }
124
125 if (version == 2) {
126 flash_size = FLASH2_SIZE;
127 }
128
129 memory_region_add_subregion(address_space, OMAP_EMIFF_BASE, machine->ram);
130
131 mpu = omap310_mpu_init(machine->ram, machine->cpu_type);
132
133 /* External Flash (EMIFS) */
134 memory_region_init_rom(flash, NULL, "omap_sx1.flash0-0", flash_size,
135 &error_fatal);
136 memory_region_add_subregion(address_space, OMAP_CS0_BASE, flash);
137
138 memory_region_init_io(&cs[0], NULL, &static_ops, &cs0val,
139 "sx1.cs0", OMAP_CS0_SIZE - flash_size);
140 memory_region_add_subregion(address_space,
141 OMAP_CS0_BASE + flash_size, &cs[0]);
142
143
144 memory_region_init_io(&cs[2], NULL, &static_ops, &cs2val,
145 "sx1.cs2", OMAP_CS2_SIZE);
146 memory_region_add_subregion(address_space,
147 OMAP_CS2_BASE, &cs[2]);
148
149 memory_region_init_io(&cs[3], NULL, &static_ops, &cs3val,
150 "sx1.cs3", OMAP_CS3_SIZE);
151 memory_region_add_subregion(address_space,
152 OMAP_CS2_BASE, &cs[3]);
153
154 fl_idx = 0;
155 if ((dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) {
156 pflash_cfi01_register(OMAP_CS0_BASE,
157 "omap_sx1.flash0-1", flash_size,
158 blk_by_legacy_dinfo(dinfo),
159 SECTOR_SIZE, 4, 0, 0, 0, 0, 0);
160 fl_idx++;
161 }
162
163 if ((version == 1) &&
164 (dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) {
165 MemoryRegion *flash_1 = g_new(MemoryRegion, 1);
166 memory_region_init_rom(flash_1, NULL, "omap_sx1.flash1-0",
167 FLASH1_SIZE, &error_fatal);
168 memory_region_add_subregion(address_space, OMAP_CS1_BASE, flash_1);
169
170 memory_region_init_io(&cs[1], NULL, &static_ops, &cs1val,
171 "sx1.cs1", OMAP_CS1_SIZE - FLASH1_SIZE);
172 memory_region_add_subregion(address_space,
173 OMAP_CS1_BASE + FLASH1_SIZE, &cs[1]);
174
175 pflash_cfi01_register(OMAP_CS1_BASE,
176 "omap_sx1.flash1-1", FLASH1_SIZE,
177 blk_by_legacy_dinfo(dinfo),
178 SECTOR_SIZE, 4, 0, 0, 0, 0, 0);
179 fl_idx++;
180 } else {
181 memory_region_init_io(&cs[1], NULL, &static_ops, &cs1val,
182 "sx1.cs1", OMAP_CS1_SIZE);
183 memory_region_add_subregion(address_space,
184 OMAP_CS1_BASE, &cs[1]);
185 }
186
187 if (!machine->kernel_filename && !fl_idx && !qtest_enabled()) {
188 error_report("Kernel or Flash image must be specified");
189 exit(1);
190 }
191
192 /* Load the kernel. */
193 arm_load_kernel(mpu->cpu, machine, &sx1_binfo);
194
195 /* TODO: fix next line */
196 //~ qemu_console_resize(ds, 640, 480);
197 }
198
sx1_init_v1(MachineState * machine)199 static void sx1_init_v1(MachineState *machine)
200 {
201 sx1_init(machine, 1);
202 }
203
sx1_init_v2(MachineState * machine)204 static void sx1_init_v2(MachineState *machine)
205 {
206 sx1_init(machine, 2);
207 }
208
sx1_machine_v2_class_init(ObjectClass * oc,void * data)209 static void sx1_machine_v2_class_init(ObjectClass *oc, void *data)
210 {
211 MachineClass *mc = MACHINE_CLASS(oc);
212
213 mc->desc = "Siemens SX1 (OMAP310) V2";
214 mc->init = sx1_init_v2;
215 mc->ignore_memory_transaction_failures = true;
216 mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t");
217 mc->default_ram_size = SDRAM_SIZE;
218 mc->default_ram_id = "omap1.dram";
219 }
220
221 static const TypeInfo sx1_machine_v2_type = {
222 .name = MACHINE_TYPE_NAME("sx1"),
223 .parent = TYPE_MACHINE,
224 .class_init = sx1_machine_v2_class_init,
225 };
226
sx1_machine_v1_class_init(ObjectClass * oc,void * data)227 static void sx1_machine_v1_class_init(ObjectClass *oc, void *data)
228 {
229 MachineClass *mc = MACHINE_CLASS(oc);
230
231 mc->desc = "Siemens SX1 (OMAP310) V1";
232 mc->init = sx1_init_v1;
233 mc->ignore_memory_transaction_failures = true;
234 mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t");
235 mc->default_ram_size = SDRAM_SIZE;
236 mc->default_ram_id = "omap1.dram";
237 }
238
239 static const TypeInfo sx1_machine_v1_type = {
240 .name = MACHINE_TYPE_NAME("sx1-v1"),
241 .parent = TYPE_MACHINE,
242 .class_init = sx1_machine_v1_class_init,
243 };
244
sx1_machine_init(void)245 static void sx1_machine_init(void)
246 {
247 type_register_static(&sx1_machine_v1_type);
248 type_register_static(&sx1_machine_v2_type);
249 }
250
251 type_init(sx1_machine_init)
252