1 /* 2 * TI OMAP processors emulation. 3 * 4 * Copyright (C) 2007-2008 Nokia Corporation 5 * Written by Andrzej Zaborowski <andrew@openedhand.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 or 10 * (at your option) version 3 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "sysemu/block-backend.h" 24 #include "sysemu/blockdev.h" 25 #include "hw/boards.h" 26 #include "hw/hw.h" 27 #include "hw/arm/arm.h" 28 #include "hw/arm/omap.h" 29 #include "sysemu/sysemu.h" 30 #include "qemu/timer.h" 31 #include "sysemu/char.h" 32 #include "hw/block/flash.h" 33 #include "hw/arm/soc_dma.h" 34 #include "hw/sysbus.h" 35 #include "audio/audio.h" 36 37 /* Enhanced Audio Controller (CODEC only) */ 38 struct omap_eac_s { 39 qemu_irq irq; 40 MemoryRegion iomem; 41 42 uint16_t sysconfig; 43 uint8_t config[4]; 44 uint8_t control; 45 uint8_t address; 46 uint16_t data; 47 uint8_t vtol; 48 uint8_t vtsl; 49 uint16_t mixer; 50 uint16_t gain[4]; 51 uint8_t att; 52 uint16_t max[7]; 53 54 struct { 55 qemu_irq txdrq; 56 qemu_irq rxdrq; 57 uint32_t (*txrx)(void *opaque, uint32_t, int); 58 void *opaque; 59 60 #define EAC_BUF_LEN 1024 61 uint32_t rxbuf[EAC_BUF_LEN]; 62 int rxoff; 63 int rxlen; 64 int rxavail; 65 uint32_t txbuf[EAC_BUF_LEN]; 66 int txlen; 67 int txavail; 68 69 int enable; 70 int rate; 71 72 uint16_t config[4]; 73 74 /* These need to be moved to the actual codec */ 75 QEMUSoundCard card; 76 SWVoiceIn *in_voice; 77 SWVoiceOut *out_voice; 78 int hw_enable; 79 } codec; 80 81 struct { 82 uint8_t control; 83 uint16_t config; 84 } modem, bt; 85 }; 86 87 static inline void omap_eac_interrupt_update(struct omap_eac_s *s) 88 { 89 qemu_set_irq(s->irq, (s->codec.config[1] >> 14) & 1); /* AURDI */ 90 } 91 92 static inline void omap_eac_in_dmarequest_update(struct omap_eac_s *s) 93 { 94 qemu_set_irq(s->codec.rxdrq, (s->codec.rxavail || s->codec.rxlen) && 95 ((s->codec.config[1] >> 12) & 1)); /* DMAREN */ 96 } 97 98 static inline void omap_eac_out_dmarequest_update(struct omap_eac_s *s) 99 { 100 qemu_set_irq(s->codec.txdrq, s->codec.txlen < s->codec.txavail && 101 ((s->codec.config[1] >> 11) & 1)); /* DMAWEN */ 102 } 103 104 static inline void omap_eac_in_refill(struct omap_eac_s *s) 105 { 106 int left = MIN(EAC_BUF_LEN - s->codec.rxlen, s->codec.rxavail) << 2; 107 int start = ((s->codec.rxoff + s->codec.rxlen) & (EAC_BUF_LEN - 1)) << 2; 108 int leftwrap = MIN(left, (EAC_BUF_LEN << 2) - start); 109 int recv = 1; 110 uint8_t *buf = (uint8_t *) s->codec.rxbuf + start; 111 112 left -= leftwrap; 113 start = 0; 114 while (leftwrap && (recv = AUD_read(s->codec.in_voice, buf + start, 115 leftwrap)) > 0) { /* Be defensive */ 116 start += recv; 117 leftwrap -= recv; 118 } 119 if (recv <= 0) 120 s->codec.rxavail = 0; 121 else 122 s->codec.rxavail -= start >> 2; 123 s->codec.rxlen += start >> 2; 124 125 if (recv > 0 && left > 0) { 126 start = 0; 127 while (left && (recv = AUD_read(s->codec.in_voice, 128 (uint8_t *) s->codec.rxbuf + start, 129 left)) > 0) { /* Be defensive */ 130 start += recv; 131 left -= recv; 132 } 133 if (recv <= 0) 134 s->codec.rxavail = 0; 135 else 136 s->codec.rxavail -= start >> 2; 137 s->codec.rxlen += start >> 2; 138 } 139 } 140 141 static inline void omap_eac_out_empty(struct omap_eac_s *s) 142 { 143 int left = s->codec.txlen << 2; 144 int start = 0; 145 int sent = 1; 146 147 while (left && (sent = AUD_write(s->codec.out_voice, 148 (uint8_t *) s->codec.txbuf + start, 149 left)) > 0) { /* Be defensive */ 150 start += sent; 151 left -= sent; 152 } 153 154 if (!sent) { 155 s->codec.txavail = 0; 156 omap_eac_out_dmarequest_update(s); 157 } 158 159 if (start) 160 s->codec.txlen = 0; 161 } 162 163 static void omap_eac_in_cb(void *opaque, int avail_b) 164 { 165 struct omap_eac_s *s = (struct omap_eac_s *) opaque; 166 167 s->codec.rxavail = avail_b >> 2; 168 omap_eac_in_refill(s); 169 /* TODO: possibly discard current buffer if overrun */ 170 omap_eac_in_dmarequest_update(s); 171 } 172 173 static void omap_eac_out_cb(void *opaque, int free_b) 174 { 175 struct omap_eac_s *s = (struct omap_eac_s *) opaque; 176 177 s->codec.txavail = free_b >> 2; 178 if (s->codec.txlen) 179 omap_eac_out_empty(s); 180 else 181 omap_eac_out_dmarequest_update(s); 182 } 183 184 static void omap_eac_enable_update(struct omap_eac_s *s) 185 { 186 s->codec.enable = !(s->codec.config[1] & 1) && /* EACPWD */ 187 (s->codec.config[1] & 2) && /* AUDEN */ 188 s->codec.hw_enable; 189 } 190 191 static const int omap_eac_fsint[4] = { 192 8000, 193 11025, 194 22050, 195 44100, 196 }; 197 198 static const int omap_eac_fsint2[8] = { 199 8000, 200 11025, 201 22050, 202 44100, 203 48000, 204 0, 0, 0, 205 }; 206 207 static const int omap_eac_fsint3[16] = { 208 8000, 209 11025, 210 16000, 211 22050, 212 24000, 213 32000, 214 44100, 215 48000, 216 0, 0, 0, 0, 0, 0, 0, 0, 217 }; 218 219 static void omap_eac_rate_update(struct omap_eac_s *s) 220 { 221 int fsint[3]; 222 223 fsint[2] = (s->codec.config[3] >> 9) & 0xf; 224 fsint[1] = (s->codec.config[2] >> 0) & 0x7; 225 fsint[0] = (s->codec.config[0] >> 6) & 0x3; 226 if (fsint[2] < 0xf) 227 s->codec.rate = omap_eac_fsint3[fsint[2]]; 228 else if (fsint[1] < 0x7) 229 s->codec.rate = omap_eac_fsint2[fsint[1]]; 230 else 231 s->codec.rate = omap_eac_fsint[fsint[0]]; 232 } 233 234 static void omap_eac_volume_update(struct omap_eac_s *s) 235 { 236 /* TODO */ 237 } 238 239 static void omap_eac_format_update(struct omap_eac_s *s) 240 { 241 struct audsettings fmt; 242 243 /* The hardware buffers at most one sample */ 244 if (s->codec.rxlen) 245 s->codec.rxlen = 1; 246 247 if (s->codec.in_voice) { 248 AUD_set_active_in(s->codec.in_voice, 0); 249 AUD_close_in(&s->codec.card, s->codec.in_voice); 250 s->codec.in_voice = NULL; 251 } 252 if (s->codec.out_voice) { 253 omap_eac_out_empty(s); 254 AUD_set_active_out(s->codec.out_voice, 0); 255 AUD_close_out(&s->codec.card, s->codec.out_voice); 256 s->codec.out_voice = NULL; 257 s->codec.txavail = 0; 258 } 259 /* Discard what couldn't be written */ 260 s->codec.txlen = 0; 261 262 omap_eac_enable_update(s); 263 if (!s->codec.enable) 264 return; 265 266 omap_eac_rate_update(s); 267 fmt.endianness = ((s->codec.config[0] >> 8) & 1); /* LI_BI */ 268 fmt.nchannels = ((s->codec.config[0] >> 10) & 1) ? 2 : 1; /* MN_ST */ 269 fmt.freq = s->codec.rate; 270 /* TODO: signedness possibly depends on the CODEC hardware - or 271 * does I2S specify it? */ 272 /* All register writes are 16 bits so we we store 16-bit samples 273 * in the buffers regardless of AGCFR[B8_16] value. */ 274 fmt.fmt = AUD_FMT_U16; 275 276 s->codec.in_voice = AUD_open_in(&s->codec.card, s->codec.in_voice, 277 "eac.codec.in", s, omap_eac_in_cb, &fmt); 278 s->codec.out_voice = AUD_open_out(&s->codec.card, s->codec.out_voice, 279 "eac.codec.out", s, omap_eac_out_cb, &fmt); 280 281 omap_eac_volume_update(s); 282 283 AUD_set_active_in(s->codec.in_voice, 1); 284 AUD_set_active_out(s->codec.out_voice, 1); 285 } 286 287 static void omap_eac_reset(struct omap_eac_s *s) 288 { 289 s->sysconfig = 0; 290 s->config[0] = 0x0c; 291 s->config[1] = 0x09; 292 s->config[2] = 0xab; 293 s->config[3] = 0x03; 294 s->control = 0x00; 295 s->address = 0x00; 296 s->data = 0x0000; 297 s->vtol = 0x00; 298 s->vtsl = 0x00; 299 s->mixer = 0x0000; 300 s->gain[0] = 0xe7e7; 301 s->gain[1] = 0x6767; 302 s->gain[2] = 0x6767; 303 s->gain[3] = 0x6767; 304 s->att = 0xce; 305 s->max[0] = 0; 306 s->max[1] = 0; 307 s->max[2] = 0; 308 s->max[3] = 0; 309 s->max[4] = 0; 310 s->max[5] = 0; 311 s->max[6] = 0; 312 313 s->modem.control = 0x00; 314 s->modem.config = 0x0000; 315 s->bt.control = 0x00; 316 s->bt.config = 0x0000; 317 s->codec.config[0] = 0x0649; 318 s->codec.config[1] = 0x0000; 319 s->codec.config[2] = 0x0007; 320 s->codec.config[3] = 0x1ffc; 321 s->codec.rxoff = 0; 322 s->codec.rxlen = 0; 323 s->codec.txlen = 0; 324 s->codec.rxavail = 0; 325 s->codec.txavail = 0; 326 327 omap_eac_format_update(s); 328 omap_eac_interrupt_update(s); 329 } 330 331 static uint64_t omap_eac_read(void *opaque, hwaddr addr, 332 unsigned size) 333 { 334 struct omap_eac_s *s = (struct omap_eac_s *) opaque; 335 uint32_t ret; 336 337 if (size != 2) { 338 return omap_badwidth_read16(opaque, addr); 339 } 340 341 switch (addr) { 342 case 0x000: /* CPCFR1 */ 343 return s->config[0]; 344 case 0x004: /* CPCFR2 */ 345 return s->config[1]; 346 case 0x008: /* CPCFR3 */ 347 return s->config[2]; 348 case 0x00c: /* CPCFR4 */ 349 return s->config[3]; 350 351 case 0x010: /* CPTCTL */ 352 return s->control | ((s->codec.rxavail + s->codec.rxlen > 0) << 7) | 353 ((s->codec.txlen < s->codec.txavail) << 5); 354 355 case 0x014: /* CPTTADR */ 356 return s->address; 357 case 0x018: /* CPTDATL */ 358 return s->data & 0xff; 359 case 0x01c: /* CPTDATH */ 360 return s->data >> 8; 361 case 0x020: /* CPTVSLL */ 362 return s->vtol; 363 case 0x024: /* CPTVSLH */ 364 return s->vtsl | (3 << 5); /* CRDY1 | CRDY2 */ 365 case 0x040: /* MPCTR */ 366 return s->modem.control; 367 case 0x044: /* MPMCCFR */ 368 return s->modem.config; 369 case 0x060: /* BPCTR */ 370 return s->bt.control; 371 case 0x064: /* BPMCCFR */ 372 return s->bt.config; 373 case 0x080: /* AMSCFR */ 374 return s->mixer; 375 case 0x084: /* AMVCTR */ 376 return s->gain[0]; 377 case 0x088: /* AM1VCTR */ 378 return s->gain[1]; 379 case 0x08c: /* AM2VCTR */ 380 return s->gain[2]; 381 case 0x090: /* AM3VCTR */ 382 return s->gain[3]; 383 case 0x094: /* ASTCTR */ 384 return s->att; 385 case 0x098: /* APD1LCR */ 386 return s->max[0]; 387 case 0x09c: /* APD1RCR */ 388 return s->max[1]; 389 case 0x0a0: /* APD2LCR */ 390 return s->max[2]; 391 case 0x0a4: /* APD2RCR */ 392 return s->max[3]; 393 case 0x0a8: /* APD3LCR */ 394 return s->max[4]; 395 case 0x0ac: /* APD3RCR */ 396 return s->max[5]; 397 case 0x0b0: /* APD4R */ 398 return s->max[6]; 399 case 0x0b4: /* ADWR */ 400 /* This should be write-only? Docs list it as read-only. */ 401 return 0x0000; 402 case 0x0b8: /* ADRDR */ 403 if (likely(s->codec.rxlen > 1)) { 404 ret = s->codec.rxbuf[s->codec.rxoff ++]; 405 s->codec.rxlen --; 406 s->codec.rxoff &= EAC_BUF_LEN - 1; 407 return ret; 408 } else if (s->codec.rxlen) { 409 ret = s->codec.rxbuf[s->codec.rxoff ++]; 410 s->codec.rxlen --; 411 s->codec.rxoff &= EAC_BUF_LEN - 1; 412 if (s->codec.rxavail) 413 omap_eac_in_refill(s); 414 omap_eac_in_dmarequest_update(s); 415 return ret; 416 } 417 return 0x0000; 418 case 0x0bc: /* AGCFR */ 419 return s->codec.config[0]; 420 case 0x0c0: /* AGCTR */ 421 return s->codec.config[1] | ((s->codec.config[1] & 2) << 14); 422 case 0x0c4: /* AGCFR2 */ 423 return s->codec.config[2]; 424 case 0x0c8: /* AGCFR3 */ 425 return s->codec.config[3]; 426 case 0x0cc: /* MBPDMACTR */ 427 case 0x0d0: /* MPDDMARR */ 428 case 0x0d8: /* MPUDMARR */ 429 case 0x0e4: /* BPDDMARR */ 430 case 0x0ec: /* BPUDMARR */ 431 return 0x0000; 432 433 case 0x100: /* VERSION_NUMBER */ 434 return 0x0010; 435 436 case 0x104: /* SYSCONFIG */ 437 return s->sysconfig; 438 439 case 0x108: /* SYSSTATUS */ 440 return 1 | 0xe; /* RESETDONE | stuff */ 441 } 442 443 OMAP_BAD_REG(addr); 444 return 0; 445 } 446 447 static void omap_eac_write(void *opaque, hwaddr addr, 448 uint64_t value, unsigned size) 449 { 450 struct omap_eac_s *s = (struct omap_eac_s *) opaque; 451 452 if (size != 2) { 453 omap_badwidth_write16(opaque, addr, value); 454 return; 455 } 456 457 switch (addr) { 458 case 0x098: /* APD1LCR */ 459 case 0x09c: /* APD1RCR */ 460 case 0x0a0: /* APD2LCR */ 461 case 0x0a4: /* APD2RCR */ 462 case 0x0a8: /* APD3LCR */ 463 case 0x0ac: /* APD3RCR */ 464 case 0x0b0: /* APD4R */ 465 case 0x0b8: /* ADRDR */ 466 case 0x0d0: /* MPDDMARR */ 467 case 0x0d8: /* MPUDMARR */ 468 case 0x0e4: /* BPDDMARR */ 469 case 0x0ec: /* BPUDMARR */ 470 case 0x100: /* VERSION_NUMBER */ 471 case 0x108: /* SYSSTATUS */ 472 OMAP_RO_REG(addr); 473 return; 474 475 case 0x000: /* CPCFR1 */ 476 s->config[0] = value & 0xff; 477 omap_eac_format_update(s); 478 break; 479 case 0x004: /* CPCFR2 */ 480 s->config[1] = value & 0xff; 481 omap_eac_format_update(s); 482 break; 483 case 0x008: /* CPCFR3 */ 484 s->config[2] = value & 0xff; 485 omap_eac_format_update(s); 486 break; 487 case 0x00c: /* CPCFR4 */ 488 s->config[3] = value & 0xff; 489 omap_eac_format_update(s); 490 break; 491 492 case 0x010: /* CPTCTL */ 493 /* Assuming TXF and TXE bits are read-only... */ 494 s->control = value & 0x5f; 495 omap_eac_interrupt_update(s); 496 break; 497 498 case 0x014: /* CPTTADR */ 499 s->address = value & 0xff; 500 break; 501 case 0x018: /* CPTDATL */ 502 s->data &= 0xff00; 503 s->data |= value & 0xff; 504 break; 505 case 0x01c: /* CPTDATH */ 506 s->data &= 0x00ff; 507 s->data |= value << 8; 508 break; 509 case 0x020: /* CPTVSLL */ 510 s->vtol = value & 0xf8; 511 break; 512 case 0x024: /* CPTVSLH */ 513 s->vtsl = value & 0x9f; 514 break; 515 case 0x040: /* MPCTR */ 516 s->modem.control = value & 0x8f; 517 break; 518 case 0x044: /* MPMCCFR */ 519 s->modem.config = value & 0x7fff; 520 break; 521 case 0x060: /* BPCTR */ 522 s->bt.control = value & 0x8f; 523 break; 524 case 0x064: /* BPMCCFR */ 525 s->bt.config = value & 0x7fff; 526 break; 527 case 0x080: /* AMSCFR */ 528 s->mixer = value & 0x0fff; 529 break; 530 case 0x084: /* AMVCTR */ 531 s->gain[0] = value & 0xffff; 532 break; 533 case 0x088: /* AM1VCTR */ 534 s->gain[1] = value & 0xff7f; 535 break; 536 case 0x08c: /* AM2VCTR */ 537 s->gain[2] = value & 0xff7f; 538 break; 539 case 0x090: /* AM3VCTR */ 540 s->gain[3] = value & 0xff7f; 541 break; 542 case 0x094: /* ASTCTR */ 543 s->att = value & 0xff; 544 break; 545 546 case 0x0b4: /* ADWR */ 547 s->codec.txbuf[s->codec.txlen ++] = value; 548 if (unlikely(s->codec.txlen == EAC_BUF_LEN || 549 s->codec.txlen == s->codec.txavail)) { 550 if (s->codec.txavail) 551 omap_eac_out_empty(s); 552 /* Discard what couldn't be written */ 553 s->codec.txlen = 0; 554 } 555 break; 556 557 case 0x0bc: /* AGCFR */ 558 s->codec.config[0] = value & 0x07ff; 559 omap_eac_format_update(s); 560 break; 561 case 0x0c0: /* AGCTR */ 562 s->codec.config[1] = value & 0x780f; 563 omap_eac_format_update(s); 564 break; 565 case 0x0c4: /* AGCFR2 */ 566 s->codec.config[2] = value & 0x003f; 567 omap_eac_format_update(s); 568 break; 569 case 0x0c8: /* AGCFR3 */ 570 s->codec.config[3] = value & 0xffff; 571 omap_eac_format_update(s); 572 break; 573 case 0x0cc: /* MBPDMACTR */ 574 case 0x0d4: /* MPDDMAWR */ 575 case 0x0e0: /* MPUDMAWR */ 576 case 0x0e8: /* BPDDMAWR */ 577 case 0x0f0: /* BPUDMAWR */ 578 break; 579 580 case 0x104: /* SYSCONFIG */ 581 if (value & (1 << 1)) /* SOFTRESET */ 582 omap_eac_reset(s); 583 s->sysconfig = value & 0x31d; 584 break; 585 586 default: 587 OMAP_BAD_REG(addr); 588 return; 589 } 590 } 591 592 static const MemoryRegionOps omap_eac_ops = { 593 .read = omap_eac_read, 594 .write = omap_eac_write, 595 .endianness = DEVICE_NATIVE_ENDIAN, 596 }; 597 598 static struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta, 599 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk) 600 { 601 struct omap_eac_s *s = g_new0(struct omap_eac_s, 1); 602 603 s->irq = irq; 604 s->codec.rxdrq = *drq ++; 605 s->codec.txdrq = *drq; 606 omap_eac_reset(s); 607 608 AUD_register_card("OMAP EAC", &s->codec.card); 609 610 memory_region_init_io(&s->iomem, NULL, &omap_eac_ops, s, "omap.eac", 611 omap_l4_region_size(ta, 0)); 612 omap_l4_attach(ta, 0, &s->iomem); 613 614 return s; 615 } 616 617 /* STI/XTI (emulation interface) console - reverse engineered only */ 618 struct omap_sti_s { 619 qemu_irq irq; 620 MemoryRegion iomem; 621 MemoryRegion iomem_fifo; 622 CharDriverState *chr; 623 624 uint32_t sysconfig; 625 uint32_t systest; 626 uint32_t irqst; 627 uint32_t irqen; 628 uint32_t clkcontrol; 629 uint32_t serial_config; 630 }; 631 632 #define STI_TRACE_CONSOLE_CHANNEL 239 633 #define STI_TRACE_CONTROL_CHANNEL 253 634 635 static inline void omap_sti_interrupt_update(struct omap_sti_s *s) 636 { 637 qemu_set_irq(s->irq, s->irqst & s->irqen); 638 } 639 640 static void omap_sti_reset(struct omap_sti_s *s) 641 { 642 s->sysconfig = 0; 643 s->irqst = 0; 644 s->irqen = 0; 645 s->clkcontrol = 0; 646 s->serial_config = 0; 647 648 omap_sti_interrupt_update(s); 649 } 650 651 static uint64_t omap_sti_read(void *opaque, hwaddr addr, 652 unsigned size) 653 { 654 struct omap_sti_s *s = (struct omap_sti_s *) opaque; 655 656 if (size != 4) { 657 return omap_badwidth_read32(opaque, addr); 658 } 659 660 switch (addr) { 661 case 0x00: /* STI_REVISION */ 662 return 0x10; 663 664 case 0x10: /* STI_SYSCONFIG */ 665 return s->sysconfig; 666 667 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */ 668 return 0x00; 669 670 case 0x18: /* STI_IRQSTATUS */ 671 return s->irqst; 672 673 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */ 674 return s->irqen; 675 676 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */ 677 case 0x28: /* STI_RX_DR / XTI_RXDATA */ 678 /* TODO */ 679 return 0; 680 681 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */ 682 return s->clkcontrol; 683 684 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */ 685 return s->serial_config; 686 } 687 688 OMAP_BAD_REG(addr); 689 return 0; 690 } 691 692 static void omap_sti_write(void *opaque, hwaddr addr, 693 uint64_t value, unsigned size) 694 { 695 struct omap_sti_s *s = (struct omap_sti_s *) opaque; 696 697 if (size != 4) { 698 omap_badwidth_write32(opaque, addr, value); 699 return; 700 } 701 702 switch (addr) { 703 case 0x00: /* STI_REVISION */ 704 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */ 705 OMAP_RO_REG(addr); 706 return; 707 708 case 0x10: /* STI_SYSCONFIG */ 709 if (value & (1 << 1)) /* SOFTRESET */ 710 omap_sti_reset(s); 711 s->sysconfig = value & 0xfe; 712 break; 713 714 case 0x18: /* STI_IRQSTATUS */ 715 s->irqst &= ~value; 716 omap_sti_interrupt_update(s); 717 break; 718 719 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */ 720 s->irqen = value & 0xffff; 721 omap_sti_interrupt_update(s); 722 break; 723 724 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */ 725 s->clkcontrol = value & 0xff; 726 break; 727 728 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */ 729 s->serial_config = value & 0xff; 730 break; 731 732 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */ 733 case 0x28: /* STI_RX_DR / XTI_RXDATA */ 734 /* TODO */ 735 return; 736 737 default: 738 OMAP_BAD_REG(addr); 739 return; 740 } 741 } 742 743 static const MemoryRegionOps omap_sti_ops = { 744 .read = omap_sti_read, 745 .write = omap_sti_write, 746 .endianness = DEVICE_NATIVE_ENDIAN, 747 }; 748 749 static uint64_t omap_sti_fifo_read(void *opaque, hwaddr addr, 750 unsigned size) 751 { 752 OMAP_BAD_REG(addr); 753 return 0; 754 } 755 756 static void omap_sti_fifo_write(void *opaque, hwaddr addr, 757 uint64_t value, unsigned size) 758 { 759 struct omap_sti_s *s = (struct omap_sti_s *) opaque; 760 int ch = addr >> 6; 761 uint8_t byte = value; 762 763 if (size != 1) { 764 omap_badwidth_write8(opaque, addr, size); 765 return; 766 } 767 768 if (ch == STI_TRACE_CONTROL_CHANNEL) { 769 /* Flush channel <i>value</i>. */ 770 qemu_chr_fe_write(s->chr, (const uint8_t *) "\r", 1); 771 } else if (ch == STI_TRACE_CONSOLE_CHANNEL || 1) { 772 if (value == 0xc0 || value == 0xc3) { 773 /* Open channel <i>ch</i>. */ 774 } else if (value == 0x00) 775 qemu_chr_fe_write(s->chr, (const uint8_t *) "\n", 1); 776 else 777 qemu_chr_fe_write(s->chr, &byte, 1); 778 } 779 } 780 781 static const MemoryRegionOps omap_sti_fifo_ops = { 782 .read = omap_sti_fifo_read, 783 .write = omap_sti_fifo_write, 784 .endianness = DEVICE_NATIVE_ENDIAN, 785 }; 786 787 static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta, 788 MemoryRegion *sysmem, 789 hwaddr channel_base, qemu_irq irq, omap_clk clk, 790 CharDriverState *chr) 791 { 792 struct omap_sti_s *s = g_new0(struct omap_sti_s, 1); 793 794 s->irq = irq; 795 omap_sti_reset(s); 796 797 s->chr = chr ?: qemu_chr_new("null", "null", NULL); 798 799 memory_region_init_io(&s->iomem, NULL, &omap_sti_ops, s, "omap.sti", 800 omap_l4_region_size(ta, 0)); 801 omap_l4_attach(ta, 0, &s->iomem); 802 803 memory_region_init_io(&s->iomem_fifo, NULL, &omap_sti_fifo_ops, s, 804 "omap.sti.fifo", 0x10000); 805 memory_region_add_subregion(sysmem, channel_base, &s->iomem_fifo); 806 807 return s; 808 } 809 810 /* L4 Interconnect */ 811 #define L4TA(n) (n) 812 #define L4TAO(n) ((n) + 39) 813 814 static const struct omap_l4_region_s omap_l4_region[125] = { 815 [ 1] = { 0x40800, 0x800, 32 }, /* Initiator agent */ 816 [ 2] = { 0x41000, 0x1000, 32 }, /* Link agent */ 817 [ 0] = { 0x40000, 0x800, 32 }, /* Address and protection */ 818 [ 3] = { 0x00000, 0x1000, 32 | 16 | 8 }, /* System Control and Pinout */ 819 [ 4] = { 0x01000, 0x1000, 32 | 16 | 8 }, /* L4TAO1 */ 820 [ 5] = { 0x04000, 0x1000, 32 | 16 }, /* 32K Timer */ 821 [ 6] = { 0x05000, 0x1000, 32 | 16 | 8 }, /* L4TAO2 */ 822 [ 7] = { 0x08000, 0x800, 32 }, /* PRCM Region A */ 823 [ 8] = { 0x08800, 0x800, 32 }, /* PRCM Region B */ 824 [ 9] = { 0x09000, 0x1000, 32 | 16 | 8 }, /* L4TAO */ 825 [ 10] = { 0x12000, 0x1000, 32 | 16 | 8 }, /* Test (BCM) */ 826 [ 11] = { 0x13000, 0x1000, 32 | 16 | 8 }, /* L4TA1 */ 827 [ 12] = { 0x14000, 0x1000, 32 }, /* Test/emulation (TAP) */ 828 [ 13] = { 0x15000, 0x1000, 32 | 16 | 8 }, /* L4TA2 */ 829 [ 14] = { 0x18000, 0x1000, 32 | 16 | 8 }, /* GPIO1 */ 830 [ 16] = { 0x1a000, 0x1000, 32 | 16 | 8 }, /* GPIO2 */ 831 [ 18] = { 0x1c000, 0x1000, 32 | 16 | 8 }, /* GPIO3 */ 832 [ 19] = { 0x1e000, 0x1000, 32 | 16 | 8 }, /* GPIO4 */ 833 [ 15] = { 0x19000, 0x1000, 32 | 16 | 8 }, /* Quad GPIO TOP */ 834 [ 17] = { 0x1b000, 0x1000, 32 | 16 | 8 }, /* L4TA3 */ 835 [ 20] = { 0x20000, 0x1000, 32 | 16 | 8 }, /* WD Timer 1 (Secure) */ 836 [ 22] = { 0x22000, 0x1000, 32 | 16 | 8 }, /* WD Timer 2 (OMAP) */ 837 [ 21] = { 0x21000, 0x1000, 32 | 16 | 8 }, /* Dual WD timer TOP */ 838 [ 23] = { 0x23000, 0x1000, 32 | 16 | 8 }, /* L4TA4 */ 839 [ 24] = { 0x28000, 0x1000, 32 | 16 | 8 }, /* GP Timer 1 */ 840 [ 25] = { 0x29000, 0x1000, 32 | 16 | 8 }, /* L4TA7 */ 841 [ 26] = { 0x48000, 0x2000, 32 | 16 | 8 }, /* Emulation (ARM11ETB) */ 842 [ 27] = { 0x4a000, 0x1000, 32 | 16 | 8 }, /* L4TA9 */ 843 [ 28] = { 0x50000, 0x400, 32 | 16 | 8 }, /* Display top */ 844 [ 29] = { 0x50400, 0x400, 32 | 16 | 8 }, /* Display control */ 845 [ 30] = { 0x50800, 0x400, 32 | 16 | 8 }, /* Display RFBI */ 846 [ 31] = { 0x50c00, 0x400, 32 | 16 | 8 }, /* Display encoder */ 847 [ 32] = { 0x51000, 0x1000, 32 | 16 | 8 }, /* L4TA10 */ 848 [ 33] = { 0x52000, 0x400, 32 | 16 | 8 }, /* Camera top */ 849 [ 34] = { 0x52400, 0x400, 32 | 16 | 8 }, /* Camera core */ 850 [ 35] = { 0x52800, 0x400, 32 | 16 | 8 }, /* Camera DMA */ 851 [ 36] = { 0x52c00, 0x400, 32 | 16 | 8 }, /* Camera MMU */ 852 [ 37] = { 0x53000, 0x1000, 32 | 16 | 8 }, /* L4TA11 */ 853 [ 38] = { 0x56000, 0x1000, 32 | 16 | 8 }, /* sDMA */ 854 [ 39] = { 0x57000, 0x1000, 32 | 16 | 8 }, /* L4TA12 */ 855 [ 40] = { 0x58000, 0x1000, 32 | 16 | 8 }, /* SSI top */ 856 [ 41] = { 0x59000, 0x1000, 32 | 16 | 8 }, /* SSI GDD */ 857 [ 42] = { 0x5a000, 0x1000, 32 | 16 | 8 }, /* SSI Port1 */ 858 [ 43] = { 0x5b000, 0x1000, 32 | 16 | 8 }, /* SSI Port2 */ 859 [ 44] = { 0x5c000, 0x1000, 32 | 16 | 8 }, /* L4TA13 */ 860 [ 45] = { 0x5e000, 0x1000, 32 | 16 | 8 }, /* USB OTG */ 861 [ 46] = { 0x5f000, 0x1000, 32 | 16 | 8 }, /* L4TAO4 */ 862 [ 47] = { 0x60000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER1SDRC) */ 863 [ 48] = { 0x61000, 0x1000, 32 | 16 | 8 }, /* L4TA14 */ 864 [ 49] = { 0x62000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER2GPMC) */ 865 [ 50] = { 0x63000, 0x1000, 32 | 16 | 8 }, /* L4TA15 */ 866 [ 51] = { 0x64000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER3OCM) */ 867 [ 52] = { 0x65000, 0x1000, 32 | 16 | 8 }, /* L4TA16 */ 868 [ 53] = { 0x66000, 0x300, 32 | 16 | 8 }, /* Emulation (WIN_TRACER4L4) */ 869 [ 54] = { 0x67000, 0x1000, 32 | 16 | 8 }, /* L4TA17 */ 870 [ 55] = { 0x68000, 0x1000, 32 | 16 | 8 }, /* Emulation (XTI) */ 871 [ 56] = { 0x69000, 0x1000, 32 | 16 | 8 }, /* L4TA18 */ 872 [ 57] = { 0x6a000, 0x1000, 16 | 8 }, /* UART1 */ 873 [ 58] = { 0x6b000, 0x1000, 32 | 16 | 8 }, /* L4TA19 */ 874 [ 59] = { 0x6c000, 0x1000, 16 | 8 }, /* UART2 */ 875 [ 60] = { 0x6d000, 0x1000, 32 | 16 | 8 }, /* L4TA20 */ 876 [ 61] = { 0x6e000, 0x1000, 16 | 8 }, /* UART3 */ 877 [ 62] = { 0x6f000, 0x1000, 32 | 16 | 8 }, /* L4TA21 */ 878 [ 63] = { 0x70000, 0x1000, 16 }, /* I2C1 */ 879 [ 64] = { 0x71000, 0x1000, 32 | 16 | 8 }, /* L4TAO5 */ 880 [ 65] = { 0x72000, 0x1000, 16 }, /* I2C2 */ 881 [ 66] = { 0x73000, 0x1000, 32 | 16 | 8 }, /* L4TAO6 */ 882 [ 67] = { 0x74000, 0x1000, 16 }, /* McBSP1 */ 883 [ 68] = { 0x75000, 0x1000, 32 | 16 | 8 }, /* L4TAO7 */ 884 [ 69] = { 0x76000, 0x1000, 16 }, /* McBSP2 */ 885 [ 70] = { 0x77000, 0x1000, 32 | 16 | 8 }, /* L4TAO8 */ 886 [ 71] = { 0x24000, 0x1000, 32 | 16 | 8 }, /* WD Timer 3 (DSP) */ 887 [ 72] = { 0x25000, 0x1000, 32 | 16 | 8 }, /* L4TA5 */ 888 [ 73] = { 0x26000, 0x1000, 32 | 16 | 8 }, /* WD Timer 4 (IVA) */ 889 [ 74] = { 0x27000, 0x1000, 32 | 16 | 8 }, /* L4TA6 */ 890 [ 75] = { 0x2a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 2 */ 891 [ 76] = { 0x2b000, 0x1000, 32 | 16 | 8 }, /* L4TA8 */ 892 [ 77] = { 0x78000, 0x1000, 32 | 16 | 8 }, /* GP Timer 3 */ 893 [ 78] = { 0x79000, 0x1000, 32 | 16 | 8 }, /* L4TA22 */ 894 [ 79] = { 0x7a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 4 */ 895 [ 80] = { 0x7b000, 0x1000, 32 | 16 | 8 }, /* L4TA23 */ 896 [ 81] = { 0x7c000, 0x1000, 32 | 16 | 8 }, /* GP Timer 5 */ 897 [ 82] = { 0x7d000, 0x1000, 32 | 16 | 8 }, /* L4TA24 */ 898 [ 83] = { 0x7e000, 0x1000, 32 | 16 | 8 }, /* GP Timer 6 */ 899 [ 84] = { 0x7f000, 0x1000, 32 | 16 | 8 }, /* L4TA25 */ 900 [ 85] = { 0x80000, 0x1000, 32 | 16 | 8 }, /* GP Timer 7 */ 901 [ 86] = { 0x81000, 0x1000, 32 | 16 | 8 }, /* L4TA26 */ 902 [ 87] = { 0x82000, 0x1000, 32 | 16 | 8 }, /* GP Timer 8 */ 903 [ 88] = { 0x83000, 0x1000, 32 | 16 | 8 }, /* L4TA27 */ 904 [ 89] = { 0x84000, 0x1000, 32 | 16 | 8 }, /* GP Timer 9 */ 905 [ 90] = { 0x85000, 0x1000, 32 | 16 | 8 }, /* L4TA28 */ 906 [ 91] = { 0x86000, 0x1000, 32 | 16 | 8 }, /* GP Timer 10 */ 907 [ 92] = { 0x87000, 0x1000, 32 | 16 | 8 }, /* L4TA29 */ 908 [ 93] = { 0x88000, 0x1000, 32 | 16 | 8 }, /* GP Timer 11 */ 909 [ 94] = { 0x89000, 0x1000, 32 | 16 | 8 }, /* L4TA30 */ 910 [ 95] = { 0x8a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 12 */ 911 [ 96] = { 0x8b000, 0x1000, 32 | 16 | 8 }, /* L4TA31 */ 912 [ 97] = { 0x90000, 0x1000, 16 }, /* EAC */ 913 [ 98] = { 0x91000, 0x1000, 32 | 16 | 8 }, /* L4TA32 */ 914 [ 99] = { 0x92000, 0x1000, 16 }, /* FAC */ 915 [100] = { 0x93000, 0x1000, 32 | 16 | 8 }, /* L4TA33 */ 916 [101] = { 0x94000, 0x1000, 32 | 16 | 8 }, /* IPC (MAILBOX) */ 917 [102] = { 0x95000, 0x1000, 32 | 16 | 8 }, /* L4TA34 */ 918 [103] = { 0x98000, 0x1000, 32 | 16 | 8 }, /* SPI1 */ 919 [104] = { 0x99000, 0x1000, 32 | 16 | 8 }, /* L4TA35 */ 920 [105] = { 0x9a000, 0x1000, 32 | 16 | 8 }, /* SPI2 */ 921 [106] = { 0x9b000, 0x1000, 32 | 16 | 8 }, /* L4TA36 */ 922 [107] = { 0x9c000, 0x1000, 16 | 8 }, /* MMC SDIO */ 923 [108] = { 0x9d000, 0x1000, 32 | 16 | 8 }, /* L4TAO9 */ 924 [109] = { 0x9e000, 0x1000, 32 | 16 | 8 }, /* MS_PRO */ 925 [110] = { 0x9f000, 0x1000, 32 | 16 | 8 }, /* L4TAO10 */ 926 [111] = { 0xa0000, 0x1000, 32 }, /* RNG */ 927 [112] = { 0xa1000, 0x1000, 32 | 16 | 8 }, /* L4TAO11 */ 928 [113] = { 0xa2000, 0x1000, 32 }, /* DES3DES */ 929 [114] = { 0xa3000, 0x1000, 32 | 16 | 8 }, /* L4TAO12 */ 930 [115] = { 0xa4000, 0x1000, 32 }, /* SHA1MD5 */ 931 [116] = { 0xa5000, 0x1000, 32 | 16 | 8 }, /* L4TAO13 */ 932 [117] = { 0xa6000, 0x1000, 32 }, /* AES */ 933 [118] = { 0xa7000, 0x1000, 32 | 16 | 8 }, /* L4TA37 */ 934 [119] = { 0xa8000, 0x2000, 32 }, /* PKA */ 935 [120] = { 0xaa000, 0x1000, 32 | 16 | 8 }, /* L4TA38 */ 936 [121] = { 0xb0000, 0x1000, 32 }, /* MG */ 937 [122] = { 0xb1000, 0x1000, 32 | 16 | 8 }, 938 [123] = { 0xb2000, 0x1000, 32 }, /* HDQ/1-Wire */ 939 [124] = { 0xb3000, 0x1000, 32 | 16 | 8 }, /* L4TA39 */ 940 }; 941 942 static const struct omap_l4_agent_info_s omap_l4_agent_info[54] = { 943 { 0, 0, 3, 2 }, /* L4IA initiatior agent */ 944 { L4TAO(1), 3, 2, 1 }, /* Control and pinout module */ 945 { L4TAO(2), 5, 2, 1 }, /* 32K timer */ 946 { L4TAO(3), 7, 3, 2 }, /* PRCM */ 947 { L4TA(1), 10, 2, 1 }, /* BCM */ 948 { L4TA(2), 12, 2, 1 }, /* Test JTAG */ 949 { L4TA(3), 14, 6, 3 }, /* Quad GPIO */ 950 { L4TA(4), 20, 4, 3 }, /* WD timer 1/2 */ 951 { L4TA(7), 24, 2, 1 }, /* GP timer 1 */ 952 { L4TA(9), 26, 2, 1 }, /* ATM11 ETB */ 953 { L4TA(10), 28, 5, 4 }, /* Display subsystem */ 954 { L4TA(11), 33, 5, 4 }, /* Camera subsystem */ 955 { L4TA(12), 38, 2, 1 }, /* sDMA */ 956 { L4TA(13), 40, 5, 4 }, /* SSI */ 957 { L4TAO(4), 45, 2, 1 }, /* USB */ 958 { L4TA(14), 47, 2, 1 }, /* Win Tracer1 */ 959 { L4TA(15), 49, 2, 1 }, /* Win Tracer2 */ 960 { L4TA(16), 51, 2, 1 }, /* Win Tracer3 */ 961 { L4TA(17), 53, 2, 1 }, /* Win Tracer4 */ 962 { L4TA(18), 55, 2, 1 }, /* XTI */ 963 { L4TA(19), 57, 2, 1 }, /* UART1 */ 964 { L4TA(20), 59, 2, 1 }, /* UART2 */ 965 { L4TA(21), 61, 2, 1 }, /* UART3 */ 966 { L4TAO(5), 63, 2, 1 }, /* I2C1 */ 967 { L4TAO(6), 65, 2, 1 }, /* I2C2 */ 968 { L4TAO(7), 67, 2, 1 }, /* McBSP1 */ 969 { L4TAO(8), 69, 2, 1 }, /* McBSP2 */ 970 { L4TA(5), 71, 2, 1 }, /* WD Timer 3 (DSP) */ 971 { L4TA(6), 73, 2, 1 }, /* WD Timer 4 (IVA) */ 972 { L4TA(8), 75, 2, 1 }, /* GP Timer 2 */ 973 { L4TA(22), 77, 2, 1 }, /* GP Timer 3 */ 974 { L4TA(23), 79, 2, 1 }, /* GP Timer 4 */ 975 { L4TA(24), 81, 2, 1 }, /* GP Timer 5 */ 976 { L4TA(25), 83, 2, 1 }, /* GP Timer 6 */ 977 { L4TA(26), 85, 2, 1 }, /* GP Timer 7 */ 978 { L4TA(27), 87, 2, 1 }, /* GP Timer 8 */ 979 { L4TA(28), 89, 2, 1 }, /* GP Timer 9 */ 980 { L4TA(29), 91, 2, 1 }, /* GP Timer 10 */ 981 { L4TA(30), 93, 2, 1 }, /* GP Timer 11 */ 982 { L4TA(31), 95, 2, 1 }, /* GP Timer 12 */ 983 { L4TA(32), 97, 2, 1 }, /* EAC */ 984 { L4TA(33), 99, 2, 1 }, /* FAC */ 985 { L4TA(34), 101, 2, 1 }, /* IPC */ 986 { L4TA(35), 103, 2, 1 }, /* SPI1 */ 987 { L4TA(36), 105, 2, 1 }, /* SPI2 */ 988 { L4TAO(9), 107, 2, 1 }, /* MMC SDIO */ 989 { L4TAO(10), 109, 2, 1 }, 990 { L4TAO(11), 111, 2, 1 }, /* RNG */ 991 { L4TAO(12), 113, 2, 1 }, /* DES3DES */ 992 { L4TAO(13), 115, 2, 1 }, /* SHA1MD5 */ 993 { L4TA(37), 117, 2, 1 }, /* AES */ 994 { L4TA(38), 119, 2, 1 }, /* PKA */ 995 { -1, 121, 2, 1 }, 996 { L4TA(39), 123, 2, 1 }, /* HDQ/1-Wire */ 997 }; 998 999 #define omap_l4ta(bus, cs) \ 1000 omap_l4ta_get(bus, omap_l4_region, omap_l4_agent_info, L4TA(cs)) 1001 #define omap_l4tao(bus, cs) \ 1002 omap_l4ta_get(bus, omap_l4_region, omap_l4_agent_info, L4TAO(cs)) 1003 1004 /* Power, Reset, and Clock Management */ 1005 struct omap_prcm_s { 1006 qemu_irq irq[3]; 1007 struct omap_mpu_state_s *mpu; 1008 MemoryRegion iomem0; 1009 MemoryRegion iomem1; 1010 1011 uint32_t irqst[3]; 1012 uint32_t irqen[3]; 1013 1014 uint32_t sysconfig; 1015 uint32_t voltctrl; 1016 uint32_t scratch[20]; 1017 1018 uint32_t clksrc[1]; 1019 uint32_t clkout[1]; 1020 uint32_t clkemul[1]; 1021 uint32_t clkpol[1]; 1022 uint32_t clksel[8]; 1023 uint32_t clken[12]; 1024 uint32_t clkctrl[4]; 1025 uint32_t clkidle[7]; 1026 uint32_t setuptime[2]; 1027 1028 uint32_t wkup[3]; 1029 uint32_t wken[3]; 1030 uint32_t wkst[3]; 1031 uint32_t rst[4]; 1032 uint32_t rstctrl[1]; 1033 uint32_t power[4]; 1034 uint32_t rsttime_wkup; 1035 1036 uint32_t ev; 1037 uint32_t evtime[2]; 1038 1039 int dpll_lock, apll_lock[2]; 1040 }; 1041 1042 static void omap_prcm_int_update(struct omap_prcm_s *s, int dom) 1043 { 1044 qemu_set_irq(s->irq[dom], s->irqst[dom] & s->irqen[dom]); 1045 /* XXX or is the mask applied before PRCM_IRQSTATUS_* ? */ 1046 } 1047 1048 static uint64_t omap_prcm_read(void *opaque, hwaddr addr, 1049 unsigned size) 1050 { 1051 struct omap_prcm_s *s = (struct omap_prcm_s *) opaque; 1052 uint32_t ret; 1053 1054 if (size != 4) { 1055 return omap_badwidth_read32(opaque, addr); 1056 } 1057 1058 switch (addr) { 1059 case 0x000: /* PRCM_REVISION */ 1060 return 0x10; 1061 1062 case 0x010: /* PRCM_SYSCONFIG */ 1063 return s->sysconfig; 1064 1065 case 0x018: /* PRCM_IRQSTATUS_MPU */ 1066 return s->irqst[0]; 1067 1068 case 0x01c: /* PRCM_IRQENABLE_MPU */ 1069 return s->irqen[0]; 1070 1071 case 0x050: /* PRCM_VOLTCTRL */ 1072 return s->voltctrl; 1073 case 0x054: /* PRCM_VOLTST */ 1074 return s->voltctrl & 3; 1075 1076 case 0x060: /* PRCM_CLKSRC_CTRL */ 1077 return s->clksrc[0]; 1078 case 0x070: /* PRCM_CLKOUT_CTRL */ 1079 return s->clkout[0]; 1080 case 0x078: /* PRCM_CLKEMUL_CTRL */ 1081 return s->clkemul[0]; 1082 case 0x080: /* PRCM_CLKCFG_CTRL */ 1083 case 0x084: /* PRCM_CLKCFG_STATUS */ 1084 return 0; 1085 1086 case 0x090: /* PRCM_VOLTSETUP */ 1087 return s->setuptime[0]; 1088 1089 case 0x094: /* PRCM_CLKSSETUP */ 1090 return s->setuptime[1]; 1091 1092 case 0x098: /* PRCM_POLCTRL */ 1093 return s->clkpol[0]; 1094 1095 case 0x0b0: /* GENERAL_PURPOSE1 */ 1096 case 0x0b4: /* GENERAL_PURPOSE2 */ 1097 case 0x0b8: /* GENERAL_PURPOSE3 */ 1098 case 0x0bc: /* GENERAL_PURPOSE4 */ 1099 case 0x0c0: /* GENERAL_PURPOSE5 */ 1100 case 0x0c4: /* GENERAL_PURPOSE6 */ 1101 case 0x0c8: /* GENERAL_PURPOSE7 */ 1102 case 0x0cc: /* GENERAL_PURPOSE8 */ 1103 case 0x0d0: /* GENERAL_PURPOSE9 */ 1104 case 0x0d4: /* GENERAL_PURPOSE10 */ 1105 case 0x0d8: /* GENERAL_PURPOSE11 */ 1106 case 0x0dc: /* GENERAL_PURPOSE12 */ 1107 case 0x0e0: /* GENERAL_PURPOSE13 */ 1108 case 0x0e4: /* GENERAL_PURPOSE14 */ 1109 case 0x0e8: /* GENERAL_PURPOSE15 */ 1110 case 0x0ec: /* GENERAL_PURPOSE16 */ 1111 case 0x0f0: /* GENERAL_PURPOSE17 */ 1112 case 0x0f4: /* GENERAL_PURPOSE18 */ 1113 case 0x0f8: /* GENERAL_PURPOSE19 */ 1114 case 0x0fc: /* GENERAL_PURPOSE20 */ 1115 return s->scratch[(addr - 0xb0) >> 2]; 1116 1117 case 0x140: /* CM_CLKSEL_MPU */ 1118 return s->clksel[0]; 1119 case 0x148: /* CM_CLKSTCTRL_MPU */ 1120 return s->clkctrl[0]; 1121 1122 case 0x158: /* RM_RSTST_MPU */ 1123 return s->rst[0]; 1124 case 0x1c8: /* PM_WKDEP_MPU */ 1125 return s->wkup[0]; 1126 case 0x1d4: /* PM_EVGENCTRL_MPU */ 1127 return s->ev; 1128 case 0x1d8: /* PM_EVEGENONTIM_MPU */ 1129 return s->evtime[0]; 1130 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */ 1131 return s->evtime[1]; 1132 case 0x1e0: /* PM_PWSTCTRL_MPU */ 1133 return s->power[0]; 1134 case 0x1e4: /* PM_PWSTST_MPU */ 1135 return 0; 1136 1137 case 0x200: /* CM_FCLKEN1_CORE */ 1138 return s->clken[0]; 1139 case 0x204: /* CM_FCLKEN2_CORE */ 1140 return s->clken[1]; 1141 case 0x210: /* CM_ICLKEN1_CORE */ 1142 return s->clken[2]; 1143 case 0x214: /* CM_ICLKEN2_CORE */ 1144 return s->clken[3]; 1145 case 0x21c: /* CM_ICLKEN4_CORE */ 1146 return s->clken[4]; 1147 1148 case 0x220: /* CM_IDLEST1_CORE */ 1149 /* TODO: check the actual iclk status */ 1150 return 0x7ffffff9; 1151 case 0x224: /* CM_IDLEST2_CORE */ 1152 /* TODO: check the actual iclk status */ 1153 return 0x00000007; 1154 case 0x22c: /* CM_IDLEST4_CORE */ 1155 /* TODO: check the actual iclk status */ 1156 return 0x0000001f; 1157 1158 case 0x230: /* CM_AUTOIDLE1_CORE */ 1159 return s->clkidle[0]; 1160 case 0x234: /* CM_AUTOIDLE2_CORE */ 1161 return s->clkidle[1]; 1162 case 0x238: /* CM_AUTOIDLE3_CORE */ 1163 return s->clkidle[2]; 1164 case 0x23c: /* CM_AUTOIDLE4_CORE */ 1165 return s->clkidle[3]; 1166 1167 case 0x240: /* CM_CLKSEL1_CORE */ 1168 return s->clksel[1]; 1169 case 0x244: /* CM_CLKSEL2_CORE */ 1170 return s->clksel[2]; 1171 1172 case 0x248: /* CM_CLKSTCTRL_CORE */ 1173 return s->clkctrl[1]; 1174 1175 case 0x2a0: /* PM_WKEN1_CORE */ 1176 return s->wken[0]; 1177 case 0x2a4: /* PM_WKEN2_CORE */ 1178 return s->wken[1]; 1179 1180 case 0x2b0: /* PM_WKST1_CORE */ 1181 return s->wkst[0]; 1182 case 0x2b4: /* PM_WKST2_CORE */ 1183 return s->wkst[1]; 1184 case 0x2c8: /* PM_WKDEP_CORE */ 1185 return 0x1e; 1186 1187 case 0x2e0: /* PM_PWSTCTRL_CORE */ 1188 return s->power[1]; 1189 case 0x2e4: /* PM_PWSTST_CORE */ 1190 return 0x000030 | (s->power[1] & 0xfc00); 1191 1192 case 0x300: /* CM_FCLKEN_GFX */ 1193 return s->clken[5]; 1194 case 0x310: /* CM_ICLKEN_GFX */ 1195 return s->clken[6]; 1196 case 0x320: /* CM_IDLEST_GFX */ 1197 /* TODO: check the actual iclk status */ 1198 return 0x00000001; 1199 case 0x340: /* CM_CLKSEL_GFX */ 1200 return s->clksel[3]; 1201 case 0x348: /* CM_CLKSTCTRL_GFX */ 1202 return s->clkctrl[2]; 1203 case 0x350: /* RM_RSTCTRL_GFX */ 1204 return s->rstctrl[0]; 1205 case 0x358: /* RM_RSTST_GFX */ 1206 return s->rst[1]; 1207 case 0x3c8: /* PM_WKDEP_GFX */ 1208 return s->wkup[1]; 1209 1210 case 0x3e0: /* PM_PWSTCTRL_GFX */ 1211 return s->power[2]; 1212 case 0x3e4: /* PM_PWSTST_GFX */ 1213 return s->power[2] & 3; 1214 1215 case 0x400: /* CM_FCLKEN_WKUP */ 1216 return s->clken[7]; 1217 case 0x410: /* CM_ICLKEN_WKUP */ 1218 return s->clken[8]; 1219 case 0x420: /* CM_IDLEST_WKUP */ 1220 /* TODO: check the actual iclk status */ 1221 return 0x0000003f; 1222 case 0x430: /* CM_AUTOIDLE_WKUP */ 1223 return s->clkidle[4]; 1224 case 0x440: /* CM_CLKSEL_WKUP */ 1225 return s->clksel[4]; 1226 case 0x450: /* RM_RSTCTRL_WKUP */ 1227 return 0; 1228 case 0x454: /* RM_RSTTIME_WKUP */ 1229 return s->rsttime_wkup; 1230 case 0x458: /* RM_RSTST_WKUP */ 1231 return s->rst[2]; 1232 case 0x4a0: /* PM_WKEN_WKUP */ 1233 return s->wken[2]; 1234 case 0x4b0: /* PM_WKST_WKUP */ 1235 return s->wkst[2]; 1236 1237 case 0x500: /* CM_CLKEN_PLL */ 1238 return s->clken[9]; 1239 case 0x520: /* CM_IDLEST_CKGEN */ 1240 ret = 0x0000070 | (s->apll_lock[0] << 9) | (s->apll_lock[1] << 8); 1241 if (!(s->clksel[6] & 3)) 1242 /* Core uses 32-kHz clock */ 1243 ret |= 3 << 0; 1244 else if (!s->dpll_lock) 1245 /* DPLL not locked, core uses ref_clk */ 1246 ret |= 1 << 0; 1247 else 1248 /* Core uses DPLL */ 1249 ret |= 2 << 0; 1250 return ret; 1251 case 0x530: /* CM_AUTOIDLE_PLL */ 1252 return s->clkidle[5]; 1253 case 0x540: /* CM_CLKSEL1_PLL */ 1254 return s->clksel[5]; 1255 case 0x544: /* CM_CLKSEL2_PLL */ 1256 return s->clksel[6]; 1257 1258 case 0x800: /* CM_FCLKEN_DSP */ 1259 return s->clken[10]; 1260 case 0x810: /* CM_ICLKEN_DSP */ 1261 return s->clken[11]; 1262 case 0x820: /* CM_IDLEST_DSP */ 1263 /* TODO: check the actual iclk status */ 1264 return 0x00000103; 1265 case 0x830: /* CM_AUTOIDLE_DSP */ 1266 return s->clkidle[6]; 1267 case 0x840: /* CM_CLKSEL_DSP */ 1268 return s->clksel[7]; 1269 case 0x848: /* CM_CLKSTCTRL_DSP */ 1270 return s->clkctrl[3]; 1271 case 0x850: /* RM_RSTCTRL_DSP */ 1272 return 0; 1273 case 0x858: /* RM_RSTST_DSP */ 1274 return s->rst[3]; 1275 case 0x8c8: /* PM_WKDEP_DSP */ 1276 return s->wkup[2]; 1277 case 0x8e0: /* PM_PWSTCTRL_DSP */ 1278 return s->power[3]; 1279 case 0x8e4: /* PM_PWSTST_DSP */ 1280 return 0x008030 | (s->power[3] & 0x3003); 1281 1282 case 0x8f0: /* PRCM_IRQSTATUS_DSP */ 1283 return s->irqst[1]; 1284 case 0x8f4: /* PRCM_IRQENABLE_DSP */ 1285 return s->irqen[1]; 1286 1287 case 0x8f8: /* PRCM_IRQSTATUS_IVA */ 1288 return s->irqst[2]; 1289 case 0x8fc: /* PRCM_IRQENABLE_IVA */ 1290 return s->irqen[2]; 1291 } 1292 1293 OMAP_BAD_REG(addr); 1294 return 0; 1295 } 1296 1297 static void omap_prcm_apll_update(struct omap_prcm_s *s) 1298 { 1299 int mode[2]; 1300 1301 mode[0] = (s->clken[9] >> 6) & 3; 1302 s->apll_lock[0] = (mode[0] == 3); 1303 mode[1] = (s->clken[9] >> 2) & 3; 1304 s->apll_lock[1] = (mode[1] == 3); 1305 /* TODO: update clocks */ 1306 1307 if (mode[0] == 1 || mode[0] == 2 || mode[1] == 1 || mode[1] == 2) 1308 fprintf(stderr, "%s: bad EN_54M_PLL or bad EN_96M_PLL\n", 1309 __FUNCTION__); 1310 } 1311 1312 static void omap_prcm_dpll_update(struct omap_prcm_s *s) 1313 { 1314 omap_clk dpll = omap_findclk(s->mpu, "dpll"); 1315 omap_clk dpll_x2 = omap_findclk(s->mpu, "dpll"); 1316 omap_clk core = omap_findclk(s->mpu, "core_clk"); 1317 int mode = (s->clken[9] >> 0) & 3; 1318 int mult, div; 1319 1320 mult = (s->clksel[5] >> 12) & 0x3ff; 1321 div = (s->clksel[5] >> 8) & 0xf; 1322 if (mult == 0 || mult == 1) 1323 mode = 1; /* Bypass */ 1324 1325 s->dpll_lock = 0; 1326 switch (mode) { 1327 case 0: 1328 fprintf(stderr, "%s: bad EN_DPLL\n", __FUNCTION__); 1329 break; 1330 case 1: /* Low-power bypass mode (Default) */ 1331 case 2: /* Fast-relock bypass mode */ 1332 omap_clk_setrate(dpll, 1, 1); 1333 omap_clk_setrate(dpll_x2, 1, 1); 1334 break; 1335 case 3: /* Lock mode */ 1336 s->dpll_lock = 1; /* After 20 FINT cycles (ref_clk / (div + 1)). */ 1337 1338 omap_clk_setrate(dpll, div + 1, mult); 1339 omap_clk_setrate(dpll_x2, div + 1, mult * 2); 1340 break; 1341 } 1342 1343 switch ((s->clksel[6] >> 0) & 3) { 1344 case 0: 1345 omap_clk_reparent(core, omap_findclk(s->mpu, "clk32-kHz")); 1346 break; 1347 case 1: 1348 omap_clk_reparent(core, dpll); 1349 break; 1350 case 2: 1351 /* Default */ 1352 omap_clk_reparent(core, dpll_x2); 1353 break; 1354 case 3: 1355 fprintf(stderr, "%s: bad CORE_CLK_SRC\n", __FUNCTION__); 1356 break; 1357 } 1358 } 1359 1360 static void omap_prcm_write(void *opaque, hwaddr addr, 1361 uint64_t value, unsigned size) 1362 { 1363 struct omap_prcm_s *s = (struct omap_prcm_s *) opaque; 1364 1365 if (size != 4) { 1366 omap_badwidth_write32(opaque, addr, value); 1367 return; 1368 } 1369 1370 switch (addr) { 1371 case 0x000: /* PRCM_REVISION */ 1372 case 0x054: /* PRCM_VOLTST */ 1373 case 0x084: /* PRCM_CLKCFG_STATUS */ 1374 case 0x1e4: /* PM_PWSTST_MPU */ 1375 case 0x220: /* CM_IDLEST1_CORE */ 1376 case 0x224: /* CM_IDLEST2_CORE */ 1377 case 0x22c: /* CM_IDLEST4_CORE */ 1378 case 0x2c8: /* PM_WKDEP_CORE */ 1379 case 0x2e4: /* PM_PWSTST_CORE */ 1380 case 0x320: /* CM_IDLEST_GFX */ 1381 case 0x3e4: /* PM_PWSTST_GFX */ 1382 case 0x420: /* CM_IDLEST_WKUP */ 1383 case 0x520: /* CM_IDLEST_CKGEN */ 1384 case 0x820: /* CM_IDLEST_DSP */ 1385 case 0x8e4: /* PM_PWSTST_DSP */ 1386 OMAP_RO_REG(addr); 1387 return; 1388 1389 case 0x010: /* PRCM_SYSCONFIG */ 1390 s->sysconfig = value & 1; 1391 break; 1392 1393 case 0x018: /* PRCM_IRQSTATUS_MPU */ 1394 s->irqst[0] &= ~value; 1395 omap_prcm_int_update(s, 0); 1396 break; 1397 case 0x01c: /* PRCM_IRQENABLE_MPU */ 1398 s->irqen[0] = value & 0x3f; 1399 omap_prcm_int_update(s, 0); 1400 break; 1401 1402 case 0x050: /* PRCM_VOLTCTRL */ 1403 s->voltctrl = value & 0xf1c3; 1404 break; 1405 1406 case 0x060: /* PRCM_CLKSRC_CTRL */ 1407 s->clksrc[0] = value & 0xdb; 1408 /* TODO update clocks */ 1409 break; 1410 1411 case 0x070: /* PRCM_CLKOUT_CTRL */ 1412 s->clkout[0] = value & 0xbbbb; 1413 /* TODO update clocks */ 1414 break; 1415 1416 case 0x078: /* PRCM_CLKEMUL_CTRL */ 1417 s->clkemul[0] = value & 1; 1418 /* TODO update clocks */ 1419 break; 1420 1421 case 0x080: /* PRCM_CLKCFG_CTRL */ 1422 break; 1423 1424 case 0x090: /* PRCM_VOLTSETUP */ 1425 s->setuptime[0] = value & 0xffff; 1426 break; 1427 case 0x094: /* PRCM_CLKSSETUP */ 1428 s->setuptime[1] = value & 0xffff; 1429 break; 1430 1431 case 0x098: /* PRCM_POLCTRL */ 1432 s->clkpol[0] = value & 0x701; 1433 break; 1434 1435 case 0x0b0: /* GENERAL_PURPOSE1 */ 1436 case 0x0b4: /* GENERAL_PURPOSE2 */ 1437 case 0x0b8: /* GENERAL_PURPOSE3 */ 1438 case 0x0bc: /* GENERAL_PURPOSE4 */ 1439 case 0x0c0: /* GENERAL_PURPOSE5 */ 1440 case 0x0c4: /* GENERAL_PURPOSE6 */ 1441 case 0x0c8: /* GENERAL_PURPOSE7 */ 1442 case 0x0cc: /* GENERAL_PURPOSE8 */ 1443 case 0x0d0: /* GENERAL_PURPOSE9 */ 1444 case 0x0d4: /* GENERAL_PURPOSE10 */ 1445 case 0x0d8: /* GENERAL_PURPOSE11 */ 1446 case 0x0dc: /* GENERAL_PURPOSE12 */ 1447 case 0x0e0: /* GENERAL_PURPOSE13 */ 1448 case 0x0e4: /* GENERAL_PURPOSE14 */ 1449 case 0x0e8: /* GENERAL_PURPOSE15 */ 1450 case 0x0ec: /* GENERAL_PURPOSE16 */ 1451 case 0x0f0: /* GENERAL_PURPOSE17 */ 1452 case 0x0f4: /* GENERAL_PURPOSE18 */ 1453 case 0x0f8: /* GENERAL_PURPOSE19 */ 1454 case 0x0fc: /* GENERAL_PURPOSE20 */ 1455 s->scratch[(addr - 0xb0) >> 2] = value; 1456 break; 1457 1458 case 0x140: /* CM_CLKSEL_MPU */ 1459 s->clksel[0] = value & 0x1f; 1460 /* TODO update clocks */ 1461 break; 1462 case 0x148: /* CM_CLKSTCTRL_MPU */ 1463 s->clkctrl[0] = value & 0x1f; 1464 break; 1465 1466 case 0x158: /* RM_RSTST_MPU */ 1467 s->rst[0] &= ~value; 1468 break; 1469 case 0x1c8: /* PM_WKDEP_MPU */ 1470 s->wkup[0] = value & 0x15; 1471 break; 1472 1473 case 0x1d4: /* PM_EVGENCTRL_MPU */ 1474 s->ev = value & 0x1f; 1475 break; 1476 case 0x1d8: /* PM_EVEGENONTIM_MPU */ 1477 s->evtime[0] = value; 1478 break; 1479 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */ 1480 s->evtime[1] = value; 1481 break; 1482 1483 case 0x1e0: /* PM_PWSTCTRL_MPU */ 1484 s->power[0] = value & 0xc0f; 1485 break; 1486 1487 case 0x200: /* CM_FCLKEN1_CORE */ 1488 s->clken[0] = value & 0xbfffffff; 1489 /* TODO update clocks */ 1490 /* The EN_EAC bit only gets/puts func_96m_clk. */ 1491 break; 1492 case 0x204: /* CM_FCLKEN2_CORE */ 1493 s->clken[1] = value & 0x00000007; 1494 /* TODO update clocks */ 1495 break; 1496 case 0x210: /* CM_ICLKEN1_CORE */ 1497 s->clken[2] = value & 0xfffffff9; 1498 /* TODO update clocks */ 1499 /* The EN_EAC bit only gets/puts core_l4_iclk. */ 1500 break; 1501 case 0x214: /* CM_ICLKEN2_CORE */ 1502 s->clken[3] = value & 0x00000007; 1503 /* TODO update clocks */ 1504 break; 1505 case 0x21c: /* CM_ICLKEN4_CORE */ 1506 s->clken[4] = value & 0x0000001f; 1507 /* TODO update clocks */ 1508 break; 1509 1510 case 0x230: /* CM_AUTOIDLE1_CORE */ 1511 s->clkidle[0] = value & 0xfffffff9; 1512 /* TODO update clocks */ 1513 break; 1514 case 0x234: /* CM_AUTOIDLE2_CORE */ 1515 s->clkidle[1] = value & 0x00000007; 1516 /* TODO update clocks */ 1517 break; 1518 case 0x238: /* CM_AUTOIDLE3_CORE */ 1519 s->clkidle[2] = value & 0x00000007; 1520 /* TODO update clocks */ 1521 break; 1522 case 0x23c: /* CM_AUTOIDLE4_CORE */ 1523 s->clkidle[3] = value & 0x0000001f; 1524 /* TODO update clocks */ 1525 break; 1526 1527 case 0x240: /* CM_CLKSEL1_CORE */ 1528 s->clksel[1] = value & 0x0fffbf7f; 1529 /* TODO update clocks */ 1530 break; 1531 1532 case 0x244: /* CM_CLKSEL2_CORE */ 1533 s->clksel[2] = value & 0x00fffffc; 1534 /* TODO update clocks */ 1535 break; 1536 1537 case 0x248: /* CM_CLKSTCTRL_CORE */ 1538 s->clkctrl[1] = value & 0x7; 1539 break; 1540 1541 case 0x2a0: /* PM_WKEN1_CORE */ 1542 s->wken[0] = value & 0x04667ff8; 1543 break; 1544 case 0x2a4: /* PM_WKEN2_CORE */ 1545 s->wken[1] = value & 0x00000005; 1546 break; 1547 1548 case 0x2b0: /* PM_WKST1_CORE */ 1549 s->wkst[0] &= ~value; 1550 break; 1551 case 0x2b4: /* PM_WKST2_CORE */ 1552 s->wkst[1] &= ~value; 1553 break; 1554 1555 case 0x2e0: /* PM_PWSTCTRL_CORE */ 1556 s->power[1] = (value & 0x00fc3f) | (1 << 2); 1557 break; 1558 1559 case 0x300: /* CM_FCLKEN_GFX */ 1560 s->clken[5] = value & 6; 1561 /* TODO update clocks */ 1562 break; 1563 case 0x310: /* CM_ICLKEN_GFX */ 1564 s->clken[6] = value & 1; 1565 /* TODO update clocks */ 1566 break; 1567 case 0x340: /* CM_CLKSEL_GFX */ 1568 s->clksel[3] = value & 7; 1569 /* TODO update clocks */ 1570 break; 1571 case 0x348: /* CM_CLKSTCTRL_GFX */ 1572 s->clkctrl[2] = value & 1; 1573 break; 1574 case 0x350: /* RM_RSTCTRL_GFX */ 1575 s->rstctrl[0] = value & 1; 1576 /* TODO: reset */ 1577 break; 1578 case 0x358: /* RM_RSTST_GFX */ 1579 s->rst[1] &= ~value; 1580 break; 1581 case 0x3c8: /* PM_WKDEP_GFX */ 1582 s->wkup[1] = value & 0x13; 1583 break; 1584 case 0x3e0: /* PM_PWSTCTRL_GFX */ 1585 s->power[2] = (value & 0x00c0f) | (3 << 2); 1586 break; 1587 1588 case 0x400: /* CM_FCLKEN_WKUP */ 1589 s->clken[7] = value & 0xd; 1590 /* TODO update clocks */ 1591 break; 1592 case 0x410: /* CM_ICLKEN_WKUP */ 1593 s->clken[8] = value & 0x3f; 1594 /* TODO update clocks */ 1595 break; 1596 case 0x430: /* CM_AUTOIDLE_WKUP */ 1597 s->clkidle[4] = value & 0x0000003f; 1598 /* TODO update clocks */ 1599 break; 1600 case 0x440: /* CM_CLKSEL_WKUP */ 1601 s->clksel[4] = value & 3; 1602 /* TODO update clocks */ 1603 break; 1604 case 0x450: /* RM_RSTCTRL_WKUP */ 1605 /* TODO: reset */ 1606 if (value & 2) 1607 qemu_system_reset_request(); 1608 break; 1609 case 0x454: /* RM_RSTTIME_WKUP */ 1610 s->rsttime_wkup = value & 0x1fff; 1611 break; 1612 case 0x458: /* RM_RSTST_WKUP */ 1613 s->rst[2] &= ~value; 1614 break; 1615 case 0x4a0: /* PM_WKEN_WKUP */ 1616 s->wken[2] = value & 0x00000005; 1617 break; 1618 case 0x4b0: /* PM_WKST_WKUP */ 1619 s->wkst[2] &= ~value; 1620 break; 1621 1622 case 0x500: /* CM_CLKEN_PLL */ 1623 if (value & 0xffffff30) 1624 fprintf(stderr, "%s: write 0s in CM_CLKEN_PLL for " 1625 "future compatibility\n", __FUNCTION__); 1626 if ((s->clken[9] ^ value) & 0xcc) { 1627 s->clken[9] &= ~0xcc; 1628 s->clken[9] |= value & 0xcc; 1629 omap_prcm_apll_update(s); 1630 } 1631 if ((s->clken[9] ^ value) & 3) { 1632 s->clken[9] &= ~3; 1633 s->clken[9] |= value & 3; 1634 omap_prcm_dpll_update(s); 1635 } 1636 break; 1637 case 0x530: /* CM_AUTOIDLE_PLL */ 1638 s->clkidle[5] = value & 0x000000cf; 1639 /* TODO update clocks */ 1640 break; 1641 case 0x540: /* CM_CLKSEL1_PLL */ 1642 if (value & 0xfc4000d7) 1643 fprintf(stderr, "%s: write 0s in CM_CLKSEL1_PLL for " 1644 "future compatibility\n", __FUNCTION__); 1645 if ((s->clksel[5] ^ value) & 0x003fff00) { 1646 s->clksel[5] = value & 0x03bfff28; 1647 omap_prcm_dpll_update(s); 1648 } 1649 /* TODO update the other clocks */ 1650 1651 s->clksel[5] = value & 0x03bfff28; 1652 break; 1653 case 0x544: /* CM_CLKSEL2_PLL */ 1654 if (value & ~3) 1655 fprintf(stderr, "%s: write 0s in CM_CLKSEL2_PLL[31:2] for " 1656 "future compatibility\n", __FUNCTION__); 1657 if (s->clksel[6] != (value & 3)) { 1658 s->clksel[6] = value & 3; 1659 omap_prcm_dpll_update(s); 1660 } 1661 break; 1662 1663 case 0x800: /* CM_FCLKEN_DSP */ 1664 s->clken[10] = value & 0x501; 1665 /* TODO update clocks */ 1666 break; 1667 case 0x810: /* CM_ICLKEN_DSP */ 1668 s->clken[11] = value & 0x2; 1669 /* TODO update clocks */ 1670 break; 1671 case 0x830: /* CM_AUTOIDLE_DSP */ 1672 s->clkidle[6] = value & 0x2; 1673 /* TODO update clocks */ 1674 break; 1675 case 0x840: /* CM_CLKSEL_DSP */ 1676 s->clksel[7] = value & 0x3fff; 1677 /* TODO update clocks */ 1678 break; 1679 case 0x848: /* CM_CLKSTCTRL_DSP */ 1680 s->clkctrl[3] = value & 0x101; 1681 break; 1682 case 0x850: /* RM_RSTCTRL_DSP */ 1683 /* TODO: reset */ 1684 break; 1685 case 0x858: /* RM_RSTST_DSP */ 1686 s->rst[3] &= ~value; 1687 break; 1688 case 0x8c8: /* PM_WKDEP_DSP */ 1689 s->wkup[2] = value & 0x13; 1690 break; 1691 case 0x8e0: /* PM_PWSTCTRL_DSP */ 1692 s->power[3] = (value & 0x03017) | (3 << 2); 1693 break; 1694 1695 case 0x8f0: /* PRCM_IRQSTATUS_DSP */ 1696 s->irqst[1] &= ~value; 1697 omap_prcm_int_update(s, 1); 1698 break; 1699 case 0x8f4: /* PRCM_IRQENABLE_DSP */ 1700 s->irqen[1] = value & 0x7; 1701 omap_prcm_int_update(s, 1); 1702 break; 1703 1704 case 0x8f8: /* PRCM_IRQSTATUS_IVA */ 1705 s->irqst[2] &= ~value; 1706 omap_prcm_int_update(s, 2); 1707 break; 1708 case 0x8fc: /* PRCM_IRQENABLE_IVA */ 1709 s->irqen[2] = value & 0x7; 1710 omap_prcm_int_update(s, 2); 1711 break; 1712 1713 default: 1714 OMAP_BAD_REG(addr); 1715 return; 1716 } 1717 } 1718 1719 static const MemoryRegionOps omap_prcm_ops = { 1720 .read = omap_prcm_read, 1721 .write = omap_prcm_write, 1722 .endianness = DEVICE_NATIVE_ENDIAN, 1723 }; 1724 1725 static void omap_prcm_reset(struct omap_prcm_s *s) 1726 { 1727 s->sysconfig = 0; 1728 s->irqst[0] = 0; 1729 s->irqst[1] = 0; 1730 s->irqst[2] = 0; 1731 s->irqen[0] = 0; 1732 s->irqen[1] = 0; 1733 s->irqen[2] = 0; 1734 s->voltctrl = 0x1040; 1735 s->ev = 0x14; 1736 s->evtime[0] = 0; 1737 s->evtime[1] = 0; 1738 s->clkctrl[0] = 0; 1739 s->clkctrl[1] = 0; 1740 s->clkctrl[2] = 0; 1741 s->clkctrl[3] = 0; 1742 s->clken[1] = 7; 1743 s->clken[3] = 7; 1744 s->clken[4] = 0; 1745 s->clken[5] = 0; 1746 s->clken[6] = 0; 1747 s->clken[7] = 0xc; 1748 s->clken[8] = 0x3e; 1749 s->clken[9] = 0x0d; 1750 s->clken[10] = 0; 1751 s->clken[11] = 0; 1752 s->clkidle[0] = 0; 1753 s->clkidle[2] = 7; 1754 s->clkidle[3] = 0; 1755 s->clkidle[4] = 0; 1756 s->clkidle[5] = 0x0c; 1757 s->clkidle[6] = 0; 1758 s->clksel[0] = 0x01; 1759 s->clksel[1] = 0x02100121; 1760 s->clksel[2] = 0x00000000; 1761 s->clksel[3] = 0x01; 1762 s->clksel[4] = 0; 1763 s->clksel[7] = 0x0121; 1764 s->wkup[0] = 0x15; 1765 s->wkup[1] = 0x13; 1766 s->wkup[2] = 0x13; 1767 s->wken[0] = 0x04667ff8; 1768 s->wken[1] = 0x00000005; 1769 s->wken[2] = 5; 1770 s->wkst[0] = 0; 1771 s->wkst[1] = 0; 1772 s->wkst[2] = 0; 1773 s->power[0] = 0x00c; 1774 s->power[1] = 4; 1775 s->power[2] = 0x0000c; 1776 s->power[3] = 0x14; 1777 s->rstctrl[0] = 1; 1778 s->rst[3] = 1; 1779 omap_prcm_apll_update(s); 1780 omap_prcm_dpll_update(s); 1781 } 1782 1783 static void omap_prcm_coldreset(struct omap_prcm_s *s) 1784 { 1785 s->setuptime[0] = 0; 1786 s->setuptime[1] = 0; 1787 memset(&s->scratch, 0, sizeof(s->scratch)); 1788 s->rst[0] = 0x01; 1789 s->rst[1] = 0x00; 1790 s->rst[2] = 0x01; 1791 s->clken[0] = 0; 1792 s->clken[2] = 0; 1793 s->clkidle[1] = 0; 1794 s->clksel[5] = 0; 1795 s->clksel[6] = 2; 1796 s->clksrc[0] = 0x43; 1797 s->clkout[0] = 0x0303; 1798 s->clkemul[0] = 0; 1799 s->clkpol[0] = 0x100; 1800 s->rsttime_wkup = 0x1002; 1801 1802 omap_prcm_reset(s); 1803 } 1804 1805 static struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta, 1806 qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int, 1807 struct omap_mpu_state_s *mpu) 1808 { 1809 struct omap_prcm_s *s = g_new0(struct omap_prcm_s, 1); 1810 1811 s->irq[0] = mpu_int; 1812 s->irq[1] = dsp_int; 1813 s->irq[2] = iva_int; 1814 s->mpu = mpu; 1815 omap_prcm_coldreset(s); 1816 1817 memory_region_init_io(&s->iomem0, NULL, &omap_prcm_ops, s, "omap.pcrm0", 1818 omap_l4_region_size(ta, 0)); 1819 memory_region_init_io(&s->iomem1, NULL, &omap_prcm_ops, s, "omap.pcrm1", 1820 omap_l4_region_size(ta, 1)); 1821 omap_l4_attach(ta, 0, &s->iomem0); 1822 omap_l4_attach(ta, 1, &s->iomem1); 1823 1824 return s; 1825 } 1826 1827 /* System and Pinout control */ 1828 struct omap_sysctl_s { 1829 struct omap_mpu_state_s *mpu; 1830 MemoryRegion iomem; 1831 1832 uint32_t sysconfig; 1833 uint32_t devconfig; 1834 uint32_t psaconfig; 1835 uint32_t padconf[0x45]; 1836 uint8_t obs; 1837 uint32_t msuspendmux[5]; 1838 }; 1839 1840 static uint32_t omap_sysctl_read8(void *opaque, hwaddr addr) 1841 { 1842 1843 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; 1844 int pad_offset, byte_offset; 1845 int value; 1846 1847 switch (addr) { 1848 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */ 1849 pad_offset = (addr - 0x30) >> 2; 1850 byte_offset = (addr - 0x30) & (4 - 1); 1851 1852 value = s->padconf[pad_offset]; 1853 value = (value >> (byte_offset * 8)) & 0xff; 1854 1855 return value; 1856 1857 default: 1858 break; 1859 } 1860 1861 OMAP_BAD_REG(addr); 1862 return 0; 1863 } 1864 1865 static uint32_t omap_sysctl_read(void *opaque, hwaddr addr) 1866 { 1867 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; 1868 1869 switch (addr) { 1870 case 0x000: /* CONTROL_REVISION */ 1871 return 0x20; 1872 1873 case 0x010: /* CONTROL_SYSCONFIG */ 1874 return s->sysconfig; 1875 1876 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */ 1877 return s->padconf[(addr - 0x30) >> 2]; 1878 1879 case 0x270: /* CONTROL_DEBOBS */ 1880 return s->obs; 1881 1882 case 0x274: /* CONTROL_DEVCONF */ 1883 return s->devconfig; 1884 1885 case 0x28c: /* CONTROL_EMU_SUPPORT */ 1886 return 0; 1887 1888 case 0x290: /* CONTROL_MSUSPENDMUX_0 */ 1889 return s->msuspendmux[0]; 1890 case 0x294: /* CONTROL_MSUSPENDMUX_1 */ 1891 return s->msuspendmux[1]; 1892 case 0x298: /* CONTROL_MSUSPENDMUX_2 */ 1893 return s->msuspendmux[2]; 1894 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */ 1895 return s->msuspendmux[3]; 1896 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */ 1897 return s->msuspendmux[4]; 1898 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */ 1899 return 0; 1900 1901 case 0x2b8: /* CONTROL_PSA_CTRL */ 1902 return s->psaconfig; 1903 case 0x2bc: /* CONTROL_PSA_CMD */ 1904 case 0x2c0: /* CONTROL_PSA_VALUE */ 1905 return 0; 1906 1907 case 0x2b0: /* CONTROL_SEC_CTRL */ 1908 return 0x800000f1; 1909 case 0x2d0: /* CONTROL_SEC_EMU */ 1910 return 0x80000015; 1911 case 0x2d4: /* CONTROL_SEC_TAP */ 1912 return 0x8000007f; 1913 case 0x2b4: /* CONTROL_SEC_TEST */ 1914 case 0x2f0: /* CONTROL_SEC_STATUS */ 1915 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */ 1916 /* Secure mode is not present on general-pusrpose device. Outside 1917 * secure mode these values cannot be read or written. */ 1918 return 0; 1919 1920 case 0x2d8: /* CONTROL_OCM_RAM_PERM */ 1921 return 0xff; 1922 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */ 1923 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */ 1924 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */ 1925 /* No secure mode so no Extended Secure RAM present. */ 1926 return 0; 1927 1928 case 0x2f8: /* CONTROL_STATUS */ 1929 /* Device Type => General-purpose */ 1930 return 0x0300; 1931 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */ 1932 1933 case 0x300: /* CONTROL_RPUB_KEY_H_0 */ 1934 case 0x304: /* CONTROL_RPUB_KEY_H_1 */ 1935 case 0x308: /* CONTROL_RPUB_KEY_H_2 */ 1936 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */ 1937 return 0xdecafbad; 1938 1939 case 0x310: /* CONTROL_RAND_KEY_0 */ 1940 case 0x314: /* CONTROL_RAND_KEY_1 */ 1941 case 0x318: /* CONTROL_RAND_KEY_2 */ 1942 case 0x31c: /* CONTROL_RAND_KEY_3 */ 1943 case 0x320: /* CONTROL_CUST_KEY_0 */ 1944 case 0x324: /* CONTROL_CUST_KEY_1 */ 1945 case 0x330: /* CONTROL_TEST_KEY_0 */ 1946 case 0x334: /* CONTROL_TEST_KEY_1 */ 1947 case 0x338: /* CONTROL_TEST_KEY_2 */ 1948 case 0x33c: /* CONTROL_TEST_KEY_3 */ 1949 case 0x340: /* CONTROL_TEST_KEY_4 */ 1950 case 0x344: /* CONTROL_TEST_KEY_5 */ 1951 case 0x348: /* CONTROL_TEST_KEY_6 */ 1952 case 0x34c: /* CONTROL_TEST_KEY_7 */ 1953 case 0x350: /* CONTROL_TEST_KEY_8 */ 1954 case 0x354: /* CONTROL_TEST_KEY_9 */ 1955 /* Can only be accessed in secure mode and when C_FieldAccEnable 1956 * bit is set in CONTROL_SEC_CTRL. 1957 * TODO: otherwise an interconnect access error is generated. */ 1958 return 0; 1959 } 1960 1961 OMAP_BAD_REG(addr); 1962 return 0; 1963 } 1964 1965 static void omap_sysctl_write8(void *opaque, hwaddr addr, 1966 uint32_t value) 1967 { 1968 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; 1969 int pad_offset, byte_offset; 1970 int prev_value; 1971 1972 switch (addr) { 1973 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */ 1974 pad_offset = (addr - 0x30) >> 2; 1975 byte_offset = (addr - 0x30) & (4 - 1); 1976 1977 prev_value = s->padconf[pad_offset]; 1978 prev_value &= ~(0xff << (byte_offset * 8)); 1979 prev_value |= ((value & 0x1f1f1f1f) << (byte_offset * 8)) & 0x1f1f1f1f; 1980 s->padconf[pad_offset] = prev_value; 1981 break; 1982 1983 default: 1984 OMAP_BAD_REG(addr); 1985 break; 1986 } 1987 } 1988 1989 static void omap_sysctl_write(void *opaque, hwaddr addr, 1990 uint32_t value) 1991 { 1992 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; 1993 1994 switch (addr) { 1995 case 0x000: /* CONTROL_REVISION */ 1996 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */ 1997 case 0x2c0: /* CONTROL_PSA_VALUE */ 1998 case 0x2f8: /* CONTROL_STATUS */ 1999 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */ 2000 case 0x300: /* CONTROL_RPUB_KEY_H_0 */ 2001 case 0x304: /* CONTROL_RPUB_KEY_H_1 */ 2002 case 0x308: /* CONTROL_RPUB_KEY_H_2 */ 2003 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */ 2004 case 0x310: /* CONTROL_RAND_KEY_0 */ 2005 case 0x314: /* CONTROL_RAND_KEY_1 */ 2006 case 0x318: /* CONTROL_RAND_KEY_2 */ 2007 case 0x31c: /* CONTROL_RAND_KEY_3 */ 2008 case 0x320: /* CONTROL_CUST_KEY_0 */ 2009 case 0x324: /* CONTROL_CUST_KEY_1 */ 2010 case 0x330: /* CONTROL_TEST_KEY_0 */ 2011 case 0x334: /* CONTROL_TEST_KEY_1 */ 2012 case 0x338: /* CONTROL_TEST_KEY_2 */ 2013 case 0x33c: /* CONTROL_TEST_KEY_3 */ 2014 case 0x340: /* CONTROL_TEST_KEY_4 */ 2015 case 0x344: /* CONTROL_TEST_KEY_5 */ 2016 case 0x348: /* CONTROL_TEST_KEY_6 */ 2017 case 0x34c: /* CONTROL_TEST_KEY_7 */ 2018 case 0x350: /* CONTROL_TEST_KEY_8 */ 2019 case 0x354: /* CONTROL_TEST_KEY_9 */ 2020 OMAP_RO_REG(addr); 2021 return; 2022 2023 case 0x010: /* CONTROL_SYSCONFIG */ 2024 s->sysconfig = value & 0x1e; 2025 break; 2026 2027 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */ 2028 /* XXX: should check constant bits */ 2029 s->padconf[(addr - 0x30) >> 2] = value & 0x1f1f1f1f; 2030 break; 2031 2032 case 0x270: /* CONTROL_DEBOBS */ 2033 s->obs = value & 0xff; 2034 break; 2035 2036 case 0x274: /* CONTROL_DEVCONF */ 2037 s->devconfig = value & 0xffffc7ff; 2038 break; 2039 2040 case 0x28c: /* CONTROL_EMU_SUPPORT */ 2041 break; 2042 2043 case 0x290: /* CONTROL_MSUSPENDMUX_0 */ 2044 s->msuspendmux[0] = value & 0x3fffffff; 2045 break; 2046 case 0x294: /* CONTROL_MSUSPENDMUX_1 */ 2047 s->msuspendmux[1] = value & 0x3fffffff; 2048 break; 2049 case 0x298: /* CONTROL_MSUSPENDMUX_2 */ 2050 s->msuspendmux[2] = value & 0x3fffffff; 2051 break; 2052 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */ 2053 s->msuspendmux[3] = value & 0x3fffffff; 2054 break; 2055 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */ 2056 s->msuspendmux[4] = value & 0x3fffffff; 2057 break; 2058 2059 case 0x2b8: /* CONTROL_PSA_CTRL */ 2060 s->psaconfig = value & 0x1c; 2061 s->psaconfig |= (value & 0x20) ? 2 : 1; 2062 break; 2063 case 0x2bc: /* CONTROL_PSA_CMD */ 2064 break; 2065 2066 case 0x2b0: /* CONTROL_SEC_CTRL */ 2067 case 0x2b4: /* CONTROL_SEC_TEST */ 2068 case 0x2d0: /* CONTROL_SEC_EMU */ 2069 case 0x2d4: /* CONTROL_SEC_TAP */ 2070 case 0x2d8: /* CONTROL_OCM_RAM_PERM */ 2071 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */ 2072 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */ 2073 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */ 2074 case 0x2f0: /* CONTROL_SEC_STATUS */ 2075 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */ 2076 break; 2077 2078 default: 2079 OMAP_BAD_REG(addr); 2080 return; 2081 } 2082 } 2083 2084 static const MemoryRegionOps omap_sysctl_ops = { 2085 .old_mmio = { 2086 .read = { 2087 omap_sysctl_read8, 2088 omap_badwidth_read32, /* TODO */ 2089 omap_sysctl_read, 2090 }, 2091 .write = { 2092 omap_sysctl_write8, 2093 omap_badwidth_write32, /* TODO */ 2094 omap_sysctl_write, 2095 }, 2096 }, 2097 .endianness = DEVICE_NATIVE_ENDIAN, 2098 }; 2099 2100 static void omap_sysctl_reset(struct omap_sysctl_s *s) 2101 { 2102 /* (power-on reset) */ 2103 s->sysconfig = 0; 2104 s->obs = 0; 2105 s->devconfig = 0x0c000000; 2106 s->msuspendmux[0] = 0x00000000; 2107 s->msuspendmux[1] = 0x00000000; 2108 s->msuspendmux[2] = 0x00000000; 2109 s->msuspendmux[3] = 0x00000000; 2110 s->msuspendmux[4] = 0x00000000; 2111 s->psaconfig = 1; 2112 2113 s->padconf[0x00] = 0x000f0f0f; 2114 s->padconf[0x01] = 0x00000000; 2115 s->padconf[0x02] = 0x00000000; 2116 s->padconf[0x03] = 0x00000000; 2117 s->padconf[0x04] = 0x00000000; 2118 s->padconf[0x05] = 0x00000000; 2119 s->padconf[0x06] = 0x00000000; 2120 s->padconf[0x07] = 0x00000000; 2121 s->padconf[0x08] = 0x08080800; 2122 s->padconf[0x09] = 0x08080808; 2123 s->padconf[0x0a] = 0x08080808; 2124 s->padconf[0x0b] = 0x08080808; 2125 s->padconf[0x0c] = 0x08080808; 2126 s->padconf[0x0d] = 0x08080800; 2127 s->padconf[0x0e] = 0x08080808; 2128 s->padconf[0x0f] = 0x08080808; 2129 s->padconf[0x10] = 0x18181808; /* | 0x07070700 if SBoot3 */ 2130 s->padconf[0x11] = 0x18181818; /* | 0x07070707 if SBoot3 */ 2131 s->padconf[0x12] = 0x18181818; /* | 0x07070707 if SBoot3 */ 2132 s->padconf[0x13] = 0x18181818; /* | 0x07070707 if SBoot3 */ 2133 s->padconf[0x14] = 0x18181818; /* | 0x00070707 if SBoot3 */ 2134 s->padconf[0x15] = 0x18181818; 2135 s->padconf[0x16] = 0x18181818; /* | 0x07000000 if SBoot3 */ 2136 s->padconf[0x17] = 0x1f001f00; 2137 s->padconf[0x18] = 0x1f1f1f1f; 2138 s->padconf[0x19] = 0x00000000; 2139 s->padconf[0x1a] = 0x1f180000; 2140 s->padconf[0x1b] = 0x00001f1f; 2141 s->padconf[0x1c] = 0x1f001f00; 2142 s->padconf[0x1d] = 0x00000000; 2143 s->padconf[0x1e] = 0x00000000; 2144 s->padconf[0x1f] = 0x08000000; 2145 s->padconf[0x20] = 0x08080808; 2146 s->padconf[0x21] = 0x08080808; 2147 s->padconf[0x22] = 0x0f080808; 2148 s->padconf[0x23] = 0x0f0f0f0f; 2149 s->padconf[0x24] = 0x000f0f0f; 2150 s->padconf[0x25] = 0x1f1f1f0f; 2151 s->padconf[0x26] = 0x080f0f1f; 2152 s->padconf[0x27] = 0x070f1808; 2153 s->padconf[0x28] = 0x0f070707; 2154 s->padconf[0x29] = 0x000f0f1f; 2155 s->padconf[0x2a] = 0x0f0f0f1f; 2156 s->padconf[0x2b] = 0x08000000; 2157 s->padconf[0x2c] = 0x0000001f; 2158 s->padconf[0x2d] = 0x0f0f1f00; 2159 s->padconf[0x2e] = 0x1f1f0f0f; 2160 s->padconf[0x2f] = 0x0f1f1f1f; 2161 s->padconf[0x30] = 0x0f0f0f0f; 2162 s->padconf[0x31] = 0x0f1f0f1f; 2163 s->padconf[0x32] = 0x0f0f0f0f; 2164 s->padconf[0x33] = 0x0f1f0f1f; 2165 s->padconf[0x34] = 0x1f1f0f0f; 2166 s->padconf[0x35] = 0x0f0f1f1f; 2167 s->padconf[0x36] = 0x0f0f1f0f; 2168 s->padconf[0x37] = 0x0f0f0f0f; 2169 s->padconf[0x38] = 0x1f18180f; 2170 s->padconf[0x39] = 0x1f1f1f1f; 2171 s->padconf[0x3a] = 0x00001f1f; 2172 s->padconf[0x3b] = 0x00000000; 2173 s->padconf[0x3c] = 0x00000000; 2174 s->padconf[0x3d] = 0x0f0f0f0f; 2175 s->padconf[0x3e] = 0x18000f0f; 2176 s->padconf[0x3f] = 0x00070000; 2177 s->padconf[0x40] = 0x00000707; 2178 s->padconf[0x41] = 0x0f1f0700; 2179 s->padconf[0x42] = 0x1f1f070f; 2180 s->padconf[0x43] = 0x0008081f; 2181 s->padconf[0x44] = 0x00000800; 2182 } 2183 2184 static struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta, 2185 omap_clk iclk, struct omap_mpu_state_s *mpu) 2186 { 2187 struct omap_sysctl_s *s = g_new0(struct omap_sysctl_s, 1); 2188 2189 s->mpu = mpu; 2190 omap_sysctl_reset(s); 2191 2192 memory_region_init_io(&s->iomem, NULL, &omap_sysctl_ops, s, "omap.sysctl", 2193 omap_l4_region_size(ta, 0)); 2194 omap_l4_attach(ta, 0, &s->iomem); 2195 2196 return s; 2197 } 2198 2199 /* General chip reset */ 2200 static void omap2_mpu_reset(void *opaque) 2201 { 2202 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; 2203 2204 omap_dma_reset(mpu->dma); 2205 omap_prcm_reset(mpu->prcm); 2206 omap_sysctl_reset(mpu->sysc); 2207 omap_gp_timer_reset(mpu->gptimer[0]); 2208 omap_gp_timer_reset(mpu->gptimer[1]); 2209 omap_gp_timer_reset(mpu->gptimer[2]); 2210 omap_gp_timer_reset(mpu->gptimer[3]); 2211 omap_gp_timer_reset(mpu->gptimer[4]); 2212 omap_gp_timer_reset(mpu->gptimer[5]); 2213 omap_gp_timer_reset(mpu->gptimer[6]); 2214 omap_gp_timer_reset(mpu->gptimer[7]); 2215 omap_gp_timer_reset(mpu->gptimer[8]); 2216 omap_gp_timer_reset(mpu->gptimer[9]); 2217 omap_gp_timer_reset(mpu->gptimer[10]); 2218 omap_gp_timer_reset(mpu->gptimer[11]); 2219 omap_synctimer_reset(mpu->synctimer); 2220 omap_sdrc_reset(mpu->sdrc); 2221 omap_gpmc_reset(mpu->gpmc); 2222 omap_dss_reset(mpu->dss); 2223 omap_uart_reset(mpu->uart[0]); 2224 omap_uart_reset(mpu->uart[1]); 2225 omap_uart_reset(mpu->uart[2]); 2226 omap_mmc_reset(mpu->mmc); 2227 omap_mcspi_reset(mpu->mcspi[0]); 2228 omap_mcspi_reset(mpu->mcspi[1]); 2229 cpu_reset(CPU(mpu->cpu)); 2230 } 2231 2232 static int omap2_validate_addr(struct omap_mpu_state_s *s, 2233 hwaddr addr) 2234 { 2235 return 1; 2236 } 2237 2238 static const struct dma_irq_map omap2_dma_irq_map[] = { 2239 { 0, OMAP_INT_24XX_SDMA_IRQ0 }, 2240 { 0, OMAP_INT_24XX_SDMA_IRQ1 }, 2241 { 0, OMAP_INT_24XX_SDMA_IRQ2 }, 2242 { 0, OMAP_INT_24XX_SDMA_IRQ3 }, 2243 }; 2244 2245 struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem, 2246 unsigned long sdram_size, 2247 const char *core) 2248 { 2249 struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1); 2250 qemu_irq dma_irqs[4]; 2251 DriveInfo *dinfo; 2252 int i; 2253 SysBusDevice *busdev; 2254 struct omap_target_agent_s *ta; 2255 2256 /* Core */ 2257 s->mpu_model = omap2420; 2258 s->cpu = cpu_arm_init(core ?: "arm1136-r2"); 2259 if (s->cpu == NULL) { 2260 fprintf(stderr, "Unable to find CPU definition\n"); 2261 exit(1); 2262 } 2263 s->sdram_size = sdram_size; 2264 s->sram_size = OMAP242X_SRAM_SIZE; 2265 2266 s->wakeup = qemu_allocate_irq(omap_mpu_wakeup, s, 0); 2267 2268 /* Clocks */ 2269 omap_clk_init(s); 2270 2271 /* Memory-mapped stuff */ 2272 memory_region_allocate_system_memory(&s->sdram, NULL, "omap2.dram", 2273 s->sdram_size); 2274 memory_region_add_subregion(sysmem, OMAP2_Q2_BASE, &s->sdram); 2275 memory_region_init_ram(&s->sram, NULL, "omap2.sram", s->sram_size, 2276 &error_fatal); 2277 vmstate_register_ram_global(&s->sram); 2278 memory_region_add_subregion(sysmem, OMAP2_SRAM_BASE, &s->sram); 2279 2280 s->l4 = omap_l4_init(sysmem, OMAP2_L4_BASE, 54); 2281 2282 /* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */ 2283 s->ih[0] = qdev_create(NULL, "omap2-intc"); 2284 qdev_prop_set_uint8(s->ih[0], "revision", 0x21); 2285 qdev_prop_set_ptr(s->ih[0], "fclk", omap_findclk(s, "mpu_intc_fclk")); 2286 qdev_prop_set_ptr(s->ih[0], "iclk", omap_findclk(s, "mpu_intc_iclk")); 2287 qdev_init_nofail(s->ih[0]); 2288 busdev = SYS_BUS_DEVICE(s->ih[0]); 2289 sysbus_connect_irq(busdev, 0, 2290 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ)); 2291 sysbus_connect_irq(busdev, 1, 2292 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ)); 2293 sysbus_mmio_map(busdev, 0, 0x480fe000); 2294 s->prcm = omap_prcm_init(omap_l4tao(s->l4, 3), 2295 qdev_get_gpio_in(s->ih[0], 2296 OMAP_INT_24XX_PRCM_MPU_IRQ), 2297 NULL, NULL, s); 2298 2299 s->sysc = omap_sysctl_init(omap_l4tao(s->l4, 1), 2300 omap_findclk(s, "omapctrl_iclk"), s); 2301 2302 for (i = 0; i < 4; i++) { 2303 dma_irqs[i] = qdev_get_gpio_in(s->ih[omap2_dma_irq_map[i].ih], 2304 omap2_dma_irq_map[i].intr); 2305 } 2306 s->dma = omap_dma4_init(0x48056000, dma_irqs, sysmem, s, 256, 32, 2307 omap_findclk(s, "sdma_iclk"), 2308 omap_findclk(s, "sdma_fclk")); 2309 s->port->addr_valid = omap2_validate_addr; 2310 2311 /* Register SDRAM and SRAM ports for fast DMA transfers. */ 2312 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->sdram), 2313 OMAP2_Q2_BASE, s->sdram_size); 2314 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->sram), 2315 OMAP2_SRAM_BASE, s->sram_size); 2316 2317 s->uart[0] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 19), 2318 qdev_get_gpio_in(s->ih[0], 2319 OMAP_INT_24XX_UART1_IRQ), 2320 omap_findclk(s, "uart1_fclk"), 2321 omap_findclk(s, "uart1_iclk"), 2322 s->drq[OMAP24XX_DMA_UART1_TX], 2323 s->drq[OMAP24XX_DMA_UART1_RX], 2324 "uart1", 2325 serial_hds[0]); 2326 s->uart[1] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 20), 2327 qdev_get_gpio_in(s->ih[0], 2328 OMAP_INT_24XX_UART2_IRQ), 2329 omap_findclk(s, "uart2_fclk"), 2330 omap_findclk(s, "uart2_iclk"), 2331 s->drq[OMAP24XX_DMA_UART2_TX], 2332 s->drq[OMAP24XX_DMA_UART2_RX], 2333 "uart2", 2334 serial_hds[0] ? serial_hds[1] : NULL); 2335 s->uart[2] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 21), 2336 qdev_get_gpio_in(s->ih[0], 2337 OMAP_INT_24XX_UART3_IRQ), 2338 omap_findclk(s, "uart3_fclk"), 2339 omap_findclk(s, "uart3_iclk"), 2340 s->drq[OMAP24XX_DMA_UART3_TX], 2341 s->drq[OMAP24XX_DMA_UART3_RX], 2342 "uart3", 2343 serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL); 2344 2345 s->gptimer[0] = omap_gp_timer_init(omap_l4ta(s->l4, 7), 2346 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER1), 2347 omap_findclk(s, "wu_gpt1_clk"), 2348 omap_findclk(s, "wu_l4_iclk")); 2349 s->gptimer[1] = omap_gp_timer_init(omap_l4ta(s->l4, 8), 2350 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER2), 2351 omap_findclk(s, "core_gpt2_clk"), 2352 omap_findclk(s, "core_l4_iclk")); 2353 s->gptimer[2] = omap_gp_timer_init(omap_l4ta(s->l4, 22), 2354 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER3), 2355 omap_findclk(s, "core_gpt3_clk"), 2356 omap_findclk(s, "core_l4_iclk")); 2357 s->gptimer[3] = omap_gp_timer_init(omap_l4ta(s->l4, 23), 2358 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER4), 2359 omap_findclk(s, "core_gpt4_clk"), 2360 omap_findclk(s, "core_l4_iclk")); 2361 s->gptimer[4] = omap_gp_timer_init(omap_l4ta(s->l4, 24), 2362 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER5), 2363 omap_findclk(s, "core_gpt5_clk"), 2364 omap_findclk(s, "core_l4_iclk")); 2365 s->gptimer[5] = omap_gp_timer_init(omap_l4ta(s->l4, 25), 2366 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER6), 2367 omap_findclk(s, "core_gpt6_clk"), 2368 omap_findclk(s, "core_l4_iclk")); 2369 s->gptimer[6] = omap_gp_timer_init(omap_l4ta(s->l4, 26), 2370 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER7), 2371 omap_findclk(s, "core_gpt7_clk"), 2372 omap_findclk(s, "core_l4_iclk")); 2373 s->gptimer[7] = omap_gp_timer_init(omap_l4ta(s->l4, 27), 2374 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER8), 2375 omap_findclk(s, "core_gpt8_clk"), 2376 omap_findclk(s, "core_l4_iclk")); 2377 s->gptimer[8] = omap_gp_timer_init(omap_l4ta(s->l4, 28), 2378 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER9), 2379 omap_findclk(s, "core_gpt9_clk"), 2380 omap_findclk(s, "core_l4_iclk")); 2381 s->gptimer[9] = omap_gp_timer_init(omap_l4ta(s->l4, 29), 2382 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER10), 2383 omap_findclk(s, "core_gpt10_clk"), 2384 omap_findclk(s, "core_l4_iclk")); 2385 s->gptimer[10] = omap_gp_timer_init(omap_l4ta(s->l4, 30), 2386 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER11), 2387 omap_findclk(s, "core_gpt11_clk"), 2388 omap_findclk(s, "core_l4_iclk")); 2389 s->gptimer[11] = omap_gp_timer_init(omap_l4ta(s->l4, 31), 2390 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER12), 2391 omap_findclk(s, "core_gpt12_clk"), 2392 omap_findclk(s, "core_l4_iclk")); 2393 2394 omap_tap_init(omap_l4ta(s->l4, 2), s); 2395 2396 s->synctimer = omap_synctimer_init(omap_l4tao(s->l4, 2), s, 2397 omap_findclk(s, "clk32-kHz"), 2398 omap_findclk(s, "core_l4_iclk")); 2399 2400 s->i2c[0] = qdev_create(NULL, "omap_i2c"); 2401 qdev_prop_set_uint8(s->i2c[0], "revision", 0x34); 2402 qdev_prop_set_ptr(s->i2c[0], "iclk", omap_findclk(s, "i2c1.iclk")); 2403 qdev_prop_set_ptr(s->i2c[0], "fclk", omap_findclk(s, "i2c1.fclk")); 2404 qdev_init_nofail(s->i2c[0]); 2405 busdev = SYS_BUS_DEVICE(s->i2c[0]); 2406 sysbus_connect_irq(busdev, 0, 2407 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C1_IRQ)); 2408 sysbus_connect_irq(busdev, 1, s->drq[OMAP24XX_DMA_I2C1_TX]); 2409 sysbus_connect_irq(busdev, 2, s->drq[OMAP24XX_DMA_I2C1_RX]); 2410 sysbus_mmio_map(busdev, 0, omap_l4_region_base(omap_l4tao(s->l4, 5), 0)); 2411 2412 s->i2c[1] = qdev_create(NULL, "omap_i2c"); 2413 qdev_prop_set_uint8(s->i2c[1], "revision", 0x34); 2414 qdev_prop_set_ptr(s->i2c[1], "iclk", omap_findclk(s, "i2c2.iclk")); 2415 qdev_prop_set_ptr(s->i2c[1], "fclk", omap_findclk(s, "i2c2.fclk")); 2416 qdev_init_nofail(s->i2c[1]); 2417 busdev = SYS_BUS_DEVICE(s->i2c[1]); 2418 sysbus_connect_irq(busdev, 0, 2419 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C2_IRQ)); 2420 sysbus_connect_irq(busdev, 1, s->drq[OMAP24XX_DMA_I2C2_TX]); 2421 sysbus_connect_irq(busdev, 2, s->drq[OMAP24XX_DMA_I2C2_RX]); 2422 sysbus_mmio_map(busdev, 0, omap_l4_region_base(omap_l4tao(s->l4, 6), 0)); 2423 2424 s->gpio = qdev_create(NULL, "omap2-gpio"); 2425 qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model); 2426 qdev_prop_set_ptr(s->gpio, "iclk", omap_findclk(s, "gpio_iclk")); 2427 qdev_prop_set_ptr(s->gpio, "fclk0", omap_findclk(s, "gpio1_dbclk")); 2428 qdev_prop_set_ptr(s->gpio, "fclk1", omap_findclk(s, "gpio2_dbclk")); 2429 qdev_prop_set_ptr(s->gpio, "fclk2", omap_findclk(s, "gpio3_dbclk")); 2430 qdev_prop_set_ptr(s->gpio, "fclk3", omap_findclk(s, "gpio4_dbclk")); 2431 if (s->mpu_model == omap2430) { 2432 qdev_prop_set_ptr(s->gpio, "fclk4", omap_findclk(s, "gpio5_dbclk")); 2433 } 2434 qdev_init_nofail(s->gpio); 2435 busdev = SYS_BUS_DEVICE(s->gpio); 2436 sysbus_connect_irq(busdev, 0, 2437 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK1)); 2438 sysbus_connect_irq(busdev, 3, 2439 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK2)); 2440 sysbus_connect_irq(busdev, 6, 2441 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK3)); 2442 sysbus_connect_irq(busdev, 9, 2443 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK4)); 2444 if (s->mpu_model == omap2430) { 2445 sysbus_connect_irq(busdev, 12, 2446 qdev_get_gpio_in(s->ih[0], 2447 OMAP_INT_243X_GPIO_BANK5)); 2448 } 2449 ta = omap_l4ta(s->l4, 3); 2450 sysbus_mmio_map(busdev, 0, omap_l4_region_base(ta, 1)); 2451 sysbus_mmio_map(busdev, 1, omap_l4_region_base(ta, 0)); 2452 sysbus_mmio_map(busdev, 2, omap_l4_region_base(ta, 2)); 2453 sysbus_mmio_map(busdev, 3, omap_l4_region_base(ta, 4)); 2454 sysbus_mmio_map(busdev, 4, omap_l4_region_base(ta, 5)); 2455 2456 s->sdrc = omap_sdrc_init(sysmem, 0x68009000); 2457 s->gpmc = omap_gpmc_init(s, 0x6800a000, 2458 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPMC_IRQ), 2459 s->drq[OMAP24XX_DMA_GPMC]); 2460 2461 dinfo = drive_get(IF_SD, 0, 0); 2462 if (!dinfo) { 2463 fprintf(stderr, "qemu: missing SecureDigital device\n"); 2464 exit(1); 2465 } 2466 s->mmc = omap2_mmc_init(omap_l4tao(s->l4, 9), 2467 blk_by_legacy_dinfo(dinfo), 2468 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MMC_IRQ), 2469 &s->drq[OMAP24XX_DMA_MMC1_TX], 2470 omap_findclk(s, "mmc_fclk"), omap_findclk(s, "mmc_iclk")); 2471 2472 s->mcspi[0] = omap_mcspi_init(omap_l4ta(s->l4, 35), 4, 2473 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MCSPI1_IRQ), 2474 &s->drq[OMAP24XX_DMA_SPI1_TX0], 2475 omap_findclk(s, "spi1_fclk"), 2476 omap_findclk(s, "spi1_iclk")); 2477 s->mcspi[1] = omap_mcspi_init(omap_l4ta(s->l4, 36), 2, 2478 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MCSPI2_IRQ), 2479 &s->drq[OMAP24XX_DMA_SPI2_TX0], 2480 omap_findclk(s, "spi2_fclk"), 2481 omap_findclk(s, "spi2_iclk")); 2482 2483 s->dss = omap_dss_init(omap_l4ta(s->l4, 10), sysmem, 0x68000800, 2484 /* XXX wire M_IRQ_25, D_L2_IRQ_30 and I_IRQ_13 together */ 2485 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_DSS_IRQ), 2486 s->drq[OMAP24XX_DMA_DSS], 2487 omap_findclk(s, "dss_clk1"), omap_findclk(s, "dss_clk2"), 2488 omap_findclk(s, "dss_54m_clk"), 2489 omap_findclk(s, "dss_l3_iclk"), 2490 omap_findclk(s, "dss_l4_iclk")); 2491 2492 omap_sti_init(omap_l4ta(s->l4, 18), sysmem, 0x54000000, 2493 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_STI), 2494 omap_findclk(s, "emul_ck"), 2495 serial_hds[0] && serial_hds[1] && serial_hds[2] ? 2496 serial_hds[3] : NULL); 2497 2498 s->eac = omap_eac_init(omap_l4ta(s->l4, 32), 2499 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_EAC_IRQ), 2500 /* Ten consecutive lines */ 2501 &s->drq[OMAP24XX_DMA_EAC_AC_RD], 2502 omap_findclk(s, "func_96m_clk"), 2503 omap_findclk(s, "core_l4_iclk")); 2504 2505 /* All register mappings (includin those not currenlty implemented): 2506 * SystemControlMod 48000000 - 48000fff 2507 * SystemControlL4 48001000 - 48001fff 2508 * 32kHz Timer Mod 48004000 - 48004fff 2509 * 32kHz Timer L4 48005000 - 48005fff 2510 * PRCM ModA 48008000 - 480087ff 2511 * PRCM ModB 48008800 - 48008fff 2512 * PRCM L4 48009000 - 48009fff 2513 * TEST-BCM Mod 48012000 - 48012fff 2514 * TEST-BCM L4 48013000 - 48013fff 2515 * TEST-TAP Mod 48014000 - 48014fff 2516 * TEST-TAP L4 48015000 - 48015fff 2517 * GPIO1 Mod 48018000 - 48018fff 2518 * GPIO Top 48019000 - 48019fff 2519 * GPIO2 Mod 4801a000 - 4801afff 2520 * GPIO L4 4801b000 - 4801bfff 2521 * GPIO3 Mod 4801c000 - 4801cfff 2522 * GPIO4 Mod 4801e000 - 4801efff 2523 * WDTIMER1 Mod 48020000 - 48010fff 2524 * WDTIMER Top 48021000 - 48011fff 2525 * WDTIMER2 Mod 48022000 - 48012fff 2526 * WDTIMER L4 48023000 - 48013fff 2527 * WDTIMER3 Mod 48024000 - 48014fff 2528 * WDTIMER3 L4 48025000 - 48015fff 2529 * WDTIMER4 Mod 48026000 - 48016fff 2530 * WDTIMER4 L4 48027000 - 48017fff 2531 * GPTIMER1 Mod 48028000 - 48018fff 2532 * GPTIMER1 L4 48029000 - 48019fff 2533 * GPTIMER2 Mod 4802a000 - 4801afff 2534 * GPTIMER2 L4 4802b000 - 4801bfff 2535 * L4-Config AP 48040000 - 480407ff 2536 * L4-Config IP 48040800 - 48040fff 2537 * L4-Config LA 48041000 - 48041fff 2538 * ARM11ETB Mod 48048000 - 48049fff 2539 * ARM11ETB L4 4804a000 - 4804afff 2540 * DISPLAY Top 48050000 - 480503ff 2541 * DISPLAY DISPC 48050400 - 480507ff 2542 * DISPLAY RFBI 48050800 - 48050bff 2543 * DISPLAY VENC 48050c00 - 48050fff 2544 * DISPLAY L4 48051000 - 48051fff 2545 * CAMERA Top 48052000 - 480523ff 2546 * CAMERA core 48052400 - 480527ff 2547 * CAMERA DMA 48052800 - 48052bff 2548 * CAMERA MMU 48052c00 - 48052fff 2549 * CAMERA L4 48053000 - 48053fff 2550 * SDMA Mod 48056000 - 48056fff 2551 * SDMA L4 48057000 - 48057fff 2552 * SSI Top 48058000 - 48058fff 2553 * SSI GDD 48059000 - 48059fff 2554 * SSI Port1 4805a000 - 4805afff 2555 * SSI Port2 4805b000 - 4805bfff 2556 * SSI L4 4805c000 - 4805cfff 2557 * USB Mod 4805e000 - 480fefff 2558 * USB L4 4805f000 - 480fffff 2559 * WIN_TRACER1 Mod 48060000 - 48060fff 2560 * WIN_TRACER1 L4 48061000 - 48061fff 2561 * WIN_TRACER2 Mod 48062000 - 48062fff 2562 * WIN_TRACER2 L4 48063000 - 48063fff 2563 * WIN_TRACER3 Mod 48064000 - 48064fff 2564 * WIN_TRACER3 L4 48065000 - 48065fff 2565 * WIN_TRACER4 Top 48066000 - 480660ff 2566 * WIN_TRACER4 ETT 48066100 - 480661ff 2567 * WIN_TRACER4 WT 48066200 - 480662ff 2568 * WIN_TRACER4 L4 48067000 - 48067fff 2569 * XTI Mod 48068000 - 48068fff 2570 * XTI L4 48069000 - 48069fff 2571 * UART1 Mod 4806a000 - 4806afff 2572 * UART1 L4 4806b000 - 4806bfff 2573 * UART2 Mod 4806c000 - 4806cfff 2574 * UART2 L4 4806d000 - 4806dfff 2575 * UART3 Mod 4806e000 - 4806efff 2576 * UART3 L4 4806f000 - 4806ffff 2577 * I2C1 Mod 48070000 - 48070fff 2578 * I2C1 L4 48071000 - 48071fff 2579 * I2C2 Mod 48072000 - 48072fff 2580 * I2C2 L4 48073000 - 48073fff 2581 * McBSP1 Mod 48074000 - 48074fff 2582 * McBSP1 L4 48075000 - 48075fff 2583 * McBSP2 Mod 48076000 - 48076fff 2584 * McBSP2 L4 48077000 - 48077fff 2585 * GPTIMER3 Mod 48078000 - 48078fff 2586 * GPTIMER3 L4 48079000 - 48079fff 2587 * GPTIMER4 Mod 4807a000 - 4807afff 2588 * GPTIMER4 L4 4807b000 - 4807bfff 2589 * GPTIMER5 Mod 4807c000 - 4807cfff 2590 * GPTIMER5 L4 4807d000 - 4807dfff 2591 * GPTIMER6 Mod 4807e000 - 4807efff 2592 * GPTIMER6 L4 4807f000 - 4807ffff 2593 * GPTIMER7 Mod 48080000 - 48080fff 2594 * GPTIMER7 L4 48081000 - 48081fff 2595 * GPTIMER8 Mod 48082000 - 48082fff 2596 * GPTIMER8 L4 48083000 - 48083fff 2597 * GPTIMER9 Mod 48084000 - 48084fff 2598 * GPTIMER9 L4 48085000 - 48085fff 2599 * GPTIMER10 Mod 48086000 - 48086fff 2600 * GPTIMER10 L4 48087000 - 48087fff 2601 * GPTIMER11 Mod 48088000 - 48088fff 2602 * GPTIMER11 L4 48089000 - 48089fff 2603 * GPTIMER12 Mod 4808a000 - 4808afff 2604 * GPTIMER12 L4 4808b000 - 4808bfff 2605 * EAC Mod 48090000 - 48090fff 2606 * EAC L4 48091000 - 48091fff 2607 * FAC Mod 48092000 - 48092fff 2608 * FAC L4 48093000 - 48093fff 2609 * MAILBOX Mod 48094000 - 48094fff 2610 * MAILBOX L4 48095000 - 48095fff 2611 * SPI1 Mod 48098000 - 48098fff 2612 * SPI1 L4 48099000 - 48099fff 2613 * SPI2 Mod 4809a000 - 4809afff 2614 * SPI2 L4 4809b000 - 4809bfff 2615 * MMC/SDIO Mod 4809c000 - 4809cfff 2616 * MMC/SDIO L4 4809d000 - 4809dfff 2617 * MS_PRO Mod 4809e000 - 4809efff 2618 * MS_PRO L4 4809f000 - 4809ffff 2619 * RNG Mod 480a0000 - 480a0fff 2620 * RNG L4 480a1000 - 480a1fff 2621 * DES3DES Mod 480a2000 - 480a2fff 2622 * DES3DES L4 480a3000 - 480a3fff 2623 * SHA1MD5 Mod 480a4000 - 480a4fff 2624 * SHA1MD5 L4 480a5000 - 480a5fff 2625 * AES Mod 480a6000 - 480a6fff 2626 * AES L4 480a7000 - 480a7fff 2627 * PKA Mod 480a8000 - 480a9fff 2628 * PKA L4 480aa000 - 480aafff 2629 * MG Mod 480b0000 - 480b0fff 2630 * MG L4 480b1000 - 480b1fff 2631 * HDQ/1-wire Mod 480b2000 - 480b2fff 2632 * HDQ/1-wire L4 480b3000 - 480b3fff 2633 * MPU interrupt 480fe000 - 480fefff 2634 * STI channel base 54000000 - 5400ffff 2635 * IVA RAM 5c000000 - 5c01ffff 2636 * IVA ROM 5c020000 - 5c027fff 2637 * IMG_BUF_A 5c040000 - 5c040fff 2638 * IMG_BUF_B 5c042000 - 5c042fff 2639 * VLCDS 5c048000 - 5c0487ff 2640 * IMX_COEF 5c049000 - 5c04afff 2641 * IMX_CMD 5c051000 - 5c051fff 2642 * VLCDQ 5c053000 - 5c0533ff 2643 * VLCDH 5c054000 - 5c054fff 2644 * SEQ_CMD 5c055000 - 5c055fff 2645 * IMX_REG 5c056000 - 5c0560ff 2646 * VLCD_REG 5c056100 - 5c0561ff 2647 * SEQ_REG 5c056200 - 5c0562ff 2648 * IMG_BUF_REG 5c056300 - 5c0563ff 2649 * SEQIRQ_REG 5c056400 - 5c0564ff 2650 * OCP_REG 5c060000 - 5c060fff 2651 * SYSC_REG 5c070000 - 5c070fff 2652 * MMU_REG 5d000000 - 5d000fff 2653 * sDMA R 68000400 - 680005ff 2654 * sDMA W 68000600 - 680007ff 2655 * Display Control 68000800 - 680009ff 2656 * DSP subsystem 68000a00 - 68000bff 2657 * MPU subsystem 68000c00 - 68000dff 2658 * IVA subsystem 68001000 - 680011ff 2659 * USB 68001200 - 680013ff 2660 * Camera 68001400 - 680015ff 2661 * VLYNQ (firewall) 68001800 - 68001bff 2662 * VLYNQ 68001e00 - 68001fff 2663 * SSI 68002000 - 680021ff 2664 * L4 68002400 - 680025ff 2665 * DSP (firewall) 68002800 - 68002bff 2666 * DSP subsystem 68002e00 - 68002fff 2667 * IVA (firewall) 68003000 - 680033ff 2668 * IVA 68003600 - 680037ff 2669 * GFX 68003a00 - 68003bff 2670 * CMDWR emulation 68003c00 - 68003dff 2671 * SMS 68004000 - 680041ff 2672 * OCM 68004200 - 680043ff 2673 * GPMC 68004400 - 680045ff 2674 * RAM (firewall) 68005000 - 680053ff 2675 * RAM (err login) 68005400 - 680057ff 2676 * ROM (firewall) 68005800 - 68005bff 2677 * ROM (err login) 68005c00 - 68005fff 2678 * GPMC (firewall) 68006000 - 680063ff 2679 * GPMC (err login) 68006400 - 680067ff 2680 * SMS (err login) 68006c00 - 68006fff 2681 * SMS registers 68008000 - 68008fff 2682 * SDRC registers 68009000 - 68009fff 2683 * GPMC registers 6800a000 6800afff 2684 */ 2685 2686 qemu_register_reset(omap2_mpu_reset, s); 2687 2688 return s; 2689 } 2690