1 /* 2 * TI OMAP processors emulation. 3 * 4 * Copyright (C) 2007-2008 Nokia Corporation 5 * Written by Andrzej Zaborowski <andrew@openedhand.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 or 10 * (at your option) version 3 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "qemu-common.h" 24 #include "cpu.h" 25 #include "sysemu/block-backend.h" 26 #include "sysemu/blockdev.h" 27 #include "hw/boards.h" 28 #include "hw/hw.h" 29 #include "hw/arm/arm.h" 30 #include "hw/arm/omap.h" 31 #include "sysemu/sysemu.h" 32 #include "qemu/timer.h" 33 #include "sysemu/char.h" 34 #include "hw/block/flash.h" 35 #include "hw/arm/soc_dma.h" 36 #include "hw/sysbus.h" 37 #include "audio/audio.h" 38 39 /* Enhanced Audio Controller (CODEC only) */ 40 struct omap_eac_s { 41 qemu_irq irq; 42 MemoryRegion iomem; 43 44 uint16_t sysconfig; 45 uint8_t config[4]; 46 uint8_t control; 47 uint8_t address; 48 uint16_t data; 49 uint8_t vtol; 50 uint8_t vtsl; 51 uint16_t mixer; 52 uint16_t gain[4]; 53 uint8_t att; 54 uint16_t max[7]; 55 56 struct { 57 qemu_irq txdrq; 58 qemu_irq rxdrq; 59 uint32_t (*txrx)(void *opaque, uint32_t, int); 60 void *opaque; 61 62 #define EAC_BUF_LEN 1024 63 uint32_t rxbuf[EAC_BUF_LEN]; 64 int rxoff; 65 int rxlen; 66 int rxavail; 67 uint32_t txbuf[EAC_BUF_LEN]; 68 int txlen; 69 int txavail; 70 71 int enable; 72 int rate; 73 74 uint16_t config[4]; 75 76 /* These need to be moved to the actual codec */ 77 QEMUSoundCard card; 78 SWVoiceIn *in_voice; 79 SWVoiceOut *out_voice; 80 int hw_enable; 81 } codec; 82 83 struct { 84 uint8_t control; 85 uint16_t config; 86 } modem, bt; 87 }; 88 89 static inline void omap_eac_interrupt_update(struct omap_eac_s *s) 90 { 91 qemu_set_irq(s->irq, (s->codec.config[1] >> 14) & 1); /* AURDI */ 92 } 93 94 static inline void omap_eac_in_dmarequest_update(struct omap_eac_s *s) 95 { 96 qemu_set_irq(s->codec.rxdrq, (s->codec.rxavail || s->codec.rxlen) && 97 ((s->codec.config[1] >> 12) & 1)); /* DMAREN */ 98 } 99 100 static inline void omap_eac_out_dmarequest_update(struct omap_eac_s *s) 101 { 102 qemu_set_irq(s->codec.txdrq, s->codec.txlen < s->codec.txavail && 103 ((s->codec.config[1] >> 11) & 1)); /* DMAWEN */ 104 } 105 106 static inline void omap_eac_in_refill(struct omap_eac_s *s) 107 { 108 int left = MIN(EAC_BUF_LEN - s->codec.rxlen, s->codec.rxavail) << 2; 109 int start = ((s->codec.rxoff + s->codec.rxlen) & (EAC_BUF_LEN - 1)) << 2; 110 int leftwrap = MIN(left, (EAC_BUF_LEN << 2) - start); 111 int recv = 1; 112 uint8_t *buf = (uint8_t *) s->codec.rxbuf + start; 113 114 left -= leftwrap; 115 start = 0; 116 while (leftwrap && (recv = AUD_read(s->codec.in_voice, buf + start, 117 leftwrap)) > 0) { /* Be defensive */ 118 start += recv; 119 leftwrap -= recv; 120 } 121 if (recv <= 0) 122 s->codec.rxavail = 0; 123 else 124 s->codec.rxavail -= start >> 2; 125 s->codec.rxlen += start >> 2; 126 127 if (recv > 0 && left > 0) { 128 start = 0; 129 while (left && (recv = AUD_read(s->codec.in_voice, 130 (uint8_t *) s->codec.rxbuf + start, 131 left)) > 0) { /* Be defensive */ 132 start += recv; 133 left -= recv; 134 } 135 if (recv <= 0) 136 s->codec.rxavail = 0; 137 else 138 s->codec.rxavail -= start >> 2; 139 s->codec.rxlen += start >> 2; 140 } 141 } 142 143 static inline void omap_eac_out_empty(struct omap_eac_s *s) 144 { 145 int left = s->codec.txlen << 2; 146 int start = 0; 147 int sent = 1; 148 149 while (left && (sent = AUD_write(s->codec.out_voice, 150 (uint8_t *) s->codec.txbuf + start, 151 left)) > 0) { /* Be defensive */ 152 start += sent; 153 left -= sent; 154 } 155 156 if (!sent) { 157 s->codec.txavail = 0; 158 omap_eac_out_dmarequest_update(s); 159 } 160 161 if (start) 162 s->codec.txlen = 0; 163 } 164 165 static void omap_eac_in_cb(void *opaque, int avail_b) 166 { 167 struct omap_eac_s *s = (struct omap_eac_s *) opaque; 168 169 s->codec.rxavail = avail_b >> 2; 170 omap_eac_in_refill(s); 171 /* TODO: possibly discard current buffer if overrun */ 172 omap_eac_in_dmarequest_update(s); 173 } 174 175 static void omap_eac_out_cb(void *opaque, int free_b) 176 { 177 struct omap_eac_s *s = (struct omap_eac_s *) opaque; 178 179 s->codec.txavail = free_b >> 2; 180 if (s->codec.txlen) 181 omap_eac_out_empty(s); 182 else 183 omap_eac_out_dmarequest_update(s); 184 } 185 186 static void omap_eac_enable_update(struct omap_eac_s *s) 187 { 188 s->codec.enable = !(s->codec.config[1] & 1) && /* EACPWD */ 189 (s->codec.config[1] & 2) && /* AUDEN */ 190 s->codec.hw_enable; 191 } 192 193 static const int omap_eac_fsint[4] = { 194 8000, 195 11025, 196 22050, 197 44100, 198 }; 199 200 static const int omap_eac_fsint2[8] = { 201 8000, 202 11025, 203 22050, 204 44100, 205 48000, 206 0, 0, 0, 207 }; 208 209 static const int omap_eac_fsint3[16] = { 210 8000, 211 11025, 212 16000, 213 22050, 214 24000, 215 32000, 216 44100, 217 48000, 218 0, 0, 0, 0, 0, 0, 0, 0, 219 }; 220 221 static void omap_eac_rate_update(struct omap_eac_s *s) 222 { 223 int fsint[3]; 224 225 fsint[2] = (s->codec.config[3] >> 9) & 0xf; 226 fsint[1] = (s->codec.config[2] >> 0) & 0x7; 227 fsint[0] = (s->codec.config[0] >> 6) & 0x3; 228 if (fsint[2] < 0xf) 229 s->codec.rate = omap_eac_fsint3[fsint[2]]; 230 else if (fsint[1] < 0x7) 231 s->codec.rate = omap_eac_fsint2[fsint[1]]; 232 else 233 s->codec.rate = omap_eac_fsint[fsint[0]]; 234 } 235 236 static void omap_eac_volume_update(struct omap_eac_s *s) 237 { 238 /* TODO */ 239 } 240 241 static void omap_eac_format_update(struct omap_eac_s *s) 242 { 243 struct audsettings fmt; 244 245 /* The hardware buffers at most one sample */ 246 if (s->codec.rxlen) 247 s->codec.rxlen = 1; 248 249 if (s->codec.in_voice) { 250 AUD_set_active_in(s->codec.in_voice, 0); 251 AUD_close_in(&s->codec.card, s->codec.in_voice); 252 s->codec.in_voice = NULL; 253 } 254 if (s->codec.out_voice) { 255 omap_eac_out_empty(s); 256 AUD_set_active_out(s->codec.out_voice, 0); 257 AUD_close_out(&s->codec.card, s->codec.out_voice); 258 s->codec.out_voice = NULL; 259 s->codec.txavail = 0; 260 } 261 /* Discard what couldn't be written */ 262 s->codec.txlen = 0; 263 264 omap_eac_enable_update(s); 265 if (!s->codec.enable) 266 return; 267 268 omap_eac_rate_update(s); 269 fmt.endianness = ((s->codec.config[0] >> 8) & 1); /* LI_BI */ 270 fmt.nchannels = ((s->codec.config[0] >> 10) & 1) ? 2 : 1; /* MN_ST */ 271 fmt.freq = s->codec.rate; 272 /* TODO: signedness possibly depends on the CODEC hardware - or 273 * does I2S specify it? */ 274 /* All register writes are 16 bits so we we store 16-bit samples 275 * in the buffers regardless of AGCFR[B8_16] value. */ 276 fmt.fmt = AUD_FMT_U16; 277 278 s->codec.in_voice = AUD_open_in(&s->codec.card, s->codec.in_voice, 279 "eac.codec.in", s, omap_eac_in_cb, &fmt); 280 s->codec.out_voice = AUD_open_out(&s->codec.card, s->codec.out_voice, 281 "eac.codec.out", s, omap_eac_out_cb, &fmt); 282 283 omap_eac_volume_update(s); 284 285 AUD_set_active_in(s->codec.in_voice, 1); 286 AUD_set_active_out(s->codec.out_voice, 1); 287 } 288 289 static void omap_eac_reset(struct omap_eac_s *s) 290 { 291 s->sysconfig = 0; 292 s->config[0] = 0x0c; 293 s->config[1] = 0x09; 294 s->config[2] = 0xab; 295 s->config[3] = 0x03; 296 s->control = 0x00; 297 s->address = 0x00; 298 s->data = 0x0000; 299 s->vtol = 0x00; 300 s->vtsl = 0x00; 301 s->mixer = 0x0000; 302 s->gain[0] = 0xe7e7; 303 s->gain[1] = 0x6767; 304 s->gain[2] = 0x6767; 305 s->gain[3] = 0x6767; 306 s->att = 0xce; 307 s->max[0] = 0; 308 s->max[1] = 0; 309 s->max[2] = 0; 310 s->max[3] = 0; 311 s->max[4] = 0; 312 s->max[5] = 0; 313 s->max[6] = 0; 314 315 s->modem.control = 0x00; 316 s->modem.config = 0x0000; 317 s->bt.control = 0x00; 318 s->bt.config = 0x0000; 319 s->codec.config[0] = 0x0649; 320 s->codec.config[1] = 0x0000; 321 s->codec.config[2] = 0x0007; 322 s->codec.config[3] = 0x1ffc; 323 s->codec.rxoff = 0; 324 s->codec.rxlen = 0; 325 s->codec.txlen = 0; 326 s->codec.rxavail = 0; 327 s->codec.txavail = 0; 328 329 omap_eac_format_update(s); 330 omap_eac_interrupt_update(s); 331 } 332 333 static uint64_t omap_eac_read(void *opaque, hwaddr addr, 334 unsigned size) 335 { 336 struct omap_eac_s *s = (struct omap_eac_s *) opaque; 337 uint32_t ret; 338 339 if (size != 2) { 340 return omap_badwidth_read16(opaque, addr); 341 } 342 343 switch (addr) { 344 case 0x000: /* CPCFR1 */ 345 return s->config[0]; 346 case 0x004: /* CPCFR2 */ 347 return s->config[1]; 348 case 0x008: /* CPCFR3 */ 349 return s->config[2]; 350 case 0x00c: /* CPCFR4 */ 351 return s->config[3]; 352 353 case 0x010: /* CPTCTL */ 354 return s->control | ((s->codec.rxavail + s->codec.rxlen > 0) << 7) | 355 ((s->codec.txlen < s->codec.txavail) << 5); 356 357 case 0x014: /* CPTTADR */ 358 return s->address; 359 case 0x018: /* CPTDATL */ 360 return s->data & 0xff; 361 case 0x01c: /* CPTDATH */ 362 return s->data >> 8; 363 case 0x020: /* CPTVSLL */ 364 return s->vtol; 365 case 0x024: /* CPTVSLH */ 366 return s->vtsl | (3 << 5); /* CRDY1 | CRDY2 */ 367 case 0x040: /* MPCTR */ 368 return s->modem.control; 369 case 0x044: /* MPMCCFR */ 370 return s->modem.config; 371 case 0x060: /* BPCTR */ 372 return s->bt.control; 373 case 0x064: /* BPMCCFR */ 374 return s->bt.config; 375 case 0x080: /* AMSCFR */ 376 return s->mixer; 377 case 0x084: /* AMVCTR */ 378 return s->gain[0]; 379 case 0x088: /* AM1VCTR */ 380 return s->gain[1]; 381 case 0x08c: /* AM2VCTR */ 382 return s->gain[2]; 383 case 0x090: /* AM3VCTR */ 384 return s->gain[3]; 385 case 0x094: /* ASTCTR */ 386 return s->att; 387 case 0x098: /* APD1LCR */ 388 return s->max[0]; 389 case 0x09c: /* APD1RCR */ 390 return s->max[1]; 391 case 0x0a0: /* APD2LCR */ 392 return s->max[2]; 393 case 0x0a4: /* APD2RCR */ 394 return s->max[3]; 395 case 0x0a8: /* APD3LCR */ 396 return s->max[4]; 397 case 0x0ac: /* APD3RCR */ 398 return s->max[5]; 399 case 0x0b0: /* APD4R */ 400 return s->max[6]; 401 case 0x0b4: /* ADWR */ 402 /* This should be write-only? Docs list it as read-only. */ 403 return 0x0000; 404 case 0x0b8: /* ADRDR */ 405 if (likely(s->codec.rxlen > 1)) { 406 ret = s->codec.rxbuf[s->codec.rxoff ++]; 407 s->codec.rxlen --; 408 s->codec.rxoff &= EAC_BUF_LEN - 1; 409 return ret; 410 } else if (s->codec.rxlen) { 411 ret = s->codec.rxbuf[s->codec.rxoff ++]; 412 s->codec.rxlen --; 413 s->codec.rxoff &= EAC_BUF_LEN - 1; 414 if (s->codec.rxavail) 415 omap_eac_in_refill(s); 416 omap_eac_in_dmarequest_update(s); 417 return ret; 418 } 419 return 0x0000; 420 case 0x0bc: /* AGCFR */ 421 return s->codec.config[0]; 422 case 0x0c0: /* AGCTR */ 423 return s->codec.config[1] | ((s->codec.config[1] & 2) << 14); 424 case 0x0c4: /* AGCFR2 */ 425 return s->codec.config[2]; 426 case 0x0c8: /* AGCFR3 */ 427 return s->codec.config[3]; 428 case 0x0cc: /* MBPDMACTR */ 429 case 0x0d0: /* MPDDMARR */ 430 case 0x0d8: /* MPUDMARR */ 431 case 0x0e4: /* BPDDMARR */ 432 case 0x0ec: /* BPUDMARR */ 433 return 0x0000; 434 435 case 0x100: /* VERSION_NUMBER */ 436 return 0x0010; 437 438 case 0x104: /* SYSCONFIG */ 439 return s->sysconfig; 440 441 case 0x108: /* SYSSTATUS */ 442 return 1 | 0xe; /* RESETDONE | stuff */ 443 } 444 445 OMAP_BAD_REG(addr); 446 return 0; 447 } 448 449 static void omap_eac_write(void *opaque, hwaddr addr, 450 uint64_t value, unsigned size) 451 { 452 struct omap_eac_s *s = (struct omap_eac_s *) opaque; 453 454 if (size != 2) { 455 omap_badwidth_write16(opaque, addr, value); 456 return; 457 } 458 459 switch (addr) { 460 case 0x098: /* APD1LCR */ 461 case 0x09c: /* APD1RCR */ 462 case 0x0a0: /* APD2LCR */ 463 case 0x0a4: /* APD2RCR */ 464 case 0x0a8: /* APD3LCR */ 465 case 0x0ac: /* APD3RCR */ 466 case 0x0b0: /* APD4R */ 467 case 0x0b8: /* ADRDR */ 468 case 0x0d0: /* MPDDMARR */ 469 case 0x0d8: /* MPUDMARR */ 470 case 0x0e4: /* BPDDMARR */ 471 case 0x0ec: /* BPUDMARR */ 472 case 0x100: /* VERSION_NUMBER */ 473 case 0x108: /* SYSSTATUS */ 474 OMAP_RO_REG(addr); 475 return; 476 477 case 0x000: /* CPCFR1 */ 478 s->config[0] = value & 0xff; 479 omap_eac_format_update(s); 480 break; 481 case 0x004: /* CPCFR2 */ 482 s->config[1] = value & 0xff; 483 omap_eac_format_update(s); 484 break; 485 case 0x008: /* CPCFR3 */ 486 s->config[2] = value & 0xff; 487 omap_eac_format_update(s); 488 break; 489 case 0x00c: /* CPCFR4 */ 490 s->config[3] = value & 0xff; 491 omap_eac_format_update(s); 492 break; 493 494 case 0x010: /* CPTCTL */ 495 /* Assuming TXF and TXE bits are read-only... */ 496 s->control = value & 0x5f; 497 omap_eac_interrupt_update(s); 498 break; 499 500 case 0x014: /* CPTTADR */ 501 s->address = value & 0xff; 502 break; 503 case 0x018: /* CPTDATL */ 504 s->data &= 0xff00; 505 s->data |= value & 0xff; 506 break; 507 case 0x01c: /* CPTDATH */ 508 s->data &= 0x00ff; 509 s->data |= value << 8; 510 break; 511 case 0x020: /* CPTVSLL */ 512 s->vtol = value & 0xf8; 513 break; 514 case 0x024: /* CPTVSLH */ 515 s->vtsl = value & 0x9f; 516 break; 517 case 0x040: /* MPCTR */ 518 s->modem.control = value & 0x8f; 519 break; 520 case 0x044: /* MPMCCFR */ 521 s->modem.config = value & 0x7fff; 522 break; 523 case 0x060: /* BPCTR */ 524 s->bt.control = value & 0x8f; 525 break; 526 case 0x064: /* BPMCCFR */ 527 s->bt.config = value & 0x7fff; 528 break; 529 case 0x080: /* AMSCFR */ 530 s->mixer = value & 0x0fff; 531 break; 532 case 0x084: /* AMVCTR */ 533 s->gain[0] = value & 0xffff; 534 break; 535 case 0x088: /* AM1VCTR */ 536 s->gain[1] = value & 0xff7f; 537 break; 538 case 0x08c: /* AM2VCTR */ 539 s->gain[2] = value & 0xff7f; 540 break; 541 case 0x090: /* AM3VCTR */ 542 s->gain[3] = value & 0xff7f; 543 break; 544 case 0x094: /* ASTCTR */ 545 s->att = value & 0xff; 546 break; 547 548 case 0x0b4: /* ADWR */ 549 s->codec.txbuf[s->codec.txlen ++] = value; 550 if (unlikely(s->codec.txlen == EAC_BUF_LEN || 551 s->codec.txlen == s->codec.txavail)) { 552 if (s->codec.txavail) 553 omap_eac_out_empty(s); 554 /* Discard what couldn't be written */ 555 s->codec.txlen = 0; 556 } 557 break; 558 559 case 0x0bc: /* AGCFR */ 560 s->codec.config[0] = value & 0x07ff; 561 omap_eac_format_update(s); 562 break; 563 case 0x0c0: /* AGCTR */ 564 s->codec.config[1] = value & 0x780f; 565 omap_eac_format_update(s); 566 break; 567 case 0x0c4: /* AGCFR2 */ 568 s->codec.config[2] = value & 0x003f; 569 omap_eac_format_update(s); 570 break; 571 case 0x0c8: /* AGCFR3 */ 572 s->codec.config[3] = value & 0xffff; 573 omap_eac_format_update(s); 574 break; 575 case 0x0cc: /* MBPDMACTR */ 576 case 0x0d4: /* MPDDMAWR */ 577 case 0x0e0: /* MPUDMAWR */ 578 case 0x0e8: /* BPDDMAWR */ 579 case 0x0f0: /* BPUDMAWR */ 580 break; 581 582 case 0x104: /* SYSCONFIG */ 583 if (value & (1 << 1)) /* SOFTRESET */ 584 omap_eac_reset(s); 585 s->sysconfig = value & 0x31d; 586 break; 587 588 default: 589 OMAP_BAD_REG(addr); 590 return; 591 } 592 } 593 594 static const MemoryRegionOps omap_eac_ops = { 595 .read = omap_eac_read, 596 .write = omap_eac_write, 597 .endianness = DEVICE_NATIVE_ENDIAN, 598 }; 599 600 static struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta, 601 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk) 602 { 603 struct omap_eac_s *s = g_new0(struct omap_eac_s, 1); 604 605 s->irq = irq; 606 s->codec.rxdrq = *drq ++; 607 s->codec.txdrq = *drq; 608 omap_eac_reset(s); 609 610 AUD_register_card("OMAP EAC", &s->codec.card); 611 612 memory_region_init_io(&s->iomem, NULL, &omap_eac_ops, s, "omap.eac", 613 omap_l4_region_size(ta, 0)); 614 omap_l4_attach(ta, 0, &s->iomem); 615 616 return s; 617 } 618 619 /* STI/XTI (emulation interface) console - reverse engineered only */ 620 struct omap_sti_s { 621 qemu_irq irq; 622 MemoryRegion iomem; 623 MemoryRegion iomem_fifo; 624 CharDriverState *chr; 625 626 uint32_t sysconfig; 627 uint32_t systest; 628 uint32_t irqst; 629 uint32_t irqen; 630 uint32_t clkcontrol; 631 uint32_t serial_config; 632 }; 633 634 #define STI_TRACE_CONSOLE_CHANNEL 239 635 #define STI_TRACE_CONTROL_CHANNEL 253 636 637 static inline void omap_sti_interrupt_update(struct omap_sti_s *s) 638 { 639 qemu_set_irq(s->irq, s->irqst & s->irqen); 640 } 641 642 static void omap_sti_reset(struct omap_sti_s *s) 643 { 644 s->sysconfig = 0; 645 s->irqst = 0; 646 s->irqen = 0; 647 s->clkcontrol = 0; 648 s->serial_config = 0; 649 650 omap_sti_interrupt_update(s); 651 } 652 653 static uint64_t omap_sti_read(void *opaque, hwaddr addr, 654 unsigned size) 655 { 656 struct omap_sti_s *s = (struct omap_sti_s *) opaque; 657 658 if (size != 4) { 659 return omap_badwidth_read32(opaque, addr); 660 } 661 662 switch (addr) { 663 case 0x00: /* STI_REVISION */ 664 return 0x10; 665 666 case 0x10: /* STI_SYSCONFIG */ 667 return s->sysconfig; 668 669 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */ 670 return 0x00; 671 672 case 0x18: /* STI_IRQSTATUS */ 673 return s->irqst; 674 675 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */ 676 return s->irqen; 677 678 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */ 679 case 0x28: /* STI_RX_DR / XTI_RXDATA */ 680 /* TODO */ 681 return 0; 682 683 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */ 684 return s->clkcontrol; 685 686 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */ 687 return s->serial_config; 688 } 689 690 OMAP_BAD_REG(addr); 691 return 0; 692 } 693 694 static void omap_sti_write(void *opaque, hwaddr addr, 695 uint64_t value, unsigned size) 696 { 697 struct omap_sti_s *s = (struct omap_sti_s *) opaque; 698 699 if (size != 4) { 700 omap_badwidth_write32(opaque, addr, value); 701 return; 702 } 703 704 switch (addr) { 705 case 0x00: /* STI_REVISION */ 706 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */ 707 OMAP_RO_REG(addr); 708 return; 709 710 case 0x10: /* STI_SYSCONFIG */ 711 if (value & (1 << 1)) /* SOFTRESET */ 712 omap_sti_reset(s); 713 s->sysconfig = value & 0xfe; 714 break; 715 716 case 0x18: /* STI_IRQSTATUS */ 717 s->irqst &= ~value; 718 omap_sti_interrupt_update(s); 719 break; 720 721 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */ 722 s->irqen = value & 0xffff; 723 omap_sti_interrupt_update(s); 724 break; 725 726 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */ 727 s->clkcontrol = value & 0xff; 728 break; 729 730 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */ 731 s->serial_config = value & 0xff; 732 break; 733 734 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */ 735 case 0x28: /* STI_RX_DR / XTI_RXDATA */ 736 /* TODO */ 737 return; 738 739 default: 740 OMAP_BAD_REG(addr); 741 return; 742 } 743 } 744 745 static const MemoryRegionOps omap_sti_ops = { 746 .read = omap_sti_read, 747 .write = omap_sti_write, 748 .endianness = DEVICE_NATIVE_ENDIAN, 749 }; 750 751 static uint64_t omap_sti_fifo_read(void *opaque, hwaddr addr, 752 unsigned size) 753 { 754 OMAP_BAD_REG(addr); 755 return 0; 756 } 757 758 static void omap_sti_fifo_write(void *opaque, hwaddr addr, 759 uint64_t value, unsigned size) 760 { 761 struct omap_sti_s *s = (struct omap_sti_s *) opaque; 762 int ch = addr >> 6; 763 uint8_t byte = value; 764 765 if (size != 1) { 766 omap_badwidth_write8(opaque, addr, size); 767 return; 768 } 769 770 if (ch == STI_TRACE_CONTROL_CHANNEL) { 771 /* Flush channel <i>value</i>. */ 772 /* XXX this blocks entire thread. Rewrite to use 773 * qemu_chr_fe_write and background I/O callbacks */ 774 qemu_chr_fe_write_all(s->chr, (const uint8_t *) "\r", 1); 775 } else if (ch == STI_TRACE_CONSOLE_CHANNEL || 1) { 776 if (value == 0xc0 || value == 0xc3) { 777 /* Open channel <i>ch</i>. */ 778 } else if (value == 0x00) 779 qemu_chr_fe_write_all(s->chr, (const uint8_t *) "\n", 1); 780 else 781 qemu_chr_fe_write_all(s->chr, &byte, 1); 782 } 783 } 784 785 static const MemoryRegionOps omap_sti_fifo_ops = { 786 .read = omap_sti_fifo_read, 787 .write = omap_sti_fifo_write, 788 .endianness = DEVICE_NATIVE_ENDIAN, 789 }; 790 791 static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta, 792 MemoryRegion *sysmem, 793 hwaddr channel_base, qemu_irq irq, omap_clk clk, 794 CharDriverState *chr) 795 { 796 struct omap_sti_s *s = g_new0(struct omap_sti_s, 1); 797 798 s->irq = irq; 799 omap_sti_reset(s); 800 801 s->chr = chr ?: qemu_chr_new("null", "null", NULL); 802 803 memory_region_init_io(&s->iomem, NULL, &omap_sti_ops, s, "omap.sti", 804 omap_l4_region_size(ta, 0)); 805 omap_l4_attach(ta, 0, &s->iomem); 806 807 memory_region_init_io(&s->iomem_fifo, NULL, &omap_sti_fifo_ops, s, 808 "omap.sti.fifo", 0x10000); 809 memory_region_add_subregion(sysmem, channel_base, &s->iomem_fifo); 810 811 return s; 812 } 813 814 /* L4 Interconnect */ 815 #define L4TA(n) (n) 816 #define L4TAO(n) ((n) + 39) 817 818 static const struct omap_l4_region_s omap_l4_region[125] = { 819 [ 1] = { 0x40800, 0x800, 32 }, /* Initiator agent */ 820 [ 2] = { 0x41000, 0x1000, 32 }, /* Link agent */ 821 [ 0] = { 0x40000, 0x800, 32 }, /* Address and protection */ 822 [ 3] = { 0x00000, 0x1000, 32 | 16 | 8 }, /* System Control and Pinout */ 823 [ 4] = { 0x01000, 0x1000, 32 | 16 | 8 }, /* L4TAO1 */ 824 [ 5] = { 0x04000, 0x1000, 32 | 16 }, /* 32K Timer */ 825 [ 6] = { 0x05000, 0x1000, 32 | 16 | 8 }, /* L4TAO2 */ 826 [ 7] = { 0x08000, 0x800, 32 }, /* PRCM Region A */ 827 [ 8] = { 0x08800, 0x800, 32 }, /* PRCM Region B */ 828 [ 9] = { 0x09000, 0x1000, 32 | 16 | 8 }, /* L4TAO */ 829 [ 10] = { 0x12000, 0x1000, 32 | 16 | 8 }, /* Test (BCM) */ 830 [ 11] = { 0x13000, 0x1000, 32 | 16 | 8 }, /* L4TA1 */ 831 [ 12] = { 0x14000, 0x1000, 32 }, /* Test/emulation (TAP) */ 832 [ 13] = { 0x15000, 0x1000, 32 | 16 | 8 }, /* L4TA2 */ 833 [ 14] = { 0x18000, 0x1000, 32 | 16 | 8 }, /* GPIO1 */ 834 [ 16] = { 0x1a000, 0x1000, 32 | 16 | 8 }, /* GPIO2 */ 835 [ 18] = { 0x1c000, 0x1000, 32 | 16 | 8 }, /* GPIO3 */ 836 [ 19] = { 0x1e000, 0x1000, 32 | 16 | 8 }, /* GPIO4 */ 837 [ 15] = { 0x19000, 0x1000, 32 | 16 | 8 }, /* Quad GPIO TOP */ 838 [ 17] = { 0x1b000, 0x1000, 32 | 16 | 8 }, /* L4TA3 */ 839 [ 20] = { 0x20000, 0x1000, 32 | 16 | 8 }, /* WD Timer 1 (Secure) */ 840 [ 22] = { 0x22000, 0x1000, 32 | 16 | 8 }, /* WD Timer 2 (OMAP) */ 841 [ 21] = { 0x21000, 0x1000, 32 | 16 | 8 }, /* Dual WD timer TOP */ 842 [ 23] = { 0x23000, 0x1000, 32 | 16 | 8 }, /* L4TA4 */ 843 [ 24] = { 0x28000, 0x1000, 32 | 16 | 8 }, /* GP Timer 1 */ 844 [ 25] = { 0x29000, 0x1000, 32 | 16 | 8 }, /* L4TA7 */ 845 [ 26] = { 0x48000, 0x2000, 32 | 16 | 8 }, /* Emulation (ARM11ETB) */ 846 [ 27] = { 0x4a000, 0x1000, 32 | 16 | 8 }, /* L4TA9 */ 847 [ 28] = { 0x50000, 0x400, 32 | 16 | 8 }, /* Display top */ 848 [ 29] = { 0x50400, 0x400, 32 | 16 | 8 }, /* Display control */ 849 [ 30] = { 0x50800, 0x400, 32 | 16 | 8 }, /* Display RFBI */ 850 [ 31] = { 0x50c00, 0x400, 32 | 16 | 8 }, /* Display encoder */ 851 [ 32] = { 0x51000, 0x1000, 32 | 16 | 8 }, /* L4TA10 */ 852 [ 33] = { 0x52000, 0x400, 32 | 16 | 8 }, /* Camera top */ 853 [ 34] = { 0x52400, 0x400, 32 | 16 | 8 }, /* Camera core */ 854 [ 35] = { 0x52800, 0x400, 32 | 16 | 8 }, /* Camera DMA */ 855 [ 36] = { 0x52c00, 0x400, 32 | 16 | 8 }, /* Camera MMU */ 856 [ 37] = { 0x53000, 0x1000, 32 | 16 | 8 }, /* L4TA11 */ 857 [ 38] = { 0x56000, 0x1000, 32 | 16 | 8 }, /* sDMA */ 858 [ 39] = { 0x57000, 0x1000, 32 | 16 | 8 }, /* L4TA12 */ 859 [ 40] = { 0x58000, 0x1000, 32 | 16 | 8 }, /* SSI top */ 860 [ 41] = { 0x59000, 0x1000, 32 | 16 | 8 }, /* SSI GDD */ 861 [ 42] = { 0x5a000, 0x1000, 32 | 16 | 8 }, /* SSI Port1 */ 862 [ 43] = { 0x5b000, 0x1000, 32 | 16 | 8 }, /* SSI Port2 */ 863 [ 44] = { 0x5c000, 0x1000, 32 | 16 | 8 }, /* L4TA13 */ 864 [ 45] = { 0x5e000, 0x1000, 32 | 16 | 8 }, /* USB OTG */ 865 [ 46] = { 0x5f000, 0x1000, 32 | 16 | 8 }, /* L4TAO4 */ 866 [ 47] = { 0x60000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER1SDRC) */ 867 [ 48] = { 0x61000, 0x1000, 32 | 16 | 8 }, /* L4TA14 */ 868 [ 49] = { 0x62000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER2GPMC) */ 869 [ 50] = { 0x63000, 0x1000, 32 | 16 | 8 }, /* L4TA15 */ 870 [ 51] = { 0x64000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER3OCM) */ 871 [ 52] = { 0x65000, 0x1000, 32 | 16 | 8 }, /* L4TA16 */ 872 [ 53] = { 0x66000, 0x300, 32 | 16 | 8 }, /* Emulation (WIN_TRACER4L4) */ 873 [ 54] = { 0x67000, 0x1000, 32 | 16 | 8 }, /* L4TA17 */ 874 [ 55] = { 0x68000, 0x1000, 32 | 16 | 8 }, /* Emulation (XTI) */ 875 [ 56] = { 0x69000, 0x1000, 32 | 16 | 8 }, /* L4TA18 */ 876 [ 57] = { 0x6a000, 0x1000, 16 | 8 }, /* UART1 */ 877 [ 58] = { 0x6b000, 0x1000, 32 | 16 | 8 }, /* L4TA19 */ 878 [ 59] = { 0x6c000, 0x1000, 16 | 8 }, /* UART2 */ 879 [ 60] = { 0x6d000, 0x1000, 32 | 16 | 8 }, /* L4TA20 */ 880 [ 61] = { 0x6e000, 0x1000, 16 | 8 }, /* UART3 */ 881 [ 62] = { 0x6f000, 0x1000, 32 | 16 | 8 }, /* L4TA21 */ 882 [ 63] = { 0x70000, 0x1000, 16 }, /* I2C1 */ 883 [ 64] = { 0x71000, 0x1000, 32 | 16 | 8 }, /* L4TAO5 */ 884 [ 65] = { 0x72000, 0x1000, 16 }, /* I2C2 */ 885 [ 66] = { 0x73000, 0x1000, 32 | 16 | 8 }, /* L4TAO6 */ 886 [ 67] = { 0x74000, 0x1000, 16 }, /* McBSP1 */ 887 [ 68] = { 0x75000, 0x1000, 32 | 16 | 8 }, /* L4TAO7 */ 888 [ 69] = { 0x76000, 0x1000, 16 }, /* McBSP2 */ 889 [ 70] = { 0x77000, 0x1000, 32 | 16 | 8 }, /* L4TAO8 */ 890 [ 71] = { 0x24000, 0x1000, 32 | 16 | 8 }, /* WD Timer 3 (DSP) */ 891 [ 72] = { 0x25000, 0x1000, 32 | 16 | 8 }, /* L4TA5 */ 892 [ 73] = { 0x26000, 0x1000, 32 | 16 | 8 }, /* WD Timer 4 (IVA) */ 893 [ 74] = { 0x27000, 0x1000, 32 | 16 | 8 }, /* L4TA6 */ 894 [ 75] = { 0x2a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 2 */ 895 [ 76] = { 0x2b000, 0x1000, 32 | 16 | 8 }, /* L4TA8 */ 896 [ 77] = { 0x78000, 0x1000, 32 | 16 | 8 }, /* GP Timer 3 */ 897 [ 78] = { 0x79000, 0x1000, 32 | 16 | 8 }, /* L4TA22 */ 898 [ 79] = { 0x7a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 4 */ 899 [ 80] = { 0x7b000, 0x1000, 32 | 16 | 8 }, /* L4TA23 */ 900 [ 81] = { 0x7c000, 0x1000, 32 | 16 | 8 }, /* GP Timer 5 */ 901 [ 82] = { 0x7d000, 0x1000, 32 | 16 | 8 }, /* L4TA24 */ 902 [ 83] = { 0x7e000, 0x1000, 32 | 16 | 8 }, /* GP Timer 6 */ 903 [ 84] = { 0x7f000, 0x1000, 32 | 16 | 8 }, /* L4TA25 */ 904 [ 85] = { 0x80000, 0x1000, 32 | 16 | 8 }, /* GP Timer 7 */ 905 [ 86] = { 0x81000, 0x1000, 32 | 16 | 8 }, /* L4TA26 */ 906 [ 87] = { 0x82000, 0x1000, 32 | 16 | 8 }, /* GP Timer 8 */ 907 [ 88] = { 0x83000, 0x1000, 32 | 16 | 8 }, /* L4TA27 */ 908 [ 89] = { 0x84000, 0x1000, 32 | 16 | 8 }, /* GP Timer 9 */ 909 [ 90] = { 0x85000, 0x1000, 32 | 16 | 8 }, /* L4TA28 */ 910 [ 91] = { 0x86000, 0x1000, 32 | 16 | 8 }, /* GP Timer 10 */ 911 [ 92] = { 0x87000, 0x1000, 32 | 16 | 8 }, /* L4TA29 */ 912 [ 93] = { 0x88000, 0x1000, 32 | 16 | 8 }, /* GP Timer 11 */ 913 [ 94] = { 0x89000, 0x1000, 32 | 16 | 8 }, /* L4TA30 */ 914 [ 95] = { 0x8a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 12 */ 915 [ 96] = { 0x8b000, 0x1000, 32 | 16 | 8 }, /* L4TA31 */ 916 [ 97] = { 0x90000, 0x1000, 16 }, /* EAC */ 917 [ 98] = { 0x91000, 0x1000, 32 | 16 | 8 }, /* L4TA32 */ 918 [ 99] = { 0x92000, 0x1000, 16 }, /* FAC */ 919 [100] = { 0x93000, 0x1000, 32 | 16 | 8 }, /* L4TA33 */ 920 [101] = { 0x94000, 0x1000, 32 | 16 | 8 }, /* IPC (MAILBOX) */ 921 [102] = { 0x95000, 0x1000, 32 | 16 | 8 }, /* L4TA34 */ 922 [103] = { 0x98000, 0x1000, 32 | 16 | 8 }, /* SPI1 */ 923 [104] = { 0x99000, 0x1000, 32 | 16 | 8 }, /* L4TA35 */ 924 [105] = { 0x9a000, 0x1000, 32 | 16 | 8 }, /* SPI2 */ 925 [106] = { 0x9b000, 0x1000, 32 | 16 | 8 }, /* L4TA36 */ 926 [107] = { 0x9c000, 0x1000, 16 | 8 }, /* MMC SDIO */ 927 [108] = { 0x9d000, 0x1000, 32 | 16 | 8 }, /* L4TAO9 */ 928 [109] = { 0x9e000, 0x1000, 32 | 16 | 8 }, /* MS_PRO */ 929 [110] = { 0x9f000, 0x1000, 32 | 16 | 8 }, /* L4TAO10 */ 930 [111] = { 0xa0000, 0x1000, 32 }, /* RNG */ 931 [112] = { 0xa1000, 0x1000, 32 | 16 | 8 }, /* L4TAO11 */ 932 [113] = { 0xa2000, 0x1000, 32 }, /* DES3DES */ 933 [114] = { 0xa3000, 0x1000, 32 | 16 | 8 }, /* L4TAO12 */ 934 [115] = { 0xa4000, 0x1000, 32 }, /* SHA1MD5 */ 935 [116] = { 0xa5000, 0x1000, 32 | 16 | 8 }, /* L4TAO13 */ 936 [117] = { 0xa6000, 0x1000, 32 }, /* AES */ 937 [118] = { 0xa7000, 0x1000, 32 | 16 | 8 }, /* L4TA37 */ 938 [119] = { 0xa8000, 0x2000, 32 }, /* PKA */ 939 [120] = { 0xaa000, 0x1000, 32 | 16 | 8 }, /* L4TA38 */ 940 [121] = { 0xb0000, 0x1000, 32 }, /* MG */ 941 [122] = { 0xb1000, 0x1000, 32 | 16 | 8 }, 942 [123] = { 0xb2000, 0x1000, 32 }, /* HDQ/1-Wire */ 943 [124] = { 0xb3000, 0x1000, 32 | 16 | 8 }, /* L4TA39 */ 944 }; 945 946 static const struct omap_l4_agent_info_s omap_l4_agent_info[54] = { 947 { 0, 0, 3, 2 }, /* L4IA initiatior agent */ 948 { L4TAO(1), 3, 2, 1 }, /* Control and pinout module */ 949 { L4TAO(2), 5, 2, 1 }, /* 32K timer */ 950 { L4TAO(3), 7, 3, 2 }, /* PRCM */ 951 { L4TA(1), 10, 2, 1 }, /* BCM */ 952 { L4TA(2), 12, 2, 1 }, /* Test JTAG */ 953 { L4TA(3), 14, 6, 3 }, /* Quad GPIO */ 954 { L4TA(4), 20, 4, 3 }, /* WD timer 1/2 */ 955 { L4TA(7), 24, 2, 1 }, /* GP timer 1 */ 956 { L4TA(9), 26, 2, 1 }, /* ATM11 ETB */ 957 { L4TA(10), 28, 5, 4 }, /* Display subsystem */ 958 { L4TA(11), 33, 5, 4 }, /* Camera subsystem */ 959 { L4TA(12), 38, 2, 1 }, /* sDMA */ 960 { L4TA(13), 40, 5, 4 }, /* SSI */ 961 { L4TAO(4), 45, 2, 1 }, /* USB */ 962 { L4TA(14), 47, 2, 1 }, /* Win Tracer1 */ 963 { L4TA(15), 49, 2, 1 }, /* Win Tracer2 */ 964 { L4TA(16), 51, 2, 1 }, /* Win Tracer3 */ 965 { L4TA(17), 53, 2, 1 }, /* Win Tracer4 */ 966 { L4TA(18), 55, 2, 1 }, /* XTI */ 967 { L4TA(19), 57, 2, 1 }, /* UART1 */ 968 { L4TA(20), 59, 2, 1 }, /* UART2 */ 969 { L4TA(21), 61, 2, 1 }, /* UART3 */ 970 { L4TAO(5), 63, 2, 1 }, /* I2C1 */ 971 { L4TAO(6), 65, 2, 1 }, /* I2C2 */ 972 { L4TAO(7), 67, 2, 1 }, /* McBSP1 */ 973 { L4TAO(8), 69, 2, 1 }, /* McBSP2 */ 974 { L4TA(5), 71, 2, 1 }, /* WD Timer 3 (DSP) */ 975 { L4TA(6), 73, 2, 1 }, /* WD Timer 4 (IVA) */ 976 { L4TA(8), 75, 2, 1 }, /* GP Timer 2 */ 977 { L4TA(22), 77, 2, 1 }, /* GP Timer 3 */ 978 { L4TA(23), 79, 2, 1 }, /* GP Timer 4 */ 979 { L4TA(24), 81, 2, 1 }, /* GP Timer 5 */ 980 { L4TA(25), 83, 2, 1 }, /* GP Timer 6 */ 981 { L4TA(26), 85, 2, 1 }, /* GP Timer 7 */ 982 { L4TA(27), 87, 2, 1 }, /* GP Timer 8 */ 983 { L4TA(28), 89, 2, 1 }, /* GP Timer 9 */ 984 { L4TA(29), 91, 2, 1 }, /* GP Timer 10 */ 985 { L4TA(30), 93, 2, 1 }, /* GP Timer 11 */ 986 { L4TA(31), 95, 2, 1 }, /* GP Timer 12 */ 987 { L4TA(32), 97, 2, 1 }, /* EAC */ 988 { L4TA(33), 99, 2, 1 }, /* FAC */ 989 { L4TA(34), 101, 2, 1 }, /* IPC */ 990 { L4TA(35), 103, 2, 1 }, /* SPI1 */ 991 { L4TA(36), 105, 2, 1 }, /* SPI2 */ 992 { L4TAO(9), 107, 2, 1 }, /* MMC SDIO */ 993 { L4TAO(10), 109, 2, 1 }, 994 { L4TAO(11), 111, 2, 1 }, /* RNG */ 995 { L4TAO(12), 113, 2, 1 }, /* DES3DES */ 996 { L4TAO(13), 115, 2, 1 }, /* SHA1MD5 */ 997 { L4TA(37), 117, 2, 1 }, /* AES */ 998 { L4TA(38), 119, 2, 1 }, /* PKA */ 999 { -1, 121, 2, 1 }, 1000 { L4TA(39), 123, 2, 1 }, /* HDQ/1-Wire */ 1001 }; 1002 1003 #define omap_l4ta(bus, cs) \ 1004 omap_l4ta_get(bus, omap_l4_region, omap_l4_agent_info, L4TA(cs)) 1005 #define omap_l4tao(bus, cs) \ 1006 omap_l4ta_get(bus, omap_l4_region, omap_l4_agent_info, L4TAO(cs)) 1007 1008 /* Power, Reset, and Clock Management */ 1009 struct omap_prcm_s { 1010 qemu_irq irq[3]; 1011 struct omap_mpu_state_s *mpu; 1012 MemoryRegion iomem0; 1013 MemoryRegion iomem1; 1014 1015 uint32_t irqst[3]; 1016 uint32_t irqen[3]; 1017 1018 uint32_t sysconfig; 1019 uint32_t voltctrl; 1020 uint32_t scratch[20]; 1021 1022 uint32_t clksrc[1]; 1023 uint32_t clkout[1]; 1024 uint32_t clkemul[1]; 1025 uint32_t clkpol[1]; 1026 uint32_t clksel[8]; 1027 uint32_t clken[12]; 1028 uint32_t clkctrl[4]; 1029 uint32_t clkidle[7]; 1030 uint32_t setuptime[2]; 1031 1032 uint32_t wkup[3]; 1033 uint32_t wken[3]; 1034 uint32_t wkst[3]; 1035 uint32_t rst[4]; 1036 uint32_t rstctrl[1]; 1037 uint32_t power[4]; 1038 uint32_t rsttime_wkup; 1039 1040 uint32_t ev; 1041 uint32_t evtime[2]; 1042 1043 int dpll_lock, apll_lock[2]; 1044 }; 1045 1046 static void omap_prcm_int_update(struct omap_prcm_s *s, int dom) 1047 { 1048 qemu_set_irq(s->irq[dom], s->irqst[dom] & s->irqen[dom]); 1049 /* XXX or is the mask applied before PRCM_IRQSTATUS_* ? */ 1050 } 1051 1052 static uint64_t omap_prcm_read(void *opaque, hwaddr addr, 1053 unsigned size) 1054 { 1055 struct omap_prcm_s *s = (struct omap_prcm_s *) opaque; 1056 uint32_t ret; 1057 1058 if (size != 4) { 1059 return omap_badwidth_read32(opaque, addr); 1060 } 1061 1062 switch (addr) { 1063 case 0x000: /* PRCM_REVISION */ 1064 return 0x10; 1065 1066 case 0x010: /* PRCM_SYSCONFIG */ 1067 return s->sysconfig; 1068 1069 case 0x018: /* PRCM_IRQSTATUS_MPU */ 1070 return s->irqst[0]; 1071 1072 case 0x01c: /* PRCM_IRQENABLE_MPU */ 1073 return s->irqen[0]; 1074 1075 case 0x050: /* PRCM_VOLTCTRL */ 1076 return s->voltctrl; 1077 case 0x054: /* PRCM_VOLTST */ 1078 return s->voltctrl & 3; 1079 1080 case 0x060: /* PRCM_CLKSRC_CTRL */ 1081 return s->clksrc[0]; 1082 case 0x070: /* PRCM_CLKOUT_CTRL */ 1083 return s->clkout[0]; 1084 case 0x078: /* PRCM_CLKEMUL_CTRL */ 1085 return s->clkemul[0]; 1086 case 0x080: /* PRCM_CLKCFG_CTRL */ 1087 case 0x084: /* PRCM_CLKCFG_STATUS */ 1088 return 0; 1089 1090 case 0x090: /* PRCM_VOLTSETUP */ 1091 return s->setuptime[0]; 1092 1093 case 0x094: /* PRCM_CLKSSETUP */ 1094 return s->setuptime[1]; 1095 1096 case 0x098: /* PRCM_POLCTRL */ 1097 return s->clkpol[0]; 1098 1099 case 0x0b0: /* GENERAL_PURPOSE1 */ 1100 case 0x0b4: /* GENERAL_PURPOSE2 */ 1101 case 0x0b8: /* GENERAL_PURPOSE3 */ 1102 case 0x0bc: /* GENERAL_PURPOSE4 */ 1103 case 0x0c0: /* GENERAL_PURPOSE5 */ 1104 case 0x0c4: /* GENERAL_PURPOSE6 */ 1105 case 0x0c8: /* GENERAL_PURPOSE7 */ 1106 case 0x0cc: /* GENERAL_PURPOSE8 */ 1107 case 0x0d0: /* GENERAL_PURPOSE9 */ 1108 case 0x0d4: /* GENERAL_PURPOSE10 */ 1109 case 0x0d8: /* GENERAL_PURPOSE11 */ 1110 case 0x0dc: /* GENERAL_PURPOSE12 */ 1111 case 0x0e0: /* GENERAL_PURPOSE13 */ 1112 case 0x0e4: /* GENERAL_PURPOSE14 */ 1113 case 0x0e8: /* GENERAL_PURPOSE15 */ 1114 case 0x0ec: /* GENERAL_PURPOSE16 */ 1115 case 0x0f0: /* GENERAL_PURPOSE17 */ 1116 case 0x0f4: /* GENERAL_PURPOSE18 */ 1117 case 0x0f8: /* GENERAL_PURPOSE19 */ 1118 case 0x0fc: /* GENERAL_PURPOSE20 */ 1119 return s->scratch[(addr - 0xb0) >> 2]; 1120 1121 case 0x140: /* CM_CLKSEL_MPU */ 1122 return s->clksel[0]; 1123 case 0x148: /* CM_CLKSTCTRL_MPU */ 1124 return s->clkctrl[0]; 1125 1126 case 0x158: /* RM_RSTST_MPU */ 1127 return s->rst[0]; 1128 case 0x1c8: /* PM_WKDEP_MPU */ 1129 return s->wkup[0]; 1130 case 0x1d4: /* PM_EVGENCTRL_MPU */ 1131 return s->ev; 1132 case 0x1d8: /* PM_EVEGENONTIM_MPU */ 1133 return s->evtime[0]; 1134 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */ 1135 return s->evtime[1]; 1136 case 0x1e0: /* PM_PWSTCTRL_MPU */ 1137 return s->power[0]; 1138 case 0x1e4: /* PM_PWSTST_MPU */ 1139 return 0; 1140 1141 case 0x200: /* CM_FCLKEN1_CORE */ 1142 return s->clken[0]; 1143 case 0x204: /* CM_FCLKEN2_CORE */ 1144 return s->clken[1]; 1145 case 0x210: /* CM_ICLKEN1_CORE */ 1146 return s->clken[2]; 1147 case 0x214: /* CM_ICLKEN2_CORE */ 1148 return s->clken[3]; 1149 case 0x21c: /* CM_ICLKEN4_CORE */ 1150 return s->clken[4]; 1151 1152 case 0x220: /* CM_IDLEST1_CORE */ 1153 /* TODO: check the actual iclk status */ 1154 return 0x7ffffff9; 1155 case 0x224: /* CM_IDLEST2_CORE */ 1156 /* TODO: check the actual iclk status */ 1157 return 0x00000007; 1158 case 0x22c: /* CM_IDLEST4_CORE */ 1159 /* TODO: check the actual iclk status */ 1160 return 0x0000001f; 1161 1162 case 0x230: /* CM_AUTOIDLE1_CORE */ 1163 return s->clkidle[0]; 1164 case 0x234: /* CM_AUTOIDLE2_CORE */ 1165 return s->clkidle[1]; 1166 case 0x238: /* CM_AUTOIDLE3_CORE */ 1167 return s->clkidle[2]; 1168 case 0x23c: /* CM_AUTOIDLE4_CORE */ 1169 return s->clkidle[3]; 1170 1171 case 0x240: /* CM_CLKSEL1_CORE */ 1172 return s->clksel[1]; 1173 case 0x244: /* CM_CLKSEL2_CORE */ 1174 return s->clksel[2]; 1175 1176 case 0x248: /* CM_CLKSTCTRL_CORE */ 1177 return s->clkctrl[1]; 1178 1179 case 0x2a0: /* PM_WKEN1_CORE */ 1180 return s->wken[0]; 1181 case 0x2a4: /* PM_WKEN2_CORE */ 1182 return s->wken[1]; 1183 1184 case 0x2b0: /* PM_WKST1_CORE */ 1185 return s->wkst[0]; 1186 case 0x2b4: /* PM_WKST2_CORE */ 1187 return s->wkst[1]; 1188 case 0x2c8: /* PM_WKDEP_CORE */ 1189 return 0x1e; 1190 1191 case 0x2e0: /* PM_PWSTCTRL_CORE */ 1192 return s->power[1]; 1193 case 0x2e4: /* PM_PWSTST_CORE */ 1194 return 0x000030 | (s->power[1] & 0xfc00); 1195 1196 case 0x300: /* CM_FCLKEN_GFX */ 1197 return s->clken[5]; 1198 case 0x310: /* CM_ICLKEN_GFX */ 1199 return s->clken[6]; 1200 case 0x320: /* CM_IDLEST_GFX */ 1201 /* TODO: check the actual iclk status */ 1202 return 0x00000001; 1203 case 0x340: /* CM_CLKSEL_GFX */ 1204 return s->clksel[3]; 1205 case 0x348: /* CM_CLKSTCTRL_GFX */ 1206 return s->clkctrl[2]; 1207 case 0x350: /* RM_RSTCTRL_GFX */ 1208 return s->rstctrl[0]; 1209 case 0x358: /* RM_RSTST_GFX */ 1210 return s->rst[1]; 1211 case 0x3c8: /* PM_WKDEP_GFX */ 1212 return s->wkup[1]; 1213 1214 case 0x3e0: /* PM_PWSTCTRL_GFX */ 1215 return s->power[2]; 1216 case 0x3e4: /* PM_PWSTST_GFX */ 1217 return s->power[2] & 3; 1218 1219 case 0x400: /* CM_FCLKEN_WKUP */ 1220 return s->clken[7]; 1221 case 0x410: /* CM_ICLKEN_WKUP */ 1222 return s->clken[8]; 1223 case 0x420: /* CM_IDLEST_WKUP */ 1224 /* TODO: check the actual iclk status */ 1225 return 0x0000003f; 1226 case 0x430: /* CM_AUTOIDLE_WKUP */ 1227 return s->clkidle[4]; 1228 case 0x440: /* CM_CLKSEL_WKUP */ 1229 return s->clksel[4]; 1230 case 0x450: /* RM_RSTCTRL_WKUP */ 1231 return 0; 1232 case 0x454: /* RM_RSTTIME_WKUP */ 1233 return s->rsttime_wkup; 1234 case 0x458: /* RM_RSTST_WKUP */ 1235 return s->rst[2]; 1236 case 0x4a0: /* PM_WKEN_WKUP */ 1237 return s->wken[2]; 1238 case 0x4b0: /* PM_WKST_WKUP */ 1239 return s->wkst[2]; 1240 1241 case 0x500: /* CM_CLKEN_PLL */ 1242 return s->clken[9]; 1243 case 0x520: /* CM_IDLEST_CKGEN */ 1244 ret = 0x0000070 | (s->apll_lock[0] << 9) | (s->apll_lock[1] << 8); 1245 if (!(s->clksel[6] & 3)) 1246 /* Core uses 32-kHz clock */ 1247 ret |= 3 << 0; 1248 else if (!s->dpll_lock) 1249 /* DPLL not locked, core uses ref_clk */ 1250 ret |= 1 << 0; 1251 else 1252 /* Core uses DPLL */ 1253 ret |= 2 << 0; 1254 return ret; 1255 case 0x530: /* CM_AUTOIDLE_PLL */ 1256 return s->clkidle[5]; 1257 case 0x540: /* CM_CLKSEL1_PLL */ 1258 return s->clksel[5]; 1259 case 0x544: /* CM_CLKSEL2_PLL */ 1260 return s->clksel[6]; 1261 1262 case 0x800: /* CM_FCLKEN_DSP */ 1263 return s->clken[10]; 1264 case 0x810: /* CM_ICLKEN_DSP */ 1265 return s->clken[11]; 1266 case 0x820: /* CM_IDLEST_DSP */ 1267 /* TODO: check the actual iclk status */ 1268 return 0x00000103; 1269 case 0x830: /* CM_AUTOIDLE_DSP */ 1270 return s->clkidle[6]; 1271 case 0x840: /* CM_CLKSEL_DSP */ 1272 return s->clksel[7]; 1273 case 0x848: /* CM_CLKSTCTRL_DSP */ 1274 return s->clkctrl[3]; 1275 case 0x850: /* RM_RSTCTRL_DSP */ 1276 return 0; 1277 case 0x858: /* RM_RSTST_DSP */ 1278 return s->rst[3]; 1279 case 0x8c8: /* PM_WKDEP_DSP */ 1280 return s->wkup[2]; 1281 case 0x8e0: /* PM_PWSTCTRL_DSP */ 1282 return s->power[3]; 1283 case 0x8e4: /* PM_PWSTST_DSP */ 1284 return 0x008030 | (s->power[3] & 0x3003); 1285 1286 case 0x8f0: /* PRCM_IRQSTATUS_DSP */ 1287 return s->irqst[1]; 1288 case 0x8f4: /* PRCM_IRQENABLE_DSP */ 1289 return s->irqen[1]; 1290 1291 case 0x8f8: /* PRCM_IRQSTATUS_IVA */ 1292 return s->irqst[2]; 1293 case 0x8fc: /* PRCM_IRQENABLE_IVA */ 1294 return s->irqen[2]; 1295 } 1296 1297 OMAP_BAD_REG(addr); 1298 return 0; 1299 } 1300 1301 static void omap_prcm_apll_update(struct omap_prcm_s *s) 1302 { 1303 int mode[2]; 1304 1305 mode[0] = (s->clken[9] >> 6) & 3; 1306 s->apll_lock[0] = (mode[0] == 3); 1307 mode[1] = (s->clken[9] >> 2) & 3; 1308 s->apll_lock[1] = (mode[1] == 3); 1309 /* TODO: update clocks */ 1310 1311 if (mode[0] == 1 || mode[0] == 2 || mode[1] == 1 || mode[1] == 2) 1312 fprintf(stderr, "%s: bad EN_54M_PLL or bad EN_96M_PLL\n", 1313 __FUNCTION__); 1314 } 1315 1316 static void omap_prcm_dpll_update(struct omap_prcm_s *s) 1317 { 1318 omap_clk dpll = omap_findclk(s->mpu, "dpll"); 1319 omap_clk dpll_x2 = omap_findclk(s->mpu, "dpll"); 1320 omap_clk core = omap_findclk(s->mpu, "core_clk"); 1321 int mode = (s->clken[9] >> 0) & 3; 1322 int mult, div; 1323 1324 mult = (s->clksel[5] >> 12) & 0x3ff; 1325 div = (s->clksel[5] >> 8) & 0xf; 1326 if (mult == 0 || mult == 1) 1327 mode = 1; /* Bypass */ 1328 1329 s->dpll_lock = 0; 1330 switch (mode) { 1331 case 0: 1332 fprintf(stderr, "%s: bad EN_DPLL\n", __FUNCTION__); 1333 break; 1334 case 1: /* Low-power bypass mode (Default) */ 1335 case 2: /* Fast-relock bypass mode */ 1336 omap_clk_setrate(dpll, 1, 1); 1337 omap_clk_setrate(dpll_x2, 1, 1); 1338 break; 1339 case 3: /* Lock mode */ 1340 s->dpll_lock = 1; /* After 20 FINT cycles (ref_clk / (div + 1)). */ 1341 1342 omap_clk_setrate(dpll, div + 1, mult); 1343 omap_clk_setrate(dpll_x2, div + 1, mult * 2); 1344 break; 1345 } 1346 1347 switch ((s->clksel[6] >> 0) & 3) { 1348 case 0: 1349 omap_clk_reparent(core, omap_findclk(s->mpu, "clk32-kHz")); 1350 break; 1351 case 1: 1352 omap_clk_reparent(core, dpll); 1353 break; 1354 case 2: 1355 /* Default */ 1356 omap_clk_reparent(core, dpll_x2); 1357 break; 1358 case 3: 1359 fprintf(stderr, "%s: bad CORE_CLK_SRC\n", __FUNCTION__); 1360 break; 1361 } 1362 } 1363 1364 static void omap_prcm_write(void *opaque, hwaddr addr, 1365 uint64_t value, unsigned size) 1366 { 1367 struct omap_prcm_s *s = (struct omap_prcm_s *) opaque; 1368 1369 if (size != 4) { 1370 omap_badwidth_write32(opaque, addr, value); 1371 return; 1372 } 1373 1374 switch (addr) { 1375 case 0x000: /* PRCM_REVISION */ 1376 case 0x054: /* PRCM_VOLTST */ 1377 case 0x084: /* PRCM_CLKCFG_STATUS */ 1378 case 0x1e4: /* PM_PWSTST_MPU */ 1379 case 0x220: /* CM_IDLEST1_CORE */ 1380 case 0x224: /* CM_IDLEST2_CORE */ 1381 case 0x22c: /* CM_IDLEST4_CORE */ 1382 case 0x2c8: /* PM_WKDEP_CORE */ 1383 case 0x2e4: /* PM_PWSTST_CORE */ 1384 case 0x320: /* CM_IDLEST_GFX */ 1385 case 0x3e4: /* PM_PWSTST_GFX */ 1386 case 0x420: /* CM_IDLEST_WKUP */ 1387 case 0x520: /* CM_IDLEST_CKGEN */ 1388 case 0x820: /* CM_IDLEST_DSP */ 1389 case 0x8e4: /* PM_PWSTST_DSP */ 1390 OMAP_RO_REG(addr); 1391 return; 1392 1393 case 0x010: /* PRCM_SYSCONFIG */ 1394 s->sysconfig = value & 1; 1395 break; 1396 1397 case 0x018: /* PRCM_IRQSTATUS_MPU */ 1398 s->irqst[0] &= ~value; 1399 omap_prcm_int_update(s, 0); 1400 break; 1401 case 0x01c: /* PRCM_IRQENABLE_MPU */ 1402 s->irqen[0] = value & 0x3f; 1403 omap_prcm_int_update(s, 0); 1404 break; 1405 1406 case 0x050: /* PRCM_VOLTCTRL */ 1407 s->voltctrl = value & 0xf1c3; 1408 break; 1409 1410 case 0x060: /* PRCM_CLKSRC_CTRL */ 1411 s->clksrc[0] = value & 0xdb; 1412 /* TODO update clocks */ 1413 break; 1414 1415 case 0x070: /* PRCM_CLKOUT_CTRL */ 1416 s->clkout[0] = value & 0xbbbb; 1417 /* TODO update clocks */ 1418 break; 1419 1420 case 0x078: /* PRCM_CLKEMUL_CTRL */ 1421 s->clkemul[0] = value & 1; 1422 /* TODO update clocks */ 1423 break; 1424 1425 case 0x080: /* PRCM_CLKCFG_CTRL */ 1426 break; 1427 1428 case 0x090: /* PRCM_VOLTSETUP */ 1429 s->setuptime[0] = value & 0xffff; 1430 break; 1431 case 0x094: /* PRCM_CLKSSETUP */ 1432 s->setuptime[1] = value & 0xffff; 1433 break; 1434 1435 case 0x098: /* PRCM_POLCTRL */ 1436 s->clkpol[0] = value & 0x701; 1437 break; 1438 1439 case 0x0b0: /* GENERAL_PURPOSE1 */ 1440 case 0x0b4: /* GENERAL_PURPOSE2 */ 1441 case 0x0b8: /* GENERAL_PURPOSE3 */ 1442 case 0x0bc: /* GENERAL_PURPOSE4 */ 1443 case 0x0c0: /* GENERAL_PURPOSE5 */ 1444 case 0x0c4: /* GENERAL_PURPOSE6 */ 1445 case 0x0c8: /* GENERAL_PURPOSE7 */ 1446 case 0x0cc: /* GENERAL_PURPOSE8 */ 1447 case 0x0d0: /* GENERAL_PURPOSE9 */ 1448 case 0x0d4: /* GENERAL_PURPOSE10 */ 1449 case 0x0d8: /* GENERAL_PURPOSE11 */ 1450 case 0x0dc: /* GENERAL_PURPOSE12 */ 1451 case 0x0e0: /* GENERAL_PURPOSE13 */ 1452 case 0x0e4: /* GENERAL_PURPOSE14 */ 1453 case 0x0e8: /* GENERAL_PURPOSE15 */ 1454 case 0x0ec: /* GENERAL_PURPOSE16 */ 1455 case 0x0f0: /* GENERAL_PURPOSE17 */ 1456 case 0x0f4: /* GENERAL_PURPOSE18 */ 1457 case 0x0f8: /* GENERAL_PURPOSE19 */ 1458 case 0x0fc: /* GENERAL_PURPOSE20 */ 1459 s->scratch[(addr - 0xb0) >> 2] = value; 1460 break; 1461 1462 case 0x140: /* CM_CLKSEL_MPU */ 1463 s->clksel[0] = value & 0x1f; 1464 /* TODO update clocks */ 1465 break; 1466 case 0x148: /* CM_CLKSTCTRL_MPU */ 1467 s->clkctrl[0] = value & 0x1f; 1468 break; 1469 1470 case 0x158: /* RM_RSTST_MPU */ 1471 s->rst[0] &= ~value; 1472 break; 1473 case 0x1c8: /* PM_WKDEP_MPU */ 1474 s->wkup[0] = value & 0x15; 1475 break; 1476 1477 case 0x1d4: /* PM_EVGENCTRL_MPU */ 1478 s->ev = value & 0x1f; 1479 break; 1480 case 0x1d8: /* PM_EVEGENONTIM_MPU */ 1481 s->evtime[0] = value; 1482 break; 1483 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */ 1484 s->evtime[1] = value; 1485 break; 1486 1487 case 0x1e0: /* PM_PWSTCTRL_MPU */ 1488 s->power[0] = value & 0xc0f; 1489 break; 1490 1491 case 0x200: /* CM_FCLKEN1_CORE */ 1492 s->clken[0] = value & 0xbfffffff; 1493 /* TODO update clocks */ 1494 /* The EN_EAC bit only gets/puts func_96m_clk. */ 1495 break; 1496 case 0x204: /* CM_FCLKEN2_CORE */ 1497 s->clken[1] = value & 0x00000007; 1498 /* TODO update clocks */ 1499 break; 1500 case 0x210: /* CM_ICLKEN1_CORE */ 1501 s->clken[2] = value & 0xfffffff9; 1502 /* TODO update clocks */ 1503 /* The EN_EAC bit only gets/puts core_l4_iclk. */ 1504 break; 1505 case 0x214: /* CM_ICLKEN2_CORE */ 1506 s->clken[3] = value & 0x00000007; 1507 /* TODO update clocks */ 1508 break; 1509 case 0x21c: /* CM_ICLKEN4_CORE */ 1510 s->clken[4] = value & 0x0000001f; 1511 /* TODO update clocks */ 1512 break; 1513 1514 case 0x230: /* CM_AUTOIDLE1_CORE */ 1515 s->clkidle[0] = value & 0xfffffff9; 1516 /* TODO update clocks */ 1517 break; 1518 case 0x234: /* CM_AUTOIDLE2_CORE */ 1519 s->clkidle[1] = value & 0x00000007; 1520 /* TODO update clocks */ 1521 break; 1522 case 0x238: /* CM_AUTOIDLE3_CORE */ 1523 s->clkidle[2] = value & 0x00000007; 1524 /* TODO update clocks */ 1525 break; 1526 case 0x23c: /* CM_AUTOIDLE4_CORE */ 1527 s->clkidle[3] = value & 0x0000001f; 1528 /* TODO update clocks */ 1529 break; 1530 1531 case 0x240: /* CM_CLKSEL1_CORE */ 1532 s->clksel[1] = value & 0x0fffbf7f; 1533 /* TODO update clocks */ 1534 break; 1535 1536 case 0x244: /* CM_CLKSEL2_CORE */ 1537 s->clksel[2] = value & 0x00fffffc; 1538 /* TODO update clocks */ 1539 break; 1540 1541 case 0x248: /* CM_CLKSTCTRL_CORE */ 1542 s->clkctrl[1] = value & 0x7; 1543 break; 1544 1545 case 0x2a0: /* PM_WKEN1_CORE */ 1546 s->wken[0] = value & 0x04667ff8; 1547 break; 1548 case 0x2a4: /* PM_WKEN2_CORE */ 1549 s->wken[1] = value & 0x00000005; 1550 break; 1551 1552 case 0x2b0: /* PM_WKST1_CORE */ 1553 s->wkst[0] &= ~value; 1554 break; 1555 case 0x2b4: /* PM_WKST2_CORE */ 1556 s->wkst[1] &= ~value; 1557 break; 1558 1559 case 0x2e0: /* PM_PWSTCTRL_CORE */ 1560 s->power[1] = (value & 0x00fc3f) | (1 << 2); 1561 break; 1562 1563 case 0x300: /* CM_FCLKEN_GFX */ 1564 s->clken[5] = value & 6; 1565 /* TODO update clocks */ 1566 break; 1567 case 0x310: /* CM_ICLKEN_GFX */ 1568 s->clken[6] = value & 1; 1569 /* TODO update clocks */ 1570 break; 1571 case 0x340: /* CM_CLKSEL_GFX */ 1572 s->clksel[3] = value & 7; 1573 /* TODO update clocks */ 1574 break; 1575 case 0x348: /* CM_CLKSTCTRL_GFX */ 1576 s->clkctrl[2] = value & 1; 1577 break; 1578 case 0x350: /* RM_RSTCTRL_GFX */ 1579 s->rstctrl[0] = value & 1; 1580 /* TODO: reset */ 1581 break; 1582 case 0x358: /* RM_RSTST_GFX */ 1583 s->rst[1] &= ~value; 1584 break; 1585 case 0x3c8: /* PM_WKDEP_GFX */ 1586 s->wkup[1] = value & 0x13; 1587 break; 1588 case 0x3e0: /* PM_PWSTCTRL_GFX */ 1589 s->power[2] = (value & 0x00c0f) | (3 << 2); 1590 break; 1591 1592 case 0x400: /* CM_FCLKEN_WKUP */ 1593 s->clken[7] = value & 0xd; 1594 /* TODO update clocks */ 1595 break; 1596 case 0x410: /* CM_ICLKEN_WKUP */ 1597 s->clken[8] = value & 0x3f; 1598 /* TODO update clocks */ 1599 break; 1600 case 0x430: /* CM_AUTOIDLE_WKUP */ 1601 s->clkidle[4] = value & 0x0000003f; 1602 /* TODO update clocks */ 1603 break; 1604 case 0x440: /* CM_CLKSEL_WKUP */ 1605 s->clksel[4] = value & 3; 1606 /* TODO update clocks */ 1607 break; 1608 case 0x450: /* RM_RSTCTRL_WKUP */ 1609 /* TODO: reset */ 1610 if (value & 2) 1611 qemu_system_reset_request(); 1612 break; 1613 case 0x454: /* RM_RSTTIME_WKUP */ 1614 s->rsttime_wkup = value & 0x1fff; 1615 break; 1616 case 0x458: /* RM_RSTST_WKUP */ 1617 s->rst[2] &= ~value; 1618 break; 1619 case 0x4a0: /* PM_WKEN_WKUP */ 1620 s->wken[2] = value & 0x00000005; 1621 break; 1622 case 0x4b0: /* PM_WKST_WKUP */ 1623 s->wkst[2] &= ~value; 1624 break; 1625 1626 case 0x500: /* CM_CLKEN_PLL */ 1627 if (value & 0xffffff30) 1628 fprintf(stderr, "%s: write 0s in CM_CLKEN_PLL for " 1629 "future compatibility\n", __FUNCTION__); 1630 if ((s->clken[9] ^ value) & 0xcc) { 1631 s->clken[9] &= ~0xcc; 1632 s->clken[9] |= value & 0xcc; 1633 omap_prcm_apll_update(s); 1634 } 1635 if ((s->clken[9] ^ value) & 3) { 1636 s->clken[9] &= ~3; 1637 s->clken[9] |= value & 3; 1638 omap_prcm_dpll_update(s); 1639 } 1640 break; 1641 case 0x530: /* CM_AUTOIDLE_PLL */ 1642 s->clkidle[5] = value & 0x000000cf; 1643 /* TODO update clocks */ 1644 break; 1645 case 0x540: /* CM_CLKSEL1_PLL */ 1646 if (value & 0xfc4000d7) 1647 fprintf(stderr, "%s: write 0s in CM_CLKSEL1_PLL for " 1648 "future compatibility\n", __FUNCTION__); 1649 if ((s->clksel[5] ^ value) & 0x003fff00) { 1650 s->clksel[5] = value & 0x03bfff28; 1651 omap_prcm_dpll_update(s); 1652 } 1653 /* TODO update the other clocks */ 1654 1655 s->clksel[5] = value & 0x03bfff28; 1656 break; 1657 case 0x544: /* CM_CLKSEL2_PLL */ 1658 if (value & ~3) 1659 fprintf(stderr, "%s: write 0s in CM_CLKSEL2_PLL[31:2] for " 1660 "future compatibility\n", __FUNCTION__); 1661 if (s->clksel[6] != (value & 3)) { 1662 s->clksel[6] = value & 3; 1663 omap_prcm_dpll_update(s); 1664 } 1665 break; 1666 1667 case 0x800: /* CM_FCLKEN_DSP */ 1668 s->clken[10] = value & 0x501; 1669 /* TODO update clocks */ 1670 break; 1671 case 0x810: /* CM_ICLKEN_DSP */ 1672 s->clken[11] = value & 0x2; 1673 /* TODO update clocks */ 1674 break; 1675 case 0x830: /* CM_AUTOIDLE_DSP */ 1676 s->clkidle[6] = value & 0x2; 1677 /* TODO update clocks */ 1678 break; 1679 case 0x840: /* CM_CLKSEL_DSP */ 1680 s->clksel[7] = value & 0x3fff; 1681 /* TODO update clocks */ 1682 break; 1683 case 0x848: /* CM_CLKSTCTRL_DSP */ 1684 s->clkctrl[3] = value & 0x101; 1685 break; 1686 case 0x850: /* RM_RSTCTRL_DSP */ 1687 /* TODO: reset */ 1688 break; 1689 case 0x858: /* RM_RSTST_DSP */ 1690 s->rst[3] &= ~value; 1691 break; 1692 case 0x8c8: /* PM_WKDEP_DSP */ 1693 s->wkup[2] = value & 0x13; 1694 break; 1695 case 0x8e0: /* PM_PWSTCTRL_DSP */ 1696 s->power[3] = (value & 0x03017) | (3 << 2); 1697 break; 1698 1699 case 0x8f0: /* PRCM_IRQSTATUS_DSP */ 1700 s->irqst[1] &= ~value; 1701 omap_prcm_int_update(s, 1); 1702 break; 1703 case 0x8f4: /* PRCM_IRQENABLE_DSP */ 1704 s->irqen[1] = value & 0x7; 1705 omap_prcm_int_update(s, 1); 1706 break; 1707 1708 case 0x8f8: /* PRCM_IRQSTATUS_IVA */ 1709 s->irqst[2] &= ~value; 1710 omap_prcm_int_update(s, 2); 1711 break; 1712 case 0x8fc: /* PRCM_IRQENABLE_IVA */ 1713 s->irqen[2] = value & 0x7; 1714 omap_prcm_int_update(s, 2); 1715 break; 1716 1717 default: 1718 OMAP_BAD_REG(addr); 1719 return; 1720 } 1721 } 1722 1723 static const MemoryRegionOps omap_prcm_ops = { 1724 .read = omap_prcm_read, 1725 .write = omap_prcm_write, 1726 .endianness = DEVICE_NATIVE_ENDIAN, 1727 }; 1728 1729 static void omap_prcm_reset(struct omap_prcm_s *s) 1730 { 1731 s->sysconfig = 0; 1732 s->irqst[0] = 0; 1733 s->irqst[1] = 0; 1734 s->irqst[2] = 0; 1735 s->irqen[0] = 0; 1736 s->irqen[1] = 0; 1737 s->irqen[2] = 0; 1738 s->voltctrl = 0x1040; 1739 s->ev = 0x14; 1740 s->evtime[0] = 0; 1741 s->evtime[1] = 0; 1742 s->clkctrl[0] = 0; 1743 s->clkctrl[1] = 0; 1744 s->clkctrl[2] = 0; 1745 s->clkctrl[3] = 0; 1746 s->clken[1] = 7; 1747 s->clken[3] = 7; 1748 s->clken[4] = 0; 1749 s->clken[5] = 0; 1750 s->clken[6] = 0; 1751 s->clken[7] = 0xc; 1752 s->clken[8] = 0x3e; 1753 s->clken[9] = 0x0d; 1754 s->clken[10] = 0; 1755 s->clken[11] = 0; 1756 s->clkidle[0] = 0; 1757 s->clkidle[2] = 7; 1758 s->clkidle[3] = 0; 1759 s->clkidle[4] = 0; 1760 s->clkidle[5] = 0x0c; 1761 s->clkidle[6] = 0; 1762 s->clksel[0] = 0x01; 1763 s->clksel[1] = 0x02100121; 1764 s->clksel[2] = 0x00000000; 1765 s->clksel[3] = 0x01; 1766 s->clksel[4] = 0; 1767 s->clksel[7] = 0x0121; 1768 s->wkup[0] = 0x15; 1769 s->wkup[1] = 0x13; 1770 s->wkup[2] = 0x13; 1771 s->wken[0] = 0x04667ff8; 1772 s->wken[1] = 0x00000005; 1773 s->wken[2] = 5; 1774 s->wkst[0] = 0; 1775 s->wkst[1] = 0; 1776 s->wkst[2] = 0; 1777 s->power[0] = 0x00c; 1778 s->power[1] = 4; 1779 s->power[2] = 0x0000c; 1780 s->power[3] = 0x14; 1781 s->rstctrl[0] = 1; 1782 s->rst[3] = 1; 1783 omap_prcm_apll_update(s); 1784 omap_prcm_dpll_update(s); 1785 } 1786 1787 static void omap_prcm_coldreset(struct omap_prcm_s *s) 1788 { 1789 s->setuptime[0] = 0; 1790 s->setuptime[1] = 0; 1791 memset(&s->scratch, 0, sizeof(s->scratch)); 1792 s->rst[0] = 0x01; 1793 s->rst[1] = 0x00; 1794 s->rst[2] = 0x01; 1795 s->clken[0] = 0; 1796 s->clken[2] = 0; 1797 s->clkidle[1] = 0; 1798 s->clksel[5] = 0; 1799 s->clksel[6] = 2; 1800 s->clksrc[0] = 0x43; 1801 s->clkout[0] = 0x0303; 1802 s->clkemul[0] = 0; 1803 s->clkpol[0] = 0x100; 1804 s->rsttime_wkup = 0x1002; 1805 1806 omap_prcm_reset(s); 1807 } 1808 1809 static struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta, 1810 qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int, 1811 struct omap_mpu_state_s *mpu) 1812 { 1813 struct omap_prcm_s *s = g_new0(struct omap_prcm_s, 1); 1814 1815 s->irq[0] = mpu_int; 1816 s->irq[1] = dsp_int; 1817 s->irq[2] = iva_int; 1818 s->mpu = mpu; 1819 omap_prcm_coldreset(s); 1820 1821 memory_region_init_io(&s->iomem0, NULL, &omap_prcm_ops, s, "omap.pcrm0", 1822 omap_l4_region_size(ta, 0)); 1823 memory_region_init_io(&s->iomem1, NULL, &omap_prcm_ops, s, "omap.pcrm1", 1824 omap_l4_region_size(ta, 1)); 1825 omap_l4_attach(ta, 0, &s->iomem0); 1826 omap_l4_attach(ta, 1, &s->iomem1); 1827 1828 return s; 1829 } 1830 1831 /* System and Pinout control */ 1832 struct omap_sysctl_s { 1833 struct omap_mpu_state_s *mpu; 1834 MemoryRegion iomem; 1835 1836 uint32_t sysconfig; 1837 uint32_t devconfig; 1838 uint32_t psaconfig; 1839 uint32_t padconf[0x45]; 1840 uint8_t obs; 1841 uint32_t msuspendmux[5]; 1842 }; 1843 1844 static uint32_t omap_sysctl_read8(void *opaque, hwaddr addr) 1845 { 1846 1847 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; 1848 int pad_offset, byte_offset; 1849 int value; 1850 1851 switch (addr) { 1852 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */ 1853 pad_offset = (addr - 0x30) >> 2; 1854 byte_offset = (addr - 0x30) & (4 - 1); 1855 1856 value = s->padconf[pad_offset]; 1857 value = (value >> (byte_offset * 8)) & 0xff; 1858 1859 return value; 1860 1861 default: 1862 break; 1863 } 1864 1865 OMAP_BAD_REG(addr); 1866 return 0; 1867 } 1868 1869 static uint32_t omap_sysctl_read(void *opaque, hwaddr addr) 1870 { 1871 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; 1872 1873 switch (addr) { 1874 case 0x000: /* CONTROL_REVISION */ 1875 return 0x20; 1876 1877 case 0x010: /* CONTROL_SYSCONFIG */ 1878 return s->sysconfig; 1879 1880 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */ 1881 return s->padconf[(addr - 0x30) >> 2]; 1882 1883 case 0x270: /* CONTROL_DEBOBS */ 1884 return s->obs; 1885 1886 case 0x274: /* CONTROL_DEVCONF */ 1887 return s->devconfig; 1888 1889 case 0x28c: /* CONTROL_EMU_SUPPORT */ 1890 return 0; 1891 1892 case 0x290: /* CONTROL_MSUSPENDMUX_0 */ 1893 return s->msuspendmux[0]; 1894 case 0x294: /* CONTROL_MSUSPENDMUX_1 */ 1895 return s->msuspendmux[1]; 1896 case 0x298: /* CONTROL_MSUSPENDMUX_2 */ 1897 return s->msuspendmux[2]; 1898 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */ 1899 return s->msuspendmux[3]; 1900 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */ 1901 return s->msuspendmux[4]; 1902 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */ 1903 return 0; 1904 1905 case 0x2b8: /* CONTROL_PSA_CTRL */ 1906 return s->psaconfig; 1907 case 0x2bc: /* CONTROL_PSA_CMD */ 1908 case 0x2c0: /* CONTROL_PSA_VALUE */ 1909 return 0; 1910 1911 case 0x2b0: /* CONTROL_SEC_CTRL */ 1912 return 0x800000f1; 1913 case 0x2d0: /* CONTROL_SEC_EMU */ 1914 return 0x80000015; 1915 case 0x2d4: /* CONTROL_SEC_TAP */ 1916 return 0x8000007f; 1917 case 0x2b4: /* CONTROL_SEC_TEST */ 1918 case 0x2f0: /* CONTROL_SEC_STATUS */ 1919 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */ 1920 /* Secure mode is not present on general-pusrpose device. Outside 1921 * secure mode these values cannot be read or written. */ 1922 return 0; 1923 1924 case 0x2d8: /* CONTROL_OCM_RAM_PERM */ 1925 return 0xff; 1926 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */ 1927 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */ 1928 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */ 1929 /* No secure mode so no Extended Secure RAM present. */ 1930 return 0; 1931 1932 case 0x2f8: /* CONTROL_STATUS */ 1933 /* Device Type => General-purpose */ 1934 return 0x0300; 1935 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */ 1936 1937 case 0x300: /* CONTROL_RPUB_KEY_H_0 */ 1938 case 0x304: /* CONTROL_RPUB_KEY_H_1 */ 1939 case 0x308: /* CONTROL_RPUB_KEY_H_2 */ 1940 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */ 1941 return 0xdecafbad; 1942 1943 case 0x310: /* CONTROL_RAND_KEY_0 */ 1944 case 0x314: /* CONTROL_RAND_KEY_1 */ 1945 case 0x318: /* CONTROL_RAND_KEY_2 */ 1946 case 0x31c: /* CONTROL_RAND_KEY_3 */ 1947 case 0x320: /* CONTROL_CUST_KEY_0 */ 1948 case 0x324: /* CONTROL_CUST_KEY_1 */ 1949 case 0x330: /* CONTROL_TEST_KEY_0 */ 1950 case 0x334: /* CONTROL_TEST_KEY_1 */ 1951 case 0x338: /* CONTROL_TEST_KEY_2 */ 1952 case 0x33c: /* CONTROL_TEST_KEY_3 */ 1953 case 0x340: /* CONTROL_TEST_KEY_4 */ 1954 case 0x344: /* CONTROL_TEST_KEY_5 */ 1955 case 0x348: /* CONTROL_TEST_KEY_6 */ 1956 case 0x34c: /* CONTROL_TEST_KEY_7 */ 1957 case 0x350: /* CONTROL_TEST_KEY_8 */ 1958 case 0x354: /* CONTROL_TEST_KEY_9 */ 1959 /* Can only be accessed in secure mode and when C_FieldAccEnable 1960 * bit is set in CONTROL_SEC_CTRL. 1961 * TODO: otherwise an interconnect access error is generated. */ 1962 return 0; 1963 } 1964 1965 OMAP_BAD_REG(addr); 1966 return 0; 1967 } 1968 1969 static void omap_sysctl_write8(void *opaque, hwaddr addr, 1970 uint32_t value) 1971 { 1972 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; 1973 int pad_offset, byte_offset; 1974 int prev_value; 1975 1976 switch (addr) { 1977 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */ 1978 pad_offset = (addr - 0x30) >> 2; 1979 byte_offset = (addr - 0x30) & (4 - 1); 1980 1981 prev_value = s->padconf[pad_offset]; 1982 prev_value &= ~(0xff << (byte_offset * 8)); 1983 prev_value |= ((value & 0x1f1f1f1f) << (byte_offset * 8)) & 0x1f1f1f1f; 1984 s->padconf[pad_offset] = prev_value; 1985 break; 1986 1987 default: 1988 OMAP_BAD_REG(addr); 1989 break; 1990 } 1991 } 1992 1993 static void omap_sysctl_write(void *opaque, hwaddr addr, 1994 uint32_t value) 1995 { 1996 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; 1997 1998 switch (addr) { 1999 case 0x000: /* CONTROL_REVISION */ 2000 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */ 2001 case 0x2c0: /* CONTROL_PSA_VALUE */ 2002 case 0x2f8: /* CONTROL_STATUS */ 2003 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */ 2004 case 0x300: /* CONTROL_RPUB_KEY_H_0 */ 2005 case 0x304: /* CONTROL_RPUB_KEY_H_1 */ 2006 case 0x308: /* CONTROL_RPUB_KEY_H_2 */ 2007 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */ 2008 case 0x310: /* CONTROL_RAND_KEY_0 */ 2009 case 0x314: /* CONTROL_RAND_KEY_1 */ 2010 case 0x318: /* CONTROL_RAND_KEY_2 */ 2011 case 0x31c: /* CONTROL_RAND_KEY_3 */ 2012 case 0x320: /* CONTROL_CUST_KEY_0 */ 2013 case 0x324: /* CONTROL_CUST_KEY_1 */ 2014 case 0x330: /* CONTROL_TEST_KEY_0 */ 2015 case 0x334: /* CONTROL_TEST_KEY_1 */ 2016 case 0x338: /* CONTROL_TEST_KEY_2 */ 2017 case 0x33c: /* CONTROL_TEST_KEY_3 */ 2018 case 0x340: /* CONTROL_TEST_KEY_4 */ 2019 case 0x344: /* CONTROL_TEST_KEY_5 */ 2020 case 0x348: /* CONTROL_TEST_KEY_6 */ 2021 case 0x34c: /* CONTROL_TEST_KEY_7 */ 2022 case 0x350: /* CONTROL_TEST_KEY_8 */ 2023 case 0x354: /* CONTROL_TEST_KEY_9 */ 2024 OMAP_RO_REG(addr); 2025 return; 2026 2027 case 0x010: /* CONTROL_SYSCONFIG */ 2028 s->sysconfig = value & 0x1e; 2029 break; 2030 2031 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */ 2032 /* XXX: should check constant bits */ 2033 s->padconf[(addr - 0x30) >> 2] = value & 0x1f1f1f1f; 2034 break; 2035 2036 case 0x270: /* CONTROL_DEBOBS */ 2037 s->obs = value & 0xff; 2038 break; 2039 2040 case 0x274: /* CONTROL_DEVCONF */ 2041 s->devconfig = value & 0xffffc7ff; 2042 break; 2043 2044 case 0x28c: /* CONTROL_EMU_SUPPORT */ 2045 break; 2046 2047 case 0x290: /* CONTROL_MSUSPENDMUX_0 */ 2048 s->msuspendmux[0] = value & 0x3fffffff; 2049 break; 2050 case 0x294: /* CONTROL_MSUSPENDMUX_1 */ 2051 s->msuspendmux[1] = value & 0x3fffffff; 2052 break; 2053 case 0x298: /* CONTROL_MSUSPENDMUX_2 */ 2054 s->msuspendmux[2] = value & 0x3fffffff; 2055 break; 2056 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */ 2057 s->msuspendmux[3] = value & 0x3fffffff; 2058 break; 2059 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */ 2060 s->msuspendmux[4] = value & 0x3fffffff; 2061 break; 2062 2063 case 0x2b8: /* CONTROL_PSA_CTRL */ 2064 s->psaconfig = value & 0x1c; 2065 s->psaconfig |= (value & 0x20) ? 2 : 1; 2066 break; 2067 case 0x2bc: /* CONTROL_PSA_CMD */ 2068 break; 2069 2070 case 0x2b0: /* CONTROL_SEC_CTRL */ 2071 case 0x2b4: /* CONTROL_SEC_TEST */ 2072 case 0x2d0: /* CONTROL_SEC_EMU */ 2073 case 0x2d4: /* CONTROL_SEC_TAP */ 2074 case 0x2d8: /* CONTROL_OCM_RAM_PERM */ 2075 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */ 2076 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */ 2077 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */ 2078 case 0x2f0: /* CONTROL_SEC_STATUS */ 2079 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */ 2080 break; 2081 2082 default: 2083 OMAP_BAD_REG(addr); 2084 return; 2085 } 2086 } 2087 2088 static const MemoryRegionOps omap_sysctl_ops = { 2089 .old_mmio = { 2090 .read = { 2091 omap_sysctl_read8, 2092 omap_badwidth_read32, /* TODO */ 2093 omap_sysctl_read, 2094 }, 2095 .write = { 2096 omap_sysctl_write8, 2097 omap_badwidth_write32, /* TODO */ 2098 omap_sysctl_write, 2099 }, 2100 }, 2101 .endianness = DEVICE_NATIVE_ENDIAN, 2102 }; 2103 2104 static void omap_sysctl_reset(struct omap_sysctl_s *s) 2105 { 2106 /* (power-on reset) */ 2107 s->sysconfig = 0; 2108 s->obs = 0; 2109 s->devconfig = 0x0c000000; 2110 s->msuspendmux[0] = 0x00000000; 2111 s->msuspendmux[1] = 0x00000000; 2112 s->msuspendmux[2] = 0x00000000; 2113 s->msuspendmux[3] = 0x00000000; 2114 s->msuspendmux[4] = 0x00000000; 2115 s->psaconfig = 1; 2116 2117 s->padconf[0x00] = 0x000f0f0f; 2118 s->padconf[0x01] = 0x00000000; 2119 s->padconf[0x02] = 0x00000000; 2120 s->padconf[0x03] = 0x00000000; 2121 s->padconf[0x04] = 0x00000000; 2122 s->padconf[0x05] = 0x00000000; 2123 s->padconf[0x06] = 0x00000000; 2124 s->padconf[0x07] = 0x00000000; 2125 s->padconf[0x08] = 0x08080800; 2126 s->padconf[0x09] = 0x08080808; 2127 s->padconf[0x0a] = 0x08080808; 2128 s->padconf[0x0b] = 0x08080808; 2129 s->padconf[0x0c] = 0x08080808; 2130 s->padconf[0x0d] = 0x08080800; 2131 s->padconf[0x0e] = 0x08080808; 2132 s->padconf[0x0f] = 0x08080808; 2133 s->padconf[0x10] = 0x18181808; /* | 0x07070700 if SBoot3 */ 2134 s->padconf[0x11] = 0x18181818; /* | 0x07070707 if SBoot3 */ 2135 s->padconf[0x12] = 0x18181818; /* | 0x07070707 if SBoot3 */ 2136 s->padconf[0x13] = 0x18181818; /* | 0x07070707 if SBoot3 */ 2137 s->padconf[0x14] = 0x18181818; /* | 0x00070707 if SBoot3 */ 2138 s->padconf[0x15] = 0x18181818; 2139 s->padconf[0x16] = 0x18181818; /* | 0x07000000 if SBoot3 */ 2140 s->padconf[0x17] = 0x1f001f00; 2141 s->padconf[0x18] = 0x1f1f1f1f; 2142 s->padconf[0x19] = 0x00000000; 2143 s->padconf[0x1a] = 0x1f180000; 2144 s->padconf[0x1b] = 0x00001f1f; 2145 s->padconf[0x1c] = 0x1f001f00; 2146 s->padconf[0x1d] = 0x00000000; 2147 s->padconf[0x1e] = 0x00000000; 2148 s->padconf[0x1f] = 0x08000000; 2149 s->padconf[0x20] = 0x08080808; 2150 s->padconf[0x21] = 0x08080808; 2151 s->padconf[0x22] = 0x0f080808; 2152 s->padconf[0x23] = 0x0f0f0f0f; 2153 s->padconf[0x24] = 0x000f0f0f; 2154 s->padconf[0x25] = 0x1f1f1f0f; 2155 s->padconf[0x26] = 0x080f0f1f; 2156 s->padconf[0x27] = 0x070f1808; 2157 s->padconf[0x28] = 0x0f070707; 2158 s->padconf[0x29] = 0x000f0f1f; 2159 s->padconf[0x2a] = 0x0f0f0f1f; 2160 s->padconf[0x2b] = 0x08000000; 2161 s->padconf[0x2c] = 0x0000001f; 2162 s->padconf[0x2d] = 0x0f0f1f00; 2163 s->padconf[0x2e] = 0x1f1f0f0f; 2164 s->padconf[0x2f] = 0x0f1f1f1f; 2165 s->padconf[0x30] = 0x0f0f0f0f; 2166 s->padconf[0x31] = 0x0f1f0f1f; 2167 s->padconf[0x32] = 0x0f0f0f0f; 2168 s->padconf[0x33] = 0x0f1f0f1f; 2169 s->padconf[0x34] = 0x1f1f0f0f; 2170 s->padconf[0x35] = 0x0f0f1f1f; 2171 s->padconf[0x36] = 0x0f0f1f0f; 2172 s->padconf[0x37] = 0x0f0f0f0f; 2173 s->padconf[0x38] = 0x1f18180f; 2174 s->padconf[0x39] = 0x1f1f1f1f; 2175 s->padconf[0x3a] = 0x00001f1f; 2176 s->padconf[0x3b] = 0x00000000; 2177 s->padconf[0x3c] = 0x00000000; 2178 s->padconf[0x3d] = 0x0f0f0f0f; 2179 s->padconf[0x3e] = 0x18000f0f; 2180 s->padconf[0x3f] = 0x00070000; 2181 s->padconf[0x40] = 0x00000707; 2182 s->padconf[0x41] = 0x0f1f0700; 2183 s->padconf[0x42] = 0x1f1f070f; 2184 s->padconf[0x43] = 0x0008081f; 2185 s->padconf[0x44] = 0x00000800; 2186 } 2187 2188 static struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta, 2189 omap_clk iclk, struct omap_mpu_state_s *mpu) 2190 { 2191 struct omap_sysctl_s *s = g_new0(struct omap_sysctl_s, 1); 2192 2193 s->mpu = mpu; 2194 omap_sysctl_reset(s); 2195 2196 memory_region_init_io(&s->iomem, NULL, &omap_sysctl_ops, s, "omap.sysctl", 2197 omap_l4_region_size(ta, 0)); 2198 omap_l4_attach(ta, 0, &s->iomem); 2199 2200 return s; 2201 } 2202 2203 /* General chip reset */ 2204 static void omap2_mpu_reset(void *opaque) 2205 { 2206 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; 2207 2208 omap_dma_reset(mpu->dma); 2209 omap_prcm_reset(mpu->prcm); 2210 omap_sysctl_reset(mpu->sysc); 2211 omap_gp_timer_reset(mpu->gptimer[0]); 2212 omap_gp_timer_reset(mpu->gptimer[1]); 2213 omap_gp_timer_reset(mpu->gptimer[2]); 2214 omap_gp_timer_reset(mpu->gptimer[3]); 2215 omap_gp_timer_reset(mpu->gptimer[4]); 2216 omap_gp_timer_reset(mpu->gptimer[5]); 2217 omap_gp_timer_reset(mpu->gptimer[6]); 2218 omap_gp_timer_reset(mpu->gptimer[7]); 2219 omap_gp_timer_reset(mpu->gptimer[8]); 2220 omap_gp_timer_reset(mpu->gptimer[9]); 2221 omap_gp_timer_reset(mpu->gptimer[10]); 2222 omap_gp_timer_reset(mpu->gptimer[11]); 2223 omap_synctimer_reset(mpu->synctimer); 2224 omap_sdrc_reset(mpu->sdrc); 2225 omap_gpmc_reset(mpu->gpmc); 2226 omap_dss_reset(mpu->dss); 2227 omap_uart_reset(mpu->uart[0]); 2228 omap_uart_reset(mpu->uart[1]); 2229 omap_uart_reset(mpu->uart[2]); 2230 omap_mmc_reset(mpu->mmc); 2231 omap_mcspi_reset(mpu->mcspi[0]); 2232 omap_mcspi_reset(mpu->mcspi[1]); 2233 cpu_reset(CPU(mpu->cpu)); 2234 } 2235 2236 static int omap2_validate_addr(struct omap_mpu_state_s *s, 2237 hwaddr addr) 2238 { 2239 return 1; 2240 } 2241 2242 static const struct dma_irq_map omap2_dma_irq_map[] = { 2243 { 0, OMAP_INT_24XX_SDMA_IRQ0 }, 2244 { 0, OMAP_INT_24XX_SDMA_IRQ1 }, 2245 { 0, OMAP_INT_24XX_SDMA_IRQ2 }, 2246 { 0, OMAP_INT_24XX_SDMA_IRQ3 }, 2247 }; 2248 2249 struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem, 2250 unsigned long sdram_size, 2251 const char *core) 2252 { 2253 struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1); 2254 qemu_irq dma_irqs[4]; 2255 DriveInfo *dinfo; 2256 int i; 2257 SysBusDevice *busdev; 2258 struct omap_target_agent_s *ta; 2259 2260 /* Core */ 2261 s->mpu_model = omap2420; 2262 s->cpu = cpu_arm_init(core ?: "arm1136-r2"); 2263 if (s->cpu == NULL) { 2264 fprintf(stderr, "Unable to find CPU definition\n"); 2265 exit(1); 2266 } 2267 s->sdram_size = sdram_size; 2268 s->sram_size = OMAP242X_SRAM_SIZE; 2269 2270 s->wakeup = qemu_allocate_irq(omap_mpu_wakeup, s, 0); 2271 2272 /* Clocks */ 2273 omap_clk_init(s); 2274 2275 /* Memory-mapped stuff */ 2276 memory_region_allocate_system_memory(&s->sdram, NULL, "omap2.dram", 2277 s->sdram_size); 2278 memory_region_add_subregion(sysmem, OMAP2_Q2_BASE, &s->sdram); 2279 memory_region_init_ram(&s->sram, NULL, "omap2.sram", s->sram_size, 2280 &error_fatal); 2281 vmstate_register_ram_global(&s->sram); 2282 memory_region_add_subregion(sysmem, OMAP2_SRAM_BASE, &s->sram); 2283 2284 s->l4 = omap_l4_init(sysmem, OMAP2_L4_BASE, 54); 2285 2286 /* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */ 2287 s->ih[0] = qdev_create(NULL, "omap2-intc"); 2288 qdev_prop_set_uint8(s->ih[0], "revision", 0x21); 2289 qdev_prop_set_ptr(s->ih[0], "fclk", omap_findclk(s, "mpu_intc_fclk")); 2290 qdev_prop_set_ptr(s->ih[0], "iclk", omap_findclk(s, "mpu_intc_iclk")); 2291 qdev_init_nofail(s->ih[0]); 2292 busdev = SYS_BUS_DEVICE(s->ih[0]); 2293 sysbus_connect_irq(busdev, 0, 2294 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ)); 2295 sysbus_connect_irq(busdev, 1, 2296 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ)); 2297 sysbus_mmio_map(busdev, 0, 0x480fe000); 2298 s->prcm = omap_prcm_init(omap_l4tao(s->l4, 3), 2299 qdev_get_gpio_in(s->ih[0], 2300 OMAP_INT_24XX_PRCM_MPU_IRQ), 2301 NULL, NULL, s); 2302 2303 s->sysc = omap_sysctl_init(omap_l4tao(s->l4, 1), 2304 omap_findclk(s, "omapctrl_iclk"), s); 2305 2306 for (i = 0; i < 4; i++) { 2307 dma_irqs[i] = qdev_get_gpio_in(s->ih[omap2_dma_irq_map[i].ih], 2308 omap2_dma_irq_map[i].intr); 2309 } 2310 s->dma = omap_dma4_init(0x48056000, dma_irqs, sysmem, s, 256, 32, 2311 omap_findclk(s, "sdma_iclk"), 2312 omap_findclk(s, "sdma_fclk")); 2313 s->port->addr_valid = omap2_validate_addr; 2314 2315 /* Register SDRAM and SRAM ports for fast DMA transfers. */ 2316 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->sdram), 2317 OMAP2_Q2_BASE, s->sdram_size); 2318 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->sram), 2319 OMAP2_SRAM_BASE, s->sram_size); 2320 2321 s->uart[0] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 19), 2322 qdev_get_gpio_in(s->ih[0], 2323 OMAP_INT_24XX_UART1_IRQ), 2324 omap_findclk(s, "uart1_fclk"), 2325 omap_findclk(s, "uart1_iclk"), 2326 s->drq[OMAP24XX_DMA_UART1_TX], 2327 s->drq[OMAP24XX_DMA_UART1_RX], 2328 "uart1", 2329 serial_hds[0]); 2330 s->uart[1] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 20), 2331 qdev_get_gpio_in(s->ih[0], 2332 OMAP_INT_24XX_UART2_IRQ), 2333 omap_findclk(s, "uart2_fclk"), 2334 omap_findclk(s, "uart2_iclk"), 2335 s->drq[OMAP24XX_DMA_UART2_TX], 2336 s->drq[OMAP24XX_DMA_UART2_RX], 2337 "uart2", 2338 serial_hds[0] ? serial_hds[1] : NULL); 2339 s->uart[2] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 21), 2340 qdev_get_gpio_in(s->ih[0], 2341 OMAP_INT_24XX_UART3_IRQ), 2342 omap_findclk(s, "uart3_fclk"), 2343 omap_findclk(s, "uart3_iclk"), 2344 s->drq[OMAP24XX_DMA_UART3_TX], 2345 s->drq[OMAP24XX_DMA_UART3_RX], 2346 "uart3", 2347 serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL); 2348 2349 s->gptimer[0] = omap_gp_timer_init(omap_l4ta(s->l4, 7), 2350 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER1), 2351 omap_findclk(s, "wu_gpt1_clk"), 2352 omap_findclk(s, "wu_l4_iclk")); 2353 s->gptimer[1] = omap_gp_timer_init(omap_l4ta(s->l4, 8), 2354 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER2), 2355 omap_findclk(s, "core_gpt2_clk"), 2356 omap_findclk(s, "core_l4_iclk")); 2357 s->gptimer[2] = omap_gp_timer_init(omap_l4ta(s->l4, 22), 2358 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER3), 2359 omap_findclk(s, "core_gpt3_clk"), 2360 omap_findclk(s, "core_l4_iclk")); 2361 s->gptimer[3] = omap_gp_timer_init(omap_l4ta(s->l4, 23), 2362 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER4), 2363 omap_findclk(s, "core_gpt4_clk"), 2364 omap_findclk(s, "core_l4_iclk")); 2365 s->gptimer[4] = omap_gp_timer_init(omap_l4ta(s->l4, 24), 2366 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER5), 2367 omap_findclk(s, "core_gpt5_clk"), 2368 omap_findclk(s, "core_l4_iclk")); 2369 s->gptimer[5] = omap_gp_timer_init(omap_l4ta(s->l4, 25), 2370 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER6), 2371 omap_findclk(s, "core_gpt6_clk"), 2372 omap_findclk(s, "core_l4_iclk")); 2373 s->gptimer[6] = omap_gp_timer_init(omap_l4ta(s->l4, 26), 2374 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER7), 2375 omap_findclk(s, "core_gpt7_clk"), 2376 omap_findclk(s, "core_l4_iclk")); 2377 s->gptimer[7] = omap_gp_timer_init(omap_l4ta(s->l4, 27), 2378 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER8), 2379 omap_findclk(s, "core_gpt8_clk"), 2380 omap_findclk(s, "core_l4_iclk")); 2381 s->gptimer[8] = omap_gp_timer_init(omap_l4ta(s->l4, 28), 2382 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER9), 2383 omap_findclk(s, "core_gpt9_clk"), 2384 omap_findclk(s, "core_l4_iclk")); 2385 s->gptimer[9] = omap_gp_timer_init(omap_l4ta(s->l4, 29), 2386 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER10), 2387 omap_findclk(s, "core_gpt10_clk"), 2388 omap_findclk(s, "core_l4_iclk")); 2389 s->gptimer[10] = omap_gp_timer_init(omap_l4ta(s->l4, 30), 2390 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER11), 2391 omap_findclk(s, "core_gpt11_clk"), 2392 omap_findclk(s, "core_l4_iclk")); 2393 s->gptimer[11] = omap_gp_timer_init(omap_l4ta(s->l4, 31), 2394 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER12), 2395 omap_findclk(s, "core_gpt12_clk"), 2396 omap_findclk(s, "core_l4_iclk")); 2397 2398 omap_tap_init(omap_l4ta(s->l4, 2), s); 2399 2400 s->synctimer = omap_synctimer_init(omap_l4tao(s->l4, 2), s, 2401 omap_findclk(s, "clk32-kHz"), 2402 omap_findclk(s, "core_l4_iclk")); 2403 2404 s->i2c[0] = qdev_create(NULL, "omap_i2c"); 2405 qdev_prop_set_uint8(s->i2c[0], "revision", 0x34); 2406 qdev_prop_set_ptr(s->i2c[0], "iclk", omap_findclk(s, "i2c1.iclk")); 2407 qdev_prop_set_ptr(s->i2c[0], "fclk", omap_findclk(s, "i2c1.fclk")); 2408 qdev_init_nofail(s->i2c[0]); 2409 busdev = SYS_BUS_DEVICE(s->i2c[0]); 2410 sysbus_connect_irq(busdev, 0, 2411 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C1_IRQ)); 2412 sysbus_connect_irq(busdev, 1, s->drq[OMAP24XX_DMA_I2C1_TX]); 2413 sysbus_connect_irq(busdev, 2, s->drq[OMAP24XX_DMA_I2C1_RX]); 2414 sysbus_mmio_map(busdev, 0, omap_l4_region_base(omap_l4tao(s->l4, 5), 0)); 2415 2416 s->i2c[1] = qdev_create(NULL, "omap_i2c"); 2417 qdev_prop_set_uint8(s->i2c[1], "revision", 0x34); 2418 qdev_prop_set_ptr(s->i2c[1], "iclk", omap_findclk(s, "i2c2.iclk")); 2419 qdev_prop_set_ptr(s->i2c[1], "fclk", omap_findclk(s, "i2c2.fclk")); 2420 qdev_init_nofail(s->i2c[1]); 2421 busdev = SYS_BUS_DEVICE(s->i2c[1]); 2422 sysbus_connect_irq(busdev, 0, 2423 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C2_IRQ)); 2424 sysbus_connect_irq(busdev, 1, s->drq[OMAP24XX_DMA_I2C2_TX]); 2425 sysbus_connect_irq(busdev, 2, s->drq[OMAP24XX_DMA_I2C2_RX]); 2426 sysbus_mmio_map(busdev, 0, omap_l4_region_base(omap_l4tao(s->l4, 6), 0)); 2427 2428 s->gpio = qdev_create(NULL, "omap2-gpio"); 2429 qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model); 2430 qdev_prop_set_ptr(s->gpio, "iclk", omap_findclk(s, "gpio_iclk")); 2431 qdev_prop_set_ptr(s->gpio, "fclk0", omap_findclk(s, "gpio1_dbclk")); 2432 qdev_prop_set_ptr(s->gpio, "fclk1", omap_findclk(s, "gpio2_dbclk")); 2433 qdev_prop_set_ptr(s->gpio, "fclk2", omap_findclk(s, "gpio3_dbclk")); 2434 qdev_prop_set_ptr(s->gpio, "fclk3", omap_findclk(s, "gpio4_dbclk")); 2435 if (s->mpu_model == omap2430) { 2436 qdev_prop_set_ptr(s->gpio, "fclk4", omap_findclk(s, "gpio5_dbclk")); 2437 } 2438 qdev_init_nofail(s->gpio); 2439 busdev = SYS_BUS_DEVICE(s->gpio); 2440 sysbus_connect_irq(busdev, 0, 2441 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK1)); 2442 sysbus_connect_irq(busdev, 3, 2443 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK2)); 2444 sysbus_connect_irq(busdev, 6, 2445 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK3)); 2446 sysbus_connect_irq(busdev, 9, 2447 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK4)); 2448 if (s->mpu_model == omap2430) { 2449 sysbus_connect_irq(busdev, 12, 2450 qdev_get_gpio_in(s->ih[0], 2451 OMAP_INT_243X_GPIO_BANK5)); 2452 } 2453 ta = omap_l4ta(s->l4, 3); 2454 sysbus_mmio_map(busdev, 0, omap_l4_region_base(ta, 1)); 2455 sysbus_mmio_map(busdev, 1, omap_l4_region_base(ta, 0)); 2456 sysbus_mmio_map(busdev, 2, omap_l4_region_base(ta, 2)); 2457 sysbus_mmio_map(busdev, 3, omap_l4_region_base(ta, 4)); 2458 sysbus_mmio_map(busdev, 4, omap_l4_region_base(ta, 5)); 2459 2460 s->sdrc = omap_sdrc_init(sysmem, 0x68009000); 2461 s->gpmc = omap_gpmc_init(s, 0x6800a000, 2462 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPMC_IRQ), 2463 s->drq[OMAP24XX_DMA_GPMC]); 2464 2465 dinfo = drive_get(IF_SD, 0, 0); 2466 if (!dinfo) { 2467 fprintf(stderr, "qemu: missing SecureDigital device\n"); 2468 exit(1); 2469 } 2470 s->mmc = omap2_mmc_init(omap_l4tao(s->l4, 9), 2471 blk_by_legacy_dinfo(dinfo), 2472 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MMC_IRQ), 2473 &s->drq[OMAP24XX_DMA_MMC1_TX], 2474 omap_findclk(s, "mmc_fclk"), omap_findclk(s, "mmc_iclk")); 2475 2476 s->mcspi[0] = omap_mcspi_init(omap_l4ta(s->l4, 35), 4, 2477 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MCSPI1_IRQ), 2478 &s->drq[OMAP24XX_DMA_SPI1_TX0], 2479 omap_findclk(s, "spi1_fclk"), 2480 omap_findclk(s, "spi1_iclk")); 2481 s->mcspi[1] = omap_mcspi_init(omap_l4ta(s->l4, 36), 2, 2482 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MCSPI2_IRQ), 2483 &s->drq[OMAP24XX_DMA_SPI2_TX0], 2484 omap_findclk(s, "spi2_fclk"), 2485 omap_findclk(s, "spi2_iclk")); 2486 2487 s->dss = omap_dss_init(omap_l4ta(s->l4, 10), sysmem, 0x68000800, 2488 /* XXX wire M_IRQ_25, D_L2_IRQ_30 and I_IRQ_13 together */ 2489 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_DSS_IRQ), 2490 s->drq[OMAP24XX_DMA_DSS], 2491 omap_findclk(s, "dss_clk1"), omap_findclk(s, "dss_clk2"), 2492 omap_findclk(s, "dss_54m_clk"), 2493 omap_findclk(s, "dss_l3_iclk"), 2494 omap_findclk(s, "dss_l4_iclk")); 2495 2496 omap_sti_init(omap_l4ta(s->l4, 18), sysmem, 0x54000000, 2497 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_STI), 2498 omap_findclk(s, "emul_ck"), 2499 serial_hds[0] && serial_hds[1] && serial_hds[2] ? 2500 serial_hds[3] : NULL); 2501 2502 s->eac = omap_eac_init(omap_l4ta(s->l4, 32), 2503 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_EAC_IRQ), 2504 /* Ten consecutive lines */ 2505 &s->drq[OMAP24XX_DMA_EAC_AC_RD], 2506 omap_findclk(s, "func_96m_clk"), 2507 omap_findclk(s, "core_l4_iclk")); 2508 2509 /* All register mappings (includin those not currenlty implemented): 2510 * SystemControlMod 48000000 - 48000fff 2511 * SystemControlL4 48001000 - 48001fff 2512 * 32kHz Timer Mod 48004000 - 48004fff 2513 * 32kHz Timer L4 48005000 - 48005fff 2514 * PRCM ModA 48008000 - 480087ff 2515 * PRCM ModB 48008800 - 48008fff 2516 * PRCM L4 48009000 - 48009fff 2517 * TEST-BCM Mod 48012000 - 48012fff 2518 * TEST-BCM L4 48013000 - 48013fff 2519 * TEST-TAP Mod 48014000 - 48014fff 2520 * TEST-TAP L4 48015000 - 48015fff 2521 * GPIO1 Mod 48018000 - 48018fff 2522 * GPIO Top 48019000 - 48019fff 2523 * GPIO2 Mod 4801a000 - 4801afff 2524 * GPIO L4 4801b000 - 4801bfff 2525 * GPIO3 Mod 4801c000 - 4801cfff 2526 * GPIO4 Mod 4801e000 - 4801efff 2527 * WDTIMER1 Mod 48020000 - 48010fff 2528 * WDTIMER Top 48021000 - 48011fff 2529 * WDTIMER2 Mod 48022000 - 48012fff 2530 * WDTIMER L4 48023000 - 48013fff 2531 * WDTIMER3 Mod 48024000 - 48014fff 2532 * WDTIMER3 L4 48025000 - 48015fff 2533 * WDTIMER4 Mod 48026000 - 48016fff 2534 * WDTIMER4 L4 48027000 - 48017fff 2535 * GPTIMER1 Mod 48028000 - 48018fff 2536 * GPTIMER1 L4 48029000 - 48019fff 2537 * GPTIMER2 Mod 4802a000 - 4801afff 2538 * GPTIMER2 L4 4802b000 - 4801bfff 2539 * L4-Config AP 48040000 - 480407ff 2540 * L4-Config IP 48040800 - 48040fff 2541 * L4-Config LA 48041000 - 48041fff 2542 * ARM11ETB Mod 48048000 - 48049fff 2543 * ARM11ETB L4 4804a000 - 4804afff 2544 * DISPLAY Top 48050000 - 480503ff 2545 * DISPLAY DISPC 48050400 - 480507ff 2546 * DISPLAY RFBI 48050800 - 48050bff 2547 * DISPLAY VENC 48050c00 - 48050fff 2548 * DISPLAY L4 48051000 - 48051fff 2549 * CAMERA Top 48052000 - 480523ff 2550 * CAMERA core 48052400 - 480527ff 2551 * CAMERA DMA 48052800 - 48052bff 2552 * CAMERA MMU 48052c00 - 48052fff 2553 * CAMERA L4 48053000 - 48053fff 2554 * SDMA Mod 48056000 - 48056fff 2555 * SDMA L4 48057000 - 48057fff 2556 * SSI Top 48058000 - 48058fff 2557 * SSI GDD 48059000 - 48059fff 2558 * SSI Port1 4805a000 - 4805afff 2559 * SSI Port2 4805b000 - 4805bfff 2560 * SSI L4 4805c000 - 4805cfff 2561 * USB Mod 4805e000 - 480fefff 2562 * USB L4 4805f000 - 480fffff 2563 * WIN_TRACER1 Mod 48060000 - 48060fff 2564 * WIN_TRACER1 L4 48061000 - 48061fff 2565 * WIN_TRACER2 Mod 48062000 - 48062fff 2566 * WIN_TRACER2 L4 48063000 - 48063fff 2567 * WIN_TRACER3 Mod 48064000 - 48064fff 2568 * WIN_TRACER3 L4 48065000 - 48065fff 2569 * WIN_TRACER4 Top 48066000 - 480660ff 2570 * WIN_TRACER4 ETT 48066100 - 480661ff 2571 * WIN_TRACER4 WT 48066200 - 480662ff 2572 * WIN_TRACER4 L4 48067000 - 48067fff 2573 * XTI Mod 48068000 - 48068fff 2574 * XTI L4 48069000 - 48069fff 2575 * UART1 Mod 4806a000 - 4806afff 2576 * UART1 L4 4806b000 - 4806bfff 2577 * UART2 Mod 4806c000 - 4806cfff 2578 * UART2 L4 4806d000 - 4806dfff 2579 * UART3 Mod 4806e000 - 4806efff 2580 * UART3 L4 4806f000 - 4806ffff 2581 * I2C1 Mod 48070000 - 48070fff 2582 * I2C1 L4 48071000 - 48071fff 2583 * I2C2 Mod 48072000 - 48072fff 2584 * I2C2 L4 48073000 - 48073fff 2585 * McBSP1 Mod 48074000 - 48074fff 2586 * McBSP1 L4 48075000 - 48075fff 2587 * McBSP2 Mod 48076000 - 48076fff 2588 * McBSP2 L4 48077000 - 48077fff 2589 * GPTIMER3 Mod 48078000 - 48078fff 2590 * GPTIMER3 L4 48079000 - 48079fff 2591 * GPTIMER4 Mod 4807a000 - 4807afff 2592 * GPTIMER4 L4 4807b000 - 4807bfff 2593 * GPTIMER5 Mod 4807c000 - 4807cfff 2594 * GPTIMER5 L4 4807d000 - 4807dfff 2595 * GPTIMER6 Mod 4807e000 - 4807efff 2596 * GPTIMER6 L4 4807f000 - 4807ffff 2597 * GPTIMER7 Mod 48080000 - 48080fff 2598 * GPTIMER7 L4 48081000 - 48081fff 2599 * GPTIMER8 Mod 48082000 - 48082fff 2600 * GPTIMER8 L4 48083000 - 48083fff 2601 * GPTIMER9 Mod 48084000 - 48084fff 2602 * GPTIMER9 L4 48085000 - 48085fff 2603 * GPTIMER10 Mod 48086000 - 48086fff 2604 * GPTIMER10 L4 48087000 - 48087fff 2605 * GPTIMER11 Mod 48088000 - 48088fff 2606 * GPTIMER11 L4 48089000 - 48089fff 2607 * GPTIMER12 Mod 4808a000 - 4808afff 2608 * GPTIMER12 L4 4808b000 - 4808bfff 2609 * EAC Mod 48090000 - 48090fff 2610 * EAC L4 48091000 - 48091fff 2611 * FAC Mod 48092000 - 48092fff 2612 * FAC L4 48093000 - 48093fff 2613 * MAILBOX Mod 48094000 - 48094fff 2614 * MAILBOX L4 48095000 - 48095fff 2615 * SPI1 Mod 48098000 - 48098fff 2616 * SPI1 L4 48099000 - 48099fff 2617 * SPI2 Mod 4809a000 - 4809afff 2618 * SPI2 L4 4809b000 - 4809bfff 2619 * MMC/SDIO Mod 4809c000 - 4809cfff 2620 * MMC/SDIO L4 4809d000 - 4809dfff 2621 * MS_PRO Mod 4809e000 - 4809efff 2622 * MS_PRO L4 4809f000 - 4809ffff 2623 * RNG Mod 480a0000 - 480a0fff 2624 * RNG L4 480a1000 - 480a1fff 2625 * DES3DES Mod 480a2000 - 480a2fff 2626 * DES3DES L4 480a3000 - 480a3fff 2627 * SHA1MD5 Mod 480a4000 - 480a4fff 2628 * SHA1MD5 L4 480a5000 - 480a5fff 2629 * AES Mod 480a6000 - 480a6fff 2630 * AES L4 480a7000 - 480a7fff 2631 * PKA Mod 480a8000 - 480a9fff 2632 * PKA L4 480aa000 - 480aafff 2633 * MG Mod 480b0000 - 480b0fff 2634 * MG L4 480b1000 - 480b1fff 2635 * HDQ/1-wire Mod 480b2000 - 480b2fff 2636 * HDQ/1-wire L4 480b3000 - 480b3fff 2637 * MPU interrupt 480fe000 - 480fefff 2638 * STI channel base 54000000 - 5400ffff 2639 * IVA RAM 5c000000 - 5c01ffff 2640 * IVA ROM 5c020000 - 5c027fff 2641 * IMG_BUF_A 5c040000 - 5c040fff 2642 * IMG_BUF_B 5c042000 - 5c042fff 2643 * VLCDS 5c048000 - 5c0487ff 2644 * IMX_COEF 5c049000 - 5c04afff 2645 * IMX_CMD 5c051000 - 5c051fff 2646 * VLCDQ 5c053000 - 5c0533ff 2647 * VLCDH 5c054000 - 5c054fff 2648 * SEQ_CMD 5c055000 - 5c055fff 2649 * IMX_REG 5c056000 - 5c0560ff 2650 * VLCD_REG 5c056100 - 5c0561ff 2651 * SEQ_REG 5c056200 - 5c0562ff 2652 * IMG_BUF_REG 5c056300 - 5c0563ff 2653 * SEQIRQ_REG 5c056400 - 5c0564ff 2654 * OCP_REG 5c060000 - 5c060fff 2655 * SYSC_REG 5c070000 - 5c070fff 2656 * MMU_REG 5d000000 - 5d000fff 2657 * sDMA R 68000400 - 680005ff 2658 * sDMA W 68000600 - 680007ff 2659 * Display Control 68000800 - 680009ff 2660 * DSP subsystem 68000a00 - 68000bff 2661 * MPU subsystem 68000c00 - 68000dff 2662 * IVA subsystem 68001000 - 680011ff 2663 * USB 68001200 - 680013ff 2664 * Camera 68001400 - 680015ff 2665 * VLYNQ (firewall) 68001800 - 68001bff 2666 * VLYNQ 68001e00 - 68001fff 2667 * SSI 68002000 - 680021ff 2668 * L4 68002400 - 680025ff 2669 * DSP (firewall) 68002800 - 68002bff 2670 * DSP subsystem 68002e00 - 68002fff 2671 * IVA (firewall) 68003000 - 680033ff 2672 * IVA 68003600 - 680037ff 2673 * GFX 68003a00 - 68003bff 2674 * CMDWR emulation 68003c00 - 68003dff 2675 * SMS 68004000 - 680041ff 2676 * OCM 68004200 - 680043ff 2677 * GPMC 68004400 - 680045ff 2678 * RAM (firewall) 68005000 - 680053ff 2679 * RAM (err login) 68005400 - 680057ff 2680 * ROM (firewall) 68005800 - 68005bff 2681 * ROM (err login) 68005c00 - 68005fff 2682 * GPMC (firewall) 68006000 - 680063ff 2683 * GPMC (err login) 68006400 - 680067ff 2684 * SMS (err login) 68006c00 - 68006fff 2685 * SMS registers 68008000 - 68008fff 2686 * SDRC registers 68009000 - 68009fff 2687 * GPMC registers 6800a000 6800afff 2688 */ 2689 2690 qemu_register_reset(omap2_mpu_reset, s); 2691 2692 return s; 2693 } 2694