1 /* 2 * TI OMAP processors emulation. 3 * 4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 or 9 * (at your option) version 3 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/error-report.h" 22 #include "qemu/main-loop.h" 23 #include "qapi/error.h" 24 #include "qemu-common.h" 25 #include "cpu.h" 26 #include "hw/boards.h" 27 #include "hw/hw.h" 28 #include "hw/irq.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/arm/boot.h" 31 #include "hw/arm/omap.h" 32 #include "sysemu/blockdev.h" 33 #include "sysemu/sysemu.h" 34 #include "hw/arm/soc_dma.h" 35 #include "sysemu/qtest.h" 36 #include "sysemu/reset.h" 37 #include "sysemu/runstate.h" 38 #include "qemu/range.h" 39 #include "hw/sysbus.h" 40 #include "qemu/cutils.h" 41 #include "qemu/bcd.h" 42 43 static inline void omap_log_badwidth(const char *funcname, hwaddr addr, int sz) 44 { 45 qemu_log_mask(LOG_GUEST_ERROR, "%s: %d-bit register %#08" HWADDR_PRIx "\n", 46 funcname, 8 * sz, addr); 47 } 48 49 /* Should signal the TCMI/GPMC */ 50 uint32_t omap_badwidth_read8(void *opaque, hwaddr addr) 51 { 52 uint8_t ret; 53 54 omap_log_badwidth(__func__, addr, 1); 55 cpu_physical_memory_read(addr, &ret, 1); 56 return ret; 57 } 58 59 void omap_badwidth_write8(void *opaque, hwaddr addr, 60 uint32_t value) 61 { 62 uint8_t val8 = value; 63 64 omap_log_badwidth(__func__, addr, 1); 65 cpu_physical_memory_write(addr, &val8, 1); 66 } 67 68 uint32_t omap_badwidth_read16(void *opaque, hwaddr addr) 69 { 70 uint16_t ret; 71 72 omap_log_badwidth(__func__, addr, 2); 73 cpu_physical_memory_read(addr, &ret, 2); 74 return ret; 75 } 76 77 void omap_badwidth_write16(void *opaque, hwaddr addr, 78 uint32_t value) 79 { 80 uint16_t val16 = value; 81 82 omap_log_badwidth(__func__, addr, 2); 83 cpu_physical_memory_write(addr, &val16, 2); 84 } 85 86 uint32_t omap_badwidth_read32(void *opaque, hwaddr addr) 87 { 88 uint32_t ret; 89 90 omap_log_badwidth(__func__, addr, 4); 91 cpu_physical_memory_read(addr, &ret, 4); 92 return ret; 93 } 94 95 void omap_badwidth_write32(void *opaque, hwaddr addr, 96 uint32_t value) 97 { 98 omap_log_badwidth(__func__, addr, 4); 99 cpu_physical_memory_write(addr, &value, 4); 100 } 101 102 /* MPU OS timers */ 103 struct omap_mpu_timer_s { 104 MemoryRegion iomem; 105 qemu_irq irq; 106 omap_clk clk; 107 uint32_t val; 108 int64_t time; 109 QEMUTimer *timer; 110 QEMUBH *tick; 111 int64_t rate; 112 int it_ena; 113 114 int enable; 115 int ptv; 116 int ar; 117 int st; 118 uint32_t reset_val; 119 }; 120 121 static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer) 122 { 123 uint64_t distance = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->time; 124 125 if (timer->st && timer->enable && timer->rate) 126 return timer->val - muldiv64(distance >> (timer->ptv + 1), 127 timer->rate, NANOSECONDS_PER_SECOND); 128 else 129 return timer->val; 130 } 131 132 static inline void omap_timer_sync(struct omap_mpu_timer_s *timer) 133 { 134 timer->val = omap_timer_read(timer); 135 timer->time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 136 } 137 138 static inline void omap_timer_update(struct omap_mpu_timer_s *timer) 139 { 140 int64_t expires; 141 142 if (timer->enable && timer->st && timer->rate) { 143 timer->val = timer->reset_val; /* Should skip this on clk enable */ 144 expires = muldiv64((uint64_t) timer->val << (timer->ptv + 1), 145 NANOSECONDS_PER_SECOND, timer->rate); 146 147 /* If timer expiry would be sooner than in about 1 ms and 148 * auto-reload isn't set, then fire immediately. This is a hack 149 * to make systems like PalmOS run in acceptable time. PalmOS 150 * sets the interval to a very low value and polls the status bit 151 * in a busy loop when it wants to sleep just a couple of CPU 152 * ticks. */ 153 if (expires > (NANOSECONDS_PER_SECOND >> 10) || timer->ar) { 154 timer_mod(timer->timer, timer->time + expires); 155 } else { 156 qemu_bh_schedule(timer->tick); 157 } 158 } else 159 timer_del(timer->timer); 160 } 161 162 static void omap_timer_fire(void *opaque) 163 { 164 struct omap_mpu_timer_s *timer = opaque; 165 166 if (!timer->ar) { 167 timer->val = 0; 168 timer->st = 0; 169 } 170 171 if (timer->it_ena) 172 /* Edge-triggered irq */ 173 qemu_irq_pulse(timer->irq); 174 } 175 176 static void omap_timer_tick(void *opaque) 177 { 178 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque; 179 180 omap_timer_sync(timer); 181 omap_timer_fire(timer); 182 omap_timer_update(timer); 183 } 184 185 static void omap_timer_clk_update(void *opaque, int line, int on) 186 { 187 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque; 188 189 omap_timer_sync(timer); 190 timer->rate = on ? omap_clk_getrate(timer->clk) : 0; 191 omap_timer_update(timer); 192 } 193 194 static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer) 195 { 196 omap_clk_adduser(timer->clk, 197 qemu_allocate_irq(omap_timer_clk_update, timer, 0)); 198 timer->rate = omap_clk_getrate(timer->clk); 199 } 200 201 static uint64_t omap_mpu_timer_read(void *opaque, hwaddr addr, 202 unsigned size) 203 { 204 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; 205 206 if (size != 4) { 207 return omap_badwidth_read32(opaque, addr); 208 } 209 210 switch (addr) { 211 case 0x00: /* CNTL_TIMER */ 212 return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st; 213 214 case 0x04: /* LOAD_TIM */ 215 break; 216 217 case 0x08: /* READ_TIM */ 218 return omap_timer_read(s); 219 } 220 221 OMAP_BAD_REG(addr); 222 return 0; 223 } 224 225 static void omap_mpu_timer_write(void *opaque, hwaddr addr, 226 uint64_t value, unsigned size) 227 { 228 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; 229 230 if (size != 4) { 231 omap_badwidth_write32(opaque, addr, value); 232 return; 233 } 234 235 switch (addr) { 236 case 0x00: /* CNTL_TIMER */ 237 omap_timer_sync(s); 238 s->enable = (value >> 5) & 1; 239 s->ptv = (value >> 2) & 7; 240 s->ar = (value >> 1) & 1; 241 s->st = value & 1; 242 omap_timer_update(s); 243 return; 244 245 case 0x04: /* LOAD_TIM */ 246 s->reset_val = value; 247 return; 248 249 case 0x08: /* READ_TIM */ 250 OMAP_RO_REG(addr); 251 break; 252 253 default: 254 OMAP_BAD_REG(addr); 255 } 256 } 257 258 static const MemoryRegionOps omap_mpu_timer_ops = { 259 .read = omap_mpu_timer_read, 260 .write = omap_mpu_timer_write, 261 .endianness = DEVICE_LITTLE_ENDIAN, 262 }; 263 264 static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s) 265 { 266 timer_del(s->timer); 267 s->enable = 0; 268 s->reset_val = 31337; 269 s->val = 0; 270 s->ptv = 0; 271 s->ar = 0; 272 s->st = 0; 273 s->it_ena = 1; 274 } 275 276 static struct omap_mpu_timer_s *omap_mpu_timer_init(MemoryRegion *system_memory, 277 hwaddr base, 278 qemu_irq irq, omap_clk clk) 279 { 280 struct omap_mpu_timer_s *s = g_new0(struct omap_mpu_timer_s, 1); 281 282 s->irq = irq; 283 s->clk = clk; 284 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, s); 285 s->tick = qemu_bh_new(omap_timer_fire, s); 286 omap_mpu_timer_reset(s); 287 omap_timer_clk_setup(s); 288 289 memory_region_init_io(&s->iomem, NULL, &omap_mpu_timer_ops, s, 290 "omap-mpu-timer", 0x100); 291 292 memory_region_add_subregion(system_memory, base, &s->iomem); 293 294 return s; 295 } 296 297 /* Watchdog timer */ 298 struct omap_watchdog_timer_s { 299 struct omap_mpu_timer_s timer; 300 MemoryRegion iomem; 301 uint8_t last_wr; 302 int mode; 303 int free; 304 int reset; 305 }; 306 307 static uint64_t omap_wd_timer_read(void *opaque, hwaddr addr, 308 unsigned size) 309 { 310 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; 311 312 if (size != 2) { 313 return omap_badwidth_read16(opaque, addr); 314 } 315 316 switch (addr) { 317 case 0x00: /* CNTL_TIMER */ 318 return (s->timer.ptv << 9) | (s->timer.ar << 8) | 319 (s->timer.st << 7) | (s->free << 1); 320 321 case 0x04: /* READ_TIMER */ 322 return omap_timer_read(&s->timer); 323 324 case 0x08: /* TIMER_MODE */ 325 return s->mode << 15; 326 } 327 328 OMAP_BAD_REG(addr); 329 return 0; 330 } 331 332 static void omap_wd_timer_write(void *opaque, hwaddr addr, 333 uint64_t value, unsigned size) 334 { 335 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; 336 337 if (size != 2) { 338 omap_badwidth_write16(opaque, addr, value); 339 return; 340 } 341 342 switch (addr) { 343 case 0x00: /* CNTL_TIMER */ 344 omap_timer_sync(&s->timer); 345 s->timer.ptv = (value >> 9) & 7; 346 s->timer.ar = (value >> 8) & 1; 347 s->timer.st = (value >> 7) & 1; 348 s->free = (value >> 1) & 1; 349 omap_timer_update(&s->timer); 350 break; 351 352 case 0x04: /* LOAD_TIMER */ 353 s->timer.reset_val = value & 0xffff; 354 break; 355 356 case 0x08: /* TIMER_MODE */ 357 if (!s->mode && ((value >> 15) & 1)) 358 omap_clk_get(s->timer.clk); 359 s->mode |= (value >> 15) & 1; 360 if (s->last_wr == 0xf5) { 361 if ((value & 0xff) == 0xa0) { 362 if (s->mode) { 363 s->mode = 0; 364 omap_clk_put(s->timer.clk); 365 } 366 } else { 367 /* XXX: on T|E hardware somehow this has no effect, 368 * on Zire 71 it works as specified. */ 369 s->reset = 1; 370 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 371 } 372 } 373 s->last_wr = value & 0xff; 374 break; 375 376 default: 377 OMAP_BAD_REG(addr); 378 } 379 } 380 381 static const MemoryRegionOps omap_wd_timer_ops = { 382 .read = omap_wd_timer_read, 383 .write = omap_wd_timer_write, 384 .endianness = DEVICE_NATIVE_ENDIAN, 385 }; 386 387 static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s) 388 { 389 timer_del(s->timer.timer); 390 if (!s->mode) 391 omap_clk_get(s->timer.clk); 392 s->mode = 1; 393 s->free = 1; 394 s->reset = 0; 395 s->timer.enable = 1; 396 s->timer.it_ena = 1; 397 s->timer.reset_val = 0xffff; 398 s->timer.val = 0; 399 s->timer.st = 0; 400 s->timer.ptv = 0; 401 s->timer.ar = 0; 402 omap_timer_update(&s->timer); 403 } 404 405 static struct omap_watchdog_timer_s *omap_wd_timer_init(MemoryRegion *memory, 406 hwaddr base, 407 qemu_irq irq, omap_clk clk) 408 { 409 struct omap_watchdog_timer_s *s = g_new0(struct omap_watchdog_timer_s, 1); 410 411 s->timer.irq = irq; 412 s->timer.clk = clk; 413 s->timer.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, &s->timer); 414 omap_wd_timer_reset(s); 415 omap_timer_clk_setup(&s->timer); 416 417 memory_region_init_io(&s->iomem, NULL, &omap_wd_timer_ops, s, 418 "omap-wd-timer", 0x100); 419 memory_region_add_subregion(memory, base, &s->iomem); 420 421 return s; 422 } 423 424 /* 32-kHz timer */ 425 struct omap_32khz_timer_s { 426 struct omap_mpu_timer_s timer; 427 MemoryRegion iomem; 428 }; 429 430 static uint64_t omap_os_timer_read(void *opaque, hwaddr addr, 431 unsigned size) 432 { 433 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; 434 int offset = addr & OMAP_MPUI_REG_MASK; 435 436 if (size != 4) { 437 return omap_badwidth_read32(opaque, addr); 438 } 439 440 switch (offset) { 441 case 0x00: /* TVR */ 442 return s->timer.reset_val; 443 444 case 0x04: /* TCR */ 445 return omap_timer_read(&s->timer); 446 447 case 0x08: /* CR */ 448 return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st; 449 450 default: 451 break; 452 } 453 OMAP_BAD_REG(addr); 454 return 0; 455 } 456 457 static void omap_os_timer_write(void *opaque, hwaddr addr, 458 uint64_t value, unsigned size) 459 { 460 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; 461 int offset = addr & OMAP_MPUI_REG_MASK; 462 463 if (size != 4) { 464 omap_badwidth_write32(opaque, addr, value); 465 return; 466 } 467 468 switch (offset) { 469 case 0x00: /* TVR */ 470 s->timer.reset_val = value & 0x00ffffff; 471 break; 472 473 case 0x04: /* TCR */ 474 OMAP_RO_REG(addr); 475 break; 476 477 case 0x08: /* CR */ 478 s->timer.ar = (value >> 3) & 1; 479 s->timer.it_ena = (value >> 2) & 1; 480 if (s->timer.st != (value & 1) || (value & 2)) { 481 omap_timer_sync(&s->timer); 482 s->timer.enable = value & 1; 483 s->timer.st = value & 1; 484 omap_timer_update(&s->timer); 485 } 486 break; 487 488 default: 489 OMAP_BAD_REG(addr); 490 } 491 } 492 493 static const MemoryRegionOps omap_os_timer_ops = { 494 .read = omap_os_timer_read, 495 .write = omap_os_timer_write, 496 .endianness = DEVICE_NATIVE_ENDIAN, 497 }; 498 499 static void omap_os_timer_reset(struct omap_32khz_timer_s *s) 500 { 501 timer_del(s->timer.timer); 502 s->timer.enable = 0; 503 s->timer.it_ena = 0; 504 s->timer.reset_val = 0x00ffffff; 505 s->timer.val = 0; 506 s->timer.st = 0; 507 s->timer.ptv = 0; 508 s->timer.ar = 1; 509 } 510 511 static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory, 512 hwaddr base, 513 qemu_irq irq, omap_clk clk) 514 { 515 struct omap_32khz_timer_s *s = g_new0(struct omap_32khz_timer_s, 1); 516 517 s->timer.irq = irq; 518 s->timer.clk = clk; 519 s->timer.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, &s->timer); 520 omap_os_timer_reset(s); 521 omap_timer_clk_setup(&s->timer); 522 523 memory_region_init_io(&s->iomem, NULL, &omap_os_timer_ops, s, 524 "omap-os-timer", 0x800); 525 memory_region_add_subregion(memory, base, &s->iomem); 526 527 return s; 528 } 529 530 /* Ultra Low-Power Device Module */ 531 static uint64_t omap_ulpd_pm_read(void *opaque, hwaddr addr, 532 unsigned size) 533 { 534 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 535 uint16_t ret; 536 537 if (size != 2) { 538 return omap_badwidth_read16(opaque, addr); 539 } 540 541 switch (addr) { 542 case 0x14: /* IT_STATUS */ 543 ret = s->ulpd_pm_regs[addr >> 2]; 544 s->ulpd_pm_regs[addr >> 2] = 0; 545 qemu_irq_lower(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K)); 546 return ret; 547 548 case 0x18: /* Reserved */ 549 case 0x1c: /* Reserved */ 550 case 0x20: /* Reserved */ 551 case 0x28: /* Reserved */ 552 case 0x2c: /* Reserved */ 553 OMAP_BAD_REG(addr); 554 /* fall through */ 555 case 0x00: /* COUNTER_32_LSB */ 556 case 0x04: /* COUNTER_32_MSB */ 557 case 0x08: /* COUNTER_HIGH_FREQ_LSB */ 558 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ 559 case 0x10: /* GAUGING_CTRL */ 560 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ 561 case 0x30: /* CLOCK_CTRL */ 562 case 0x34: /* SOFT_REQ */ 563 case 0x38: /* COUNTER_32_FIQ */ 564 case 0x3c: /* DPLL_CTRL */ 565 case 0x40: /* STATUS_REQ */ 566 /* XXX: check clk::usecount state for every clock */ 567 case 0x48: /* LOCL_TIME */ 568 case 0x4c: /* APLL_CTRL */ 569 case 0x50: /* POWER_CTRL */ 570 return s->ulpd_pm_regs[addr >> 2]; 571 } 572 573 OMAP_BAD_REG(addr); 574 return 0; 575 } 576 577 static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s, 578 uint16_t diff, uint16_t value) 579 { 580 if (diff & (1 << 4)) /* USB_MCLK_EN */ 581 omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1); 582 if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */ 583 omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1); 584 } 585 586 static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s, 587 uint16_t diff, uint16_t value) 588 { 589 if (diff & (1 << 0)) /* SOFT_DPLL_REQ */ 590 omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1); 591 if (diff & (1 << 1)) /* SOFT_COM_REQ */ 592 omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1); 593 if (diff & (1 << 2)) /* SOFT_SDW_REQ */ 594 omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1); 595 if (diff & (1 << 3)) /* SOFT_USB_REQ */ 596 omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1); 597 } 598 599 static void omap_ulpd_pm_write(void *opaque, hwaddr addr, 600 uint64_t value, unsigned size) 601 { 602 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 603 int64_t now, ticks; 604 int div, mult; 605 static const int bypass_div[4] = { 1, 2, 4, 4 }; 606 uint16_t diff; 607 608 if (size != 2) { 609 omap_badwidth_write16(opaque, addr, value); 610 return; 611 } 612 613 switch (addr) { 614 case 0x00: /* COUNTER_32_LSB */ 615 case 0x04: /* COUNTER_32_MSB */ 616 case 0x08: /* COUNTER_HIGH_FREQ_LSB */ 617 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ 618 case 0x14: /* IT_STATUS */ 619 case 0x40: /* STATUS_REQ */ 620 OMAP_RO_REG(addr); 621 break; 622 623 case 0x10: /* GAUGING_CTRL */ 624 /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */ 625 if ((s->ulpd_pm_regs[addr >> 2] ^ value) & 1) { 626 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 627 628 if (value & 1) 629 s->ulpd_gauge_start = now; 630 else { 631 now -= s->ulpd_gauge_start; 632 633 /* 32-kHz ticks */ 634 ticks = muldiv64(now, 32768, NANOSECONDS_PER_SECOND); 635 s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff; 636 s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff; 637 if (ticks >> 32) /* OVERFLOW_32K */ 638 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2; 639 640 /* High frequency ticks */ 641 ticks = muldiv64(now, 12000000, NANOSECONDS_PER_SECOND); 642 s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff; 643 s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff; 644 if (ticks >> 32) /* OVERFLOW_HI_FREQ */ 645 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1; 646 647 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */ 648 qemu_irq_raise(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K)); 649 } 650 } 651 s->ulpd_pm_regs[addr >> 2] = value; 652 break; 653 654 case 0x18: /* Reserved */ 655 case 0x1c: /* Reserved */ 656 case 0x20: /* Reserved */ 657 case 0x28: /* Reserved */ 658 case 0x2c: /* Reserved */ 659 OMAP_BAD_REG(addr); 660 /* fall through */ 661 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ 662 case 0x38: /* COUNTER_32_FIQ */ 663 case 0x48: /* LOCL_TIME */ 664 case 0x50: /* POWER_CTRL */ 665 s->ulpd_pm_regs[addr >> 2] = value; 666 break; 667 668 case 0x30: /* CLOCK_CTRL */ 669 diff = s->ulpd_pm_regs[addr >> 2] ^ value; 670 s->ulpd_pm_regs[addr >> 2] = value & 0x3f; 671 omap_ulpd_clk_update(s, diff, value); 672 break; 673 674 case 0x34: /* SOFT_REQ */ 675 diff = s->ulpd_pm_regs[addr >> 2] ^ value; 676 s->ulpd_pm_regs[addr >> 2] = value & 0x1f; 677 omap_ulpd_req_update(s, diff, value); 678 break; 679 680 case 0x3c: /* DPLL_CTRL */ 681 /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is 682 * omitted altogether, probably a typo. */ 683 /* This register has identical semantics with DPLL(1:3) control 684 * registers, see omap_dpll_write() */ 685 diff = s->ulpd_pm_regs[addr >> 2] & value; 686 s->ulpd_pm_regs[addr >> 2] = value & 0x2fff; 687 if (diff & (0x3ff << 2)) { 688 if (value & (1 << 4)) { /* PLL_ENABLE */ 689 div = ((value >> 5) & 3) + 1; /* PLL_DIV */ 690 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ 691 } else { 692 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ 693 mult = 1; 694 } 695 omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult); 696 } 697 698 /* Enter the desired mode. */ 699 s->ulpd_pm_regs[addr >> 2] = 700 (s->ulpd_pm_regs[addr >> 2] & 0xfffe) | 701 ((s->ulpd_pm_regs[addr >> 2] >> 4) & 1); 702 703 /* Act as if the lock is restored. */ 704 s->ulpd_pm_regs[addr >> 2] |= 2; 705 break; 706 707 case 0x4c: /* APLL_CTRL */ 708 diff = s->ulpd_pm_regs[addr >> 2] & value; 709 s->ulpd_pm_regs[addr >> 2] = value & 0xf; 710 if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */ 711 omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s, 712 (value & (1 << 0)) ? "apll" : "dpll4")); 713 break; 714 715 default: 716 OMAP_BAD_REG(addr); 717 } 718 } 719 720 static const MemoryRegionOps omap_ulpd_pm_ops = { 721 .read = omap_ulpd_pm_read, 722 .write = omap_ulpd_pm_write, 723 .endianness = DEVICE_NATIVE_ENDIAN, 724 }; 725 726 static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu) 727 { 728 mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001; 729 mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000; 730 mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001; 731 mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000; 732 mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000; 733 mpu->ulpd_pm_regs[0x18 >> 2] = 0x01; 734 mpu->ulpd_pm_regs[0x1c >> 2] = 0x01; 735 mpu->ulpd_pm_regs[0x20 >> 2] = 0x01; 736 mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff; 737 mpu->ulpd_pm_regs[0x28 >> 2] = 0x01; 738 mpu->ulpd_pm_regs[0x2c >> 2] = 0x01; 739 omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000); 740 mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000; 741 omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000); 742 mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000; 743 mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001; 744 mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211; 745 mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */ 746 mpu->ulpd_pm_regs[0x48 >> 2] = 0x960; 747 mpu->ulpd_pm_regs[0x4c >> 2] = 0x08; 748 mpu->ulpd_pm_regs[0x50 >> 2] = 0x08; 749 omap_clk_setrate(omap_findclk(mpu, "dpll4"), 1, 4); 750 omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4")); 751 } 752 753 static void omap_ulpd_pm_init(MemoryRegion *system_memory, 754 hwaddr base, 755 struct omap_mpu_state_s *mpu) 756 { 757 memory_region_init_io(&mpu->ulpd_pm_iomem, NULL, &omap_ulpd_pm_ops, mpu, 758 "omap-ulpd-pm", 0x800); 759 memory_region_add_subregion(system_memory, base, &mpu->ulpd_pm_iomem); 760 omap_ulpd_pm_reset(mpu); 761 } 762 763 /* OMAP Pin Configuration */ 764 static uint64_t omap_pin_cfg_read(void *opaque, hwaddr addr, 765 unsigned size) 766 { 767 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 768 769 if (size != 4) { 770 return omap_badwidth_read32(opaque, addr); 771 } 772 773 switch (addr) { 774 case 0x00: /* FUNC_MUX_CTRL_0 */ 775 case 0x04: /* FUNC_MUX_CTRL_1 */ 776 case 0x08: /* FUNC_MUX_CTRL_2 */ 777 return s->func_mux_ctrl[addr >> 2]; 778 779 case 0x0c: /* COMP_MODE_CTRL_0 */ 780 return s->comp_mode_ctrl[0]; 781 782 case 0x10: /* FUNC_MUX_CTRL_3 */ 783 case 0x14: /* FUNC_MUX_CTRL_4 */ 784 case 0x18: /* FUNC_MUX_CTRL_5 */ 785 case 0x1c: /* FUNC_MUX_CTRL_6 */ 786 case 0x20: /* FUNC_MUX_CTRL_7 */ 787 case 0x24: /* FUNC_MUX_CTRL_8 */ 788 case 0x28: /* FUNC_MUX_CTRL_9 */ 789 case 0x2c: /* FUNC_MUX_CTRL_A */ 790 case 0x30: /* FUNC_MUX_CTRL_B */ 791 case 0x34: /* FUNC_MUX_CTRL_C */ 792 case 0x38: /* FUNC_MUX_CTRL_D */ 793 return s->func_mux_ctrl[(addr >> 2) - 1]; 794 795 case 0x40: /* PULL_DWN_CTRL_0 */ 796 case 0x44: /* PULL_DWN_CTRL_1 */ 797 case 0x48: /* PULL_DWN_CTRL_2 */ 798 case 0x4c: /* PULL_DWN_CTRL_3 */ 799 return s->pull_dwn_ctrl[(addr & 0xf) >> 2]; 800 801 case 0x50: /* GATE_INH_CTRL_0 */ 802 return s->gate_inh_ctrl[0]; 803 804 case 0x60: /* VOLTAGE_CTRL_0 */ 805 return s->voltage_ctrl[0]; 806 807 case 0x70: /* TEST_DBG_CTRL_0 */ 808 return s->test_dbg_ctrl[0]; 809 810 case 0x80: /* MOD_CONF_CTRL_0 */ 811 return s->mod_conf_ctrl[0]; 812 } 813 814 OMAP_BAD_REG(addr); 815 return 0; 816 } 817 818 static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s, 819 uint32_t diff, uint32_t value) 820 { 821 if (s->compat1509) { 822 if (diff & (1 << 9)) /* BLUETOOTH */ 823 omap_clk_onoff(omap_findclk(s, "bt_mclk_out"), 824 (~value >> 9) & 1); 825 if (diff & (1 << 7)) /* USB.CLKO */ 826 omap_clk_onoff(omap_findclk(s, "usb.clko"), 827 (value >> 7) & 1); 828 } 829 } 830 831 static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s, 832 uint32_t diff, uint32_t value) 833 { 834 if (s->compat1509) { 835 if (diff & (1U << 31)) { 836 /* MCBSP3_CLK_HIZ_DI */ 837 omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"), (value >> 31) & 1); 838 } 839 if (diff & (1 << 1)) { 840 /* CLK32K */ 841 omap_clk_onoff(omap_findclk(s, "clk32k_out"), (~value >> 1) & 1); 842 } 843 } 844 } 845 846 static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s, 847 uint32_t diff, uint32_t value) 848 { 849 if (diff & (1U << 31)) { 850 /* CONF_MOD_UART3_CLK_MODE_R */ 851 omap_clk_reparent(omap_findclk(s, "uart3_ck"), 852 omap_findclk(s, ((value >> 31) & 1) ? 853 "ck_48m" : "armper_ck")); 854 } 855 if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */ 856 omap_clk_reparent(omap_findclk(s, "uart2_ck"), 857 omap_findclk(s, ((value >> 30) & 1) ? 858 "ck_48m" : "armper_ck")); 859 if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */ 860 omap_clk_reparent(omap_findclk(s, "uart1_ck"), 861 omap_findclk(s, ((value >> 29) & 1) ? 862 "ck_48m" : "armper_ck")); 863 if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */ 864 omap_clk_reparent(omap_findclk(s, "mmc_ck"), 865 omap_findclk(s, ((value >> 23) & 1) ? 866 "ck_48m" : "armper_ck")); 867 if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */ 868 omap_clk_reparent(omap_findclk(s, "com_mclk_out"), 869 omap_findclk(s, ((value >> 12) & 1) ? 870 "ck_48m" : "armper_ck")); 871 if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */ 872 omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1); 873 } 874 875 static void omap_pin_cfg_write(void *opaque, hwaddr addr, 876 uint64_t value, unsigned size) 877 { 878 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 879 uint32_t diff; 880 881 if (size != 4) { 882 omap_badwidth_write32(opaque, addr, value); 883 return; 884 } 885 886 switch (addr) { 887 case 0x00: /* FUNC_MUX_CTRL_0 */ 888 diff = s->func_mux_ctrl[addr >> 2] ^ value; 889 s->func_mux_ctrl[addr >> 2] = value; 890 omap_pin_funcmux0_update(s, diff, value); 891 return; 892 893 case 0x04: /* FUNC_MUX_CTRL_1 */ 894 diff = s->func_mux_ctrl[addr >> 2] ^ value; 895 s->func_mux_ctrl[addr >> 2] = value; 896 omap_pin_funcmux1_update(s, diff, value); 897 return; 898 899 case 0x08: /* FUNC_MUX_CTRL_2 */ 900 s->func_mux_ctrl[addr >> 2] = value; 901 return; 902 903 case 0x0c: /* COMP_MODE_CTRL_0 */ 904 s->comp_mode_ctrl[0] = value; 905 s->compat1509 = (value != 0x0000eaef); 906 omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]); 907 omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]); 908 return; 909 910 case 0x10: /* FUNC_MUX_CTRL_3 */ 911 case 0x14: /* FUNC_MUX_CTRL_4 */ 912 case 0x18: /* FUNC_MUX_CTRL_5 */ 913 case 0x1c: /* FUNC_MUX_CTRL_6 */ 914 case 0x20: /* FUNC_MUX_CTRL_7 */ 915 case 0x24: /* FUNC_MUX_CTRL_8 */ 916 case 0x28: /* FUNC_MUX_CTRL_9 */ 917 case 0x2c: /* FUNC_MUX_CTRL_A */ 918 case 0x30: /* FUNC_MUX_CTRL_B */ 919 case 0x34: /* FUNC_MUX_CTRL_C */ 920 case 0x38: /* FUNC_MUX_CTRL_D */ 921 s->func_mux_ctrl[(addr >> 2) - 1] = value; 922 return; 923 924 case 0x40: /* PULL_DWN_CTRL_0 */ 925 case 0x44: /* PULL_DWN_CTRL_1 */ 926 case 0x48: /* PULL_DWN_CTRL_2 */ 927 case 0x4c: /* PULL_DWN_CTRL_3 */ 928 s->pull_dwn_ctrl[(addr & 0xf) >> 2] = value; 929 return; 930 931 case 0x50: /* GATE_INH_CTRL_0 */ 932 s->gate_inh_ctrl[0] = value; 933 return; 934 935 case 0x60: /* VOLTAGE_CTRL_0 */ 936 s->voltage_ctrl[0] = value; 937 return; 938 939 case 0x70: /* TEST_DBG_CTRL_0 */ 940 s->test_dbg_ctrl[0] = value; 941 return; 942 943 case 0x80: /* MOD_CONF_CTRL_0 */ 944 diff = s->mod_conf_ctrl[0] ^ value; 945 s->mod_conf_ctrl[0] = value; 946 omap_pin_modconf1_update(s, diff, value); 947 return; 948 949 default: 950 OMAP_BAD_REG(addr); 951 } 952 } 953 954 static const MemoryRegionOps omap_pin_cfg_ops = { 955 .read = omap_pin_cfg_read, 956 .write = omap_pin_cfg_write, 957 .endianness = DEVICE_NATIVE_ENDIAN, 958 }; 959 960 static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu) 961 { 962 /* Start in Compatibility Mode. */ 963 mpu->compat1509 = 1; 964 omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0); 965 omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0); 966 omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0); 967 memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl)); 968 memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl)); 969 memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl)); 970 memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl)); 971 memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl)); 972 memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl)); 973 memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl)); 974 } 975 976 static void omap_pin_cfg_init(MemoryRegion *system_memory, 977 hwaddr base, 978 struct omap_mpu_state_s *mpu) 979 { 980 memory_region_init_io(&mpu->pin_cfg_iomem, NULL, &omap_pin_cfg_ops, mpu, 981 "omap-pin-cfg", 0x800); 982 memory_region_add_subregion(system_memory, base, &mpu->pin_cfg_iomem); 983 omap_pin_cfg_reset(mpu); 984 } 985 986 /* Device Identification, Die Identification */ 987 static uint64_t omap_id_read(void *opaque, hwaddr addr, 988 unsigned size) 989 { 990 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 991 992 if (size != 4) { 993 return omap_badwidth_read32(opaque, addr); 994 } 995 996 switch (addr) { 997 case 0xfffe1800: /* DIE_ID_LSB */ 998 return 0xc9581f0e; 999 case 0xfffe1804: /* DIE_ID_MSB */ 1000 return 0xa8858bfa; 1001 1002 case 0xfffe2000: /* PRODUCT_ID_LSB */ 1003 return 0x00aaaafc; 1004 case 0xfffe2004: /* PRODUCT_ID_MSB */ 1005 return 0xcafeb574; 1006 1007 case 0xfffed400: /* JTAG_ID_LSB */ 1008 switch (s->mpu_model) { 1009 case omap310: 1010 return 0x03310315; 1011 case omap1510: 1012 return 0x03310115; 1013 default: 1014 hw_error("%s: bad mpu model\n", __func__); 1015 } 1016 break; 1017 1018 case 0xfffed404: /* JTAG_ID_MSB */ 1019 switch (s->mpu_model) { 1020 case omap310: 1021 return 0xfb57402f; 1022 case omap1510: 1023 return 0xfb47002f; 1024 default: 1025 hw_error("%s: bad mpu model\n", __func__); 1026 } 1027 break; 1028 } 1029 1030 OMAP_BAD_REG(addr); 1031 return 0; 1032 } 1033 1034 static void omap_id_write(void *opaque, hwaddr addr, 1035 uint64_t value, unsigned size) 1036 { 1037 if (size != 4) { 1038 omap_badwidth_write32(opaque, addr, value); 1039 return; 1040 } 1041 1042 OMAP_BAD_REG(addr); 1043 } 1044 1045 static const MemoryRegionOps omap_id_ops = { 1046 .read = omap_id_read, 1047 .write = omap_id_write, 1048 .endianness = DEVICE_NATIVE_ENDIAN, 1049 }; 1050 1051 static void omap_id_init(MemoryRegion *memory, struct omap_mpu_state_s *mpu) 1052 { 1053 memory_region_init_io(&mpu->id_iomem, NULL, &omap_id_ops, mpu, 1054 "omap-id", 0x100000000ULL); 1055 memory_region_init_alias(&mpu->id_iomem_e18, NULL, "omap-id-e18", &mpu->id_iomem, 1056 0xfffe1800, 0x800); 1057 memory_region_add_subregion(memory, 0xfffe1800, &mpu->id_iomem_e18); 1058 memory_region_init_alias(&mpu->id_iomem_ed4, NULL, "omap-id-ed4", &mpu->id_iomem, 1059 0xfffed400, 0x100); 1060 memory_region_add_subregion(memory, 0xfffed400, &mpu->id_iomem_ed4); 1061 if (!cpu_is_omap15xx(mpu)) { 1062 memory_region_init_alias(&mpu->id_iomem_ed4, NULL, "omap-id-e20", 1063 &mpu->id_iomem, 0xfffe2000, 0x800); 1064 memory_region_add_subregion(memory, 0xfffe2000, &mpu->id_iomem_e20); 1065 } 1066 } 1067 1068 /* MPUI Control (Dummy) */ 1069 static uint64_t omap_mpui_read(void *opaque, hwaddr addr, 1070 unsigned size) 1071 { 1072 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1073 1074 if (size != 4) { 1075 return omap_badwidth_read32(opaque, addr); 1076 } 1077 1078 switch (addr) { 1079 case 0x00: /* CTRL */ 1080 return s->mpui_ctrl; 1081 case 0x04: /* DEBUG_ADDR */ 1082 return 0x01ffffff; 1083 case 0x08: /* DEBUG_DATA */ 1084 return 0xffffffff; 1085 case 0x0c: /* DEBUG_FLAG */ 1086 return 0x00000800; 1087 case 0x10: /* STATUS */ 1088 return 0x00000000; 1089 1090 /* Not in OMAP310 */ 1091 case 0x14: /* DSP_STATUS */ 1092 case 0x18: /* DSP_BOOT_CONFIG */ 1093 return 0x00000000; 1094 case 0x1c: /* DSP_MPUI_CONFIG */ 1095 return 0x0000ffff; 1096 } 1097 1098 OMAP_BAD_REG(addr); 1099 return 0; 1100 } 1101 1102 static void omap_mpui_write(void *opaque, hwaddr addr, 1103 uint64_t value, unsigned size) 1104 { 1105 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1106 1107 if (size != 4) { 1108 omap_badwidth_write32(opaque, addr, value); 1109 return; 1110 } 1111 1112 switch (addr) { 1113 case 0x00: /* CTRL */ 1114 s->mpui_ctrl = value & 0x007fffff; 1115 break; 1116 1117 case 0x04: /* DEBUG_ADDR */ 1118 case 0x08: /* DEBUG_DATA */ 1119 case 0x0c: /* DEBUG_FLAG */ 1120 case 0x10: /* STATUS */ 1121 /* Not in OMAP310 */ 1122 case 0x14: /* DSP_STATUS */ 1123 OMAP_RO_REG(addr); 1124 break; 1125 case 0x18: /* DSP_BOOT_CONFIG */ 1126 case 0x1c: /* DSP_MPUI_CONFIG */ 1127 break; 1128 1129 default: 1130 OMAP_BAD_REG(addr); 1131 } 1132 } 1133 1134 static const MemoryRegionOps omap_mpui_ops = { 1135 .read = omap_mpui_read, 1136 .write = omap_mpui_write, 1137 .endianness = DEVICE_NATIVE_ENDIAN, 1138 }; 1139 1140 static void omap_mpui_reset(struct omap_mpu_state_s *s) 1141 { 1142 s->mpui_ctrl = 0x0003ff1b; 1143 } 1144 1145 static void omap_mpui_init(MemoryRegion *memory, hwaddr base, 1146 struct omap_mpu_state_s *mpu) 1147 { 1148 memory_region_init_io(&mpu->mpui_iomem, NULL, &omap_mpui_ops, mpu, 1149 "omap-mpui", 0x100); 1150 memory_region_add_subregion(memory, base, &mpu->mpui_iomem); 1151 1152 omap_mpui_reset(mpu); 1153 } 1154 1155 /* TIPB Bridges */ 1156 struct omap_tipb_bridge_s { 1157 qemu_irq abort; 1158 MemoryRegion iomem; 1159 1160 int width_intr; 1161 uint16_t control; 1162 uint16_t alloc; 1163 uint16_t buffer; 1164 uint16_t enh_control; 1165 }; 1166 1167 static uint64_t omap_tipb_bridge_read(void *opaque, hwaddr addr, 1168 unsigned size) 1169 { 1170 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; 1171 1172 if (size < 2) { 1173 return omap_badwidth_read16(opaque, addr); 1174 } 1175 1176 switch (addr) { 1177 case 0x00: /* TIPB_CNTL */ 1178 return s->control; 1179 case 0x04: /* TIPB_BUS_ALLOC */ 1180 return s->alloc; 1181 case 0x08: /* MPU_TIPB_CNTL */ 1182 return s->buffer; 1183 case 0x0c: /* ENHANCED_TIPB_CNTL */ 1184 return s->enh_control; 1185 case 0x10: /* ADDRESS_DBG */ 1186 case 0x14: /* DATA_DEBUG_LOW */ 1187 case 0x18: /* DATA_DEBUG_HIGH */ 1188 return 0xffff; 1189 case 0x1c: /* DEBUG_CNTR_SIG */ 1190 return 0x00f8; 1191 } 1192 1193 OMAP_BAD_REG(addr); 1194 return 0; 1195 } 1196 1197 static void omap_tipb_bridge_write(void *opaque, hwaddr addr, 1198 uint64_t value, unsigned size) 1199 { 1200 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; 1201 1202 if (size < 2) { 1203 omap_badwidth_write16(opaque, addr, value); 1204 return; 1205 } 1206 1207 switch (addr) { 1208 case 0x00: /* TIPB_CNTL */ 1209 s->control = value & 0xffff; 1210 break; 1211 1212 case 0x04: /* TIPB_BUS_ALLOC */ 1213 s->alloc = value & 0x003f; 1214 break; 1215 1216 case 0x08: /* MPU_TIPB_CNTL */ 1217 s->buffer = value & 0x0003; 1218 break; 1219 1220 case 0x0c: /* ENHANCED_TIPB_CNTL */ 1221 s->width_intr = !(value & 2); 1222 s->enh_control = value & 0x000f; 1223 break; 1224 1225 case 0x10: /* ADDRESS_DBG */ 1226 case 0x14: /* DATA_DEBUG_LOW */ 1227 case 0x18: /* DATA_DEBUG_HIGH */ 1228 case 0x1c: /* DEBUG_CNTR_SIG */ 1229 OMAP_RO_REG(addr); 1230 break; 1231 1232 default: 1233 OMAP_BAD_REG(addr); 1234 } 1235 } 1236 1237 static const MemoryRegionOps omap_tipb_bridge_ops = { 1238 .read = omap_tipb_bridge_read, 1239 .write = omap_tipb_bridge_write, 1240 .endianness = DEVICE_NATIVE_ENDIAN, 1241 }; 1242 1243 static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s) 1244 { 1245 s->control = 0xffff; 1246 s->alloc = 0x0009; 1247 s->buffer = 0x0000; 1248 s->enh_control = 0x000f; 1249 } 1250 1251 static struct omap_tipb_bridge_s *omap_tipb_bridge_init( 1252 MemoryRegion *memory, hwaddr base, 1253 qemu_irq abort_irq, omap_clk clk) 1254 { 1255 struct omap_tipb_bridge_s *s = g_new0(struct omap_tipb_bridge_s, 1); 1256 1257 s->abort = abort_irq; 1258 omap_tipb_bridge_reset(s); 1259 1260 memory_region_init_io(&s->iomem, NULL, &omap_tipb_bridge_ops, s, 1261 "omap-tipb-bridge", 0x100); 1262 memory_region_add_subregion(memory, base, &s->iomem); 1263 1264 return s; 1265 } 1266 1267 /* Dummy Traffic Controller's Memory Interface */ 1268 static uint64_t omap_tcmi_read(void *opaque, hwaddr addr, 1269 unsigned size) 1270 { 1271 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1272 uint32_t ret; 1273 1274 if (size != 4) { 1275 return omap_badwidth_read32(opaque, addr); 1276 } 1277 1278 switch (addr) { 1279 case 0x00: /* IMIF_PRIO */ 1280 case 0x04: /* EMIFS_PRIO */ 1281 case 0x08: /* EMIFF_PRIO */ 1282 case 0x0c: /* EMIFS_CONFIG */ 1283 case 0x10: /* EMIFS_CS0_CONFIG */ 1284 case 0x14: /* EMIFS_CS1_CONFIG */ 1285 case 0x18: /* EMIFS_CS2_CONFIG */ 1286 case 0x1c: /* EMIFS_CS3_CONFIG */ 1287 case 0x24: /* EMIFF_MRS */ 1288 case 0x28: /* TIMEOUT1 */ 1289 case 0x2c: /* TIMEOUT2 */ 1290 case 0x30: /* TIMEOUT3 */ 1291 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ 1292 case 0x40: /* EMIFS_CFG_DYN_WAIT */ 1293 return s->tcmi_regs[addr >> 2]; 1294 1295 case 0x20: /* EMIFF_SDRAM_CONFIG */ 1296 ret = s->tcmi_regs[addr >> 2]; 1297 s->tcmi_regs[addr >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */ 1298 /* XXX: We can try using the VGA_DIRTY flag for this */ 1299 return ret; 1300 } 1301 1302 OMAP_BAD_REG(addr); 1303 return 0; 1304 } 1305 1306 static void omap_tcmi_write(void *opaque, hwaddr addr, 1307 uint64_t value, unsigned size) 1308 { 1309 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1310 1311 if (size != 4) { 1312 omap_badwidth_write32(opaque, addr, value); 1313 return; 1314 } 1315 1316 switch (addr) { 1317 case 0x00: /* IMIF_PRIO */ 1318 case 0x04: /* EMIFS_PRIO */ 1319 case 0x08: /* EMIFF_PRIO */ 1320 case 0x10: /* EMIFS_CS0_CONFIG */ 1321 case 0x14: /* EMIFS_CS1_CONFIG */ 1322 case 0x18: /* EMIFS_CS2_CONFIG */ 1323 case 0x1c: /* EMIFS_CS3_CONFIG */ 1324 case 0x20: /* EMIFF_SDRAM_CONFIG */ 1325 case 0x24: /* EMIFF_MRS */ 1326 case 0x28: /* TIMEOUT1 */ 1327 case 0x2c: /* TIMEOUT2 */ 1328 case 0x30: /* TIMEOUT3 */ 1329 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ 1330 case 0x40: /* EMIFS_CFG_DYN_WAIT */ 1331 s->tcmi_regs[addr >> 2] = value; 1332 break; 1333 case 0x0c: /* EMIFS_CONFIG */ 1334 s->tcmi_regs[addr >> 2] = (value & 0xf) | (1 << 4); 1335 break; 1336 1337 default: 1338 OMAP_BAD_REG(addr); 1339 } 1340 } 1341 1342 static const MemoryRegionOps omap_tcmi_ops = { 1343 .read = omap_tcmi_read, 1344 .write = omap_tcmi_write, 1345 .endianness = DEVICE_NATIVE_ENDIAN, 1346 }; 1347 1348 static void omap_tcmi_reset(struct omap_mpu_state_s *mpu) 1349 { 1350 mpu->tcmi_regs[0x00 >> 2] = 0x00000000; 1351 mpu->tcmi_regs[0x04 >> 2] = 0x00000000; 1352 mpu->tcmi_regs[0x08 >> 2] = 0x00000000; 1353 mpu->tcmi_regs[0x0c >> 2] = 0x00000010; 1354 mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb; 1355 mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb; 1356 mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb; 1357 mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb; 1358 mpu->tcmi_regs[0x20 >> 2] = 0x00618800; 1359 mpu->tcmi_regs[0x24 >> 2] = 0x00000037; 1360 mpu->tcmi_regs[0x28 >> 2] = 0x00000000; 1361 mpu->tcmi_regs[0x2c >> 2] = 0x00000000; 1362 mpu->tcmi_regs[0x30 >> 2] = 0x00000000; 1363 mpu->tcmi_regs[0x3c >> 2] = 0x00000003; 1364 mpu->tcmi_regs[0x40 >> 2] = 0x00000000; 1365 } 1366 1367 static void omap_tcmi_init(MemoryRegion *memory, hwaddr base, 1368 struct omap_mpu_state_s *mpu) 1369 { 1370 memory_region_init_io(&mpu->tcmi_iomem, NULL, &omap_tcmi_ops, mpu, 1371 "omap-tcmi", 0x100); 1372 memory_region_add_subregion(memory, base, &mpu->tcmi_iomem); 1373 omap_tcmi_reset(mpu); 1374 } 1375 1376 /* Digital phase-locked loops control */ 1377 struct dpll_ctl_s { 1378 MemoryRegion iomem; 1379 uint16_t mode; 1380 omap_clk dpll; 1381 }; 1382 1383 static uint64_t omap_dpll_read(void *opaque, hwaddr addr, 1384 unsigned size) 1385 { 1386 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; 1387 1388 if (size != 2) { 1389 return omap_badwidth_read16(opaque, addr); 1390 } 1391 1392 if (addr == 0x00) /* CTL_REG */ 1393 return s->mode; 1394 1395 OMAP_BAD_REG(addr); 1396 return 0; 1397 } 1398 1399 static void omap_dpll_write(void *opaque, hwaddr addr, 1400 uint64_t value, unsigned size) 1401 { 1402 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; 1403 uint16_t diff; 1404 static const int bypass_div[4] = { 1, 2, 4, 4 }; 1405 int div, mult; 1406 1407 if (size != 2) { 1408 omap_badwidth_write16(opaque, addr, value); 1409 return; 1410 } 1411 1412 if (addr == 0x00) { /* CTL_REG */ 1413 /* See omap_ulpd_pm_write() too */ 1414 diff = s->mode & value; 1415 s->mode = value & 0x2fff; 1416 if (diff & (0x3ff << 2)) { 1417 if (value & (1 << 4)) { /* PLL_ENABLE */ 1418 div = ((value >> 5) & 3) + 1; /* PLL_DIV */ 1419 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ 1420 } else { 1421 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ 1422 mult = 1; 1423 } 1424 omap_clk_setrate(s->dpll, div, mult); 1425 } 1426 1427 /* Enter the desired mode. */ 1428 s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1); 1429 1430 /* Act as if the lock is restored. */ 1431 s->mode |= 2; 1432 } else { 1433 OMAP_BAD_REG(addr); 1434 } 1435 } 1436 1437 static const MemoryRegionOps omap_dpll_ops = { 1438 .read = omap_dpll_read, 1439 .write = omap_dpll_write, 1440 .endianness = DEVICE_NATIVE_ENDIAN, 1441 }; 1442 1443 static void omap_dpll_reset(struct dpll_ctl_s *s) 1444 { 1445 s->mode = 0x2002; 1446 omap_clk_setrate(s->dpll, 1, 1); 1447 } 1448 1449 static struct dpll_ctl_s *omap_dpll_init(MemoryRegion *memory, 1450 hwaddr base, omap_clk clk) 1451 { 1452 struct dpll_ctl_s *s = g_malloc0(sizeof(*s)); 1453 memory_region_init_io(&s->iomem, NULL, &omap_dpll_ops, s, "omap-dpll", 0x100); 1454 1455 s->dpll = clk; 1456 omap_dpll_reset(s); 1457 1458 memory_region_add_subregion(memory, base, &s->iomem); 1459 return s; 1460 } 1461 1462 /* MPU Clock/Reset/Power Mode Control */ 1463 static uint64_t omap_clkm_read(void *opaque, hwaddr addr, 1464 unsigned size) 1465 { 1466 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1467 1468 if (size != 2) { 1469 return omap_badwidth_read16(opaque, addr); 1470 } 1471 1472 switch (addr) { 1473 case 0x00: /* ARM_CKCTL */ 1474 return s->clkm.arm_ckctl; 1475 1476 case 0x04: /* ARM_IDLECT1 */ 1477 return s->clkm.arm_idlect1; 1478 1479 case 0x08: /* ARM_IDLECT2 */ 1480 return s->clkm.arm_idlect2; 1481 1482 case 0x0c: /* ARM_EWUPCT */ 1483 return s->clkm.arm_ewupct; 1484 1485 case 0x10: /* ARM_RSTCT1 */ 1486 return s->clkm.arm_rstct1; 1487 1488 case 0x14: /* ARM_RSTCT2 */ 1489 return s->clkm.arm_rstct2; 1490 1491 case 0x18: /* ARM_SYSST */ 1492 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start; 1493 1494 case 0x1c: /* ARM_CKOUT1 */ 1495 return s->clkm.arm_ckout1; 1496 1497 case 0x20: /* ARM_CKOUT2 */ 1498 break; 1499 } 1500 1501 OMAP_BAD_REG(addr); 1502 return 0; 1503 } 1504 1505 static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s, 1506 uint16_t diff, uint16_t value) 1507 { 1508 omap_clk clk; 1509 1510 if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */ 1511 if (value & (1 << 14)) 1512 /* Reserved */; 1513 else { 1514 clk = omap_findclk(s, "arminth_ck"); 1515 omap_clk_reparent(clk, omap_findclk(s, "tc_ck")); 1516 } 1517 } 1518 if (diff & (1 << 12)) { /* ARM_TIMXO */ 1519 clk = omap_findclk(s, "armtim_ck"); 1520 if (value & (1 << 12)) 1521 omap_clk_reparent(clk, omap_findclk(s, "clkin")); 1522 else 1523 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1")); 1524 } 1525 /* XXX: en_dspck */ 1526 if (diff & (3 << 10)) { /* DSPMMUDIV */ 1527 clk = omap_findclk(s, "dspmmu_ck"); 1528 omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1); 1529 } 1530 if (diff & (3 << 8)) { /* TCDIV */ 1531 clk = omap_findclk(s, "tc_ck"); 1532 omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1); 1533 } 1534 if (diff & (3 << 6)) { /* DSPDIV */ 1535 clk = omap_findclk(s, "dsp_ck"); 1536 omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1); 1537 } 1538 if (diff & (3 << 4)) { /* ARMDIV */ 1539 clk = omap_findclk(s, "arm_ck"); 1540 omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1); 1541 } 1542 if (diff & (3 << 2)) { /* LCDDIV */ 1543 clk = omap_findclk(s, "lcd_ck"); 1544 omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1); 1545 } 1546 if (diff & (3 << 0)) { /* PERDIV */ 1547 clk = omap_findclk(s, "armper_ck"); 1548 omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1); 1549 } 1550 } 1551 1552 static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s, 1553 uint16_t diff, uint16_t value) 1554 { 1555 omap_clk clk; 1556 1557 if (value & (1 << 11)) { /* SETARM_IDLE */ 1558 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); 1559 } 1560 if (!(value & (1 << 10))) { /* WKUP_MODE */ 1561 /* XXX: disable wakeup from IRQ */ 1562 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 1563 } 1564 1565 #define SET_CANIDLE(clock, bit) \ 1566 if (diff & (1 << bit)) { \ 1567 clk = omap_findclk(s, clock); \ 1568 omap_clk_canidle(clk, (value >> bit) & 1); \ 1569 } 1570 SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */ 1571 SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */ 1572 SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */ 1573 SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */ 1574 SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */ 1575 SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */ 1576 SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */ 1577 SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */ 1578 SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */ 1579 SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */ 1580 SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */ 1581 SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */ 1582 SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */ 1583 SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */ 1584 } 1585 1586 static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s, 1587 uint16_t diff, uint16_t value) 1588 { 1589 omap_clk clk; 1590 1591 #define SET_ONOFF(clock, bit) \ 1592 if (diff & (1 << bit)) { \ 1593 clk = omap_findclk(s, clock); \ 1594 omap_clk_onoff(clk, (value >> bit) & 1); \ 1595 } 1596 SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */ 1597 SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */ 1598 SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */ 1599 SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */ 1600 SET_ONOFF("lb_ck", 4) /* EN_LBCK */ 1601 SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */ 1602 SET_ONOFF("mpui_ck", 6) /* EN_APICK */ 1603 SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */ 1604 SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */ 1605 SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */ 1606 SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */ 1607 } 1608 1609 static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s, 1610 uint16_t diff, uint16_t value) 1611 { 1612 omap_clk clk; 1613 1614 if (diff & (3 << 4)) { /* TCLKOUT */ 1615 clk = omap_findclk(s, "tclk_out"); 1616 switch ((value >> 4) & 3) { 1617 case 1: 1618 omap_clk_reparent(clk, omap_findclk(s, "ck_gen3")); 1619 omap_clk_onoff(clk, 1); 1620 break; 1621 case 2: 1622 omap_clk_reparent(clk, omap_findclk(s, "tc_ck")); 1623 omap_clk_onoff(clk, 1); 1624 break; 1625 default: 1626 omap_clk_onoff(clk, 0); 1627 } 1628 } 1629 if (diff & (3 << 2)) { /* DCLKOUT */ 1630 clk = omap_findclk(s, "dclk_out"); 1631 switch ((value >> 2) & 3) { 1632 case 0: 1633 omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck")); 1634 break; 1635 case 1: 1636 omap_clk_reparent(clk, omap_findclk(s, "ck_gen2")); 1637 break; 1638 case 2: 1639 omap_clk_reparent(clk, omap_findclk(s, "dsp_ck")); 1640 break; 1641 case 3: 1642 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14")); 1643 break; 1644 } 1645 } 1646 if (diff & (3 << 0)) { /* ACLKOUT */ 1647 clk = omap_findclk(s, "aclk_out"); 1648 switch ((value >> 0) & 3) { 1649 case 1: 1650 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1")); 1651 omap_clk_onoff(clk, 1); 1652 break; 1653 case 2: 1654 omap_clk_reparent(clk, omap_findclk(s, "arm_ck")); 1655 omap_clk_onoff(clk, 1); 1656 break; 1657 case 3: 1658 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14")); 1659 omap_clk_onoff(clk, 1); 1660 break; 1661 default: 1662 omap_clk_onoff(clk, 0); 1663 } 1664 } 1665 } 1666 1667 static void omap_clkm_write(void *opaque, hwaddr addr, 1668 uint64_t value, unsigned size) 1669 { 1670 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1671 uint16_t diff; 1672 omap_clk clk; 1673 static const char *clkschemename[8] = { 1674 "fully synchronous", "fully asynchronous", "synchronous scalable", 1675 "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4", 1676 }; 1677 1678 if (size != 2) { 1679 omap_badwidth_write16(opaque, addr, value); 1680 return; 1681 } 1682 1683 switch (addr) { 1684 case 0x00: /* ARM_CKCTL */ 1685 diff = s->clkm.arm_ckctl ^ value; 1686 s->clkm.arm_ckctl = value & 0x7fff; 1687 omap_clkm_ckctl_update(s, diff, value); 1688 return; 1689 1690 case 0x04: /* ARM_IDLECT1 */ 1691 diff = s->clkm.arm_idlect1 ^ value; 1692 s->clkm.arm_idlect1 = value & 0x0fff; 1693 omap_clkm_idlect1_update(s, diff, value); 1694 return; 1695 1696 case 0x08: /* ARM_IDLECT2 */ 1697 diff = s->clkm.arm_idlect2 ^ value; 1698 s->clkm.arm_idlect2 = value & 0x07ff; 1699 omap_clkm_idlect2_update(s, diff, value); 1700 return; 1701 1702 case 0x0c: /* ARM_EWUPCT */ 1703 s->clkm.arm_ewupct = value & 0x003f; 1704 return; 1705 1706 case 0x10: /* ARM_RSTCT1 */ 1707 diff = s->clkm.arm_rstct1 ^ value; 1708 s->clkm.arm_rstct1 = value & 0x0007; 1709 if (value & 9) { 1710 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 1711 s->clkm.cold_start = 0xa; 1712 } 1713 if (diff & ~value & 4) { /* DSP_RST */ 1714 omap_mpui_reset(s); 1715 omap_tipb_bridge_reset(s->private_tipb); 1716 omap_tipb_bridge_reset(s->public_tipb); 1717 } 1718 if (diff & 2) { /* DSP_EN */ 1719 clk = omap_findclk(s, "dsp_ck"); 1720 omap_clk_canidle(clk, (~value >> 1) & 1); 1721 } 1722 return; 1723 1724 case 0x14: /* ARM_RSTCT2 */ 1725 s->clkm.arm_rstct2 = value & 0x0001; 1726 return; 1727 1728 case 0x18: /* ARM_SYSST */ 1729 if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) { 1730 s->clkm.clocking_scheme = (value >> 11) & 7; 1731 printf("%s: clocking scheme set to %s\n", __func__, 1732 clkschemename[s->clkm.clocking_scheme]); 1733 } 1734 s->clkm.cold_start &= value & 0x3f; 1735 return; 1736 1737 case 0x1c: /* ARM_CKOUT1 */ 1738 diff = s->clkm.arm_ckout1 ^ value; 1739 s->clkm.arm_ckout1 = value & 0x003f; 1740 omap_clkm_ckout1_update(s, diff, value); 1741 return; 1742 1743 case 0x20: /* ARM_CKOUT2 */ 1744 default: 1745 OMAP_BAD_REG(addr); 1746 } 1747 } 1748 1749 static const MemoryRegionOps omap_clkm_ops = { 1750 .read = omap_clkm_read, 1751 .write = omap_clkm_write, 1752 .endianness = DEVICE_NATIVE_ENDIAN, 1753 }; 1754 1755 static uint64_t omap_clkdsp_read(void *opaque, hwaddr addr, 1756 unsigned size) 1757 { 1758 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1759 CPUState *cpu = CPU(s->cpu); 1760 1761 if (size != 2) { 1762 return omap_badwidth_read16(opaque, addr); 1763 } 1764 1765 switch (addr) { 1766 case 0x04: /* DSP_IDLECT1 */ 1767 return s->clkm.dsp_idlect1; 1768 1769 case 0x08: /* DSP_IDLECT2 */ 1770 return s->clkm.dsp_idlect2; 1771 1772 case 0x14: /* DSP_RSTCT2 */ 1773 return s->clkm.dsp_rstct2; 1774 1775 case 0x18: /* DSP_SYSST */ 1776 cpu = CPU(s->cpu); 1777 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start | 1778 (cpu->halted << 6); /* Quite useless... */ 1779 } 1780 1781 OMAP_BAD_REG(addr); 1782 return 0; 1783 } 1784 1785 static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s, 1786 uint16_t diff, uint16_t value) 1787 { 1788 omap_clk clk; 1789 1790 SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */ 1791 } 1792 1793 static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s, 1794 uint16_t diff, uint16_t value) 1795 { 1796 omap_clk clk; 1797 1798 SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */ 1799 } 1800 1801 static void omap_clkdsp_write(void *opaque, hwaddr addr, 1802 uint64_t value, unsigned size) 1803 { 1804 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1805 uint16_t diff; 1806 1807 if (size != 2) { 1808 omap_badwidth_write16(opaque, addr, value); 1809 return; 1810 } 1811 1812 switch (addr) { 1813 case 0x04: /* DSP_IDLECT1 */ 1814 diff = s->clkm.dsp_idlect1 ^ value; 1815 s->clkm.dsp_idlect1 = value & 0x01f7; 1816 omap_clkdsp_idlect1_update(s, diff, value); 1817 break; 1818 1819 case 0x08: /* DSP_IDLECT2 */ 1820 s->clkm.dsp_idlect2 = value & 0x0037; 1821 diff = s->clkm.dsp_idlect1 ^ value; 1822 omap_clkdsp_idlect2_update(s, diff, value); 1823 break; 1824 1825 case 0x14: /* DSP_RSTCT2 */ 1826 s->clkm.dsp_rstct2 = value & 0x0001; 1827 break; 1828 1829 case 0x18: /* DSP_SYSST */ 1830 s->clkm.cold_start &= value & 0x3f; 1831 break; 1832 1833 default: 1834 OMAP_BAD_REG(addr); 1835 } 1836 } 1837 1838 static const MemoryRegionOps omap_clkdsp_ops = { 1839 .read = omap_clkdsp_read, 1840 .write = omap_clkdsp_write, 1841 .endianness = DEVICE_NATIVE_ENDIAN, 1842 }; 1843 1844 static void omap_clkm_reset(struct omap_mpu_state_s *s) 1845 { 1846 if (s->wdt && s->wdt->reset) 1847 s->clkm.cold_start = 0x6; 1848 s->clkm.clocking_scheme = 0; 1849 omap_clkm_ckctl_update(s, ~0, 0x3000); 1850 s->clkm.arm_ckctl = 0x3000; 1851 omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 ^ 0x0400, 0x0400); 1852 s->clkm.arm_idlect1 = 0x0400; 1853 omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 ^ 0x0100, 0x0100); 1854 s->clkm.arm_idlect2 = 0x0100; 1855 s->clkm.arm_ewupct = 0x003f; 1856 s->clkm.arm_rstct1 = 0x0000; 1857 s->clkm.arm_rstct2 = 0x0000; 1858 s->clkm.arm_ckout1 = 0x0015; 1859 s->clkm.dpll1_mode = 0x2002; 1860 omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040); 1861 s->clkm.dsp_idlect1 = 0x0040; 1862 omap_clkdsp_idlect2_update(s, ~0, 0x0000); 1863 s->clkm.dsp_idlect2 = 0x0000; 1864 s->clkm.dsp_rstct2 = 0x0000; 1865 } 1866 1867 static void omap_clkm_init(MemoryRegion *memory, hwaddr mpu_base, 1868 hwaddr dsp_base, struct omap_mpu_state_s *s) 1869 { 1870 memory_region_init_io(&s->clkm_iomem, NULL, &omap_clkm_ops, s, 1871 "omap-clkm", 0x100); 1872 memory_region_init_io(&s->clkdsp_iomem, NULL, &omap_clkdsp_ops, s, 1873 "omap-clkdsp", 0x1000); 1874 1875 s->clkm.arm_idlect1 = 0x03ff; 1876 s->clkm.arm_idlect2 = 0x0100; 1877 s->clkm.dsp_idlect1 = 0x0002; 1878 omap_clkm_reset(s); 1879 s->clkm.cold_start = 0x3a; 1880 1881 memory_region_add_subregion(memory, mpu_base, &s->clkm_iomem); 1882 memory_region_add_subregion(memory, dsp_base, &s->clkdsp_iomem); 1883 } 1884 1885 /* MPU I/O */ 1886 struct omap_mpuio_s { 1887 qemu_irq irq; 1888 qemu_irq kbd_irq; 1889 qemu_irq *in; 1890 qemu_irq handler[16]; 1891 qemu_irq wakeup; 1892 MemoryRegion iomem; 1893 1894 uint16_t inputs; 1895 uint16_t outputs; 1896 uint16_t dir; 1897 uint16_t edge; 1898 uint16_t mask; 1899 uint16_t ints; 1900 1901 uint16_t debounce; 1902 uint16_t latch; 1903 uint8_t event; 1904 1905 uint8_t buttons[5]; 1906 uint8_t row_latch; 1907 uint8_t cols; 1908 int kbd_mask; 1909 int clk; 1910 }; 1911 1912 static void omap_mpuio_set(void *opaque, int line, int level) 1913 { 1914 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; 1915 uint16_t prev = s->inputs; 1916 1917 if (level) 1918 s->inputs |= 1 << line; 1919 else 1920 s->inputs &= ~(1 << line); 1921 1922 if (((1 << line) & s->dir & ~s->mask) && s->clk) { 1923 if ((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) { 1924 s->ints |= 1 << line; 1925 qemu_irq_raise(s->irq); 1926 /* TODO: wakeup */ 1927 } 1928 if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */ 1929 (s->event >> 1) == line) /* PIN_SELECT */ 1930 s->latch = s->inputs; 1931 } 1932 } 1933 1934 static void omap_mpuio_kbd_update(struct omap_mpuio_s *s) 1935 { 1936 int i; 1937 uint8_t *row, rows = 0, cols = ~s->cols; 1938 1939 for (row = s->buttons + 4, i = 1 << 4; i; row --, i >>= 1) 1940 if (*row & cols) 1941 rows |= i; 1942 1943 qemu_set_irq(s->kbd_irq, rows && !s->kbd_mask && s->clk); 1944 s->row_latch = ~rows; 1945 } 1946 1947 static uint64_t omap_mpuio_read(void *opaque, hwaddr addr, 1948 unsigned size) 1949 { 1950 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; 1951 int offset = addr & OMAP_MPUI_REG_MASK; 1952 uint16_t ret; 1953 1954 if (size != 2) { 1955 return omap_badwidth_read16(opaque, addr); 1956 } 1957 1958 switch (offset) { 1959 case 0x00: /* INPUT_LATCH */ 1960 return s->inputs; 1961 1962 case 0x04: /* OUTPUT_REG */ 1963 return s->outputs; 1964 1965 case 0x08: /* IO_CNTL */ 1966 return s->dir; 1967 1968 case 0x10: /* KBR_LATCH */ 1969 return s->row_latch; 1970 1971 case 0x14: /* KBC_REG */ 1972 return s->cols; 1973 1974 case 0x18: /* GPIO_EVENT_MODE_REG */ 1975 return s->event; 1976 1977 case 0x1c: /* GPIO_INT_EDGE_REG */ 1978 return s->edge; 1979 1980 case 0x20: /* KBD_INT */ 1981 return (~s->row_latch & 0x1f) && !s->kbd_mask; 1982 1983 case 0x24: /* GPIO_INT */ 1984 ret = s->ints; 1985 s->ints &= s->mask; 1986 if (ret) 1987 qemu_irq_lower(s->irq); 1988 return ret; 1989 1990 case 0x28: /* KBD_MASKIT */ 1991 return s->kbd_mask; 1992 1993 case 0x2c: /* GPIO_MASKIT */ 1994 return s->mask; 1995 1996 case 0x30: /* GPIO_DEBOUNCING_REG */ 1997 return s->debounce; 1998 1999 case 0x34: /* GPIO_LATCH_REG */ 2000 return s->latch; 2001 } 2002 2003 OMAP_BAD_REG(addr); 2004 return 0; 2005 } 2006 2007 static void omap_mpuio_write(void *opaque, hwaddr addr, 2008 uint64_t value, unsigned size) 2009 { 2010 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; 2011 int offset = addr & OMAP_MPUI_REG_MASK; 2012 uint16_t diff; 2013 int ln; 2014 2015 if (size != 2) { 2016 omap_badwidth_write16(opaque, addr, value); 2017 return; 2018 } 2019 2020 switch (offset) { 2021 case 0x04: /* OUTPUT_REG */ 2022 diff = (s->outputs ^ value) & ~s->dir; 2023 s->outputs = value; 2024 while ((ln = ctz32(diff)) != 32) { 2025 if (s->handler[ln]) 2026 qemu_set_irq(s->handler[ln], (value >> ln) & 1); 2027 diff &= ~(1 << ln); 2028 } 2029 break; 2030 2031 case 0x08: /* IO_CNTL */ 2032 diff = s->outputs & (s->dir ^ value); 2033 s->dir = value; 2034 2035 value = s->outputs & ~s->dir; 2036 while ((ln = ctz32(diff)) != 32) { 2037 if (s->handler[ln]) 2038 qemu_set_irq(s->handler[ln], (value >> ln) & 1); 2039 diff &= ~(1 << ln); 2040 } 2041 break; 2042 2043 case 0x14: /* KBC_REG */ 2044 s->cols = value; 2045 omap_mpuio_kbd_update(s); 2046 break; 2047 2048 case 0x18: /* GPIO_EVENT_MODE_REG */ 2049 s->event = value & 0x1f; 2050 break; 2051 2052 case 0x1c: /* GPIO_INT_EDGE_REG */ 2053 s->edge = value; 2054 break; 2055 2056 case 0x28: /* KBD_MASKIT */ 2057 s->kbd_mask = value & 1; 2058 omap_mpuio_kbd_update(s); 2059 break; 2060 2061 case 0x2c: /* GPIO_MASKIT */ 2062 s->mask = value; 2063 break; 2064 2065 case 0x30: /* GPIO_DEBOUNCING_REG */ 2066 s->debounce = value & 0x1ff; 2067 break; 2068 2069 case 0x00: /* INPUT_LATCH */ 2070 case 0x10: /* KBR_LATCH */ 2071 case 0x20: /* KBD_INT */ 2072 case 0x24: /* GPIO_INT */ 2073 case 0x34: /* GPIO_LATCH_REG */ 2074 OMAP_RO_REG(addr); 2075 return; 2076 2077 default: 2078 OMAP_BAD_REG(addr); 2079 return; 2080 } 2081 } 2082 2083 static const MemoryRegionOps omap_mpuio_ops = { 2084 .read = omap_mpuio_read, 2085 .write = omap_mpuio_write, 2086 .endianness = DEVICE_NATIVE_ENDIAN, 2087 }; 2088 2089 static void omap_mpuio_reset(struct omap_mpuio_s *s) 2090 { 2091 s->inputs = 0; 2092 s->outputs = 0; 2093 s->dir = ~0; 2094 s->event = 0; 2095 s->edge = 0; 2096 s->kbd_mask = 0; 2097 s->mask = 0; 2098 s->debounce = 0; 2099 s->latch = 0; 2100 s->ints = 0; 2101 s->row_latch = 0x1f; 2102 s->clk = 1; 2103 } 2104 2105 static void omap_mpuio_onoff(void *opaque, int line, int on) 2106 { 2107 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; 2108 2109 s->clk = on; 2110 if (on) 2111 omap_mpuio_kbd_update(s); 2112 } 2113 2114 static struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *memory, 2115 hwaddr base, 2116 qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup, 2117 omap_clk clk) 2118 { 2119 struct omap_mpuio_s *s = g_new0(struct omap_mpuio_s, 1); 2120 2121 s->irq = gpio_int; 2122 s->kbd_irq = kbd_int; 2123 s->wakeup = wakeup; 2124 s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16); 2125 omap_mpuio_reset(s); 2126 2127 memory_region_init_io(&s->iomem, NULL, &omap_mpuio_ops, s, 2128 "omap-mpuio", 0x800); 2129 memory_region_add_subregion(memory, base, &s->iomem); 2130 2131 omap_clk_adduser(clk, qemu_allocate_irq(omap_mpuio_onoff, s, 0)); 2132 2133 return s; 2134 } 2135 2136 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s) 2137 { 2138 return s->in; 2139 } 2140 2141 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler) 2142 { 2143 if (line >= 16 || line < 0) 2144 hw_error("%s: No GPIO line %i\n", __func__, line); 2145 s->handler[line] = handler; 2146 } 2147 2148 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down) 2149 { 2150 if (row >= 5 || row < 0) 2151 hw_error("%s: No key %i-%i\n", __func__, col, row); 2152 2153 if (down) 2154 s->buttons[row] |= 1 << col; 2155 else 2156 s->buttons[row] &= ~(1 << col); 2157 2158 omap_mpuio_kbd_update(s); 2159 } 2160 2161 /* MicroWire Interface */ 2162 struct omap_uwire_s { 2163 MemoryRegion iomem; 2164 qemu_irq txirq; 2165 qemu_irq rxirq; 2166 qemu_irq txdrq; 2167 2168 uint16_t txbuf; 2169 uint16_t rxbuf; 2170 uint16_t control; 2171 uint16_t setup[5]; 2172 2173 uWireSlave *chip[4]; 2174 }; 2175 2176 static void omap_uwire_transfer_start(struct omap_uwire_s *s) 2177 { 2178 int chipselect = (s->control >> 10) & 3; /* INDEX */ 2179 uWireSlave *slave = s->chip[chipselect]; 2180 2181 if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */ 2182 if (s->control & (1 << 12)) /* CS_CMD */ 2183 if (slave && slave->send) 2184 slave->send(slave->opaque, 2185 s->txbuf >> (16 - ((s->control >> 5) & 0x1f))); 2186 s->control &= ~(1 << 14); /* CSRB */ 2187 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or 2188 * a DRQ. When is the level IRQ supposed to be reset? */ 2189 } 2190 2191 if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */ 2192 if (s->control & (1 << 12)) /* CS_CMD */ 2193 if (slave && slave->receive) 2194 s->rxbuf = slave->receive(slave->opaque); 2195 s->control |= 1 << 15; /* RDRB */ 2196 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or 2197 * a DRQ. When is the level IRQ supposed to be reset? */ 2198 } 2199 } 2200 2201 static uint64_t omap_uwire_read(void *opaque, hwaddr addr, 2202 unsigned size) 2203 { 2204 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; 2205 int offset = addr & OMAP_MPUI_REG_MASK; 2206 2207 if (size != 2) { 2208 return omap_badwidth_read16(opaque, addr); 2209 } 2210 2211 switch (offset) { 2212 case 0x00: /* RDR */ 2213 s->control &= ~(1 << 15); /* RDRB */ 2214 return s->rxbuf; 2215 2216 case 0x04: /* CSR */ 2217 return s->control; 2218 2219 case 0x08: /* SR1 */ 2220 return s->setup[0]; 2221 case 0x0c: /* SR2 */ 2222 return s->setup[1]; 2223 case 0x10: /* SR3 */ 2224 return s->setup[2]; 2225 case 0x14: /* SR4 */ 2226 return s->setup[3]; 2227 case 0x18: /* SR5 */ 2228 return s->setup[4]; 2229 } 2230 2231 OMAP_BAD_REG(addr); 2232 return 0; 2233 } 2234 2235 static void omap_uwire_write(void *opaque, hwaddr addr, 2236 uint64_t value, unsigned size) 2237 { 2238 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; 2239 int offset = addr & OMAP_MPUI_REG_MASK; 2240 2241 if (size != 2) { 2242 omap_badwidth_write16(opaque, addr, value); 2243 return; 2244 } 2245 2246 switch (offset) { 2247 case 0x00: /* TDR */ 2248 s->txbuf = value; /* TD */ 2249 if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */ 2250 ((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */ 2251 (s->control & (1 << 12)))) { /* CS_CMD */ 2252 s->control |= 1 << 14; /* CSRB */ 2253 omap_uwire_transfer_start(s); 2254 } 2255 break; 2256 2257 case 0x04: /* CSR */ 2258 s->control = value & 0x1fff; 2259 if (value & (1 << 13)) /* START */ 2260 omap_uwire_transfer_start(s); 2261 break; 2262 2263 case 0x08: /* SR1 */ 2264 s->setup[0] = value & 0x003f; 2265 break; 2266 2267 case 0x0c: /* SR2 */ 2268 s->setup[1] = value & 0x0fc0; 2269 break; 2270 2271 case 0x10: /* SR3 */ 2272 s->setup[2] = value & 0x0003; 2273 break; 2274 2275 case 0x14: /* SR4 */ 2276 s->setup[3] = value & 0x0001; 2277 break; 2278 2279 case 0x18: /* SR5 */ 2280 s->setup[4] = value & 0x000f; 2281 break; 2282 2283 default: 2284 OMAP_BAD_REG(addr); 2285 return; 2286 } 2287 } 2288 2289 static const MemoryRegionOps omap_uwire_ops = { 2290 .read = omap_uwire_read, 2291 .write = omap_uwire_write, 2292 .endianness = DEVICE_NATIVE_ENDIAN, 2293 }; 2294 2295 static void omap_uwire_reset(struct omap_uwire_s *s) 2296 { 2297 s->control = 0; 2298 s->setup[0] = 0; 2299 s->setup[1] = 0; 2300 s->setup[2] = 0; 2301 s->setup[3] = 0; 2302 s->setup[4] = 0; 2303 } 2304 2305 static struct omap_uwire_s *omap_uwire_init(MemoryRegion *system_memory, 2306 hwaddr base, 2307 qemu_irq txirq, qemu_irq rxirq, 2308 qemu_irq dma, 2309 omap_clk clk) 2310 { 2311 struct omap_uwire_s *s = g_new0(struct omap_uwire_s, 1); 2312 2313 s->txirq = txirq; 2314 s->rxirq = rxirq; 2315 s->txdrq = dma; 2316 omap_uwire_reset(s); 2317 2318 memory_region_init_io(&s->iomem, NULL, &omap_uwire_ops, s, "omap-uwire", 0x800); 2319 memory_region_add_subregion(system_memory, base, &s->iomem); 2320 2321 return s; 2322 } 2323 2324 void omap_uwire_attach(struct omap_uwire_s *s, 2325 uWireSlave *slave, int chipselect) 2326 { 2327 if (chipselect < 0 || chipselect > 3) { 2328 error_report("%s: Bad chipselect %i", __func__, chipselect); 2329 exit(-1); 2330 } 2331 2332 s->chip[chipselect] = slave; 2333 } 2334 2335 /* Pseudonoise Pulse-Width Light Modulator */ 2336 struct omap_pwl_s { 2337 MemoryRegion iomem; 2338 uint8_t output; 2339 uint8_t level; 2340 uint8_t enable; 2341 int clk; 2342 }; 2343 2344 static void omap_pwl_update(struct omap_pwl_s *s) 2345 { 2346 int output = (s->clk && s->enable) ? s->level : 0; 2347 2348 if (output != s->output) { 2349 s->output = output; 2350 printf("%s: Backlight now at %i/256\n", __func__, output); 2351 } 2352 } 2353 2354 static uint64_t omap_pwl_read(void *opaque, hwaddr addr, 2355 unsigned size) 2356 { 2357 struct omap_pwl_s *s = (struct omap_pwl_s *) opaque; 2358 int offset = addr & OMAP_MPUI_REG_MASK; 2359 2360 if (size != 1) { 2361 return omap_badwidth_read8(opaque, addr); 2362 } 2363 2364 switch (offset) { 2365 case 0x00: /* PWL_LEVEL */ 2366 return s->level; 2367 case 0x04: /* PWL_CTRL */ 2368 return s->enable; 2369 } 2370 OMAP_BAD_REG(addr); 2371 return 0; 2372 } 2373 2374 static void omap_pwl_write(void *opaque, hwaddr addr, 2375 uint64_t value, unsigned size) 2376 { 2377 struct omap_pwl_s *s = (struct omap_pwl_s *) opaque; 2378 int offset = addr & OMAP_MPUI_REG_MASK; 2379 2380 if (size != 1) { 2381 omap_badwidth_write8(opaque, addr, value); 2382 return; 2383 } 2384 2385 switch (offset) { 2386 case 0x00: /* PWL_LEVEL */ 2387 s->level = value; 2388 omap_pwl_update(s); 2389 break; 2390 case 0x04: /* PWL_CTRL */ 2391 s->enable = value & 1; 2392 omap_pwl_update(s); 2393 break; 2394 default: 2395 OMAP_BAD_REG(addr); 2396 return; 2397 } 2398 } 2399 2400 static const MemoryRegionOps omap_pwl_ops = { 2401 .read = omap_pwl_read, 2402 .write = omap_pwl_write, 2403 .endianness = DEVICE_NATIVE_ENDIAN, 2404 }; 2405 2406 static void omap_pwl_reset(struct omap_pwl_s *s) 2407 { 2408 s->output = 0; 2409 s->level = 0; 2410 s->enable = 0; 2411 s->clk = 1; 2412 omap_pwl_update(s); 2413 } 2414 2415 static void omap_pwl_clk_update(void *opaque, int line, int on) 2416 { 2417 struct omap_pwl_s *s = (struct omap_pwl_s *) opaque; 2418 2419 s->clk = on; 2420 omap_pwl_update(s); 2421 } 2422 2423 static struct omap_pwl_s *omap_pwl_init(MemoryRegion *system_memory, 2424 hwaddr base, 2425 omap_clk clk) 2426 { 2427 struct omap_pwl_s *s = g_malloc0(sizeof(*s)); 2428 2429 omap_pwl_reset(s); 2430 2431 memory_region_init_io(&s->iomem, NULL, &omap_pwl_ops, s, 2432 "omap-pwl", 0x800); 2433 memory_region_add_subregion(system_memory, base, &s->iomem); 2434 2435 omap_clk_adduser(clk, qemu_allocate_irq(omap_pwl_clk_update, s, 0)); 2436 return s; 2437 } 2438 2439 /* Pulse-Width Tone module */ 2440 struct omap_pwt_s { 2441 MemoryRegion iomem; 2442 uint8_t frc; 2443 uint8_t vrc; 2444 uint8_t gcr; 2445 omap_clk clk; 2446 }; 2447 2448 static uint64_t omap_pwt_read(void *opaque, hwaddr addr, 2449 unsigned size) 2450 { 2451 struct omap_pwt_s *s = (struct omap_pwt_s *) opaque; 2452 int offset = addr & OMAP_MPUI_REG_MASK; 2453 2454 if (size != 1) { 2455 return omap_badwidth_read8(opaque, addr); 2456 } 2457 2458 switch (offset) { 2459 case 0x00: /* FRC */ 2460 return s->frc; 2461 case 0x04: /* VCR */ 2462 return s->vrc; 2463 case 0x08: /* GCR */ 2464 return s->gcr; 2465 } 2466 OMAP_BAD_REG(addr); 2467 return 0; 2468 } 2469 2470 static void omap_pwt_write(void *opaque, hwaddr addr, 2471 uint64_t value, unsigned size) 2472 { 2473 struct omap_pwt_s *s = (struct omap_pwt_s *) opaque; 2474 int offset = addr & OMAP_MPUI_REG_MASK; 2475 2476 if (size != 1) { 2477 omap_badwidth_write8(opaque, addr, value); 2478 return; 2479 } 2480 2481 switch (offset) { 2482 case 0x00: /* FRC */ 2483 s->frc = value & 0x3f; 2484 break; 2485 case 0x04: /* VRC */ 2486 if ((value ^ s->vrc) & 1) { 2487 if (value & 1) 2488 printf("%s: %iHz buzz on\n", __func__, (int) 2489 /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */ 2490 ((omap_clk_getrate(s->clk) >> 3) / 2491 /* Pre-multiplexer divider */ 2492 ((s->gcr & 2) ? 1 : 154) / 2493 /* Octave multiplexer */ 2494 (2 << (value & 3)) * 2495 /* 101/107 divider */ 2496 ((value & (1 << 2)) ? 101 : 107) * 2497 /* 49/55 divider */ 2498 ((value & (1 << 3)) ? 49 : 55) * 2499 /* 50/63 divider */ 2500 ((value & (1 << 4)) ? 50 : 63) * 2501 /* 80/127 divider */ 2502 ((value & (1 << 5)) ? 80 : 127) / 2503 (107 * 55 * 63 * 127))); 2504 else 2505 printf("%s: silence!\n", __func__); 2506 } 2507 s->vrc = value & 0x7f; 2508 break; 2509 case 0x08: /* GCR */ 2510 s->gcr = value & 3; 2511 break; 2512 default: 2513 OMAP_BAD_REG(addr); 2514 return; 2515 } 2516 } 2517 2518 static const MemoryRegionOps omap_pwt_ops = { 2519 .read =omap_pwt_read, 2520 .write = omap_pwt_write, 2521 .endianness = DEVICE_NATIVE_ENDIAN, 2522 }; 2523 2524 static void omap_pwt_reset(struct omap_pwt_s *s) 2525 { 2526 s->frc = 0; 2527 s->vrc = 0; 2528 s->gcr = 0; 2529 } 2530 2531 static struct omap_pwt_s *omap_pwt_init(MemoryRegion *system_memory, 2532 hwaddr base, 2533 omap_clk clk) 2534 { 2535 struct omap_pwt_s *s = g_malloc0(sizeof(*s)); 2536 s->clk = clk; 2537 omap_pwt_reset(s); 2538 2539 memory_region_init_io(&s->iomem, NULL, &omap_pwt_ops, s, 2540 "omap-pwt", 0x800); 2541 memory_region_add_subregion(system_memory, base, &s->iomem); 2542 return s; 2543 } 2544 2545 /* Real-time Clock module */ 2546 struct omap_rtc_s { 2547 MemoryRegion iomem; 2548 qemu_irq irq; 2549 qemu_irq alarm; 2550 QEMUTimer *clk; 2551 2552 uint8_t interrupts; 2553 uint8_t status; 2554 int16_t comp_reg; 2555 int running; 2556 int pm_am; 2557 int auto_comp; 2558 int round; 2559 struct tm alarm_tm; 2560 time_t alarm_ti; 2561 2562 struct tm current_tm; 2563 time_t ti; 2564 uint64_t tick; 2565 }; 2566 2567 static void omap_rtc_interrupts_update(struct omap_rtc_s *s) 2568 { 2569 /* s->alarm is level-triggered */ 2570 qemu_set_irq(s->alarm, (s->status >> 6) & 1); 2571 } 2572 2573 static void omap_rtc_alarm_update(struct omap_rtc_s *s) 2574 { 2575 s->alarm_ti = mktimegm(&s->alarm_tm); 2576 if (s->alarm_ti == -1) 2577 printf("%s: conversion failed\n", __func__); 2578 } 2579 2580 static uint64_t omap_rtc_read(void *opaque, hwaddr addr, 2581 unsigned size) 2582 { 2583 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; 2584 int offset = addr & OMAP_MPUI_REG_MASK; 2585 uint8_t i; 2586 2587 if (size != 1) { 2588 return omap_badwidth_read8(opaque, addr); 2589 } 2590 2591 switch (offset) { 2592 case 0x00: /* SECONDS_REG */ 2593 return to_bcd(s->current_tm.tm_sec); 2594 2595 case 0x04: /* MINUTES_REG */ 2596 return to_bcd(s->current_tm.tm_min); 2597 2598 case 0x08: /* HOURS_REG */ 2599 if (s->pm_am) 2600 return ((s->current_tm.tm_hour > 11) << 7) | 2601 to_bcd(((s->current_tm.tm_hour - 1) % 12) + 1); 2602 else 2603 return to_bcd(s->current_tm.tm_hour); 2604 2605 case 0x0c: /* DAYS_REG */ 2606 return to_bcd(s->current_tm.tm_mday); 2607 2608 case 0x10: /* MONTHS_REG */ 2609 return to_bcd(s->current_tm.tm_mon + 1); 2610 2611 case 0x14: /* YEARS_REG */ 2612 return to_bcd(s->current_tm.tm_year % 100); 2613 2614 case 0x18: /* WEEK_REG */ 2615 return s->current_tm.tm_wday; 2616 2617 case 0x20: /* ALARM_SECONDS_REG */ 2618 return to_bcd(s->alarm_tm.tm_sec); 2619 2620 case 0x24: /* ALARM_MINUTES_REG */ 2621 return to_bcd(s->alarm_tm.tm_min); 2622 2623 case 0x28: /* ALARM_HOURS_REG */ 2624 if (s->pm_am) 2625 return ((s->alarm_tm.tm_hour > 11) << 7) | 2626 to_bcd(((s->alarm_tm.tm_hour - 1) % 12) + 1); 2627 else 2628 return to_bcd(s->alarm_tm.tm_hour); 2629 2630 case 0x2c: /* ALARM_DAYS_REG */ 2631 return to_bcd(s->alarm_tm.tm_mday); 2632 2633 case 0x30: /* ALARM_MONTHS_REG */ 2634 return to_bcd(s->alarm_tm.tm_mon + 1); 2635 2636 case 0x34: /* ALARM_YEARS_REG */ 2637 return to_bcd(s->alarm_tm.tm_year % 100); 2638 2639 case 0x40: /* RTC_CTRL_REG */ 2640 return (s->pm_am << 3) | (s->auto_comp << 2) | 2641 (s->round << 1) | s->running; 2642 2643 case 0x44: /* RTC_STATUS_REG */ 2644 i = s->status; 2645 s->status &= ~0x3d; 2646 return i; 2647 2648 case 0x48: /* RTC_INTERRUPTS_REG */ 2649 return s->interrupts; 2650 2651 case 0x4c: /* RTC_COMP_LSB_REG */ 2652 return ((uint16_t) s->comp_reg) & 0xff; 2653 2654 case 0x50: /* RTC_COMP_MSB_REG */ 2655 return ((uint16_t) s->comp_reg) >> 8; 2656 } 2657 2658 OMAP_BAD_REG(addr); 2659 return 0; 2660 } 2661 2662 static void omap_rtc_write(void *opaque, hwaddr addr, 2663 uint64_t value, unsigned size) 2664 { 2665 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; 2666 int offset = addr & OMAP_MPUI_REG_MASK; 2667 struct tm new_tm; 2668 time_t ti[2]; 2669 2670 if (size != 1) { 2671 omap_badwidth_write8(opaque, addr, value); 2672 return; 2673 } 2674 2675 switch (offset) { 2676 case 0x00: /* SECONDS_REG */ 2677 #ifdef ALMDEBUG 2678 printf("RTC SEC_REG <-- %02x\n", value); 2679 #endif 2680 s->ti -= s->current_tm.tm_sec; 2681 s->ti += from_bcd(value); 2682 return; 2683 2684 case 0x04: /* MINUTES_REG */ 2685 #ifdef ALMDEBUG 2686 printf("RTC MIN_REG <-- %02x\n", value); 2687 #endif 2688 s->ti -= s->current_tm.tm_min * 60; 2689 s->ti += from_bcd(value) * 60; 2690 return; 2691 2692 case 0x08: /* HOURS_REG */ 2693 #ifdef ALMDEBUG 2694 printf("RTC HRS_REG <-- %02x\n", value); 2695 #endif 2696 s->ti -= s->current_tm.tm_hour * 3600; 2697 if (s->pm_am) { 2698 s->ti += (from_bcd(value & 0x3f) & 12) * 3600; 2699 s->ti += ((value >> 7) & 1) * 43200; 2700 } else 2701 s->ti += from_bcd(value & 0x3f) * 3600; 2702 return; 2703 2704 case 0x0c: /* DAYS_REG */ 2705 #ifdef ALMDEBUG 2706 printf("RTC DAY_REG <-- %02x\n", value); 2707 #endif 2708 s->ti -= s->current_tm.tm_mday * 86400; 2709 s->ti += from_bcd(value) * 86400; 2710 return; 2711 2712 case 0x10: /* MONTHS_REG */ 2713 #ifdef ALMDEBUG 2714 printf("RTC MTH_REG <-- %02x\n", value); 2715 #endif 2716 memcpy(&new_tm, &s->current_tm, sizeof(new_tm)); 2717 new_tm.tm_mon = from_bcd(value); 2718 ti[0] = mktimegm(&s->current_tm); 2719 ti[1] = mktimegm(&new_tm); 2720 2721 if (ti[0] != -1 && ti[1] != -1) { 2722 s->ti -= ti[0]; 2723 s->ti += ti[1]; 2724 } else { 2725 /* A less accurate version */ 2726 s->ti -= s->current_tm.tm_mon * 2592000; 2727 s->ti += from_bcd(value) * 2592000; 2728 } 2729 return; 2730 2731 case 0x14: /* YEARS_REG */ 2732 #ifdef ALMDEBUG 2733 printf("RTC YRS_REG <-- %02x\n", value); 2734 #endif 2735 memcpy(&new_tm, &s->current_tm, sizeof(new_tm)); 2736 new_tm.tm_year += from_bcd(value) - (new_tm.tm_year % 100); 2737 ti[0] = mktimegm(&s->current_tm); 2738 ti[1] = mktimegm(&new_tm); 2739 2740 if (ti[0] != -1 && ti[1] != -1) { 2741 s->ti -= ti[0]; 2742 s->ti += ti[1]; 2743 } else { 2744 /* A less accurate version */ 2745 s->ti -= (time_t)(s->current_tm.tm_year % 100) * 31536000; 2746 s->ti += (time_t)from_bcd(value) * 31536000; 2747 } 2748 return; 2749 2750 case 0x18: /* WEEK_REG */ 2751 return; /* Ignored */ 2752 2753 case 0x20: /* ALARM_SECONDS_REG */ 2754 #ifdef ALMDEBUG 2755 printf("ALM SEC_REG <-- %02x\n", value); 2756 #endif 2757 s->alarm_tm.tm_sec = from_bcd(value); 2758 omap_rtc_alarm_update(s); 2759 return; 2760 2761 case 0x24: /* ALARM_MINUTES_REG */ 2762 #ifdef ALMDEBUG 2763 printf("ALM MIN_REG <-- %02x\n", value); 2764 #endif 2765 s->alarm_tm.tm_min = from_bcd(value); 2766 omap_rtc_alarm_update(s); 2767 return; 2768 2769 case 0x28: /* ALARM_HOURS_REG */ 2770 #ifdef ALMDEBUG 2771 printf("ALM HRS_REG <-- %02x\n", value); 2772 #endif 2773 if (s->pm_am) 2774 s->alarm_tm.tm_hour = 2775 ((from_bcd(value & 0x3f)) % 12) + 2776 ((value >> 7) & 1) * 12; 2777 else 2778 s->alarm_tm.tm_hour = from_bcd(value); 2779 omap_rtc_alarm_update(s); 2780 return; 2781 2782 case 0x2c: /* ALARM_DAYS_REG */ 2783 #ifdef ALMDEBUG 2784 printf("ALM DAY_REG <-- %02x\n", value); 2785 #endif 2786 s->alarm_tm.tm_mday = from_bcd(value); 2787 omap_rtc_alarm_update(s); 2788 return; 2789 2790 case 0x30: /* ALARM_MONTHS_REG */ 2791 #ifdef ALMDEBUG 2792 printf("ALM MON_REG <-- %02x\n", value); 2793 #endif 2794 s->alarm_tm.tm_mon = from_bcd(value); 2795 omap_rtc_alarm_update(s); 2796 return; 2797 2798 case 0x34: /* ALARM_YEARS_REG */ 2799 #ifdef ALMDEBUG 2800 printf("ALM YRS_REG <-- %02x\n", value); 2801 #endif 2802 s->alarm_tm.tm_year = from_bcd(value); 2803 omap_rtc_alarm_update(s); 2804 return; 2805 2806 case 0x40: /* RTC_CTRL_REG */ 2807 #ifdef ALMDEBUG 2808 printf("RTC CONTROL <-- %02x\n", value); 2809 #endif 2810 s->pm_am = (value >> 3) & 1; 2811 s->auto_comp = (value >> 2) & 1; 2812 s->round = (value >> 1) & 1; 2813 s->running = value & 1; 2814 s->status &= 0xfd; 2815 s->status |= s->running << 1; 2816 return; 2817 2818 case 0x44: /* RTC_STATUS_REG */ 2819 #ifdef ALMDEBUG 2820 printf("RTC STATUSL <-- %02x\n", value); 2821 #endif 2822 s->status &= ~((value & 0xc0) ^ 0x80); 2823 omap_rtc_interrupts_update(s); 2824 return; 2825 2826 case 0x48: /* RTC_INTERRUPTS_REG */ 2827 #ifdef ALMDEBUG 2828 printf("RTC INTRS <-- %02x\n", value); 2829 #endif 2830 s->interrupts = value; 2831 return; 2832 2833 case 0x4c: /* RTC_COMP_LSB_REG */ 2834 #ifdef ALMDEBUG 2835 printf("RTC COMPLSB <-- %02x\n", value); 2836 #endif 2837 s->comp_reg &= 0xff00; 2838 s->comp_reg |= 0x00ff & value; 2839 return; 2840 2841 case 0x50: /* RTC_COMP_MSB_REG */ 2842 #ifdef ALMDEBUG 2843 printf("RTC COMPMSB <-- %02x\n", value); 2844 #endif 2845 s->comp_reg &= 0x00ff; 2846 s->comp_reg |= 0xff00 & (value << 8); 2847 return; 2848 2849 default: 2850 OMAP_BAD_REG(addr); 2851 return; 2852 } 2853 } 2854 2855 static const MemoryRegionOps omap_rtc_ops = { 2856 .read = omap_rtc_read, 2857 .write = omap_rtc_write, 2858 .endianness = DEVICE_NATIVE_ENDIAN, 2859 }; 2860 2861 static void omap_rtc_tick(void *opaque) 2862 { 2863 struct omap_rtc_s *s = opaque; 2864 2865 if (s->round) { 2866 /* Round to nearest full minute. */ 2867 if (s->current_tm.tm_sec < 30) 2868 s->ti -= s->current_tm.tm_sec; 2869 else 2870 s->ti += 60 - s->current_tm.tm_sec; 2871 2872 s->round = 0; 2873 } 2874 2875 localtime_r(&s->ti, &s->current_tm); 2876 2877 if ((s->interrupts & 0x08) && s->ti == s->alarm_ti) { 2878 s->status |= 0x40; 2879 omap_rtc_interrupts_update(s); 2880 } 2881 2882 if (s->interrupts & 0x04) 2883 switch (s->interrupts & 3) { 2884 case 0: 2885 s->status |= 0x04; 2886 qemu_irq_pulse(s->irq); 2887 break; 2888 case 1: 2889 if (s->current_tm.tm_sec) 2890 break; 2891 s->status |= 0x08; 2892 qemu_irq_pulse(s->irq); 2893 break; 2894 case 2: 2895 if (s->current_tm.tm_sec || s->current_tm.tm_min) 2896 break; 2897 s->status |= 0x10; 2898 qemu_irq_pulse(s->irq); 2899 break; 2900 case 3: 2901 if (s->current_tm.tm_sec || 2902 s->current_tm.tm_min || s->current_tm.tm_hour) 2903 break; 2904 s->status |= 0x20; 2905 qemu_irq_pulse(s->irq); 2906 break; 2907 } 2908 2909 /* Move on */ 2910 if (s->running) 2911 s->ti ++; 2912 s->tick += 1000; 2913 2914 /* 2915 * Every full hour add a rough approximation of the compensation 2916 * register to the 32kHz Timer (which drives the RTC) value. 2917 */ 2918 if (s->auto_comp && !s->current_tm.tm_sec && !s->current_tm.tm_min) 2919 s->tick += s->comp_reg * 1000 / 32768; 2920 2921 timer_mod(s->clk, s->tick); 2922 } 2923 2924 static void omap_rtc_reset(struct omap_rtc_s *s) 2925 { 2926 struct tm tm; 2927 2928 s->interrupts = 0; 2929 s->comp_reg = 0; 2930 s->running = 0; 2931 s->pm_am = 0; 2932 s->auto_comp = 0; 2933 s->round = 0; 2934 s->tick = qemu_clock_get_ms(rtc_clock); 2935 memset(&s->alarm_tm, 0, sizeof(s->alarm_tm)); 2936 s->alarm_tm.tm_mday = 0x01; 2937 s->status = 1 << 7; 2938 qemu_get_timedate(&tm, 0); 2939 s->ti = mktimegm(&tm); 2940 2941 omap_rtc_alarm_update(s); 2942 omap_rtc_tick(s); 2943 } 2944 2945 static struct omap_rtc_s *omap_rtc_init(MemoryRegion *system_memory, 2946 hwaddr base, 2947 qemu_irq timerirq, qemu_irq alarmirq, 2948 omap_clk clk) 2949 { 2950 struct omap_rtc_s *s = g_new0(struct omap_rtc_s, 1); 2951 2952 s->irq = timerirq; 2953 s->alarm = alarmirq; 2954 s->clk = timer_new_ms(rtc_clock, omap_rtc_tick, s); 2955 2956 omap_rtc_reset(s); 2957 2958 memory_region_init_io(&s->iomem, NULL, &omap_rtc_ops, s, 2959 "omap-rtc", 0x800); 2960 memory_region_add_subregion(system_memory, base, &s->iomem); 2961 2962 return s; 2963 } 2964 2965 /* Multi-channel Buffered Serial Port interfaces */ 2966 struct omap_mcbsp_s { 2967 MemoryRegion iomem; 2968 qemu_irq txirq; 2969 qemu_irq rxirq; 2970 qemu_irq txdrq; 2971 qemu_irq rxdrq; 2972 2973 uint16_t spcr[2]; 2974 uint16_t rcr[2]; 2975 uint16_t xcr[2]; 2976 uint16_t srgr[2]; 2977 uint16_t mcr[2]; 2978 uint16_t pcr; 2979 uint16_t rcer[8]; 2980 uint16_t xcer[8]; 2981 int tx_rate; 2982 int rx_rate; 2983 int tx_req; 2984 int rx_req; 2985 2986 I2SCodec *codec; 2987 QEMUTimer *source_timer; 2988 QEMUTimer *sink_timer; 2989 }; 2990 2991 static void omap_mcbsp_intr_update(struct omap_mcbsp_s *s) 2992 { 2993 int irq; 2994 2995 switch ((s->spcr[0] >> 4) & 3) { /* RINTM */ 2996 case 0: 2997 irq = (s->spcr[0] >> 1) & 1; /* RRDY */ 2998 break; 2999 case 3: 3000 irq = (s->spcr[0] >> 3) & 1; /* RSYNCERR */ 3001 break; 3002 default: 3003 irq = 0; 3004 break; 3005 } 3006 3007 if (irq) 3008 qemu_irq_pulse(s->rxirq); 3009 3010 switch ((s->spcr[1] >> 4) & 3) { /* XINTM */ 3011 case 0: 3012 irq = (s->spcr[1] >> 1) & 1; /* XRDY */ 3013 break; 3014 case 3: 3015 irq = (s->spcr[1] >> 3) & 1; /* XSYNCERR */ 3016 break; 3017 default: 3018 irq = 0; 3019 break; 3020 } 3021 3022 if (irq) 3023 qemu_irq_pulse(s->txirq); 3024 } 3025 3026 static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s) 3027 { 3028 if ((s->spcr[0] >> 1) & 1) /* RRDY */ 3029 s->spcr[0] |= 1 << 2; /* RFULL */ 3030 s->spcr[0] |= 1 << 1; /* RRDY */ 3031 qemu_irq_raise(s->rxdrq); 3032 omap_mcbsp_intr_update(s); 3033 } 3034 3035 static void omap_mcbsp_source_tick(void *opaque) 3036 { 3037 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3038 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 }; 3039 3040 if (!s->rx_rate) 3041 return; 3042 if (s->rx_req) 3043 printf("%s: Rx FIFO overrun\n", __func__); 3044 3045 s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7]; 3046 3047 omap_mcbsp_rx_newdata(s); 3048 timer_mod(s->source_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 3049 NANOSECONDS_PER_SECOND); 3050 } 3051 3052 static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s) 3053 { 3054 if (!s->codec || !s->codec->rts) 3055 omap_mcbsp_source_tick(s); 3056 else if (s->codec->in.len) { 3057 s->rx_req = s->codec->in.len; 3058 omap_mcbsp_rx_newdata(s); 3059 } 3060 } 3061 3062 static void omap_mcbsp_rx_stop(struct omap_mcbsp_s *s) 3063 { 3064 timer_del(s->source_timer); 3065 } 3066 3067 static void omap_mcbsp_rx_done(struct omap_mcbsp_s *s) 3068 { 3069 s->spcr[0] &= ~(1 << 1); /* RRDY */ 3070 qemu_irq_lower(s->rxdrq); 3071 omap_mcbsp_intr_update(s); 3072 } 3073 3074 static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s) 3075 { 3076 s->spcr[1] |= 1 << 1; /* XRDY */ 3077 qemu_irq_raise(s->txdrq); 3078 omap_mcbsp_intr_update(s); 3079 } 3080 3081 static void omap_mcbsp_sink_tick(void *opaque) 3082 { 3083 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3084 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 }; 3085 3086 if (!s->tx_rate) 3087 return; 3088 if (s->tx_req) 3089 printf("%s: Tx FIFO underrun\n", __func__); 3090 3091 s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7]; 3092 3093 omap_mcbsp_tx_newdata(s); 3094 timer_mod(s->sink_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 3095 NANOSECONDS_PER_SECOND); 3096 } 3097 3098 static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s) 3099 { 3100 if (!s->codec || !s->codec->cts) 3101 omap_mcbsp_sink_tick(s); 3102 else if (s->codec->out.size) { 3103 s->tx_req = s->codec->out.size; 3104 omap_mcbsp_tx_newdata(s); 3105 } 3106 } 3107 3108 static void omap_mcbsp_tx_done(struct omap_mcbsp_s *s) 3109 { 3110 s->spcr[1] &= ~(1 << 1); /* XRDY */ 3111 qemu_irq_lower(s->txdrq); 3112 omap_mcbsp_intr_update(s); 3113 if (s->codec && s->codec->cts) 3114 s->codec->tx_swallow(s->codec->opaque); 3115 } 3116 3117 static void omap_mcbsp_tx_stop(struct omap_mcbsp_s *s) 3118 { 3119 s->tx_req = 0; 3120 omap_mcbsp_tx_done(s); 3121 timer_del(s->sink_timer); 3122 } 3123 3124 static void omap_mcbsp_req_update(struct omap_mcbsp_s *s) 3125 { 3126 int prev_rx_rate, prev_tx_rate; 3127 int rx_rate = 0, tx_rate = 0; 3128 int cpu_rate = 1500000; /* XXX */ 3129 3130 /* TODO: check CLKSTP bit */ 3131 if (s->spcr[1] & (1 << 6)) { /* GRST */ 3132 if (s->spcr[0] & (1 << 0)) { /* RRST */ 3133 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ 3134 (s->pcr & (1 << 8))) { /* CLKRM */ 3135 if (~s->pcr & (1 << 7)) /* SCLKME */ 3136 rx_rate = cpu_rate / 3137 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ 3138 } else 3139 if (s->codec) 3140 rx_rate = s->codec->rx_rate; 3141 } 3142 3143 if (s->spcr[1] & (1 << 0)) { /* XRST */ 3144 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ 3145 (s->pcr & (1 << 9))) { /* CLKXM */ 3146 if (~s->pcr & (1 << 7)) /* SCLKME */ 3147 tx_rate = cpu_rate / 3148 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ 3149 } else 3150 if (s->codec) 3151 tx_rate = s->codec->tx_rate; 3152 } 3153 } 3154 prev_tx_rate = s->tx_rate; 3155 prev_rx_rate = s->rx_rate; 3156 s->tx_rate = tx_rate; 3157 s->rx_rate = rx_rate; 3158 3159 if (s->codec) 3160 s->codec->set_rate(s->codec->opaque, rx_rate, tx_rate); 3161 3162 if (!prev_tx_rate && tx_rate) 3163 omap_mcbsp_tx_start(s); 3164 else if (s->tx_rate && !tx_rate) 3165 omap_mcbsp_tx_stop(s); 3166 3167 if (!prev_rx_rate && rx_rate) 3168 omap_mcbsp_rx_start(s); 3169 else if (prev_tx_rate && !tx_rate) 3170 omap_mcbsp_rx_stop(s); 3171 } 3172 3173 static uint64_t omap_mcbsp_read(void *opaque, hwaddr addr, 3174 unsigned size) 3175 { 3176 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3177 int offset = addr & OMAP_MPUI_REG_MASK; 3178 uint16_t ret; 3179 3180 if (size != 2) { 3181 return omap_badwidth_read16(opaque, addr); 3182 } 3183 3184 switch (offset) { 3185 case 0x00: /* DRR2 */ 3186 if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */ 3187 return 0x0000; 3188 /* Fall through. */ 3189 case 0x02: /* DRR1 */ 3190 if (s->rx_req < 2) { 3191 printf("%s: Rx FIFO underrun\n", __func__); 3192 omap_mcbsp_rx_done(s); 3193 } else { 3194 s->tx_req -= 2; 3195 if (s->codec && s->codec->in.len >= 2) { 3196 ret = s->codec->in.fifo[s->codec->in.start ++] << 8; 3197 ret |= s->codec->in.fifo[s->codec->in.start ++]; 3198 s->codec->in.len -= 2; 3199 } else 3200 ret = 0x0000; 3201 if (!s->tx_req) 3202 omap_mcbsp_rx_done(s); 3203 return ret; 3204 } 3205 return 0x0000; 3206 3207 case 0x04: /* DXR2 */ 3208 case 0x06: /* DXR1 */ 3209 return 0x0000; 3210 3211 case 0x08: /* SPCR2 */ 3212 return s->spcr[1]; 3213 case 0x0a: /* SPCR1 */ 3214 return s->spcr[0]; 3215 case 0x0c: /* RCR2 */ 3216 return s->rcr[1]; 3217 case 0x0e: /* RCR1 */ 3218 return s->rcr[0]; 3219 case 0x10: /* XCR2 */ 3220 return s->xcr[1]; 3221 case 0x12: /* XCR1 */ 3222 return s->xcr[0]; 3223 case 0x14: /* SRGR2 */ 3224 return s->srgr[1]; 3225 case 0x16: /* SRGR1 */ 3226 return s->srgr[0]; 3227 case 0x18: /* MCR2 */ 3228 return s->mcr[1]; 3229 case 0x1a: /* MCR1 */ 3230 return s->mcr[0]; 3231 case 0x1c: /* RCERA */ 3232 return s->rcer[0]; 3233 case 0x1e: /* RCERB */ 3234 return s->rcer[1]; 3235 case 0x20: /* XCERA */ 3236 return s->xcer[0]; 3237 case 0x22: /* XCERB */ 3238 return s->xcer[1]; 3239 case 0x24: /* PCR0 */ 3240 return s->pcr; 3241 case 0x26: /* RCERC */ 3242 return s->rcer[2]; 3243 case 0x28: /* RCERD */ 3244 return s->rcer[3]; 3245 case 0x2a: /* XCERC */ 3246 return s->xcer[2]; 3247 case 0x2c: /* XCERD */ 3248 return s->xcer[3]; 3249 case 0x2e: /* RCERE */ 3250 return s->rcer[4]; 3251 case 0x30: /* RCERF */ 3252 return s->rcer[5]; 3253 case 0x32: /* XCERE */ 3254 return s->xcer[4]; 3255 case 0x34: /* XCERF */ 3256 return s->xcer[5]; 3257 case 0x36: /* RCERG */ 3258 return s->rcer[6]; 3259 case 0x38: /* RCERH */ 3260 return s->rcer[7]; 3261 case 0x3a: /* XCERG */ 3262 return s->xcer[6]; 3263 case 0x3c: /* XCERH */ 3264 return s->xcer[7]; 3265 } 3266 3267 OMAP_BAD_REG(addr); 3268 return 0; 3269 } 3270 3271 static void omap_mcbsp_writeh(void *opaque, hwaddr addr, 3272 uint32_t value) 3273 { 3274 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3275 int offset = addr & OMAP_MPUI_REG_MASK; 3276 3277 switch (offset) { 3278 case 0x00: /* DRR2 */ 3279 case 0x02: /* DRR1 */ 3280 OMAP_RO_REG(addr); 3281 return; 3282 3283 case 0x04: /* DXR2 */ 3284 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ 3285 return; 3286 /* Fall through. */ 3287 case 0x06: /* DXR1 */ 3288 if (s->tx_req > 1) { 3289 s->tx_req -= 2; 3290 if (s->codec && s->codec->cts) { 3291 s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff; 3292 s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff; 3293 } 3294 if (s->tx_req < 2) 3295 omap_mcbsp_tx_done(s); 3296 } else 3297 printf("%s: Tx FIFO overrun\n", __func__); 3298 return; 3299 3300 case 0x08: /* SPCR2 */ 3301 s->spcr[1] &= 0x0002; 3302 s->spcr[1] |= 0x03f9 & value; 3303 s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */ 3304 if (~value & 1) /* XRST */ 3305 s->spcr[1] &= ~6; 3306 omap_mcbsp_req_update(s); 3307 return; 3308 case 0x0a: /* SPCR1 */ 3309 s->spcr[0] &= 0x0006; 3310 s->spcr[0] |= 0xf8f9 & value; 3311 if (value & (1 << 15)) /* DLB */ 3312 printf("%s: Digital Loopback mode enable attempt\n", __func__); 3313 if (~value & 1) { /* RRST */ 3314 s->spcr[0] &= ~6; 3315 s->rx_req = 0; 3316 omap_mcbsp_rx_done(s); 3317 } 3318 omap_mcbsp_req_update(s); 3319 return; 3320 3321 case 0x0c: /* RCR2 */ 3322 s->rcr[1] = value & 0xffff; 3323 return; 3324 case 0x0e: /* RCR1 */ 3325 s->rcr[0] = value & 0x7fe0; 3326 return; 3327 case 0x10: /* XCR2 */ 3328 s->xcr[1] = value & 0xffff; 3329 return; 3330 case 0x12: /* XCR1 */ 3331 s->xcr[0] = value & 0x7fe0; 3332 return; 3333 case 0x14: /* SRGR2 */ 3334 s->srgr[1] = value & 0xffff; 3335 omap_mcbsp_req_update(s); 3336 return; 3337 case 0x16: /* SRGR1 */ 3338 s->srgr[0] = value & 0xffff; 3339 omap_mcbsp_req_update(s); 3340 return; 3341 case 0x18: /* MCR2 */ 3342 s->mcr[1] = value & 0x03e3; 3343 if (value & 3) /* XMCM */ 3344 printf("%s: Tx channel selection mode enable attempt\n", __func__); 3345 return; 3346 case 0x1a: /* MCR1 */ 3347 s->mcr[0] = value & 0x03e1; 3348 if (value & 1) /* RMCM */ 3349 printf("%s: Rx channel selection mode enable attempt\n", __func__); 3350 return; 3351 case 0x1c: /* RCERA */ 3352 s->rcer[0] = value & 0xffff; 3353 return; 3354 case 0x1e: /* RCERB */ 3355 s->rcer[1] = value & 0xffff; 3356 return; 3357 case 0x20: /* XCERA */ 3358 s->xcer[0] = value & 0xffff; 3359 return; 3360 case 0x22: /* XCERB */ 3361 s->xcer[1] = value & 0xffff; 3362 return; 3363 case 0x24: /* PCR0 */ 3364 s->pcr = value & 0x7faf; 3365 return; 3366 case 0x26: /* RCERC */ 3367 s->rcer[2] = value & 0xffff; 3368 return; 3369 case 0x28: /* RCERD */ 3370 s->rcer[3] = value & 0xffff; 3371 return; 3372 case 0x2a: /* XCERC */ 3373 s->xcer[2] = value & 0xffff; 3374 return; 3375 case 0x2c: /* XCERD */ 3376 s->xcer[3] = value & 0xffff; 3377 return; 3378 case 0x2e: /* RCERE */ 3379 s->rcer[4] = value & 0xffff; 3380 return; 3381 case 0x30: /* RCERF */ 3382 s->rcer[5] = value & 0xffff; 3383 return; 3384 case 0x32: /* XCERE */ 3385 s->xcer[4] = value & 0xffff; 3386 return; 3387 case 0x34: /* XCERF */ 3388 s->xcer[5] = value & 0xffff; 3389 return; 3390 case 0x36: /* RCERG */ 3391 s->rcer[6] = value & 0xffff; 3392 return; 3393 case 0x38: /* RCERH */ 3394 s->rcer[7] = value & 0xffff; 3395 return; 3396 case 0x3a: /* XCERG */ 3397 s->xcer[6] = value & 0xffff; 3398 return; 3399 case 0x3c: /* XCERH */ 3400 s->xcer[7] = value & 0xffff; 3401 return; 3402 } 3403 3404 OMAP_BAD_REG(addr); 3405 } 3406 3407 static void omap_mcbsp_writew(void *opaque, hwaddr addr, 3408 uint32_t value) 3409 { 3410 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3411 int offset = addr & OMAP_MPUI_REG_MASK; 3412 3413 if (offset == 0x04) { /* DXR */ 3414 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ 3415 return; 3416 if (s->tx_req > 3) { 3417 s->tx_req -= 4; 3418 if (s->codec && s->codec->cts) { 3419 s->codec->out.fifo[s->codec->out.len ++] = 3420 (value >> 24) & 0xff; 3421 s->codec->out.fifo[s->codec->out.len ++] = 3422 (value >> 16) & 0xff; 3423 s->codec->out.fifo[s->codec->out.len ++] = 3424 (value >> 8) & 0xff; 3425 s->codec->out.fifo[s->codec->out.len ++] = 3426 (value >> 0) & 0xff; 3427 } 3428 if (s->tx_req < 4) 3429 omap_mcbsp_tx_done(s); 3430 } else 3431 printf("%s: Tx FIFO overrun\n", __func__); 3432 return; 3433 } 3434 3435 omap_badwidth_write16(opaque, addr, value); 3436 } 3437 3438 static void omap_mcbsp_write(void *opaque, hwaddr addr, 3439 uint64_t value, unsigned size) 3440 { 3441 switch (size) { 3442 case 2: 3443 omap_mcbsp_writeh(opaque, addr, value); 3444 break; 3445 case 4: 3446 omap_mcbsp_writew(opaque, addr, value); 3447 break; 3448 default: 3449 omap_badwidth_write16(opaque, addr, value); 3450 } 3451 } 3452 3453 static const MemoryRegionOps omap_mcbsp_ops = { 3454 .read = omap_mcbsp_read, 3455 .write = omap_mcbsp_write, 3456 .endianness = DEVICE_NATIVE_ENDIAN, 3457 }; 3458 3459 static void omap_mcbsp_reset(struct omap_mcbsp_s *s) 3460 { 3461 memset(&s->spcr, 0, sizeof(s->spcr)); 3462 memset(&s->rcr, 0, sizeof(s->rcr)); 3463 memset(&s->xcr, 0, sizeof(s->xcr)); 3464 s->srgr[0] = 0x0001; 3465 s->srgr[1] = 0x2000; 3466 memset(&s->mcr, 0, sizeof(s->mcr)); 3467 memset(&s->pcr, 0, sizeof(s->pcr)); 3468 memset(&s->rcer, 0, sizeof(s->rcer)); 3469 memset(&s->xcer, 0, sizeof(s->xcer)); 3470 s->tx_req = 0; 3471 s->rx_req = 0; 3472 s->tx_rate = 0; 3473 s->rx_rate = 0; 3474 timer_del(s->source_timer); 3475 timer_del(s->sink_timer); 3476 } 3477 3478 static struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory, 3479 hwaddr base, 3480 qemu_irq txirq, qemu_irq rxirq, 3481 qemu_irq *dma, omap_clk clk) 3482 { 3483 struct omap_mcbsp_s *s = g_new0(struct omap_mcbsp_s, 1); 3484 3485 s->txirq = txirq; 3486 s->rxirq = rxirq; 3487 s->txdrq = dma[0]; 3488 s->rxdrq = dma[1]; 3489 s->sink_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_mcbsp_sink_tick, s); 3490 s->source_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_mcbsp_source_tick, s); 3491 omap_mcbsp_reset(s); 3492 3493 memory_region_init_io(&s->iomem, NULL, &omap_mcbsp_ops, s, "omap-mcbsp", 0x800); 3494 memory_region_add_subregion(system_memory, base, &s->iomem); 3495 3496 return s; 3497 } 3498 3499 static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level) 3500 { 3501 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3502 3503 if (s->rx_rate) { 3504 s->rx_req = s->codec->in.len; 3505 omap_mcbsp_rx_newdata(s); 3506 } 3507 } 3508 3509 static void omap_mcbsp_i2s_start(void *opaque, int line, int level) 3510 { 3511 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3512 3513 if (s->tx_rate) { 3514 s->tx_req = s->codec->out.size; 3515 omap_mcbsp_tx_newdata(s); 3516 } 3517 } 3518 3519 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave) 3520 { 3521 s->codec = slave; 3522 slave->rx_swallow = qemu_allocate_irq(omap_mcbsp_i2s_swallow, s, 0); 3523 slave->tx_start = qemu_allocate_irq(omap_mcbsp_i2s_start, s, 0); 3524 } 3525 3526 /* LED Pulse Generators */ 3527 struct omap_lpg_s { 3528 MemoryRegion iomem; 3529 QEMUTimer *tm; 3530 3531 uint8_t control; 3532 uint8_t power; 3533 int64_t on; 3534 int64_t period; 3535 int clk; 3536 int cycle; 3537 }; 3538 3539 static void omap_lpg_tick(void *opaque) 3540 { 3541 struct omap_lpg_s *s = opaque; 3542 3543 if (s->cycle) 3544 timer_mod(s->tm, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->period - s->on); 3545 else 3546 timer_mod(s->tm, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->on); 3547 3548 s->cycle = !s->cycle; 3549 printf("%s: LED is %s\n", __func__, s->cycle ? "on" : "off"); 3550 } 3551 3552 static void omap_lpg_update(struct omap_lpg_s *s) 3553 { 3554 int64_t on, period = 1, ticks = 1000; 3555 static const int per[8] = { 1, 2, 4, 8, 12, 16, 20, 24 }; 3556 3557 if (~s->control & (1 << 6)) /* LPGRES */ 3558 on = 0; 3559 else if (s->control & (1 << 7)) /* PERM_ON */ 3560 on = period; 3561 else { 3562 period = muldiv64(ticks, per[s->control & 7], /* PERCTRL */ 3563 256 / 32); 3564 on = (s->clk && s->power) ? muldiv64(ticks, 3565 per[(s->control >> 3) & 7], 256) : 0; /* ONCTRL */ 3566 } 3567 3568 timer_del(s->tm); 3569 if (on == period && s->on < s->period) 3570 printf("%s: LED is on\n", __func__); 3571 else if (on == 0 && s->on) 3572 printf("%s: LED is off\n", __func__); 3573 else if (on && (on != s->on || period != s->period)) { 3574 s->cycle = 0; 3575 s->on = on; 3576 s->period = period; 3577 omap_lpg_tick(s); 3578 return; 3579 } 3580 3581 s->on = on; 3582 s->period = period; 3583 } 3584 3585 static void omap_lpg_reset(struct omap_lpg_s *s) 3586 { 3587 s->control = 0x00; 3588 s->power = 0x00; 3589 s->clk = 1; 3590 omap_lpg_update(s); 3591 } 3592 3593 static uint64_t omap_lpg_read(void *opaque, hwaddr addr, 3594 unsigned size) 3595 { 3596 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; 3597 int offset = addr & OMAP_MPUI_REG_MASK; 3598 3599 if (size != 1) { 3600 return omap_badwidth_read8(opaque, addr); 3601 } 3602 3603 switch (offset) { 3604 case 0x00: /* LCR */ 3605 return s->control; 3606 3607 case 0x04: /* PMR */ 3608 return s->power; 3609 } 3610 3611 OMAP_BAD_REG(addr); 3612 return 0; 3613 } 3614 3615 static void omap_lpg_write(void *opaque, hwaddr addr, 3616 uint64_t value, unsigned size) 3617 { 3618 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; 3619 int offset = addr & OMAP_MPUI_REG_MASK; 3620 3621 if (size != 1) { 3622 omap_badwidth_write8(opaque, addr, value); 3623 return; 3624 } 3625 3626 switch (offset) { 3627 case 0x00: /* LCR */ 3628 if (~value & (1 << 6)) /* LPGRES */ 3629 omap_lpg_reset(s); 3630 s->control = value & 0xff; 3631 omap_lpg_update(s); 3632 return; 3633 3634 case 0x04: /* PMR */ 3635 s->power = value & 0x01; 3636 omap_lpg_update(s); 3637 return; 3638 3639 default: 3640 OMAP_BAD_REG(addr); 3641 return; 3642 } 3643 } 3644 3645 static const MemoryRegionOps omap_lpg_ops = { 3646 .read = omap_lpg_read, 3647 .write = omap_lpg_write, 3648 .endianness = DEVICE_NATIVE_ENDIAN, 3649 }; 3650 3651 static void omap_lpg_clk_update(void *opaque, int line, int on) 3652 { 3653 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; 3654 3655 s->clk = on; 3656 omap_lpg_update(s); 3657 } 3658 3659 static struct omap_lpg_s *omap_lpg_init(MemoryRegion *system_memory, 3660 hwaddr base, omap_clk clk) 3661 { 3662 struct omap_lpg_s *s = g_new0(struct omap_lpg_s, 1); 3663 3664 s->tm = timer_new_ms(QEMU_CLOCK_VIRTUAL, omap_lpg_tick, s); 3665 3666 omap_lpg_reset(s); 3667 3668 memory_region_init_io(&s->iomem, NULL, &omap_lpg_ops, s, "omap-lpg", 0x800); 3669 memory_region_add_subregion(system_memory, base, &s->iomem); 3670 3671 omap_clk_adduser(clk, qemu_allocate_irq(omap_lpg_clk_update, s, 0)); 3672 3673 return s; 3674 } 3675 3676 /* MPUI Peripheral Bridge configuration */ 3677 static uint64_t omap_mpui_io_read(void *opaque, hwaddr addr, 3678 unsigned size) 3679 { 3680 if (size != 2) { 3681 return omap_badwidth_read16(opaque, addr); 3682 } 3683 3684 if (addr == OMAP_MPUI_BASE) /* CMR */ 3685 return 0xfe4d; 3686 3687 OMAP_BAD_REG(addr); 3688 return 0; 3689 } 3690 3691 static void omap_mpui_io_write(void *opaque, hwaddr addr, 3692 uint64_t value, unsigned size) 3693 { 3694 /* FIXME: infinite loop */ 3695 omap_badwidth_write16(opaque, addr, value); 3696 } 3697 3698 static const MemoryRegionOps omap_mpui_io_ops = { 3699 .read = omap_mpui_io_read, 3700 .write = omap_mpui_io_write, 3701 .endianness = DEVICE_NATIVE_ENDIAN, 3702 }; 3703 3704 static void omap_setup_mpui_io(MemoryRegion *system_memory, 3705 struct omap_mpu_state_s *mpu) 3706 { 3707 memory_region_init_io(&mpu->mpui_io_iomem, NULL, &omap_mpui_io_ops, mpu, 3708 "omap-mpui-io", 0x7fff); 3709 memory_region_add_subregion(system_memory, OMAP_MPUI_BASE, 3710 &mpu->mpui_io_iomem); 3711 } 3712 3713 /* General chip reset */ 3714 static void omap1_mpu_reset(void *opaque) 3715 { 3716 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; 3717 3718 omap_dma_reset(mpu->dma); 3719 omap_mpu_timer_reset(mpu->timer[0]); 3720 omap_mpu_timer_reset(mpu->timer[1]); 3721 omap_mpu_timer_reset(mpu->timer[2]); 3722 omap_wd_timer_reset(mpu->wdt); 3723 omap_os_timer_reset(mpu->os_timer); 3724 omap_lcdc_reset(mpu->lcd); 3725 omap_ulpd_pm_reset(mpu); 3726 omap_pin_cfg_reset(mpu); 3727 omap_mpui_reset(mpu); 3728 omap_tipb_bridge_reset(mpu->private_tipb); 3729 omap_tipb_bridge_reset(mpu->public_tipb); 3730 omap_dpll_reset(mpu->dpll[0]); 3731 omap_dpll_reset(mpu->dpll[1]); 3732 omap_dpll_reset(mpu->dpll[2]); 3733 omap_uart_reset(mpu->uart[0]); 3734 omap_uart_reset(mpu->uart[1]); 3735 omap_uart_reset(mpu->uart[2]); 3736 omap_mmc_reset(mpu->mmc); 3737 omap_mpuio_reset(mpu->mpuio); 3738 omap_uwire_reset(mpu->microwire); 3739 omap_pwl_reset(mpu->pwl); 3740 omap_pwt_reset(mpu->pwt); 3741 omap_rtc_reset(mpu->rtc); 3742 omap_mcbsp_reset(mpu->mcbsp1); 3743 omap_mcbsp_reset(mpu->mcbsp2); 3744 omap_mcbsp_reset(mpu->mcbsp3); 3745 omap_lpg_reset(mpu->led[0]); 3746 omap_lpg_reset(mpu->led[1]); 3747 omap_clkm_reset(mpu); 3748 cpu_reset(CPU(mpu->cpu)); 3749 } 3750 3751 static const struct omap_map_s { 3752 hwaddr phys_dsp; 3753 hwaddr phys_mpu; 3754 uint32_t size; 3755 const char *name; 3756 } omap15xx_dsp_mm[] = { 3757 /* Strobe 0 */ 3758 { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */ 3759 { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */ 3760 { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */ 3761 { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */ 3762 { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */ 3763 { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */ 3764 { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */ 3765 { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */ 3766 { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */ 3767 { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */ 3768 { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */ 3769 { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */ 3770 { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */ 3771 { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */ 3772 { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */ 3773 { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */ 3774 { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */ 3775 /* Strobe 1 */ 3776 { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */ 3777 3778 { 0 } 3779 }; 3780 3781 static void omap_setup_dsp_mapping(MemoryRegion *system_memory, 3782 const struct omap_map_s *map) 3783 { 3784 MemoryRegion *io; 3785 3786 for (; map->phys_dsp; map ++) { 3787 io = g_new(MemoryRegion, 1); 3788 memory_region_init_alias(io, NULL, map->name, 3789 system_memory, map->phys_mpu, map->size); 3790 memory_region_add_subregion(system_memory, map->phys_dsp, io); 3791 } 3792 } 3793 3794 void omap_mpu_wakeup(void *opaque, int irq, int req) 3795 { 3796 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; 3797 CPUState *cpu = CPU(mpu->cpu); 3798 3799 if (cpu->halted) { 3800 cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB); 3801 } 3802 } 3803 3804 static const struct dma_irq_map omap1_dma_irq_map[] = { 3805 { 0, OMAP_INT_DMA_CH0_6 }, 3806 { 0, OMAP_INT_DMA_CH1_7 }, 3807 { 0, OMAP_INT_DMA_CH2_8 }, 3808 { 0, OMAP_INT_DMA_CH3 }, 3809 { 0, OMAP_INT_DMA_CH4 }, 3810 { 0, OMAP_INT_DMA_CH5 }, 3811 { 1, OMAP_INT_1610_DMA_CH6 }, 3812 { 1, OMAP_INT_1610_DMA_CH7 }, 3813 { 1, OMAP_INT_1610_DMA_CH8 }, 3814 { 1, OMAP_INT_1610_DMA_CH9 }, 3815 { 1, OMAP_INT_1610_DMA_CH10 }, 3816 { 1, OMAP_INT_1610_DMA_CH11 }, 3817 { 1, OMAP_INT_1610_DMA_CH12 }, 3818 { 1, OMAP_INT_1610_DMA_CH13 }, 3819 { 1, OMAP_INT_1610_DMA_CH14 }, 3820 { 1, OMAP_INT_1610_DMA_CH15 } 3821 }; 3822 3823 /* DMA ports for OMAP1 */ 3824 static int omap_validate_emiff_addr(struct omap_mpu_state_s *s, 3825 hwaddr addr) 3826 { 3827 return range_covers_byte(OMAP_EMIFF_BASE, s->sdram_size, addr); 3828 } 3829 3830 static int omap_validate_emifs_addr(struct omap_mpu_state_s *s, 3831 hwaddr addr) 3832 { 3833 return range_covers_byte(OMAP_EMIFS_BASE, OMAP_EMIFF_BASE - OMAP_EMIFS_BASE, 3834 addr); 3835 } 3836 3837 static int omap_validate_imif_addr(struct omap_mpu_state_s *s, 3838 hwaddr addr) 3839 { 3840 return range_covers_byte(OMAP_IMIF_BASE, s->sram_size, addr); 3841 } 3842 3843 static int omap_validate_tipb_addr(struct omap_mpu_state_s *s, 3844 hwaddr addr) 3845 { 3846 return range_covers_byte(0xfffb0000, 0xffff0000 - 0xfffb0000, addr); 3847 } 3848 3849 static int omap_validate_local_addr(struct omap_mpu_state_s *s, 3850 hwaddr addr) 3851 { 3852 return range_covers_byte(OMAP_LOCALBUS_BASE, 0x1000000, addr); 3853 } 3854 3855 static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s, 3856 hwaddr addr) 3857 { 3858 return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr); 3859 } 3860 3861 struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory, 3862 unsigned long sdram_size, 3863 const char *cpu_type) 3864 { 3865 int i; 3866 struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1); 3867 qemu_irq dma_irqs[6]; 3868 DriveInfo *dinfo; 3869 SysBusDevice *busdev; 3870 3871 /* Core */ 3872 s->mpu_model = omap310; 3873 s->cpu = ARM_CPU(cpu_create(cpu_type)); 3874 s->sdram_size = sdram_size; 3875 s->sram_size = OMAP15XX_SRAM_SIZE; 3876 3877 s->wakeup = qemu_allocate_irq(omap_mpu_wakeup, s, 0); 3878 3879 /* Clocks */ 3880 omap_clk_init(s); 3881 3882 /* Memory-mapped stuff */ 3883 memory_region_allocate_system_memory(&s->emiff_ram, NULL, "omap1.dram", 3884 s->sdram_size); 3885 memory_region_add_subregion(system_memory, OMAP_EMIFF_BASE, &s->emiff_ram); 3886 memory_region_init_ram(&s->imif_ram, NULL, "omap1.sram", s->sram_size, 3887 &error_fatal); 3888 memory_region_add_subregion(system_memory, OMAP_IMIF_BASE, &s->imif_ram); 3889 3890 omap_clkm_init(system_memory, 0xfffece00, 0xe1008000, s); 3891 3892 s->ih[0] = qdev_create(NULL, "omap-intc"); 3893 qdev_prop_set_uint32(s->ih[0], "size", 0x100); 3894 qdev_prop_set_ptr(s->ih[0], "clk", omap_findclk(s, "arminth_ck")); 3895 qdev_init_nofail(s->ih[0]); 3896 busdev = SYS_BUS_DEVICE(s->ih[0]); 3897 sysbus_connect_irq(busdev, 0, 3898 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ)); 3899 sysbus_connect_irq(busdev, 1, 3900 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ)); 3901 sysbus_mmio_map(busdev, 0, 0xfffecb00); 3902 s->ih[1] = qdev_create(NULL, "omap-intc"); 3903 qdev_prop_set_uint32(s->ih[1], "size", 0x800); 3904 qdev_prop_set_ptr(s->ih[1], "clk", omap_findclk(s, "arminth_ck")); 3905 qdev_init_nofail(s->ih[1]); 3906 busdev = SYS_BUS_DEVICE(s->ih[1]); 3907 sysbus_connect_irq(busdev, 0, 3908 qdev_get_gpio_in(s->ih[0], OMAP_INT_15XX_IH2_IRQ)); 3909 /* The second interrupt controller's FIQ output is not wired up */ 3910 sysbus_mmio_map(busdev, 0, 0xfffe0000); 3911 3912 for (i = 0; i < 6; i++) { 3913 dma_irqs[i] = qdev_get_gpio_in(s->ih[omap1_dma_irq_map[i].ih], 3914 omap1_dma_irq_map[i].intr); 3915 } 3916 s->dma = omap_dma_init(0xfffed800, dma_irqs, system_memory, 3917 qdev_get_gpio_in(s->ih[0], OMAP_INT_DMA_LCD), 3918 s, omap_findclk(s, "dma_ck"), omap_dma_3_1); 3919 3920 s->port[emiff ].addr_valid = omap_validate_emiff_addr; 3921 s->port[emifs ].addr_valid = omap_validate_emifs_addr; 3922 s->port[imif ].addr_valid = omap_validate_imif_addr; 3923 s->port[tipb ].addr_valid = omap_validate_tipb_addr; 3924 s->port[local ].addr_valid = omap_validate_local_addr; 3925 s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr; 3926 3927 /* Register SDRAM and SRAM DMA ports for fast transfers. */ 3928 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->emiff_ram), 3929 OMAP_EMIFF_BASE, s->sdram_size); 3930 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->imif_ram), 3931 OMAP_IMIF_BASE, s->sram_size); 3932 3933 s->timer[0] = omap_mpu_timer_init(system_memory, 0xfffec500, 3934 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER1), 3935 omap_findclk(s, "mputim_ck")); 3936 s->timer[1] = omap_mpu_timer_init(system_memory, 0xfffec600, 3937 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER2), 3938 omap_findclk(s, "mputim_ck")); 3939 s->timer[2] = omap_mpu_timer_init(system_memory, 0xfffec700, 3940 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER3), 3941 omap_findclk(s, "mputim_ck")); 3942 3943 s->wdt = omap_wd_timer_init(system_memory, 0xfffec800, 3944 qdev_get_gpio_in(s->ih[0], OMAP_INT_WD_TIMER), 3945 omap_findclk(s, "armwdt_ck")); 3946 3947 s->os_timer = omap_os_timer_init(system_memory, 0xfffb9000, 3948 qdev_get_gpio_in(s->ih[1], OMAP_INT_OS_TIMER), 3949 omap_findclk(s, "clk32-kHz")); 3950 3951 s->lcd = omap_lcdc_init(system_memory, 0xfffec000, 3952 qdev_get_gpio_in(s->ih[0], OMAP_INT_LCD_CTRL), 3953 omap_dma_get_lcdch(s->dma), 3954 omap_findclk(s, "lcd_ck")); 3955 3956 omap_ulpd_pm_init(system_memory, 0xfffe0800, s); 3957 omap_pin_cfg_init(system_memory, 0xfffe1000, s); 3958 omap_id_init(system_memory, s); 3959 3960 omap_mpui_init(system_memory, 0xfffec900, s); 3961 3962 s->private_tipb = omap_tipb_bridge_init(system_memory, 0xfffeca00, 3963 qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PRIV), 3964 omap_findclk(s, "tipb_ck")); 3965 s->public_tipb = omap_tipb_bridge_init(system_memory, 0xfffed300, 3966 qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PUB), 3967 omap_findclk(s, "tipb_ck")); 3968 3969 omap_tcmi_init(system_memory, 0xfffecc00, s); 3970 3971 s->uart[0] = omap_uart_init(0xfffb0000, 3972 qdev_get_gpio_in(s->ih[1], OMAP_INT_UART1), 3973 omap_findclk(s, "uart1_ck"), 3974 omap_findclk(s, "uart1_ck"), 3975 s->drq[OMAP_DMA_UART1_TX], s->drq[OMAP_DMA_UART1_RX], 3976 "uart1", 3977 serial_hd(0)); 3978 s->uart[1] = omap_uart_init(0xfffb0800, 3979 qdev_get_gpio_in(s->ih[1], OMAP_INT_UART2), 3980 omap_findclk(s, "uart2_ck"), 3981 omap_findclk(s, "uart2_ck"), 3982 s->drq[OMAP_DMA_UART2_TX], s->drq[OMAP_DMA_UART2_RX], 3983 "uart2", 3984 serial_hd(0) ? serial_hd(1) : NULL); 3985 s->uart[2] = omap_uart_init(0xfffb9800, 3986 qdev_get_gpio_in(s->ih[0], OMAP_INT_UART3), 3987 omap_findclk(s, "uart3_ck"), 3988 omap_findclk(s, "uart3_ck"), 3989 s->drq[OMAP_DMA_UART3_TX], s->drq[OMAP_DMA_UART3_RX], 3990 "uart3", 3991 serial_hd(0) && serial_hd(1) ? serial_hd(2) : NULL); 3992 3993 s->dpll[0] = omap_dpll_init(system_memory, 0xfffecf00, 3994 omap_findclk(s, "dpll1")); 3995 s->dpll[1] = omap_dpll_init(system_memory, 0xfffed000, 3996 omap_findclk(s, "dpll2")); 3997 s->dpll[2] = omap_dpll_init(system_memory, 0xfffed100, 3998 omap_findclk(s, "dpll3")); 3999 4000 dinfo = drive_get(IF_SD, 0, 0); 4001 if (!dinfo && !qtest_enabled()) { 4002 warn_report("missing SecureDigital device"); 4003 } 4004 s->mmc = omap_mmc_init(0xfffb7800, system_memory, 4005 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 4006 qdev_get_gpio_in(s->ih[1], OMAP_INT_OQN), 4007 &s->drq[OMAP_DMA_MMC_TX], 4008 omap_findclk(s, "mmc_ck")); 4009 4010 s->mpuio = omap_mpuio_init(system_memory, 0xfffb5000, 4011 qdev_get_gpio_in(s->ih[1], OMAP_INT_KEYBOARD), 4012 qdev_get_gpio_in(s->ih[1], OMAP_INT_MPUIO), 4013 s->wakeup, omap_findclk(s, "clk32-kHz")); 4014 4015 s->gpio = qdev_create(NULL, "omap-gpio"); 4016 qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model); 4017 qdev_prop_set_ptr(s->gpio, "clk", omap_findclk(s, "arm_gpio_ck")); 4018 qdev_init_nofail(s->gpio); 4019 sysbus_connect_irq(SYS_BUS_DEVICE(s->gpio), 0, 4020 qdev_get_gpio_in(s->ih[0], OMAP_INT_GPIO_BANK1)); 4021 sysbus_mmio_map(SYS_BUS_DEVICE(s->gpio), 0, 0xfffce000); 4022 4023 s->microwire = omap_uwire_init(system_memory, 0xfffb3000, 4024 qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireTX), 4025 qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireRX), 4026 s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck")); 4027 4028 s->pwl = omap_pwl_init(system_memory, 0xfffb5800, 4029 omap_findclk(s, "armxor_ck")); 4030 s->pwt = omap_pwt_init(system_memory, 0xfffb6000, 4031 omap_findclk(s, "armxor_ck")); 4032 4033 s->i2c[0] = qdev_create(NULL, "omap_i2c"); 4034 qdev_prop_set_uint8(s->i2c[0], "revision", 0x11); 4035 qdev_prop_set_ptr(s->i2c[0], "fclk", omap_findclk(s, "mpuper_ck")); 4036 qdev_init_nofail(s->i2c[0]); 4037 busdev = SYS_BUS_DEVICE(s->i2c[0]); 4038 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C)); 4039 sysbus_connect_irq(busdev, 1, s->drq[OMAP_DMA_I2C_TX]); 4040 sysbus_connect_irq(busdev, 2, s->drq[OMAP_DMA_I2C_RX]); 4041 sysbus_mmio_map(busdev, 0, 0xfffb3800); 4042 4043 s->rtc = omap_rtc_init(system_memory, 0xfffb4800, 4044 qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_TIMER), 4045 qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_ALARM), 4046 omap_findclk(s, "clk32-kHz")); 4047 4048 s->mcbsp1 = omap_mcbsp_init(system_memory, 0xfffb1800, 4049 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1TX), 4050 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1RX), 4051 &s->drq[OMAP_DMA_MCBSP1_TX], omap_findclk(s, "dspxor_ck")); 4052 s->mcbsp2 = omap_mcbsp_init(system_memory, 0xfffb1000, 4053 qdev_get_gpio_in(s->ih[0], 4054 OMAP_INT_310_McBSP2_TX), 4055 qdev_get_gpio_in(s->ih[0], 4056 OMAP_INT_310_McBSP2_RX), 4057 &s->drq[OMAP_DMA_MCBSP2_TX], omap_findclk(s, "mpuper_ck")); 4058 s->mcbsp3 = omap_mcbsp_init(system_memory, 0xfffb7000, 4059 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3TX), 4060 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3RX), 4061 &s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck")); 4062 4063 s->led[0] = omap_lpg_init(system_memory, 4064 0xfffbd000, omap_findclk(s, "clk32-kHz")); 4065 s->led[1] = omap_lpg_init(system_memory, 4066 0xfffbd800, omap_findclk(s, "clk32-kHz")); 4067 4068 /* Register mappings not currenlty implemented: 4069 * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310) 4070 * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310) 4071 * USB W2FC fffb4000 - fffb47ff 4072 * Camera Interface fffb6800 - fffb6fff 4073 * USB Host fffba000 - fffba7ff 4074 * FAC fffba800 - fffbafff 4075 * HDQ/1-Wire fffbc000 - fffbc7ff 4076 * TIPB switches fffbc800 - fffbcfff 4077 * Mailbox fffcf000 - fffcf7ff 4078 * Local bus IF fffec100 - fffec1ff 4079 * Local bus MMU fffec200 - fffec2ff 4080 * DSP MMU fffed200 - fffed2ff 4081 */ 4082 4083 omap_setup_dsp_mapping(system_memory, omap15xx_dsp_mm); 4084 omap_setup_mpui_io(system_memory, s); 4085 4086 qemu_register_reset(omap1_mpu_reset, s); 4087 4088 return s; 4089 } 4090