1 /* 2 * TI OMAP processors emulation. 3 * 4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 or 9 * (at your option) version 3 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "hw/boards.h" 21 #include "hw/hw.h" 22 #include "hw/arm/arm.h" 23 #include "hw/arm/omap.h" 24 #include "sysemu/sysemu.h" 25 #include "hw/arm/soc_dma.h" 26 #include "sysemu/block-backend.h" 27 #include "sysemu/blockdev.h" 28 #include "qemu/range.h" 29 #include "hw/sysbus.h" 30 31 /* Should signal the TCMI/GPMC */ 32 uint32_t omap_badwidth_read8(void *opaque, hwaddr addr) 33 { 34 uint8_t ret; 35 36 OMAP_8B_REG(addr); 37 cpu_physical_memory_read(addr, &ret, 1); 38 return ret; 39 } 40 41 void omap_badwidth_write8(void *opaque, hwaddr addr, 42 uint32_t value) 43 { 44 uint8_t val8 = value; 45 46 OMAP_8B_REG(addr); 47 cpu_physical_memory_write(addr, &val8, 1); 48 } 49 50 uint32_t omap_badwidth_read16(void *opaque, hwaddr addr) 51 { 52 uint16_t ret; 53 54 OMAP_16B_REG(addr); 55 cpu_physical_memory_read(addr, &ret, 2); 56 return ret; 57 } 58 59 void omap_badwidth_write16(void *opaque, hwaddr addr, 60 uint32_t value) 61 { 62 uint16_t val16 = value; 63 64 OMAP_16B_REG(addr); 65 cpu_physical_memory_write(addr, &val16, 2); 66 } 67 68 uint32_t omap_badwidth_read32(void *opaque, hwaddr addr) 69 { 70 uint32_t ret; 71 72 OMAP_32B_REG(addr); 73 cpu_physical_memory_read(addr, &ret, 4); 74 return ret; 75 } 76 77 void omap_badwidth_write32(void *opaque, hwaddr addr, 78 uint32_t value) 79 { 80 OMAP_32B_REG(addr); 81 cpu_physical_memory_write(addr, &value, 4); 82 } 83 84 /* MPU OS timers */ 85 struct omap_mpu_timer_s { 86 MemoryRegion iomem; 87 qemu_irq irq; 88 omap_clk clk; 89 uint32_t val; 90 int64_t time; 91 QEMUTimer *timer; 92 QEMUBH *tick; 93 int64_t rate; 94 int it_ena; 95 96 int enable; 97 int ptv; 98 int ar; 99 int st; 100 uint32_t reset_val; 101 }; 102 103 static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer) 104 { 105 uint64_t distance = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->time; 106 107 if (timer->st && timer->enable && timer->rate) 108 return timer->val - muldiv64(distance >> (timer->ptv + 1), 109 timer->rate, get_ticks_per_sec()); 110 else 111 return timer->val; 112 } 113 114 static inline void omap_timer_sync(struct omap_mpu_timer_s *timer) 115 { 116 timer->val = omap_timer_read(timer); 117 timer->time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 118 } 119 120 static inline void omap_timer_update(struct omap_mpu_timer_s *timer) 121 { 122 int64_t expires; 123 124 if (timer->enable && timer->st && timer->rate) { 125 timer->val = timer->reset_val; /* Should skip this on clk enable */ 126 expires = muldiv64((uint64_t) timer->val << (timer->ptv + 1), 127 get_ticks_per_sec(), timer->rate); 128 129 /* If timer expiry would be sooner than in about 1 ms and 130 * auto-reload isn't set, then fire immediately. This is a hack 131 * to make systems like PalmOS run in acceptable time. PalmOS 132 * sets the interval to a very low value and polls the status bit 133 * in a busy loop when it wants to sleep just a couple of CPU 134 * ticks. */ 135 if (expires > (get_ticks_per_sec() >> 10) || timer->ar) 136 timer_mod(timer->timer, timer->time + expires); 137 else 138 qemu_bh_schedule(timer->tick); 139 } else 140 timer_del(timer->timer); 141 } 142 143 static void omap_timer_fire(void *opaque) 144 { 145 struct omap_mpu_timer_s *timer = opaque; 146 147 if (!timer->ar) { 148 timer->val = 0; 149 timer->st = 0; 150 } 151 152 if (timer->it_ena) 153 /* Edge-triggered irq */ 154 qemu_irq_pulse(timer->irq); 155 } 156 157 static void omap_timer_tick(void *opaque) 158 { 159 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque; 160 161 omap_timer_sync(timer); 162 omap_timer_fire(timer); 163 omap_timer_update(timer); 164 } 165 166 static void omap_timer_clk_update(void *opaque, int line, int on) 167 { 168 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque; 169 170 omap_timer_sync(timer); 171 timer->rate = on ? omap_clk_getrate(timer->clk) : 0; 172 omap_timer_update(timer); 173 } 174 175 static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer) 176 { 177 omap_clk_adduser(timer->clk, 178 qemu_allocate_irq(omap_timer_clk_update, timer, 0)); 179 timer->rate = omap_clk_getrate(timer->clk); 180 } 181 182 static uint64_t omap_mpu_timer_read(void *opaque, hwaddr addr, 183 unsigned size) 184 { 185 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; 186 187 if (size != 4) { 188 return omap_badwidth_read32(opaque, addr); 189 } 190 191 switch (addr) { 192 case 0x00: /* CNTL_TIMER */ 193 return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st; 194 195 case 0x04: /* LOAD_TIM */ 196 break; 197 198 case 0x08: /* READ_TIM */ 199 return omap_timer_read(s); 200 } 201 202 OMAP_BAD_REG(addr); 203 return 0; 204 } 205 206 static void omap_mpu_timer_write(void *opaque, hwaddr addr, 207 uint64_t value, unsigned size) 208 { 209 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; 210 211 if (size != 4) { 212 omap_badwidth_write32(opaque, addr, value); 213 return; 214 } 215 216 switch (addr) { 217 case 0x00: /* CNTL_TIMER */ 218 omap_timer_sync(s); 219 s->enable = (value >> 5) & 1; 220 s->ptv = (value >> 2) & 7; 221 s->ar = (value >> 1) & 1; 222 s->st = value & 1; 223 omap_timer_update(s); 224 return; 225 226 case 0x04: /* LOAD_TIM */ 227 s->reset_val = value; 228 return; 229 230 case 0x08: /* READ_TIM */ 231 OMAP_RO_REG(addr); 232 break; 233 234 default: 235 OMAP_BAD_REG(addr); 236 } 237 } 238 239 static const MemoryRegionOps omap_mpu_timer_ops = { 240 .read = omap_mpu_timer_read, 241 .write = omap_mpu_timer_write, 242 .endianness = DEVICE_LITTLE_ENDIAN, 243 }; 244 245 static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s) 246 { 247 timer_del(s->timer); 248 s->enable = 0; 249 s->reset_val = 31337; 250 s->val = 0; 251 s->ptv = 0; 252 s->ar = 0; 253 s->st = 0; 254 s->it_ena = 1; 255 } 256 257 static struct omap_mpu_timer_s *omap_mpu_timer_init(MemoryRegion *system_memory, 258 hwaddr base, 259 qemu_irq irq, omap_clk clk) 260 { 261 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) 262 g_malloc0(sizeof(struct omap_mpu_timer_s)); 263 264 s->irq = irq; 265 s->clk = clk; 266 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, s); 267 s->tick = qemu_bh_new(omap_timer_fire, s); 268 omap_mpu_timer_reset(s); 269 omap_timer_clk_setup(s); 270 271 memory_region_init_io(&s->iomem, NULL, &omap_mpu_timer_ops, s, 272 "omap-mpu-timer", 0x100); 273 274 memory_region_add_subregion(system_memory, base, &s->iomem); 275 276 return s; 277 } 278 279 /* Watchdog timer */ 280 struct omap_watchdog_timer_s { 281 struct omap_mpu_timer_s timer; 282 MemoryRegion iomem; 283 uint8_t last_wr; 284 int mode; 285 int free; 286 int reset; 287 }; 288 289 static uint64_t omap_wd_timer_read(void *opaque, hwaddr addr, 290 unsigned size) 291 { 292 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; 293 294 if (size != 2) { 295 return omap_badwidth_read16(opaque, addr); 296 } 297 298 switch (addr) { 299 case 0x00: /* CNTL_TIMER */ 300 return (s->timer.ptv << 9) | (s->timer.ar << 8) | 301 (s->timer.st << 7) | (s->free << 1); 302 303 case 0x04: /* READ_TIMER */ 304 return omap_timer_read(&s->timer); 305 306 case 0x08: /* TIMER_MODE */ 307 return s->mode << 15; 308 } 309 310 OMAP_BAD_REG(addr); 311 return 0; 312 } 313 314 static void omap_wd_timer_write(void *opaque, hwaddr addr, 315 uint64_t value, unsigned size) 316 { 317 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; 318 319 if (size != 2) { 320 omap_badwidth_write16(opaque, addr, value); 321 return; 322 } 323 324 switch (addr) { 325 case 0x00: /* CNTL_TIMER */ 326 omap_timer_sync(&s->timer); 327 s->timer.ptv = (value >> 9) & 7; 328 s->timer.ar = (value >> 8) & 1; 329 s->timer.st = (value >> 7) & 1; 330 s->free = (value >> 1) & 1; 331 omap_timer_update(&s->timer); 332 break; 333 334 case 0x04: /* LOAD_TIMER */ 335 s->timer.reset_val = value & 0xffff; 336 break; 337 338 case 0x08: /* TIMER_MODE */ 339 if (!s->mode && ((value >> 15) & 1)) 340 omap_clk_get(s->timer.clk); 341 s->mode |= (value >> 15) & 1; 342 if (s->last_wr == 0xf5) { 343 if ((value & 0xff) == 0xa0) { 344 if (s->mode) { 345 s->mode = 0; 346 omap_clk_put(s->timer.clk); 347 } 348 } else { 349 /* XXX: on T|E hardware somehow this has no effect, 350 * on Zire 71 it works as specified. */ 351 s->reset = 1; 352 qemu_system_reset_request(); 353 } 354 } 355 s->last_wr = value & 0xff; 356 break; 357 358 default: 359 OMAP_BAD_REG(addr); 360 } 361 } 362 363 static const MemoryRegionOps omap_wd_timer_ops = { 364 .read = omap_wd_timer_read, 365 .write = omap_wd_timer_write, 366 .endianness = DEVICE_NATIVE_ENDIAN, 367 }; 368 369 static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s) 370 { 371 timer_del(s->timer.timer); 372 if (!s->mode) 373 omap_clk_get(s->timer.clk); 374 s->mode = 1; 375 s->free = 1; 376 s->reset = 0; 377 s->timer.enable = 1; 378 s->timer.it_ena = 1; 379 s->timer.reset_val = 0xffff; 380 s->timer.val = 0; 381 s->timer.st = 0; 382 s->timer.ptv = 0; 383 s->timer.ar = 0; 384 omap_timer_update(&s->timer); 385 } 386 387 static struct omap_watchdog_timer_s *omap_wd_timer_init(MemoryRegion *memory, 388 hwaddr base, 389 qemu_irq irq, omap_clk clk) 390 { 391 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) 392 g_malloc0(sizeof(struct omap_watchdog_timer_s)); 393 394 s->timer.irq = irq; 395 s->timer.clk = clk; 396 s->timer.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, &s->timer); 397 omap_wd_timer_reset(s); 398 omap_timer_clk_setup(&s->timer); 399 400 memory_region_init_io(&s->iomem, NULL, &omap_wd_timer_ops, s, 401 "omap-wd-timer", 0x100); 402 memory_region_add_subregion(memory, base, &s->iomem); 403 404 return s; 405 } 406 407 /* 32-kHz timer */ 408 struct omap_32khz_timer_s { 409 struct omap_mpu_timer_s timer; 410 MemoryRegion iomem; 411 }; 412 413 static uint64_t omap_os_timer_read(void *opaque, hwaddr addr, 414 unsigned size) 415 { 416 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; 417 int offset = addr & OMAP_MPUI_REG_MASK; 418 419 if (size != 4) { 420 return omap_badwidth_read32(opaque, addr); 421 } 422 423 switch (offset) { 424 case 0x00: /* TVR */ 425 return s->timer.reset_val; 426 427 case 0x04: /* TCR */ 428 return omap_timer_read(&s->timer); 429 430 case 0x08: /* CR */ 431 return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st; 432 433 default: 434 break; 435 } 436 OMAP_BAD_REG(addr); 437 return 0; 438 } 439 440 static void omap_os_timer_write(void *opaque, hwaddr addr, 441 uint64_t value, unsigned size) 442 { 443 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; 444 int offset = addr & OMAP_MPUI_REG_MASK; 445 446 if (size != 4) { 447 omap_badwidth_write32(opaque, addr, value); 448 return; 449 } 450 451 switch (offset) { 452 case 0x00: /* TVR */ 453 s->timer.reset_val = value & 0x00ffffff; 454 break; 455 456 case 0x04: /* TCR */ 457 OMAP_RO_REG(addr); 458 break; 459 460 case 0x08: /* CR */ 461 s->timer.ar = (value >> 3) & 1; 462 s->timer.it_ena = (value >> 2) & 1; 463 if (s->timer.st != (value & 1) || (value & 2)) { 464 omap_timer_sync(&s->timer); 465 s->timer.enable = value & 1; 466 s->timer.st = value & 1; 467 omap_timer_update(&s->timer); 468 } 469 break; 470 471 default: 472 OMAP_BAD_REG(addr); 473 } 474 } 475 476 static const MemoryRegionOps omap_os_timer_ops = { 477 .read = omap_os_timer_read, 478 .write = omap_os_timer_write, 479 .endianness = DEVICE_NATIVE_ENDIAN, 480 }; 481 482 static void omap_os_timer_reset(struct omap_32khz_timer_s *s) 483 { 484 timer_del(s->timer.timer); 485 s->timer.enable = 0; 486 s->timer.it_ena = 0; 487 s->timer.reset_val = 0x00ffffff; 488 s->timer.val = 0; 489 s->timer.st = 0; 490 s->timer.ptv = 0; 491 s->timer.ar = 1; 492 } 493 494 static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory, 495 hwaddr base, 496 qemu_irq irq, omap_clk clk) 497 { 498 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) 499 g_malloc0(sizeof(struct omap_32khz_timer_s)); 500 501 s->timer.irq = irq; 502 s->timer.clk = clk; 503 s->timer.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, &s->timer); 504 omap_os_timer_reset(s); 505 omap_timer_clk_setup(&s->timer); 506 507 memory_region_init_io(&s->iomem, NULL, &omap_os_timer_ops, s, 508 "omap-os-timer", 0x800); 509 memory_region_add_subregion(memory, base, &s->iomem); 510 511 return s; 512 } 513 514 /* Ultra Low-Power Device Module */ 515 static uint64_t omap_ulpd_pm_read(void *opaque, hwaddr addr, 516 unsigned size) 517 { 518 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 519 uint16_t ret; 520 521 if (size != 2) { 522 return omap_badwidth_read16(opaque, addr); 523 } 524 525 switch (addr) { 526 case 0x14: /* IT_STATUS */ 527 ret = s->ulpd_pm_regs[addr >> 2]; 528 s->ulpd_pm_regs[addr >> 2] = 0; 529 qemu_irq_lower(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K)); 530 return ret; 531 532 case 0x18: /* Reserved */ 533 case 0x1c: /* Reserved */ 534 case 0x20: /* Reserved */ 535 case 0x28: /* Reserved */ 536 case 0x2c: /* Reserved */ 537 OMAP_BAD_REG(addr); 538 /* fall through */ 539 case 0x00: /* COUNTER_32_LSB */ 540 case 0x04: /* COUNTER_32_MSB */ 541 case 0x08: /* COUNTER_HIGH_FREQ_LSB */ 542 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ 543 case 0x10: /* GAUGING_CTRL */ 544 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ 545 case 0x30: /* CLOCK_CTRL */ 546 case 0x34: /* SOFT_REQ */ 547 case 0x38: /* COUNTER_32_FIQ */ 548 case 0x3c: /* DPLL_CTRL */ 549 case 0x40: /* STATUS_REQ */ 550 /* XXX: check clk::usecount state for every clock */ 551 case 0x48: /* LOCL_TIME */ 552 case 0x4c: /* APLL_CTRL */ 553 case 0x50: /* POWER_CTRL */ 554 return s->ulpd_pm_regs[addr >> 2]; 555 } 556 557 OMAP_BAD_REG(addr); 558 return 0; 559 } 560 561 static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s, 562 uint16_t diff, uint16_t value) 563 { 564 if (diff & (1 << 4)) /* USB_MCLK_EN */ 565 omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1); 566 if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */ 567 omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1); 568 } 569 570 static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s, 571 uint16_t diff, uint16_t value) 572 { 573 if (diff & (1 << 0)) /* SOFT_DPLL_REQ */ 574 omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1); 575 if (diff & (1 << 1)) /* SOFT_COM_REQ */ 576 omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1); 577 if (diff & (1 << 2)) /* SOFT_SDW_REQ */ 578 omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1); 579 if (diff & (1 << 3)) /* SOFT_USB_REQ */ 580 omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1); 581 } 582 583 static void omap_ulpd_pm_write(void *opaque, hwaddr addr, 584 uint64_t value, unsigned size) 585 { 586 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 587 int64_t now, ticks; 588 int div, mult; 589 static const int bypass_div[4] = { 1, 2, 4, 4 }; 590 uint16_t diff; 591 592 if (size != 2) { 593 omap_badwidth_write16(opaque, addr, value); 594 return; 595 } 596 597 switch (addr) { 598 case 0x00: /* COUNTER_32_LSB */ 599 case 0x04: /* COUNTER_32_MSB */ 600 case 0x08: /* COUNTER_HIGH_FREQ_LSB */ 601 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ 602 case 0x14: /* IT_STATUS */ 603 case 0x40: /* STATUS_REQ */ 604 OMAP_RO_REG(addr); 605 break; 606 607 case 0x10: /* GAUGING_CTRL */ 608 /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */ 609 if ((s->ulpd_pm_regs[addr >> 2] ^ value) & 1) { 610 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 611 612 if (value & 1) 613 s->ulpd_gauge_start = now; 614 else { 615 now -= s->ulpd_gauge_start; 616 617 /* 32-kHz ticks */ 618 ticks = muldiv64(now, 32768, get_ticks_per_sec()); 619 s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff; 620 s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff; 621 if (ticks >> 32) /* OVERFLOW_32K */ 622 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2; 623 624 /* High frequency ticks */ 625 ticks = muldiv64(now, 12000000, get_ticks_per_sec()); 626 s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff; 627 s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff; 628 if (ticks >> 32) /* OVERFLOW_HI_FREQ */ 629 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1; 630 631 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */ 632 qemu_irq_raise(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K)); 633 } 634 } 635 s->ulpd_pm_regs[addr >> 2] = value; 636 break; 637 638 case 0x18: /* Reserved */ 639 case 0x1c: /* Reserved */ 640 case 0x20: /* Reserved */ 641 case 0x28: /* Reserved */ 642 case 0x2c: /* Reserved */ 643 OMAP_BAD_REG(addr); 644 /* fall through */ 645 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ 646 case 0x38: /* COUNTER_32_FIQ */ 647 case 0x48: /* LOCL_TIME */ 648 case 0x50: /* POWER_CTRL */ 649 s->ulpd_pm_regs[addr >> 2] = value; 650 break; 651 652 case 0x30: /* CLOCK_CTRL */ 653 diff = s->ulpd_pm_regs[addr >> 2] ^ value; 654 s->ulpd_pm_regs[addr >> 2] = value & 0x3f; 655 omap_ulpd_clk_update(s, diff, value); 656 break; 657 658 case 0x34: /* SOFT_REQ */ 659 diff = s->ulpd_pm_regs[addr >> 2] ^ value; 660 s->ulpd_pm_regs[addr >> 2] = value & 0x1f; 661 omap_ulpd_req_update(s, diff, value); 662 break; 663 664 case 0x3c: /* DPLL_CTRL */ 665 /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is 666 * omitted altogether, probably a typo. */ 667 /* This register has identical semantics with DPLL(1:3) control 668 * registers, see omap_dpll_write() */ 669 diff = s->ulpd_pm_regs[addr >> 2] & value; 670 s->ulpd_pm_regs[addr >> 2] = value & 0x2fff; 671 if (diff & (0x3ff << 2)) { 672 if (value & (1 << 4)) { /* PLL_ENABLE */ 673 div = ((value >> 5) & 3) + 1; /* PLL_DIV */ 674 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ 675 } else { 676 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ 677 mult = 1; 678 } 679 omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult); 680 } 681 682 /* Enter the desired mode. */ 683 s->ulpd_pm_regs[addr >> 2] = 684 (s->ulpd_pm_regs[addr >> 2] & 0xfffe) | 685 ((s->ulpd_pm_regs[addr >> 2] >> 4) & 1); 686 687 /* Act as if the lock is restored. */ 688 s->ulpd_pm_regs[addr >> 2] |= 2; 689 break; 690 691 case 0x4c: /* APLL_CTRL */ 692 diff = s->ulpd_pm_regs[addr >> 2] & value; 693 s->ulpd_pm_regs[addr >> 2] = value & 0xf; 694 if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */ 695 omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s, 696 (value & (1 << 0)) ? "apll" : "dpll4")); 697 break; 698 699 default: 700 OMAP_BAD_REG(addr); 701 } 702 } 703 704 static const MemoryRegionOps omap_ulpd_pm_ops = { 705 .read = omap_ulpd_pm_read, 706 .write = omap_ulpd_pm_write, 707 .endianness = DEVICE_NATIVE_ENDIAN, 708 }; 709 710 static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu) 711 { 712 mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001; 713 mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000; 714 mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001; 715 mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000; 716 mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000; 717 mpu->ulpd_pm_regs[0x18 >> 2] = 0x01; 718 mpu->ulpd_pm_regs[0x1c >> 2] = 0x01; 719 mpu->ulpd_pm_regs[0x20 >> 2] = 0x01; 720 mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff; 721 mpu->ulpd_pm_regs[0x28 >> 2] = 0x01; 722 mpu->ulpd_pm_regs[0x2c >> 2] = 0x01; 723 omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000); 724 mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000; 725 omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000); 726 mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000; 727 mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001; 728 mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211; 729 mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */ 730 mpu->ulpd_pm_regs[0x48 >> 2] = 0x960; 731 mpu->ulpd_pm_regs[0x4c >> 2] = 0x08; 732 mpu->ulpd_pm_regs[0x50 >> 2] = 0x08; 733 omap_clk_setrate(omap_findclk(mpu, "dpll4"), 1, 4); 734 omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4")); 735 } 736 737 static void omap_ulpd_pm_init(MemoryRegion *system_memory, 738 hwaddr base, 739 struct omap_mpu_state_s *mpu) 740 { 741 memory_region_init_io(&mpu->ulpd_pm_iomem, NULL, &omap_ulpd_pm_ops, mpu, 742 "omap-ulpd-pm", 0x800); 743 memory_region_add_subregion(system_memory, base, &mpu->ulpd_pm_iomem); 744 omap_ulpd_pm_reset(mpu); 745 } 746 747 /* OMAP Pin Configuration */ 748 static uint64_t omap_pin_cfg_read(void *opaque, hwaddr addr, 749 unsigned size) 750 { 751 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 752 753 if (size != 4) { 754 return omap_badwidth_read32(opaque, addr); 755 } 756 757 switch (addr) { 758 case 0x00: /* FUNC_MUX_CTRL_0 */ 759 case 0x04: /* FUNC_MUX_CTRL_1 */ 760 case 0x08: /* FUNC_MUX_CTRL_2 */ 761 return s->func_mux_ctrl[addr >> 2]; 762 763 case 0x0c: /* COMP_MODE_CTRL_0 */ 764 return s->comp_mode_ctrl[0]; 765 766 case 0x10: /* FUNC_MUX_CTRL_3 */ 767 case 0x14: /* FUNC_MUX_CTRL_4 */ 768 case 0x18: /* FUNC_MUX_CTRL_5 */ 769 case 0x1c: /* FUNC_MUX_CTRL_6 */ 770 case 0x20: /* FUNC_MUX_CTRL_7 */ 771 case 0x24: /* FUNC_MUX_CTRL_8 */ 772 case 0x28: /* FUNC_MUX_CTRL_9 */ 773 case 0x2c: /* FUNC_MUX_CTRL_A */ 774 case 0x30: /* FUNC_MUX_CTRL_B */ 775 case 0x34: /* FUNC_MUX_CTRL_C */ 776 case 0x38: /* FUNC_MUX_CTRL_D */ 777 return s->func_mux_ctrl[(addr >> 2) - 1]; 778 779 case 0x40: /* PULL_DWN_CTRL_0 */ 780 case 0x44: /* PULL_DWN_CTRL_1 */ 781 case 0x48: /* PULL_DWN_CTRL_2 */ 782 case 0x4c: /* PULL_DWN_CTRL_3 */ 783 return s->pull_dwn_ctrl[(addr & 0xf) >> 2]; 784 785 case 0x50: /* GATE_INH_CTRL_0 */ 786 return s->gate_inh_ctrl[0]; 787 788 case 0x60: /* VOLTAGE_CTRL_0 */ 789 return s->voltage_ctrl[0]; 790 791 case 0x70: /* TEST_DBG_CTRL_0 */ 792 return s->test_dbg_ctrl[0]; 793 794 case 0x80: /* MOD_CONF_CTRL_0 */ 795 return s->mod_conf_ctrl[0]; 796 } 797 798 OMAP_BAD_REG(addr); 799 return 0; 800 } 801 802 static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s, 803 uint32_t diff, uint32_t value) 804 { 805 if (s->compat1509) { 806 if (diff & (1 << 9)) /* BLUETOOTH */ 807 omap_clk_onoff(omap_findclk(s, "bt_mclk_out"), 808 (~value >> 9) & 1); 809 if (diff & (1 << 7)) /* USB.CLKO */ 810 omap_clk_onoff(omap_findclk(s, "usb.clko"), 811 (value >> 7) & 1); 812 } 813 } 814 815 static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s, 816 uint32_t diff, uint32_t value) 817 { 818 if (s->compat1509) { 819 if (diff & (1U << 31)) { 820 /* MCBSP3_CLK_HIZ_DI */ 821 omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"), (value >> 31) & 1); 822 } 823 if (diff & (1 << 1)) { 824 /* CLK32K */ 825 omap_clk_onoff(omap_findclk(s, "clk32k_out"), (~value >> 1) & 1); 826 } 827 } 828 } 829 830 static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s, 831 uint32_t diff, uint32_t value) 832 { 833 if (diff & (1U << 31)) { 834 /* CONF_MOD_UART3_CLK_MODE_R */ 835 omap_clk_reparent(omap_findclk(s, "uart3_ck"), 836 omap_findclk(s, ((value >> 31) & 1) ? 837 "ck_48m" : "armper_ck")); 838 } 839 if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */ 840 omap_clk_reparent(omap_findclk(s, "uart2_ck"), 841 omap_findclk(s, ((value >> 30) & 1) ? 842 "ck_48m" : "armper_ck")); 843 if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */ 844 omap_clk_reparent(omap_findclk(s, "uart1_ck"), 845 omap_findclk(s, ((value >> 29) & 1) ? 846 "ck_48m" : "armper_ck")); 847 if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */ 848 omap_clk_reparent(omap_findclk(s, "mmc_ck"), 849 omap_findclk(s, ((value >> 23) & 1) ? 850 "ck_48m" : "armper_ck")); 851 if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */ 852 omap_clk_reparent(omap_findclk(s, "com_mclk_out"), 853 omap_findclk(s, ((value >> 12) & 1) ? 854 "ck_48m" : "armper_ck")); 855 if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */ 856 omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1); 857 } 858 859 static void omap_pin_cfg_write(void *opaque, hwaddr addr, 860 uint64_t value, unsigned size) 861 { 862 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 863 uint32_t diff; 864 865 if (size != 4) { 866 omap_badwidth_write32(opaque, addr, value); 867 return; 868 } 869 870 switch (addr) { 871 case 0x00: /* FUNC_MUX_CTRL_0 */ 872 diff = s->func_mux_ctrl[addr >> 2] ^ value; 873 s->func_mux_ctrl[addr >> 2] = value; 874 omap_pin_funcmux0_update(s, diff, value); 875 return; 876 877 case 0x04: /* FUNC_MUX_CTRL_1 */ 878 diff = s->func_mux_ctrl[addr >> 2] ^ value; 879 s->func_mux_ctrl[addr >> 2] = value; 880 omap_pin_funcmux1_update(s, diff, value); 881 return; 882 883 case 0x08: /* FUNC_MUX_CTRL_2 */ 884 s->func_mux_ctrl[addr >> 2] = value; 885 return; 886 887 case 0x0c: /* COMP_MODE_CTRL_0 */ 888 s->comp_mode_ctrl[0] = value; 889 s->compat1509 = (value != 0x0000eaef); 890 omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]); 891 omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]); 892 return; 893 894 case 0x10: /* FUNC_MUX_CTRL_3 */ 895 case 0x14: /* FUNC_MUX_CTRL_4 */ 896 case 0x18: /* FUNC_MUX_CTRL_5 */ 897 case 0x1c: /* FUNC_MUX_CTRL_6 */ 898 case 0x20: /* FUNC_MUX_CTRL_7 */ 899 case 0x24: /* FUNC_MUX_CTRL_8 */ 900 case 0x28: /* FUNC_MUX_CTRL_9 */ 901 case 0x2c: /* FUNC_MUX_CTRL_A */ 902 case 0x30: /* FUNC_MUX_CTRL_B */ 903 case 0x34: /* FUNC_MUX_CTRL_C */ 904 case 0x38: /* FUNC_MUX_CTRL_D */ 905 s->func_mux_ctrl[(addr >> 2) - 1] = value; 906 return; 907 908 case 0x40: /* PULL_DWN_CTRL_0 */ 909 case 0x44: /* PULL_DWN_CTRL_1 */ 910 case 0x48: /* PULL_DWN_CTRL_2 */ 911 case 0x4c: /* PULL_DWN_CTRL_3 */ 912 s->pull_dwn_ctrl[(addr & 0xf) >> 2] = value; 913 return; 914 915 case 0x50: /* GATE_INH_CTRL_0 */ 916 s->gate_inh_ctrl[0] = value; 917 return; 918 919 case 0x60: /* VOLTAGE_CTRL_0 */ 920 s->voltage_ctrl[0] = value; 921 return; 922 923 case 0x70: /* TEST_DBG_CTRL_0 */ 924 s->test_dbg_ctrl[0] = value; 925 return; 926 927 case 0x80: /* MOD_CONF_CTRL_0 */ 928 diff = s->mod_conf_ctrl[0] ^ value; 929 s->mod_conf_ctrl[0] = value; 930 omap_pin_modconf1_update(s, diff, value); 931 return; 932 933 default: 934 OMAP_BAD_REG(addr); 935 } 936 } 937 938 static const MemoryRegionOps omap_pin_cfg_ops = { 939 .read = omap_pin_cfg_read, 940 .write = omap_pin_cfg_write, 941 .endianness = DEVICE_NATIVE_ENDIAN, 942 }; 943 944 static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu) 945 { 946 /* Start in Compatibility Mode. */ 947 mpu->compat1509 = 1; 948 omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0); 949 omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0); 950 omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0); 951 memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl)); 952 memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl)); 953 memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl)); 954 memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl)); 955 memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl)); 956 memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl)); 957 memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl)); 958 } 959 960 static void omap_pin_cfg_init(MemoryRegion *system_memory, 961 hwaddr base, 962 struct omap_mpu_state_s *mpu) 963 { 964 memory_region_init_io(&mpu->pin_cfg_iomem, NULL, &omap_pin_cfg_ops, mpu, 965 "omap-pin-cfg", 0x800); 966 memory_region_add_subregion(system_memory, base, &mpu->pin_cfg_iomem); 967 omap_pin_cfg_reset(mpu); 968 } 969 970 /* Device Identification, Die Identification */ 971 static uint64_t omap_id_read(void *opaque, hwaddr addr, 972 unsigned size) 973 { 974 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 975 976 if (size != 4) { 977 return omap_badwidth_read32(opaque, addr); 978 } 979 980 switch (addr) { 981 case 0xfffe1800: /* DIE_ID_LSB */ 982 return 0xc9581f0e; 983 case 0xfffe1804: /* DIE_ID_MSB */ 984 return 0xa8858bfa; 985 986 case 0xfffe2000: /* PRODUCT_ID_LSB */ 987 return 0x00aaaafc; 988 case 0xfffe2004: /* PRODUCT_ID_MSB */ 989 return 0xcafeb574; 990 991 case 0xfffed400: /* JTAG_ID_LSB */ 992 switch (s->mpu_model) { 993 case omap310: 994 return 0x03310315; 995 case omap1510: 996 return 0x03310115; 997 default: 998 hw_error("%s: bad mpu model\n", __FUNCTION__); 999 } 1000 break; 1001 1002 case 0xfffed404: /* JTAG_ID_MSB */ 1003 switch (s->mpu_model) { 1004 case omap310: 1005 return 0xfb57402f; 1006 case omap1510: 1007 return 0xfb47002f; 1008 default: 1009 hw_error("%s: bad mpu model\n", __FUNCTION__); 1010 } 1011 break; 1012 } 1013 1014 OMAP_BAD_REG(addr); 1015 return 0; 1016 } 1017 1018 static void omap_id_write(void *opaque, hwaddr addr, 1019 uint64_t value, unsigned size) 1020 { 1021 if (size != 4) { 1022 omap_badwidth_write32(opaque, addr, value); 1023 return; 1024 } 1025 1026 OMAP_BAD_REG(addr); 1027 } 1028 1029 static const MemoryRegionOps omap_id_ops = { 1030 .read = omap_id_read, 1031 .write = omap_id_write, 1032 .endianness = DEVICE_NATIVE_ENDIAN, 1033 }; 1034 1035 static void omap_id_init(MemoryRegion *memory, struct omap_mpu_state_s *mpu) 1036 { 1037 memory_region_init_io(&mpu->id_iomem, NULL, &omap_id_ops, mpu, 1038 "omap-id", 0x100000000ULL); 1039 memory_region_init_alias(&mpu->id_iomem_e18, NULL, "omap-id-e18", &mpu->id_iomem, 1040 0xfffe1800, 0x800); 1041 memory_region_add_subregion(memory, 0xfffe1800, &mpu->id_iomem_e18); 1042 memory_region_init_alias(&mpu->id_iomem_ed4, NULL, "omap-id-ed4", &mpu->id_iomem, 1043 0xfffed400, 0x100); 1044 memory_region_add_subregion(memory, 0xfffed400, &mpu->id_iomem_ed4); 1045 if (!cpu_is_omap15xx(mpu)) { 1046 memory_region_init_alias(&mpu->id_iomem_ed4, NULL, "omap-id-e20", 1047 &mpu->id_iomem, 0xfffe2000, 0x800); 1048 memory_region_add_subregion(memory, 0xfffe2000, &mpu->id_iomem_e20); 1049 } 1050 } 1051 1052 /* MPUI Control (Dummy) */ 1053 static uint64_t omap_mpui_read(void *opaque, hwaddr addr, 1054 unsigned size) 1055 { 1056 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1057 1058 if (size != 4) { 1059 return omap_badwidth_read32(opaque, addr); 1060 } 1061 1062 switch (addr) { 1063 case 0x00: /* CTRL */ 1064 return s->mpui_ctrl; 1065 case 0x04: /* DEBUG_ADDR */ 1066 return 0x01ffffff; 1067 case 0x08: /* DEBUG_DATA */ 1068 return 0xffffffff; 1069 case 0x0c: /* DEBUG_FLAG */ 1070 return 0x00000800; 1071 case 0x10: /* STATUS */ 1072 return 0x00000000; 1073 1074 /* Not in OMAP310 */ 1075 case 0x14: /* DSP_STATUS */ 1076 case 0x18: /* DSP_BOOT_CONFIG */ 1077 return 0x00000000; 1078 case 0x1c: /* DSP_MPUI_CONFIG */ 1079 return 0x0000ffff; 1080 } 1081 1082 OMAP_BAD_REG(addr); 1083 return 0; 1084 } 1085 1086 static void omap_mpui_write(void *opaque, hwaddr addr, 1087 uint64_t value, unsigned size) 1088 { 1089 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1090 1091 if (size != 4) { 1092 omap_badwidth_write32(opaque, addr, value); 1093 return; 1094 } 1095 1096 switch (addr) { 1097 case 0x00: /* CTRL */ 1098 s->mpui_ctrl = value & 0x007fffff; 1099 break; 1100 1101 case 0x04: /* DEBUG_ADDR */ 1102 case 0x08: /* DEBUG_DATA */ 1103 case 0x0c: /* DEBUG_FLAG */ 1104 case 0x10: /* STATUS */ 1105 /* Not in OMAP310 */ 1106 case 0x14: /* DSP_STATUS */ 1107 OMAP_RO_REG(addr); 1108 break; 1109 case 0x18: /* DSP_BOOT_CONFIG */ 1110 case 0x1c: /* DSP_MPUI_CONFIG */ 1111 break; 1112 1113 default: 1114 OMAP_BAD_REG(addr); 1115 } 1116 } 1117 1118 static const MemoryRegionOps omap_mpui_ops = { 1119 .read = omap_mpui_read, 1120 .write = omap_mpui_write, 1121 .endianness = DEVICE_NATIVE_ENDIAN, 1122 }; 1123 1124 static void omap_mpui_reset(struct omap_mpu_state_s *s) 1125 { 1126 s->mpui_ctrl = 0x0003ff1b; 1127 } 1128 1129 static void omap_mpui_init(MemoryRegion *memory, hwaddr base, 1130 struct omap_mpu_state_s *mpu) 1131 { 1132 memory_region_init_io(&mpu->mpui_iomem, NULL, &omap_mpui_ops, mpu, 1133 "omap-mpui", 0x100); 1134 memory_region_add_subregion(memory, base, &mpu->mpui_iomem); 1135 1136 omap_mpui_reset(mpu); 1137 } 1138 1139 /* TIPB Bridges */ 1140 struct omap_tipb_bridge_s { 1141 qemu_irq abort; 1142 MemoryRegion iomem; 1143 1144 int width_intr; 1145 uint16_t control; 1146 uint16_t alloc; 1147 uint16_t buffer; 1148 uint16_t enh_control; 1149 }; 1150 1151 static uint64_t omap_tipb_bridge_read(void *opaque, hwaddr addr, 1152 unsigned size) 1153 { 1154 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; 1155 1156 if (size < 2) { 1157 return omap_badwidth_read16(opaque, addr); 1158 } 1159 1160 switch (addr) { 1161 case 0x00: /* TIPB_CNTL */ 1162 return s->control; 1163 case 0x04: /* TIPB_BUS_ALLOC */ 1164 return s->alloc; 1165 case 0x08: /* MPU_TIPB_CNTL */ 1166 return s->buffer; 1167 case 0x0c: /* ENHANCED_TIPB_CNTL */ 1168 return s->enh_control; 1169 case 0x10: /* ADDRESS_DBG */ 1170 case 0x14: /* DATA_DEBUG_LOW */ 1171 case 0x18: /* DATA_DEBUG_HIGH */ 1172 return 0xffff; 1173 case 0x1c: /* DEBUG_CNTR_SIG */ 1174 return 0x00f8; 1175 } 1176 1177 OMAP_BAD_REG(addr); 1178 return 0; 1179 } 1180 1181 static void omap_tipb_bridge_write(void *opaque, hwaddr addr, 1182 uint64_t value, unsigned size) 1183 { 1184 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; 1185 1186 if (size < 2) { 1187 omap_badwidth_write16(opaque, addr, value); 1188 return; 1189 } 1190 1191 switch (addr) { 1192 case 0x00: /* TIPB_CNTL */ 1193 s->control = value & 0xffff; 1194 break; 1195 1196 case 0x04: /* TIPB_BUS_ALLOC */ 1197 s->alloc = value & 0x003f; 1198 break; 1199 1200 case 0x08: /* MPU_TIPB_CNTL */ 1201 s->buffer = value & 0x0003; 1202 break; 1203 1204 case 0x0c: /* ENHANCED_TIPB_CNTL */ 1205 s->width_intr = !(value & 2); 1206 s->enh_control = value & 0x000f; 1207 break; 1208 1209 case 0x10: /* ADDRESS_DBG */ 1210 case 0x14: /* DATA_DEBUG_LOW */ 1211 case 0x18: /* DATA_DEBUG_HIGH */ 1212 case 0x1c: /* DEBUG_CNTR_SIG */ 1213 OMAP_RO_REG(addr); 1214 break; 1215 1216 default: 1217 OMAP_BAD_REG(addr); 1218 } 1219 } 1220 1221 static const MemoryRegionOps omap_tipb_bridge_ops = { 1222 .read = omap_tipb_bridge_read, 1223 .write = omap_tipb_bridge_write, 1224 .endianness = DEVICE_NATIVE_ENDIAN, 1225 }; 1226 1227 static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s) 1228 { 1229 s->control = 0xffff; 1230 s->alloc = 0x0009; 1231 s->buffer = 0x0000; 1232 s->enh_control = 0x000f; 1233 } 1234 1235 static struct omap_tipb_bridge_s *omap_tipb_bridge_init( 1236 MemoryRegion *memory, hwaddr base, 1237 qemu_irq abort_irq, omap_clk clk) 1238 { 1239 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) 1240 g_malloc0(sizeof(struct omap_tipb_bridge_s)); 1241 1242 s->abort = abort_irq; 1243 omap_tipb_bridge_reset(s); 1244 1245 memory_region_init_io(&s->iomem, NULL, &omap_tipb_bridge_ops, s, 1246 "omap-tipb-bridge", 0x100); 1247 memory_region_add_subregion(memory, base, &s->iomem); 1248 1249 return s; 1250 } 1251 1252 /* Dummy Traffic Controller's Memory Interface */ 1253 static uint64_t omap_tcmi_read(void *opaque, hwaddr addr, 1254 unsigned size) 1255 { 1256 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1257 uint32_t ret; 1258 1259 if (size != 4) { 1260 return omap_badwidth_read32(opaque, addr); 1261 } 1262 1263 switch (addr) { 1264 case 0x00: /* IMIF_PRIO */ 1265 case 0x04: /* EMIFS_PRIO */ 1266 case 0x08: /* EMIFF_PRIO */ 1267 case 0x0c: /* EMIFS_CONFIG */ 1268 case 0x10: /* EMIFS_CS0_CONFIG */ 1269 case 0x14: /* EMIFS_CS1_CONFIG */ 1270 case 0x18: /* EMIFS_CS2_CONFIG */ 1271 case 0x1c: /* EMIFS_CS3_CONFIG */ 1272 case 0x24: /* EMIFF_MRS */ 1273 case 0x28: /* TIMEOUT1 */ 1274 case 0x2c: /* TIMEOUT2 */ 1275 case 0x30: /* TIMEOUT3 */ 1276 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ 1277 case 0x40: /* EMIFS_CFG_DYN_WAIT */ 1278 return s->tcmi_regs[addr >> 2]; 1279 1280 case 0x20: /* EMIFF_SDRAM_CONFIG */ 1281 ret = s->tcmi_regs[addr >> 2]; 1282 s->tcmi_regs[addr >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */ 1283 /* XXX: We can try using the VGA_DIRTY flag for this */ 1284 return ret; 1285 } 1286 1287 OMAP_BAD_REG(addr); 1288 return 0; 1289 } 1290 1291 static void omap_tcmi_write(void *opaque, hwaddr addr, 1292 uint64_t value, unsigned size) 1293 { 1294 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1295 1296 if (size != 4) { 1297 omap_badwidth_write32(opaque, addr, value); 1298 return; 1299 } 1300 1301 switch (addr) { 1302 case 0x00: /* IMIF_PRIO */ 1303 case 0x04: /* EMIFS_PRIO */ 1304 case 0x08: /* EMIFF_PRIO */ 1305 case 0x10: /* EMIFS_CS0_CONFIG */ 1306 case 0x14: /* EMIFS_CS1_CONFIG */ 1307 case 0x18: /* EMIFS_CS2_CONFIG */ 1308 case 0x1c: /* EMIFS_CS3_CONFIG */ 1309 case 0x20: /* EMIFF_SDRAM_CONFIG */ 1310 case 0x24: /* EMIFF_MRS */ 1311 case 0x28: /* TIMEOUT1 */ 1312 case 0x2c: /* TIMEOUT2 */ 1313 case 0x30: /* TIMEOUT3 */ 1314 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ 1315 case 0x40: /* EMIFS_CFG_DYN_WAIT */ 1316 s->tcmi_regs[addr >> 2] = value; 1317 break; 1318 case 0x0c: /* EMIFS_CONFIG */ 1319 s->tcmi_regs[addr >> 2] = (value & 0xf) | (1 << 4); 1320 break; 1321 1322 default: 1323 OMAP_BAD_REG(addr); 1324 } 1325 } 1326 1327 static const MemoryRegionOps omap_tcmi_ops = { 1328 .read = omap_tcmi_read, 1329 .write = omap_tcmi_write, 1330 .endianness = DEVICE_NATIVE_ENDIAN, 1331 }; 1332 1333 static void omap_tcmi_reset(struct omap_mpu_state_s *mpu) 1334 { 1335 mpu->tcmi_regs[0x00 >> 2] = 0x00000000; 1336 mpu->tcmi_regs[0x04 >> 2] = 0x00000000; 1337 mpu->tcmi_regs[0x08 >> 2] = 0x00000000; 1338 mpu->tcmi_regs[0x0c >> 2] = 0x00000010; 1339 mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb; 1340 mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb; 1341 mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb; 1342 mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb; 1343 mpu->tcmi_regs[0x20 >> 2] = 0x00618800; 1344 mpu->tcmi_regs[0x24 >> 2] = 0x00000037; 1345 mpu->tcmi_regs[0x28 >> 2] = 0x00000000; 1346 mpu->tcmi_regs[0x2c >> 2] = 0x00000000; 1347 mpu->tcmi_regs[0x30 >> 2] = 0x00000000; 1348 mpu->tcmi_regs[0x3c >> 2] = 0x00000003; 1349 mpu->tcmi_regs[0x40 >> 2] = 0x00000000; 1350 } 1351 1352 static void omap_tcmi_init(MemoryRegion *memory, hwaddr base, 1353 struct omap_mpu_state_s *mpu) 1354 { 1355 memory_region_init_io(&mpu->tcmi_iomem, NULL, &omap_tcmi_ops, mpu, 1356 "omap-tcmi", 0x100); 1357 memory_region_add_subregion(memory, base, &mpu->tcmi_iomem); 1358 omap_tcmi_reset(mpu); 1359 } 1360 1361 /* Digital phase-locked loops control */ 1362 struct dpll_ctl_s { 1363 MemoryRegion iomem; 1364 uint16_t mode; 1365 omap_clk dpll; 1366 }; 1367 1368 static uint64_t omap_dpll_read(void *opaque, hwaddr addr, 1369 unsigned size) 1370 { 1371 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; 1372 1373 if (size != 2) { 1374 return omap_badwidth_read16(opaque, addr); 1375 } 1376 1377 if (addr == 0x00) /* CTL_REG */ 1378 return s->mode; 1379 1380 OMAP_BAD_REG(addr); 1381 return 0; 1382 } 1383 1384 static void omap_dpll_write(void *opaque, hwaddr addr, 1385 uint64_t value, unsigned size) 1386 { 1387 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; 1388 uint16_t diff; 1389 static const int bypass_div[4] = { 1, 2, 4, 4 }; 1390 int div, mult; 1391 1392 if (size != 2) { 1393 omap_badwidth_write16(opaque, addr, value); 1394 return; 1395 } 1396 1397 if (addr == 0x00) { /* CTL_REG */ 1398 /* See omap_ulpd_pm_write() too */ 1399 diff = s->mode & value; 1400 s->mode = value & 0x2fff; 1401 if (diff & (0x3ff << 2)) { 1402 if (value & (1 << 4)) { /* PLL_ENABLE */ 1403 div = ((value >> 5) & 3) + 1; /* PLL_DIV */ 1404 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ 1405 } else { 1406 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ 1407 mult = 1; 1408 } 1409 omap_clk_setrate(s->dpll, div, mult); 1410 } 1411 1412 /* Enter the desired mode. */ 1413 s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1); 1414 1415 /* Act as if the lock is restored. */ 1416 s->mode |= 2; 1417 } else { 1418 OMAP_BAD_REG(addr); 1419 } 1420 } 1421 1422 static const MemoryRegionOps omap_dpll_ops = { 1423 .read = omap_dpll_read, 1424 .write = omap_dpll_write, 1425 .endianness = DEVICE_NATIVE_ENDIAN, 1426 }; 1427 1428 static void omap_dpll_reset(struct dpll_ctl_s *s) 1429 { 1430 s->mode = 0x2002; 1431 omap_clk_setrate(s->dpll, 1, 1); 1432 } 1433 1434 static struct dpll_ctl_s *omap_dpll_init(MemoryRegion *memory, 1435 hwaddr base, omap_clk clk) 1436 { 1437 struct dpll_ctl_s *s = g_malloc0(sizeof(*s)); 1438 memory_region_init_io(&s->iomem, NULL, &omap_dpll_ops, s, "omap-dpll", 0x100); 1439 1440 s->dpll = clk; 1441 omap_dpll_reset(s); 1442 1443 memory_region_add_subregion(memory, base, &s->iomem); 1444 return s; 1445 } 1446 1447 /* MPU Clock/Reset/Power Mode Control */ 1448 static uint64_t omap_clkm_read(void *opaque, hwaddr addr, 1449 unsigned size) 1450 { 1451 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1452 1453 if (size != 2) { 1454 return omap_badwidth_read16(opaque, addr); 1455 } 1456 1457 switch (addr) { 1458 case 0x00: /* ARM_CKCTL */ 1459 return s->clkm.arm_ckctl; 1460 1461 case 0x04: /* ARM_IDLECT1 */ 1462 return s->clkm.arm_idlect1; 1463 1464 case 0x08: /* ARM_IDLECT2 */ 1465 return s->clkm.arm_idlect2; 1466 1467 case 0x0c: /* ARM_EWUPCT */ 1468 return s->clkm.arm_ewupct; 1469 1470 case 0x10: /* ARM_RSTCT1 */ 1471 return s->clkm.arm_rstct1; 1472 1473 case 0x14: /* ARM_RSTCT2 */ 1474 return s->clkm.arm_rstct2; 1475 1476 case 0x18: /* ARM_SYSST */ 1477 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start; 1478 1479 case 0x1c: /* ARM_CKOUT1 */ 1480 return s->clkm.arm_ckout1; 1481 1482 case 0x20: /* ARM_CKOUT2 */ 1483 break; 1484 } 1485 1486 OMAP_BAD_REG(addr); 1487 return 0; 1488 } 1489 1490 static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s, 1491 uint16_t diff, uint16_t value) 1492 { 1493 omap_clk clk; 1494 1495 if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */ 1496 if (value & (1 << 14)) 1497 /* Reserved */; 1498 else { 1499 clk = omap_findclk(s, "arminth_ck"); 1500 omap_clk_reparent(clk, omap_findclk(s, "tc_ck")); 1501 } 1502 } 1503 if (diff & (1 << 12)) { /* ARM_TIMXO */ 1504 clk = omap_findclk(s, "armtim_ck"); 1505 if (value & (1 << 12)) 1506 omap_clk_reparent(clk, omap_findclk(s, "clkin")); 1507 else 1508 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1")); 1509 } 1510 /* XXX: en_dspck */ 1511 if (diff & (3 << 10)) { /* DSPMMUDIV */ 1512 clk = omap_findclk(s, "dspmmu_ck"); 1513 omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1); 1514 } 1515 if (diff & (3 << 8)) { /* TCDIV */ 1516 clk = omap_findclk(s, "tc_ck"); 1517 omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1); 1518 } 1519 if (diff & (3 << 6)) { /* DSPDIV */ 1520 clk = omap_findclk(s, "dsp_ck"); 1521 omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1); 1522 } 1523 if (diff & (3 << 4)) { /* ARMDIV */ 1524 clk = omap_findclk(s, "arm_ck"); 1525 omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1); 1526 } 1527 if (diff & (3 << 2)) { /* LCDDIV */ 1528 clk = omap_findclk(s, "lcd_ck"); 1529 omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1); 1530 } 1531 if (diff & (3 << 0)) { /* PERDIV */ 1532 clk = omap_findclk(s, "armper_ck"); 1533 omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1); 1534 } 1535 } 1536 1537 static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s, 1538 uint16_t diff, uint16_t value) 1539 { 1540 omap_clk clk; 1541 1542 if (value & (1 << 11)) { /* SETARM_IDLE */ 1543 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); 1544 } 1545 if (!(value & (1 << 10))) /* WKUP_MODE */ 1546 qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */ 1547 1548 #define SET_CANIDLE(clock, bit) \ 1549 if (diff & (1 << bit)) { \ 1550 clk = omap_findclk(s, clock); \ 1551 omap_clk_canidle(clk, (value >> bit) & 1); \ 1552 } 1553 SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */ 1554 SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */ 1555 SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */ 1556 SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */ 1557 SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */ 1558 SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */ 1559 SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */ 1560 SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */ 1561 SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */ 1562 SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */ 1563 SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */ 1564 SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */ 1565 SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */ 1566 SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */ 1567 } 1568 1569 static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s, 1570 uint16_t diff, uint16_t value) 1571 { 1572 omap_clk clk; 1573 1574 #define SET_ONOFF(clock, bit) \ 1575 if (diff & (1 << bit)) { \ 1576 clk = omap_findclk(s, clock); \ 1577 omap_clk_onoff(clk, (value >> bit) & 1); \ 1578 } 1579 SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */ 1580 SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */ 1581 SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */ 1582 SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */ 1583 SET_ONOFF("lb_ck", 4) /* EN_LBCK */ 1584 SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */ 1585 SET_ONOFF("mpui_ck", 6) /* EN_APICK */ 1586 SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */ 1587 SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */ 1588 SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */ 1589 SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */ 1590 } 1591 1592 static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s, 1593 uint16_t diff, uint16_t value) 1594 { 1595 omap_clk clk; 1596 1597 if (diff & (3 << 4)) { /* TCLKOUT */ 1598 clk = omap_findclk(s, "tclk_out"); 1599 switch ((value >> 4) & 3) { 1600 case 1: 1601 omap_clk_reparent(clk, omap_findclk(s, "ck_gen3")); 1602 omap_clk_onoff(clk, 1); 1603 break; 1604 case 2: 1605 omap_clk_reparent(clk, omap_findclk(s, "tc_ck")); 1606 omap_clk_onoff(clk, 1); 1607 break; 1608 default: 1609 omap_clk_onoff(clk, 0); 1610 } 1611 } 1612 if (diff & (3 << 2)) { /* DCLKOUT */ 1613 clk = omap_findclk(s, "dclk_out"); 1614 switch ((value >> 2) & 3) { 1615 case 0: 1616 omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck")); 1617 break; 1618 case 1: 1619 omap_clk_reparent(clk, omap_findclk(s, "ck_gen2")); 1620 break; 1621 case 2: 1622 omap_clk_reparent(clk, omap_findclk(s, "dsp_ck")); 1623 break; 1624 case 3: 1625 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14")); 1626 break; 1627 } 1628 } 1629 if (diff & (3 << 0)) { /* ACLKOUT */ 1630 clk = omap_findclk(s, "aclk_out"); 1631 switch ((value >> 0) & 3) { 1632 case 1: 1633 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1")); 1634 omap_clk_onoff(clk, 1); 1635 break; 1636 case 2: 1637 omap_clk_reparent(clk, omap_findclk(s, "arm_ck")); 1638 omap_clk_onoff(clk, 1); 1639 break; 1640 case 3: 1641 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14")); 1642 omap_clk_onoff(clk, 1); 1643 break; 1644 default: 1645 omap_clk_onoff(clk, 0); 1646 } 1647 } 1648 } 1649 1650 static void omap_clkm_write(void *opaque, hwaddr addr, 1651 uint64_t value, unsigned size) 1652 { 1653 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1654 uint16_t diff; 1655 omap_clk clk; 1656 static const char *clkschemename[8] = { 1657 "fully synchronous", "fully asynchronous", "synchronous scalable", 1658 "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4", 1659 }; 1660 1661 if (size != 2) { 1662 omap_badwidth_write16(opaque, addr, value); 1663 return; 1664 } 1665 1666 switch (addr) { 1667 case 0x00: /* ARM_CKCTL */ 1668 diff = s->clkm.arm_ckctl ^ value; 1669 s->clkm.arm_ckctl = value & 0x7fff; 1670 omap_clkm_ckctl_update(s, diff, value); 1671 return; 1672 1673 case 0x04: /* ARM_IDLECT1 */ 1674 diff = s->clkm.arm_idlect1 ^ value; 1675 s->clkm.arm_idlect1 = value & 0x0fff; 1676 omap_clkm_idlect1_update(s, diff, value); 1677 return; 1678 1679 case 0x08: /* ARM_IDLECT2 */ 1680 diff = s->clkm.arm_idlect2 ^ value; 1681 s->clkm.arm_idlect2 = value & 0x07ff; 1682 omap_clkm_idlect2_update(s, diff, value); 1683 return; 1684 1685 case 0x0c: /* ARM_EWUPCT */ 1686 s->clkm.arm_ewupct = value & 0x003f; 1687 return; 1688 1689 case 0x10: /* ARM_RSTCT1 */ 1690 diff = s->clkm.arm_rstct1 ^ value; 1691 s->clkm.arm_rstct1 = value & 0x0007; 1692 if (value & 9) { 1693 qemu_system_reset_request(); 1694 s->clkm.cold_start = 0xa; 1695 } 1696 if (diff & ~value & 4) { /* DSP_RST */ 1697 omap_mpui_reset(s); 1698 omap_tipb_bridge_reset(s->private_tipb); 1699 omap_tipb_bridge_reset(s->public_tipb); 1700 } 1701 if (diff & 2) { /* DSP_EN */ 1702 clk = omap_findclk(s, "dsp_ck"); 1703 omap_clk_canidle(clk, (~value >> 1) & 1); 1704 } 1705 return; 1706 1707 case 0x14: /* ARM_RSTCT2 */ 1708 s->clkm.arm_rstct2 = value & 0x0001; 1709 return; 1710 1711 case 0x18: /* ARM_SYSST */ 1712 if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) { 1713 s->clkm.clocking_scheme = (value >> 11) & 7; 1714 printf("%s: clocking scheme set to %s\n", __FUNCTION__, 1715 clkschemename[s->clkm.clocking_scheme]); 1716 } 1717 s->clkm.cold_start &= value & 0x3f; 1718 return; 1719 1720 case 0x1c: /* ARM_CKOUT1 */ 1721 diff = s->clkm.arm_ckout1 ^ value; 1722 s->clkm.arm_ckout1 = value & 0x003f; 1723 omap_clkm_ckout1_update(s, diff, value); 1724 return; 1725 1726 case 0x20: /* ARM_CKOUT2 */ 1727 default: 1728 OMAP_BAD_REG(addr); 1729 } 1730 } 1731 1732 static const MemoryRegionOps omap_clkm_ops = { 1733 .read = omap_clkm_read, 1734 .write = omap_clkm_write, 1735 .endianness = DEVICE_NATIVE_ENDIAN, 1736 }; 1737 1738 static uint64_t omap_clkdsp_read(void *opaque, hwaddr addr, 1739 unsigned size) 1740 { 1741 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1742 CPUState *cpu = CPU(s->cpu); 1743 1744 if (size != 2) { 1745 return omap_badwidth_read16(opaque, addr); 1746 } 1747 1748 switch (addr) { 1749 case 0x04: /* DSP_IDLECT1 */ 1750 return s->clkm.dsp_idlect1; 1751 1752 case 0x08: /* DSP_IDLECT2 */ 1753 return s->clkm.dsp_idlect2; 1754 1755 case 0x14: /* DSP_RSTCT2 */ 1756 return s->clkm.dsp_rstct2; 1757 1758 case 0x18: /* DSP_SYSST */ 1759 cpu = CPU(s->cpu); 1760 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start | 1761 (cpu->halted << 6); /* Quite useless... */ 1762 } 1763 1764 OMAP_BAD_REG(addr); 1765 return 0; 1766 } 1767 1768 static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s, 1769 uint16_t diff, uint16_t value) 1770 { 1771 omap_clk clk; 1772 1773 SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */ 1774 } 1775 1776 static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s, 1777 uint16_t diff, uint16_t value) 1778 { 1779 omap_clk clk; 1780 1781 SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */ 1782 } 1783 1784 static void omap_clkdsp_write(void *opaque, hwaddr addr, 1785 uint64_t value, unsigned size) 1786 { 1787 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1788 uint16_t diff; 1789 1790 if (size != 2) { 1791 omap_badwidth_write16(opaque, addr, value); 1792 return; 1793 } 1794 1795 switch (addr) { 1796 case 0x04: /* DSP_IDLECT1 */ 1797 diff = s->clkm.dsp_idlect1 ^ value; 1798 s->clkm.dsp_idlect1 = value & 0x01f7; 1799 omap_clkdsp_idlect1_update(s, diff, value); 1800 break; 1801 1802 case 0x08: /* DSP_IDLECT2 */ 1803 s->clkm.dsp_idlect2 = value & 0x0037; 1804 diff = s->clkm.dsp_idlect1 ^ value; 1805 omap_clkdsp_idlect2_update(s, diff, value); 1806 break; 1807 1808 case 0x14: /* DSP_RSTCT2 */ 1809 s->clkm.dsp_rstct2 = value & 0x0001; 1810 break; 1811 1812 case 0x18: /* DSP_SYSST */ 1813 s->clkm.cold_start &= value & 0x3f; 1814 break; 1815 1816 default: 1817 OMAP_BAD_REG(addr); 1818 } 1819 } 1820 1821 static const MemoryRegionOps omap_clkdsp_ops = { 1822 .read = omap_clkdsp_read, 1823 .write = omap_clkdsp_write, 1824 .endianness = DEVICE_NATIVE_ENDIAN, 1825 }; 1826 1827 static void omap_clkm_reset(struct omap_mpu_state_s *s) 1828 { 1829 if (s->wdt && s->wdt->reset) 1830 s->clkm.cold_start = 0x6; 1831 s->clkm.clocking_scheme = 0; 1832 omap_clkm_ckctl_update(s, ~0, 0x3000); 1833 s->clkm.arm_ckctl = 0x3000; 1834 omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 ^ 0x0400, 0x0400); 1835 s->clkm.arm_idlect1 = 0x0400; 1836 omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 ^ 0x0100, 0x0100); 1837 s->clkm.arm_idlect2 = 0x0100; 1838 s->clkm.arm_ewupct = 0x003f; 1839 s->clkm.arm_rstct1 = 0x0000; 1840 s->clkm.arm_rstct2 = 0x0000; 1841 s->clkm.arm_ckout1 = 0x0015; 1842 s->clkm.dpll1_mode = 0x2002; 1843 omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040); 1844 s->clkm.dsp_idlect1 = 0x0040; 1845 omap_clkdsp_idlect2_update(s, ~0, 0x0000); 1846 s->clkm.dsp_idlect2 = 0x0000; 1847 s->clkm.dsp_rstct2 = 0x0000; 1848 } 1849 1850 static void omap_clkm_init(MemoryRegion *memory, hwaddr mpu_base, 1851 hwaddr dsp_base, struct omap_mpu_state_s *s) 1852 { 1853 memory_region_init_io(&s->clkm_iomem, NULL, &omap_clkm_ops, s, 1854 "omap-clkm", 0x100); 1855 memory_region_init_io(&s->clkdsp_iomem, NULL, &omap_clkdsp_ops, s, 1856 "omap-clkdsp", 0x1000); 1857 1858 s->clkm.arm_idlect1 = 0x03ff; 1859 s->clkm.arm_idlect2 = 0x0100; 1860 s->clkm.dsp_idlect1 = 0x0002; 1861 omap_clkm_reset(s); 1862 s->clkm.cold_start = 0x3a; 1863 1864 memory_region_add_subregion(memory, mpu_base, &s->clkm_iomem); 1865 memory_region_add_subregion(memory, dsp_base, &s->clkdsp_iomem); 1866 } 1867 1868 /* MPU I/O */ 1869 struct omap_mpuio_s { 1870 qemu_irq irq; 1871 qemu_irq kbd_irq; 1872 qemu_irq *in; 1873 qemu_irq handler[16]; 1874 qemu_irq wakeup; 1875 MemoryRegion iomem; 1876 1877 uint16_t inputs; 1878 uint16_t outputs; 1879 uint16_t dir; 1880 uint16_t edge; 1881 uint16_t mask; 1882 uint16_t ints; 1883 1884 uint16_t debounce; 1885 uint16_t latch; 1886 uint8_t event; 1887 1888 uint8_t buttons[5]; 1889 uint8_t row_latch; 1890 uint8_t cols; 1891 int kbd_mask; 1892 int clk; 1893 }; 1894 1895 static void omap_mpuio_set(void *opaque, int line, int level) 1896 { 1897 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; 1898 uint16_t prev = s->inputs; 1899 1900 if (level) 1901 s->inputs |= 1 << line; 1902 else 1903 s->inputs &= ~(1 << line); 1904 1905 if (((1 << line) & s->dir & ~s->mask) && s->clk) { 1906 if ((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) { 1907 s->ints |= 1 << line; 1908 qemu_irq_raise(s->irq); 1909 /* TODO: wakeup */ 1910 } 1911 if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */ 1912 (s->event >> 1) == line) /* PIN_SELECT */ 1913 s->latch = s->inputs; 1914 } 1915 } 1916 1917 static void omap_mpuio_kbd_update(struct omap_mpuio_s *s) 1918 { 1919 int i; 1920 uint8_t *row, rows = 0, cols = ~s->cols; 1921 1922 for (row = s->buttons + 4, i = 1 << 4; i; row --, i >>= 1) 1923 if (*row & cols) 1924 rows |= i; 1925 1926 qemu_set_irq(s->kbd_irq, rows && !s->kbd_mask && s->clk); 1927 s->row_latch = ~rows; 1928 } 1929 1930 static uint64_t omap_mpuio_read(void *opaque, hwaddr addr, 1931 unsigned size) 1932 { 1933 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; 1934 int offset = addr & OMAP_MPUI_REG_MASK; 1935 uint16_t ret; 1936 1937 if (size != 2) { 1938 return omap_badwidth_read16(opaque, addr); 1939 } 1940 1941 switch (offset) { 1942 case 0x00: /* INPUT_LATCH */ 1943 return s->inputs; 1944 1945 case 0x04: /* OUTPUT_REG */ 1946 return s->outputs; 1947 1948 case 0x08: /* IO_CNTL */ 1949 return s->dir; 1950 1951 case 0x10: /* KBR_LATCH */ 1952 return s->row_latch; 1953 1954 case 0x14: /* KBC_REG */ 1955 return s->cols; 1956 1957 case 0x18: /* GPIO_EVENT_MODE_REG */ 1958 return s->event; 1959 1960 case 0x1c: /* GPIO_INT_EDGE_REG */ 1961 return s->edge; 1962 1963 case 0x20: /* KBD_INT */ 1964 return (~s->row_latch & 0x1f) && !s->kbd_mask; 1965 1966 case 0x24: /* GPIO_INT */ 1967 ret = s->ints; 1968 s->ints &= s->mask; 1969 if (ret) 1970 qemu_irq_lower(s->irq); 1971 return ret; 1972 1973 case 0x28: /* KBD_MASKIT */ 1974 return s->kbd_mask; 1975 1976 case 0x2c: /* GPIO_MASKIT */ 1977 return s->mask; 1978 1979 case 0x30: /* GPIO_DEBOUNCING_REG */ 1980 return s->debounce; 1981 1982 case 0x34: /* GPIO_LATCH_REG */ 1983 return s->latch; 1984 } 1985 1986 OMAP_BAD_REG(addr); 1987 return 0; 1988 } 1989 1990 static void omap_mpuio_write(void *opaque, hwaddr addr, 1991 uint64_t value, unsigned size) 1992 { 1993 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; 1994 int offset = addr & OMAP_MPUI_REG_MASK; 1995 uint16_t diff; 1996 int ln; 1997 1998 if (size != 2) { 1999 omap_badwidth_write16(opaque, addr, value); 2000 return; 2001 } 2002 2003 switch (offset) { 2004 case 0x04: /* OUTPUT_REG */ 2005 diff = (s->outputs ^ value) & ~s->dir; 2006 s->outputs = value; 2007 while ((ln = ffs(diff))) { 2008 ln --; 2009 if (s->handler[ln]) 2010 qemu_set_irq(s->handler[ln], (value >> ln) & 1); 2011 diff &= ~(1 << ln); 2012 } 2013 break; 2014 2015 case 0x08: /* IO_CNTL */ 2016 diff = s->outputs & (s->dir ^ value); 2017 s->dir = value; 2018 2019 value = s->outputs & ~s->dir; 2020 while ((ln = ffs(diff))) { 2021 ln --; 2022 if (s->handler[ln]) 2023 qemu_set_irq(s->handler[ln], (value >> ln) & 1); 2024 diff &= ~(1 << ln); 2025 } 2026 break; 2027 2028 case 0x14: /* KBC_REG */ 2029 s->cols = value; 2030 omap_mpuio_kbd_update(s); 2031 break; 2032 2033 case 0x18: /* GPIO_EVENT_MODE_REG */ 2034 s->event = value & 0x1f; 2035 break; 2036 2037 case 0x1c: /* GPIO_INT_EDGE_REG */ 2038 s->edge = value; 2039 break; 2040 2041 case 0x28: /* KBD_MASKIT */ 2042 s->kbd_mask = value & 1; 2043 omap_mpuio_kbd_update(s); 2044 break; 2045 2046 case 0x2c: /* GPIO_MASKIT */ 2047 s->mask = value; 2048 break; 2049 2050 case 0x30: /* GPIO_DEBOUNCING_REG */ 2051 s->debounce = value & 0x1ff; 2052 break; 2053 2054 case 0x00: /* INPUT_LATCH */ 2055 case 0x10: /* KBR_LATCH */ 2056 case 0x20: /* KBD_INT */ 2057 case 0x24: /* GPIO_INT */ 2058 case 0x34: /* GPIO_LATCH_REG */ 2059 OMAP_RO_REG(addr); 2060 return; 2061 2062 default: 2063 OMAP_BAD_REG(addr); 2064 return; 2065 } 2066 } 2067 2068 static const MemoryRegionOps omap_mpuio_ops = { 2069 .read = omap_mpuio_read, 2070 .write = omap_mpuio_write, 2071 .endianness = DEVICE_NATIVE_ENDIAN, 2072 }; 2073 2074 static void omap_mpuio_reset(struct omap_mpuio_s *s) 2075 { 2076 s->inputs = 0; 2077 s->outputs = 0; 2078 s->dir = ~0; 2079 s->event = 0; 2080 s->edge = 0; 2081 s->kbd_mask = 0; 2082 s->mask = 0; 2083 s->debounce = 0; 2084 s->latch = 0; 2085 s->ints = 0; 2086 s->row_latch = 0x1f; 2087 s->clk = 1; 2088 } 2089 2090 static void omap_mpuio_onoff(void *opaque, int line, int on) 2091 { 2092 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; 2093 2094 s->clk = on; 2095 if (on) 2096 omap_mpuio_kbd_update(s); 2097 } 2098 2099 static struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *memory, 2100 hwaddr base, 2101 qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup, 2102 omap_clk clk) 2103 { 2104 struct omap_mpuio_s *s = (struct omap_mpuio_s *) 2105 g_malloc0(sizeof(struct omap_mpuio_s)); 2106 2107 s->irq = gpio_int; 2108 s->kbd_irq = kbd_int; 2109 s->wakeup = wakeup; 2110 s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16); 2111 omap_mpuio_reset(s); 2112 2113 memory_region_init_io(&s->iomem, NULL, &omap_mpuio_ops, s, 2114 "omap-mpuio", 0x800); 2115 memory_region_add_subregion(memory, base, &s->iomem); 2116 2117 omap_clk_adduser(clk, qemu_allocate_irq(omap_mpuio_onoff, s, 0)); 2118 2119 return s; 2120 } 2121 2122 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s) 2123 { 2124 return s->in; 2125 } 2126 2127 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler) 2128 { 2129 if (line >= 16 || line < 0) 2130 hw_error("%s: No GPIO line %i\n", __FUNCTION__, line); 2131 s->handler[line] = handler; 2132 } 2133 2134 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down) 2135 { 2136 if (row >= 5 || row < 0) 2137 hw_error("%s: No key %i-%i\n", __FUNCTION__, col, row); 2138 2139 if (down) 2140 s->buttons[row] |= 1 << col; 2141 else 2142 s->buttons[row] &= ~(1 << col); 2143 2144 omap_mpuio_kbd_update(s); 2145 } 2146 2147 /* MicroWire Interface */ 2148 struct omap_uwire_s { 2149 MemoryRegion iomem; 2150 qemu_irq txirq; 2151 qemu_irq rxirq; 2152 qemu_irq txdrq; 2153 2154 uint16_t txbuf; 2155 uint16_t rxbuf; 2156 uint16_t control; 2157 uint16_t setup[5]; 2158 2159 uWireSlave *chip[4]; 2160 }; 2161 2162 static void omap_uwire_transfer_start(struct omap_uwire_s *s) 2163 { 2164 int chipselect = (s->control >> 10) & 3; /* INDEX */ 2165 uWireSlave *slave = s->chip[chipselect]; 2166 2167 if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */ 2168 if (s->control & (1 << 12)) /* CS_CMD */ 2169 if (slave && slave->send) 2170 slave->send(slave->opaque, 2171 s->txbuf >> (16 - ((s->control >> 5) & 0x1f))); 2172 s->control &= ~(1 << 14); /* CSRB */ 2173 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or 2174 * a DRQ. When is the level IRQ supposed to be reset? */ 2175 } 2176 2177 if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */ 2178 if (s->control & (1 << 12)) /* CS_CMD */ 2179 if (slave && slave->receive) 2180 s->rxbuf = slave->receive(slave->opaque); 2181 s->control |= 1 << 15; /* RDRB */ 2182 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or 2183 * a DRQ. When is the level IRQ supposed to be reset? */ 2184 } 2185 } 2186 2187 static uint64_t omap_uwire_read(void *opaque, hwaddr addr, 2188 unsigned size) 2189 { 2190 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; 2191 int offset = addr & OMAP_MPUI_REG_MASK; 2192 2193 if (size != 2) { 2194 return omap_badwidth_read16(opaque, addr); 2195 } 2196 2197 switch (offset) { 2198 case 0x00: /* RDR */ 2199 s->control &= ~(1 << 15); /* RDRB */ 2200 return s->rxbuf; 2201 2202 case 0x04: /* CSR */ 2203 return s->control; 2204 2205 case 0x08: /* SR1 */ 2206 return s->setup[0]; 2207 case 0x0c: /* SR2 */ 2208 return s->setup[1]; 2209 case 0x10: /* SR3 */ 2210 return s->setup[2]; 2211 case 0x14: /* SR4 */ 2212 return s->setup[3]; 2213 case 0x18: /* SR5 */ 2214 return s->setup[4]; 2215 } 2216 2217 OMAP_BAD_REG(addr); 2218 return 0; 2219 } 2220 2221 static void omap_uwire_write(void *opaque, hwaddr addr, 2222 uint64_t value, unsigned size) 2223 { 2224 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; 2225 int offset = addr & OMAP_MPUI_REG_MASK; 2226 2227 if (size != 2) { 2228 omap_badwidth_write16(opaque, addr, value); 2229 return; 2230 } 2231 2232 switch (offset) { 2233 case 0x00: /* TDR */ 2234 s->txbuf = value; /* TD */ 2235 if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */ 2236 ((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */ 2237 (s->control & (1 << 12)))) { /* CS_CMD */ 2238 s->control |= 1 << 14; /* CSRB */ 2239 omap_uwire_transfer_start(s); 2240 } 2241 break; 2242 2243 case 0x04: /* CSR */ 2244 s->control = value & 0x1fff; 2245 if (value & (1 << 13)) /* START */ 2246 omap_uwire_transfer_start(s); 2247 break; 2248 2249 case 0x08: /* SR1 */ 2250 s->setup[0] = value & 0x003f; 2251 break; 2252 2253 case 0x0c: /* SR2 */ 2254 s->setup[1] = value & 0x0fc0; 2255 break; 2256 2257 case 0x10: /* SR3 */ 2258 s->setup[2] = value & 0x0003; 2259 break; 2260 2261 case 0x14: /* SR4 */ 2262 s->setup[3] = value & 0x0001; 2263 break; 2264 2265 case 0x18: /* SR5 */ 2266 s->setup[4] = value & 0x000f; 2267 break; 2268 2269 default: 2270 OMAP_BAD_REG(addr); 2271 return; 2272 } 2273 } 2274 2275 static const MemoryRegionOps omap_uwire_ops = { 2276 .read = omap_uwire_read, 2277 .write = omap_uwire_write, 2278 .endianness = DEVICE_NATIVE_ENDIAN, 2279 }; 2280 2281 static void omap_uwire_reset(struct omap_uwire_s *s) 2282 { 2283 s->control = 0; 2284 s->setup[0] = 0; 2285 s->setup[1] = 0; 2286 s->setup[2] = 0; 2287 s->setup[3] = 0; 2288 s->setup[4] = 0; 2289 } 2290 2291 static struct omap_uwire_s *omap_uwire_init(MemoryRegion *system_memory, 2292 hwaddr base, 2293 qemu_irq txirq, qemu_irq rxirq, 2294 qemu_irq dma, 2295 omap_clk clk) 2296 { 2297 struct omap_uwire_s *s = (struct omap_uwire_s *) 2298 g_malloc0(sizeof(struct omap_uwire_s)); 2299 2300 s->txirq = txirq; 2301 s->rxirq = rxirq; 2302 s->txdrq = dma; 2303 omap_uwire_reset(s); 2304 2305 memory_region_init_io(&s->iomem, NULL, &omap_uwire_ops, s, "omap-uwire", 0x800); 2306 memory_region_add_subregion(system_memory, base, &s->iomem); 2307 2308 return s; 2309 } 2310 2311 void omap_uwire_attach(struct omap_uwire_s *s, 2312 uWireSlave *slave, int chipselect) 2313 { 2314 if (chipselect < 0 || chipselect > 3) { 2315 fprintf(stderr, "%s: Bad chipselect %i\n", __FUNCTION__, chipselect); 2316 exit(-1); 2317 } 2318 2319 s->chip[chipselect] = slave; 2320 } 2321 2322 /* Pseudonoise Pulse-Width Light Modulator */ 2323 struct omap_pwl_s { 2324 MemoryRegion iomem; 2325 uint8_t output; 2326 uint8_t level; 2327 uint8_t enable; 2328 int clk; 2329 }; 2330 2331 static void omap_pwl_update(struct omap_pwl_s *s) 2332 { 2333 int output = (s->clk && s->enable) ? s->level : 0; 2334 2335 if (output != s->output) { 2336 s->output = output; 2337 printf("%s: Backlight now at %i/256\n", __FUNCTION__, output); 2338 } 2339 } 2340 2341 static uint64_t omap_pwl_read(void *opaque, hwaddr addr, 2342 unsigned size) 2343 { 2344 struct omap_pwl_s *s = (struct omap_pwl_s *) opaque; 2345 int offset = addr & OMAP_MPUI_REG_MASK; 2346 2347 if (size != 1) { 2348 return omap_badwidth_read8(opaque, addr); 2349 } 2350 2351 switch (offset) { 2352 case 0x00: /* PWL_LEVEL */ 2353 return s->level; 2354 case 0x04: /* PWL_CTRL */ 2355 return s->enable; 2356 } 2357 OMAP_BAD_REG(addr); 2358 return 0; 2359 } 2360 2361 static void omap_pwl_write(void *opaque, hwaddr addr, 2362 uint64_t value, unsigned size) 2363 { 2364 struct omap_pwl_s *s = (struct omap_pwl_s *) opaque; 2365 int offset = addr & OMAP_MPUI_REG_MASK; 2366 2367 if (size != 1) { 2368 omap_badwidth_write8(opaque, addr, value); 2369 return; 2370 } 2371 2372 switch (offset) { 2373 case 0x00: /* PWL_LEVEL */ 2374 s->level = value; 2375 omap_pwl_update(s); 2376 break; 2377 case 0x04: /* PWL_CTRL */ 2378 s->enable = value & 1; 2379 omap_pwl_update(s); 2380 break; 2381 default: 2382 OMAP_BAD_REG(addr); 2383 return; 2384 } 2385 } 2386 2387 static const MemoryRegionOps omap_pwl_ops = { 2388 .read = omap_pwl_read, 2389 .write = omap_pwl_write, 2390 .endianness = DEVICE_NATIVE_ENDIAN, 2391 }; 2392 2393 static void omap_pwl_reset(struct omap_pwl_s *s) 2394 { 2395 s->output = 0; 2396 s->level = 0; 2397 s->enable = 0; 2398 s->clk = 1; 2399 omap_pwl_update(s); 2400 } 2401 2402 static void omap_pwl_clk_update(void *opaque, int line, int on) 2403 { 2404 struct omap_pwl_s *s = (struct omap_pwl_s *) opaque; 2405 2406 s->clk = on; 2407 omap_pwl_update(s); 2408 } 2409 2410 static struct omap_pwl_s *omap_pwl_init(MemoryRegion *system_memory, 2411 hwaddr base, 2412 omap_clk clk) 2413 { 2414 struct omap_pwl_s *s = g_malloc0(sizeof(*s)); 2415 2416 omap_pwl_reset(s); 2417 2418 memory_region_init_io(&s->iomem, NULL, &omap_pwl_ops, s, 2419 "omap-pwl", 0x800); 2420 memory_region_add_subregion(system_memory, base, &s->iomem); 2421 2422 omap_clk_adduser(clk, qemu_allocate_irq(omap_pwl_clk_update, s, 0)); 2423 return s; 2424 } 2425 2426 /* Pulse-Width Tone module */ 2427 struct omap_pwt_s { 2428 MemoryRegion iomem; 2429 uint8_t frc; 2430 uint8_t vrc; 2431 uint8_t gcr; 2432 omap_clk clk; 2433 }; 2434 2435 static uint64_t omap_pwt_read(void *opaque, hwaddr addr, 2436 unsigned size) 2437 { 2438 struct omap_pwt_s *s = (struct omap_pwt_s *) opaque; 2439 int offset = addr & OMAP_MPUI_REG_MASK; 2440 2441 if (size != 1) { 2442 return omap_badwidth_read8(opaque, addr); 2443 } 2444 2445 switch (offset) { 2446 case 0x00: /* FRC */ 2447 return s->frc; 2448 case 0x04: /* VCR */ 2449 return s->vrc; 2450 case 0x08: /* GCR */ 2451 return s->gcr; 2452 } 2453 OMAP_BAD_REG(addr); 2454 return 0; 2455 } 2456 2457 static void omap_pwt_write(void *opaque, hwaddr addr, 2458 uint64_t value, unsigned size) 2459 { 2460 struct omap_pwt_s *s = (struct omap_pwt_s *) opaque; 2461 int offset = addr & OMAP_MPUI_REG_MASK; 2462 2463 if (size != 1) { 2464 omap_badwidth_write8(opaque, addr, value); 2465 return; 2466 } 2467 2468 switch (offset) { 2469 case 0x00: /* FRC */ 2470 s->frc = value & 0x3f; 2471 break; 2472 case 0x04: /* VRC */ 2473 if ((value ^ s->vrc) & 1) { 2474 if (value & 1) 2475 printf("%s: %iHz buzz on\n", __FUNCTION__, (int) 2476 /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */ 2477 ((omap_clk_getrate(s->clk) >> 3) / 2478 /* Pre-multiplexer divider */ 2479 ((s->gcr & 2) ? 1 : 154) / 2480 /* Octave multiplexer */ 2481 (2 << (value & 3)) * 2482 /* 101/107 divider */ 2483 ((value & (1 << 2)) ? 101 : 107) * 2484 /* 49/55 divider */ 2485 ((value & (1 << 3)) ? 49 : 55) * 2486 /* 50/63 divider */ 2487 ((value & (1 << 4)) ? 50 : 63) * 2488 /* 80/127 divider */ 2489 ((value & (1 << 5)) ? 80 : 127) / 2490 (107 * 55 * 63 * 127))); 2491 else 2492 printf("%s: silence!\n", __FUNCTION__); 2493 } 2494 s->vrc = value & 0x7f; 2495 break; 2496 case 0x08: /* GCR */ 2497 s->gcr = value & 3; 2498 break; 2499 default: 2500 OMAP_BAD_REG(addr); 2501 return; 2502 } 2503 } 2504 2505 static const MemoryRegionOps omap_pwt_ops = { 2506 .read =omap_pwt_read, 2507 .write = omap_pwt_write, 2508 .endianness = DEVICE_NATIVE_ENDIAN, 2509 }; 2510 2511 static void omap_pwt_reset(struct omap_pwt_s *s) 2512 { 2513 s->frc = 0; 2514 s->vrc = 0; 2515 s->gcr = 0; 2516 } 2517 2518 static struct omap_pwt_s *omap_pwt_init(MemoryRegion *system_memory, 2519 hwaddr base, 2520 omap_clk clk) 2521 { 2522 struct omap_pwt_s *s = g_malloc0(sizeof(*s)); 2523 s->clk = clk; 2524 omap_pwt_reset(s); 2525 2526 memory_region_init_io(&s->iomem, NULL, &omap_pwt_ops, s, 2527 "omap-pwt", 0x800); 2528 memory_region_add_subregion(system_memory, base, &s->iomem); 2529 return s; 2530 } 2531 2532 /* Real-time Clock module */ 2533 struct omap_rtc_s { 2534 MemoryRegion iomem; 2535 qemu_irq irq; 2536 qemu_irq alarm; 2537 QEMUTimer *clk; 2538 2539 uint8_t interrupts; 2540 uint8_t status; 2541 int16_t comp_reg; 2542 int running; 2543 int pm_am; 2544 int auto_comp; 2545 int round; 2546 struct tm alarm_tm; 2547 time_t alarm_ti; 2548 2549 struct tm current_tm; 2550 time_t ti; 2551 uint64_t tick; 2552 }; 2553 2554 static void omap_rtc_interrupts_update(struct omap_rtc_s *s) 2555 { 2556 /* s->alarm is level-triggered */ 2557 qemu_set_irq(s->alarm, (s->status >> 6) & 1); 2558 } 2559 2560 static void omap_rtc_alarm_update(struct omap_rtc_s *s) 2561 { 2562 s->alarm_ti = mktimegm(&s->alarm_tm); 2563 if (s->alarm_ti == -1) 2564 printf("%s: conversion failed\n", __FUNCTION__); 2565 } 2566 2567 static uint64_t omap_rtc_read(void *opaque, hwaddr addr, 2568 unsigned size) 2569 { 2570 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; 2571 int offset = addr & OMAP_MPUI_REG_MASK; 2572 uint8_t i; 2573 2574 if (size != 1) { 2575 return omap_badwidth_read8(opaque, addr); 2576 } 2577 2578 switch (offset) { 2579 case 0x00: /* SECONDS_REG */ 2580 return to_bcd(s->current_tm.tm_sec); 2581 2582 case 0x04: /* MINUTES_REG */ 2583 return to_bcd(s->current_tm.tm_min); 2584 2585 case 0x08: /* HOURS_REG */ 2586 if (s->pm_am) 2587 return ((s->current_tm.tm_hour > 11) << 7) | 2588 to_bcd(((s->current_tm.tm_hour - 1) % 12) + 1); 2589 else 2590 return to_bcd(s->current_tm.tm_hour); 2591 2592 case 0x0c: /* DAYS_REG */ 2593 return to_bcd(s->current_tm.tm_mday); 2594 2595 case 0x10: /* MONTHS_REG */ 2596 return to_bcd(s->current_tm.tm_mon + 1); 2597 2598 case 0x14: /* YEARS_REG */ 2599 return to_bcd(s->current_tm.tm_year % 100); 2600 2601 case 0x18: /* WEEK_REG */ 2602 return s->current_tm.tm_wday; 2603 2604 case 0x20: /* ALARM_SECONDS_REG */ 2605 return to_bcd(s->alarm_tm.tm_sec); 2606 2607 case 0x24: /* ALARM_MINUTES_REG */ 2608 return to_bcd(s->alarm_tm.tm_min); 2609 2610 case 0x28: /* ALARM_HOURS_REG */ 2611 if (s->pm_am) 2612 return ((s->alarm_tm.tm_hour > 11) << 7) | 2613 to_bcd(((s->alarm_tm.tm_hour - 1) % 12) + 1); 2614 else 2615 return to_bcd(s->alarm_tm.tm_hour); 2616 2617 case 0x2c: /* ALARM_DAYS_REG */ 2618 return to_bcd(s->alarm_tm.tm_mday); 2619 2620 case 0x30: /* ALARM_MONTHS_REG */ 2621 return to_bcd(s->alarm_tm.tm_mon + 1); 2622 2623 case 0x34: /* ALARM_YEARS_REG */ 2624 return to_bcd(s->alarm_tm.tm_year % 100); 2625 2626 case 0x40: /* RTC_CTRL_REG */ 2627 return (s->pm_am << 3) | (s->auto_comp << 2) | 2628 (s->round << 1) | s->running; 2629 2630 case 0x44: /* RTC_STATUS_REG */ 2631 i = s->status; 2632 s->status &= ~0x3d; 2633 return i; 2634 2635 case 0x48: /* RTC_INTERRUPTS_REG */ 2636 return s->interrupts; 2637 2638 case 0x4c: /* RTC_COMP_LSB_REG */ 2639 return ((uint16_t) s->comp_reg) & 0xff; 2640 2641 case 0x50: /* RTC_COMP_MSB_REG */ 2642 return ((uint16_t) s->comp_reg) >> 8; 2643 } 2644 2645 OMAP_BAD_REG(addr); 2646 return 0; 2647 } 2648 2649 static void omap_rtc_write(void *opaque, hwaddr addr, 2650 uint64_t value, unsigned size) 2651 { 2652 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; 2653 int offset = addr & OMAP_MPUI_REG_MASK; 2654 struct tm new_tm; 2655 time_t ti[2]; 2656 2657 if (size != 1) { 2658 omap_badwidth_write8(opaque, addr, value); 2659 return; 2660 } 2661 2662 switch (offset) { 2663 case 0x00: /* SECONDS_REG */ 2664 #ifdef ALMDEBUG 2665 printf("RTC SEC_REG <-- %02x\n", value); 2666 #endif 2667 s->ti -= s->current_tm.tm_sec; 2668 s->ti += from_bcd(value); 2669 return; 2670 2671 case 0x04: /* MINUTES_REG */ 2672 #ifdef ALMDEBUG 2673 printf("RTC MIN_REG <-- %02x\n", value); 2674 #endif 2675 s->ti -= s->current_tm.tm_min * 60; 2676 s->ti += from_bcd(value) * 60; 2677 return; 2678 2679 case 0x08: /* HOURS_REG */ 2680 #ifdef ALMDEBUG 2681 printf("RTC HRS_REG <-- %02x\n", value); 2682 #endif 2683 s->ti -= s->current_tm.tm_hour * 3600; 2684 if (s->pm_am) { 2685 s->ti += (from_bcd(value & 0x3f) & 12) * 3600; 2686 s->ti += ((value >> 7) & 1) * 43200; 2687 } else 2688 s->ti += from_bcd(value & 0x3f) * 3600; 2689 return; 2690 2691 case 0x0c: /* DAYS_REG */ 2692 #ifdef ALMDEBUG 2693 printf("RTC DAY_REG <-- %02x\n", value); 2694 #endif 2695 s->ti -= s->current_tm.tm_mday * 86400; 2696 s->ti += from_bcd(value) * 86400; 2697 return; 2698 2699 case 0x10: /* MONTHS_REG */ 2700 #ifdef ALMDEBUG 2701 printf("RTC MTH_REG <-- %02x\n", value); 2702 #endif 2703 memcpy(&new_tm, &s->current_tm, sizeof(new_tm)); 2704 new_tm.tm_mon = from_bcd(value); 2705 ti[0] = mktimegm(&s->current_tm); 2706 ti[1] = mktimegm(&new_tm); 2707 2708 if (ti[0] != -1 && ti[1] != -1) { 2709 s->ti -= ti[0]; 2710 s->ti += ti[1]; 2711 } else { 2712 /* A less accurate version */ 2713 s->ti -= s->current_tm.tm_mon * 2592000; 2714 s->ti += from_bcd(value) * 2592000; 2715 } 2716 return; 2717 2718 case 0x14: /* YEARS_REG */ 2719 #ifdef ALMDEBUG 2720 printf("RTC YRS_REG <-- %02x\n", value); 2721 #endif 2722 memcpy(&new_tm, &s->current_tm, sizeof(new_tm)); 2723 new_tm.tm_year += from_bcd(value) - (new_tm.tm_year % 100); 2724 ti[0] = mktimegm(&s->current_tm); 2725 ti[1] = mktimegm(&new_tm); 2726 2727 if (ti[0] != -1 && ti[1] != -1) { 2728 s->ti -= ti[0]; 2729 s->ti += ti[1]; 2730 } else { 2731 /* A less accurate version */ 2732 s->ti -= (time_t)(s->current_tm.tm_year % 100) * 31536000; 2733 s->ti += (time_t)from_bcd(value) * 31536000; 2734 } 2735 return; 2736 2737 case 0x18: /* WEEK_REG */ 2738 return; /* Ignored */ 2739 2740 case 0x20: /* ALARM_SECONDS_REG */ 2741 #ifdef ALMDEBUG 2742 printf("ALM SEC_REG <-- %02x\n", value); 2743 #endif 2744 s->alarm_tm.tm_sec = from_bcd(value); 2745 omap_rtc_alarm_update(s); 2746 return; 2747 2748 case 0x24: /* ALARM_MINUTES_REG */ 2749 #ifdef ALMDEBUG 2750 printf("ALM MIN_REG <-- %02x\n", value); 2751 #endif 2752 s->alarm_tm.tm_min = from_bcd(value); 2753 omap_rtc_alarm_update(s); 2754 return; 2755 2756 case 0x28: /* ALARM_HOURS_REG */ 2757 #ifdef ALMDEBUG 2758 printf("ALM HRS_REG <-- %02x\n", value); 2759 #endif 2760 if (s->pm_am) 2761 s->alarm_tm.tm_hour = 2762 ((from_bcd(value & 0x3f)) % 12) + 2763 ((value >> 7) & 1) * 12; 2764 else 2765 s->alarm_tm.tm_hour = from_bcd(value); 2766 omap_rtc_alarm_update(s); 2767 return; 2768 2769 case 0x2c: /* ALARM_DAYS_REG */ 2770 #ifdef ALMDEBUG 2771 printf("ALM DAY_REG <-- %02x\n", value); 2772 #endif 2773 s->alarm_tm.tm_mday = from_bcd(value); 2774 omap_rtc_alarm_update(s); 2775 return; 2776 2777 case 0x30: /* ALARM_MONTHS_REG */ 2778 #ifdef ALMDEBUG 2779 printf("ALM MON_REG <-- %02x\n", value); 2780 #endif 2781 s->alarm_tm.tm_mon = from_bcd(value); 2782 omap_rtc_alarm_update(s); 2783 return; 2784 2785 case 0x34: /* ALARM_YEARS_REG */ 2786 #ifdef ALMDEBUG 2787 printf("ALM YRS_REG <-- %02x\n", value); 2788 #endif 2789 s->alarm_tm.tm_year = from_bcd(value); 2790 omap_rtc_alarm_update(s); 2791 return; 2792 2793 case 0x40: /* RTC_CTRL_REG */ 2794 #ifdef ALMDEBUG 2795 printf("RTC CONTROL <-- %02x\n", value); 2796 #endif 2797 s->pm_am = (value >> 3) & 1; 2798 s->auto_comp = (value >> 2) & 1; 2799 s->round = (value >> 1) & 1; 2800 s->running = value & 1; 2801 s->status &= 0xfd; 2802 s->status |= s->running << 1; 2803 return; 2804 2805 case 0x44: /* RTC_STATUS_REG */ 2806 #ifdef ALMDEBUG 2807 printf("RTC STATUSL <-- %02x\n", value); 2808 #endif 2809 s->status &= ~((value & 0xc0) ^ 0x80); 2810 omap_rtc_interrupts_update(s); 2811 return; 2812 2813 case 0x48: /* RTC_INTERRUPTS_REG */ 2814 #ifdef ALMDEBUG 2815 printf("RTC INTRS <-- %02x\n", value); 2816 #endif 2817 s->interrupts = value; 2818 return; 2819 2820 case 0x4c: /* RTC_COMP_LSB_REG */ 2821 #ifdef ALMDEBUG 2822 printf("RTC COMPLSB <-- %02x\n", value); 2823 #endif 2824 s->comp_reg &= 0xff00; 2825 s->comp_reg |= 0x00ff & value; 2826 return; 2827 2828 case 0x50: /* RTC_COMP_MSB_REG */ 2829 #ifdef ALMDEBUG 2830 printf("RTC COMPMSB <-- %02x\n", value); 2831 #endif 2832 s->comp_reg &= 0x00ff; 2833 s->comp_reg |= 0xff00 & (value << 8); 2834 return; 2835 2836 default: 2837 OMAP_BAD_REG(addr); 2838 return; 2839 } 2840 } 2841 2842 static const MemoryRegionOps omap_rtc_ops = { 2843 .read = omap_rtc_read, 2844 .write = omap_rtc_write, 2845 .endianness = DEVICE_NATIVE_ENDIAN, 2846 }; 2847 2848 static void omap_rtc_tick(void *opaque) 2849 { 2850 struct omap_rtc_s *s = opaque; 2851 2852 if (s->round) { 2853 /* Round to nearest full minute. */ 2854 if (s->current_tm.tm_sec < 30) 2855 s->ti -= s->current_tm.tm_sec; 2856 else 2857 s->ti += 60 - s->current_tm.tm_sec; 2858 2859 s->round = 0; 2860 } 2861 2862 localtime_r(&s->ti, &s->current_tm); 2863 2864 if ((s->interrupts & 0x08) && s->ti == s->alarm_ti) { 2865 s->status |= 0x40; 2866 omap_rtc_interrupts_update(s); 2867 } 2868 2869 if (s->interrupts & 0x04) 2870 switch (s->interrupts & 3) { 2871 case 0: 2872 s->status |= 0x04; 2873 qemu_irq_pulse(s->irq); 2874 break; 2875 case 1: 2876 if (s->current_tm.tm_sec) 2877 break; 2878 s->status |= 0x08; 2879 qemu_irq_pulse(s->irq); 2880 break; 2881 case 2: 2882 if (s->current_tm.tm_sec || s->current_tm.tm_min) 2883 break; 2884 s->status |= 0x10; 2885 qemu_irq_pulse(s->irq); 2886 break; 2887 case 3: 2888 if (s->current_tm.tm_sec || 2889 s->current_tm.tm_min || s->current_tm.tm_hour) 2890 break; 2891 s->status |= 0x20; 2892 qemu_irq_pulse(s->irq); 2893 break; 2894 } 2895 2896 /* Move on */ 2897 if (s->running) 2898 s->ti ++; 2899 s->tick += 1000; 2900 2901 /* 2902 * Every full hour add a rough approximation of the compensation 2903 * register to the 32kHz Timer (which drives the RTC) value. 2904 */ 2905 if (s->auto_comp && !s->current_tm.tm_sec && !s->current_tm.tm_min) 2906 s->tick += s->comp_reg * 1000 / 32768; 2907 2908 timer_mod(s->clk, s->tick); 2909 } 2910 2911 static void omap_rtc_reset(struct omap_rtc_s *s) 2912 { 2913 struct tm tm; 2914 2915 s->interrupts = 0; 2916 s->comp_reg = 0; 2917 s->running = 0; 2918 s->pm_am = 0; 2919 s->auto_comp = 0; 2920 s->round = 0; 2921 s->tick = qemu_clock_get_ms(rtc_clock); 2922 memset(&s->alarm_tm, 0, sizeof(s->alarm_tm)); 2923 s->alarm_tm.tm_mday = 0x01; 2924 s->status = 1 << 7; 2925 qemu_get_timedate(&tm, 0); 2926 s->ti = mktimegm(&tm); 2927 2928 omap_rtc_alarm_update(s); 2929 omap_rtc_tick(s); 2930 } 2931 2932 static struct omap_rtc_s *omap_rtc_init(MemoryRegion *system_memory, 2933 hwaddr base, 2934 qemu_irq timerirq, qemu_irq alarmirq, 2935 omap_clk clk) 2936 { 2937 struct omap_rtc_s *s = (struct omap_rtc_s *) 2938 g_malloc0(sizeof(struct omap_rtc_s)); 2939 2940 s->irq = timerirq; 2941 s->alarm = alarmirq; 2942 s->clk = timer_new_ms(rtc_clock, omap_rtc_tick, s); 2943 2944 omap_rtc_reset(s); 2945 2946 memory_region_init_io(&s->iomem, NULL, &omap_rtc_ops, s, 2947 "omap-rtc", 0x800); 2948 memory_region_add_subregion(system_memory, base, &s->iomem); 2949 2950 return s; 2951 } 2952 2953 /* Multi-channel Buffered Serial Port interfaces */ 2954 struct omap_mcbsp_s { 2955 MemoryRegion iomem; 2956 qemu_irq txirq; 2957 qemu_irq rxirq; 2958 qemu_irq txdrq; 2959 qemu_irq rxdrq; 2960 2961 uint16_t spcr[2]; 2962 uint16_t rcr[2]; 2963 uint16_t xcr[2]; 2964 uint16_t srgr[2]; 2965 uint16_t mcr[2]; 2966 uint16_t pcr; 2967 uint16_t rcer[8]; 2968 uint16_t xcer[8]; 2969 int tx_rate; 2970 int rx_rate; 2971 int tx_req; 2972 int rx_req; 2973 2974 I2SCodec *codec; 2975 QEMUTimer *source_timer; 2976 QEMUTimer *sink_timer; 2977 }; 2978 2979 static void omap_mcbsp_intr_update(struct omap_mcbsp_s *s) 2980 { 2981 int irq; 2982 2983 switch ((s->spcr[0] >> 4) & 3) { /* RINTM */ 2984 case 0: 2985 irq = (s->spcr[0] >> 1) & 1; /* RRDY */ 2986 break; 2987 case 3: 2988 irq = (s->spcr[0] >> 3) & 1; /* RSYNCERR */ 2989 break; 2990 default: 2991 irq = 0; 2992 break; 2993 } 2994 2995 if (irq) 2996 qemu_irq_pulse(s->rxirq); 2997 2998 switch ((s->spcr[1] >> 4) & 3) { /* XINTM */ 2999 case 0: 3000 irq = (s->spcr[1] >> 1) & 1; /* XRDY */ 3001 break; 3002 case 3: 3003 irq = (s->spcr[1] >> 3) & 1; /* XSYNCERR */ 3004 break; 3005 default: 3006 irq = 0; 3007 break; 3008 } 3009 3010 if (irq) 3011 qemu_irq_pulse(s->txirq); 3012 } 3013 3014 static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s) 3015 { 3016 if ((s->spcr[0] >> 1) & 1) /* RRDY */ 3017 s->spcr[0] |= 1 << 2; /* RFULL */ 3018 s->spcr[0] |= 1 << 1; /* RRDY */ 3019 qemu_irq_raise(s->rxdrq); 3020 omap_mcbsp_intr_update(s); 3021 } 3022 3023 static void omap_mcbsp_source_tick(void *opaque) 3024 { 3025 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3026 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 }; 3027 3028 if (!s->rx_rate) 3029 return; 3030 if (s->rx_req) 3031 printf("%s: Rx FIFO overrun\n", __FUNCTION__); 3032 3033 s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7]; 3034 3035 omap_mcbsp_rx_newdata(s); 3036 timer_mod(s->source_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 3037 get_ticks_per_sec()); 3038 } 3039 3040 static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s) 3041 { 3042 if (!s->codec || !s->codec->rts) 3043 omap_mcbsp_source_tick(s); 3044 else if (s->codec->in.len) { 3045 s->rx_req = s->codec->in.len; 3046 omap_mcbsp_rx_newdata(s); 3047 } 3048 } 3049 3050 static void omap_mcbsp_rx_stop(struct omap_mcbsp_s *s) 3051 { 3052 timer_del(s->source_timer); 3053 } 3054 3055 static void omap_mcbsp_rx_done(struct omap_mcbsp_s *s) 3056 { 3057 s->spcr[0] &= ~(1 << 1); /* RRDY */ 3058 qemu_irq_lower(s->rxdrq); 3059 omap_mcbsp_intr_update(s); 3060 } 3061 3062 static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s) 3063 { 3064 s->spcr[1] |= 1 << 1; /* XRDY */ 3065 qemu_irq_raise(s->txdrq); 3066 omap_mcbsp_intr_update(s); 3067 } 3068 3069 static void omap_mcbsp_sink_tick(void *opaque) 3070 { 3071 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3072 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 }; 3073 3074 if (!s->tx_rate) 3075 return; 3076 if (s->tx_req) 3077 printf("%s: Tx FIFO underrun\n", __FUNCTION__); 3078 3079 s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7]; 3080 3081 omap_mcbsp_tx_newdata(s); 3082 timer_mod(s->sink_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 3083 get_ticks_per_sec()); 3084 } 3085 3086 static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s) 3087 { 3088 if (!s->codec || !s->codec->cts) 3089 omap_mcbsp_sink_tick(s); 3090 else if (s->codec->out.size) { 3091 s->tx_req = s->codec->out.size; 3092 omap_mcbsp_tx_newdata(s); 3093 } 3094 } 3095 3096 static void omap_mcbsp_tx_done(struct omap_mcbsp_s *s) 3097 { 3098 s->spcr[1] &= ~(1 << 1); /* XRDY */ 3099 qemu_irq_lower(s->txdrq); 3100 omap_mcbsp_intr_update(s); 3101 if (s->codec && s->codec->cts) 3102 s->codec->tx_swallow(s->codec->opaque); 3103 } 3104 3105 static void omap_mcbsp_tx_stop(struct omap_mcbsp_s *s) 3106 { 3107 s->tx_req = 0; 3108 omap_mcbsp_tx_done(s); 3109 timer_del(s->sink_timer); 3110 } 3111 3112 static void omap_mcbsp_req_update(struct omap_mcbsp_s *s) 3113 { 3114 int prev_rx_rate, prev_tx_rate; 3115 int rx_rate = 0, tx_rate = 0; 3116 int cpu_rate = 1500000; /* XXX */ 3117 3118 /* TODO: check CLKSTP bit */ 3119 if (s->spcr[1] & (1 << 6)) { /* GRST */ 3120 if (s->spcr[0] & (1 << 0)) { /* RRST */ 3121 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ 3122 (s->pcr & (1 << 8))) { /* CLKRM */ 3123 if (~s->pcr & (1 << 7)) /* SCLKME */ 3124 rx_rate = cpu_rate / 3125 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ 3126 } else 3127 if (s->codec) 3128 rx_rate = s->codec->rx_rate; 3129 } 3130 3131 if (s->spcr[1] & (1 << 0)) { /* XRST */ 3132 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ 3133 (s->pcr & (1 << 9))) { /* CLKXM */ 3134 if (~s->pcr & (1 << 7)) /* SCLKME */ 3135 tx_rate = cpu_rate / 3136 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ 3137 } else 3138 if (s->codec) 3139 tx_rate = s->codec->tx_rate; 3140 } 3141 } 3142 prev_tx_rate = s->tx_rate; 3143 prev_rx_rate = s->rx_rate; 3144 s->tx_rate = tx_rate; 3145 s->rx_rate = rx_rate; 3146 3147 if (s->codec) 3148 s->codec->set_rate(s->codec->opaque, rx_rate, tx_rate); 3149 3150 if (!prev_tx_rate && tx_rate) 3151 omap_mcbsp_tx_start(s); 3152 else if (s->tx_rate && !tx_rate) 3153 omap_mcbsp_tx_stop(s); 3154 3155 if (!prev_rx_rate && rx_rate) 3156 omap_mcbsp_rx_start(s); 3157 else if (prev_tx_rate && !tx_rate) 3158 omap_mcbsp_rx_stop(s); 3159 } 3160 3161 static uint64_t omap_mcbsp_read(void *opaque, hwaddr addr, 3162 unsigned size) 3163 { 3164 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3165 int offset = addr & OMAP_MPUI_REG_MASK; 3166 uint16_t ret; 3167 3168 if (size != 2) { 3169 return omap_badwidth_read16(opaque, addr); 3170 } 3171 3172 switch (offset) { 3173 case 0x00: /* DRR2 */ 3174 if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */ 3175 return 0x0000; 3176 /* Fall through. */ 3177 case 0x02: /* DRR1 */ 3178 if (s->rx_req < 2) { 3179 printf("%s: Rx FIFO underrun\n", __FUNCTION__); 3180 omap_mcbsp_rx_done(s); 3181 } else { 3182 s->tx_req -= 2; 3183 if (s->codec && s->codec->in.len >= 2) { 3184 ret = s->codec->in.fifo[s->codec->in.start ++] << 8; 3185 ret |= s->codec->in.fifo[s->codec->in.start ++]; 3186 s->codec->in.len -= 2; 3187 } else 3188 ret = 0x0000; 3189 if (!s->tx_req) 3190 omap_mcbsp_rx_done(s); 3191 return ret; 3192 } 3193 return 0x0000; 3194 3195 case 0x04: /* DXR2 */ 3196 case 0x06: /* DXR1 */ 3197 return 0x0000; 3198 3199 case 0x08: /* SPCR2 */ 3200 return s->spcr[1]; 3201 case 0x0a: /* SPCR1 */ 3202 return s->spcr[0]; 3203 case 0x0c: /* RCR2 */ 3204 return s->rcr[1]; 3205 case 0x0e: /* RCR1 */ 3206 return s->rcr[0]; 3207 case 0x10: /* XCR2 */ 3208 return s->xcr[1]; 3209 case 0x12: /* XCR1 */ 3210 return s->xcr[0]; 3211 case 0x14: /* SRGR2 */ 3212 return s->srgr[1]; 3213 case 0x16: /* SRGR1 */ 3214 return s->srgr[0]; 3215 case 0x18: /* MCR2 */ 3216 return s->mcr[1]; 3217 case 0x1a: /* MCR1 */ 3218 return s->mcr[0]; 3219 case 0x1c: /* RCERA */ 3220 return s->rcer[0]; 3221 case 0x1e: /* RCERB */ 3222 return s->rcer[1]; 3223 case 0x20: /* XCERA */ 3224 return s->xcer[0]; 3225 case 0x22: /* XCERB */ 3226 return s->xcer[1]; 3227 case 0x24: /* PCR0 */ 3228 return s->pcr; 3229 case 0x26: /* RCERC */ 3230 return s->rcer[2]; 3231 case 0x28: /* RCERD */ 3232 return s->rcer[3]; 3233 case 0x2a: /* XCERC */ 3234 return s->xcer[2]; 3235 case 0x2c: /* XCERD */ 3236 return s->xcer[3]; 3237 case 0x2e: /* RCERE */ 3238 return s->rcer[4]; 3239 case 0x30: /* RCERF */ 3240 return s->rcer[5]; 3241 case 0x32: /* XCERE */ 3242 return s->xcer[4]; 3243 case 0x34: /* XCERF */ 3244 return s->xcer[5]; 3245 case 0x36: /* RCERG */ 3246 return s->rcer[6]; 3247 case 0x38: /* RCERH */ 3248 return s->rcer[7]; 3249 case 0x3a: /* XCERG */ 3250 return s->xcer[6]; 3251 case 0x3c: /* XCERH */ 3252 return s->xcer[7]; 3253 } 3254 3255 OMAP_BAD_REG(addr); 3256 return 0; 3257 } 3258 3259 static void omap_mcbsp_writeh(void *opaque, hwaddr addr, 3260 uint32_t value) 3261 { 3262 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3263 int offset = addr & OMAP_MPUI_REG_MASK; 3264 3265 switch (offset) { 3266 case 0x00: /* DRR2 */ 3267 case 0x02: /* DRR1 */ 3268 OMAP_RO_REG(addr); 3269 return; 3270 3271 case 0x04: /* DXR2 */ 3272 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ 3273 return; 3274 /* Fall through. */ 3275 case 0x06: /* DXR1 */ 3276 if (s->tx_req > 1) { 3277 s->tx_req -= 2; 3278 if (s->codec && s->codec->cts) { 3279 s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff; 3280 s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff; 3281 } 3282 if (s->tx_req < 2) 3283 omap_mcbsp_tx_done(s); 3284 } else 3285 printf("%s: Tx FIFO overrun\n", __FUNCTION__); 3286 return; 3287 3288 case 0x08: /* SPCR2 */ 3289 s->spcr[1] &= 0x0002; 3290 s->spcr[1] |= 0x03f9 & value; 3291 s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */ 3292 if (~value & 1) /* XRST */ 3293 s->spcr[1] &= ~6; 3294 omap_mcbsp_req_update(s); 3295 return; 3296 case 0x0a: /* SPCR1 */ 3297 s->spcr[0] &= 0x0006; 3298 s->spcr[0] |= 0xf8f9 & value; 3299 if (value & (1 << 15)) /* DLB */ 3300 printf("%s: Digital Loopback mode enable attempt\n", __FUNCTION__); 3301 if (~value & 1) { /* RRST */ 3302 s->spcr[0] &= ~6; 3303 s->rx_req = 0; 3304 omap_mcbsp_rx_done(s); 3305 } 3306 omap_mcbsp_req_update(s); 3307 return; 3308 3309 case 0x0c: /* RCR2 */ 3310 s->rcr[1] = value & 0xffff; 3311 return; 3312 case 0x0e: /* RCR1 */ 3313 s->rcr[0] = value & 0x7fe0; 3314 return; 3315 case 0x10: /* XCR2 */ 3316 s->xcr[1] = value & 0xffff; 3317 return; 3318 case 0x12: /* XCR1 */ 3319 s->xcr[0] = value & 0x7fe0; 3320 return; 3321 case 0x14: /* SRGR2 */ 3322 s->srgr[1] = value & 0xffff; 3323 omap_mcbsp_req_update(s); 3324 return; 3325 case 0x16: /* SRGR1 */ 3326 s->srgr[0] = value & 0xffff; 3327 omap_mcbsp_req_update(s); 3328 return; 3329 case 0x18: /* MCR2 */ 3330 s->mcr[1] = value & 0x03e3; 3331 if (value & 3) /* XMCM */ 3332 printf("%s: Tx channel selection mode enable attempt\n", 3333 __FUNCTION__); 3334 return; 3335 case 0x1a: /* MCR1 */ 3336 s->mcr[0] = value & 0x03e1; 3337 if (value & 1) /* RMCM */ 3338 printf("%s: Rx channel selection mode enable attempt\n", 3339 __FUNCTION__); 3340 return; 3341 case 0x1c: /* RCERA */ 3342 s->rcer[0] = value & 0xffff; 3343 return; 3344 case 0x1e: /* RCERB */ 3345 s->rcer[1] = value & 0xffff; 3346 return; 3347 case 0x20: /* XCERA */ 3348 s->xcer[0] = value & 0xffff; 3349 return; 3350 case 0x22: /* XCERB */ 3351 s->xcer[1] = value & 0xffff; 3352 return; 3353 case 0x24: /* PCR0 */ 3354 s->pcr = value & 0x7faf; 3355 return; 3356 case 0x26: /* RCERC */ 3357 s->rcer[2] = value & 0xffff; 3358 return; 3359 case 0x28: /* RCERD */ 3360 s->rcer[3] = value & 0xffff; 3361 return; 3362 case 0x2a: /* XCERC */ 3363 s->xcer[2] = value & 0xffff; 3364 return; 3365 case 0x2c: /* XCERD */ 3366 s->xcer[3] = value & 0xffff; 3367 return; 3368 case 0x2e: /* RCERE */ 3369 s->rcer[4] = value & 0xffff; 3370 return; 3371 case 0x30: /* RCERF */ 3372 s->rcer[5] = value & 0xffff; 3373 return; 3374 case 0x32: /* XCERE */ 3375 s->xcer[4] = value & 0xffff; 3376 return; 3377 case 0x34: /* XCERF */ 3378 s->xcer[5] = value & 0xffff; 3379 return; 3380 case 0x36: /* RCERG */ 3381 s->rcer[6] = value & 0xffff; 3382 return; 3383 case 0x38: /* RCERH */ 3384 s->rcer[7] = value & 0xffff; 3385 return; 3386 case 0x3a: /* XCERG */ 3387 s->xcer[6] = value & 0xffff; 3388 return; 3389 case 0x3c: /* XCERH */ 3390 s->xcer[7] = value & 0xffff; 3391 return; 3392 } 3393 3394 OMAP_BAD_REG(addr); 3395 } 3396 3397 static void omap_mcbsp_writew(void *opaque, hwaddr addr, 3398 uint32_t value) 3399 { 3400 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3401 int offset = addr & OMAP_MPUI_REG_MASK; 3402 3403 if (offset == 0x04) { /* DXR */ 3404 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ 3405 return; 3406 if (s->tx_req > 3) { 3407 s->tx_req -= 4; 3408 if (s->codec && s->codec->cts) { 3409 s->codec->out.fifo[s->codec->out.len ++] = 3410 (value >> 24) & 0xff; 3411 s->codec->out.fifo[s->codec->out.len ++] = 3412 (value >> 16) & 0xff; 3413 s->codec->out.fifo[s->codec->out.len ++] = 3414 (value >> 8) & 0xff; 3415 s->codec->out.fifo[s->codec->out.len ++] = 3416 (value >> 0) & 0xff; 3417 } 3418 if (s->tx_req < 4) 3419 omap_mcbsp_tx_done(s); 3420 } else 3421 printf("%s: Tx FIFO overrun\n", __FUNCTION__); 3422 return; 3423 } 3424 3425 omap_badwidth_write16(opaque, addr, value); 3426 } 3427 3428 static void omap_mcbsp_write(void *opaque, hwaddr addr, 3429 uint64_t value, unsigned size) 3430 { 3431 switch (size) { 3432 case 2: 3433 omap_mcbsp_writeh(opaque, addr, value); 3434 break; 3435 case 4: 3436 omap_mcbsp_writew(opaque, addr, value); 3437 break; 3438 default: 3439 omap_badwidth_write16(opaque, addr, value); 3440 } 3441 } 3442 3443 static const MemoryRegionOps omap_mcbsp_ops = { 3444 .read = omap_mcbsp_read, 3445 .write = omap_mcbsp_write, 3446 .endianness = DEVICE_NATIVE_ENDIAN, 3447 }; 3448 3449 static void omap_mcbsp_reset(struct omap_mcbsp_s *s) 3450 { 3451 memset(&s->spcr, 0, sizeof(s->spcr)); 3452 memset(&s->rcr, 0, sizeof(s->rcr)); 3453 memset(&s->xcr, 0, sizeof(s->xcr)); 3454 s->srgr[0] = 0x0001; 3455 s->srgr[1] = 0x2000; 3456 memset(&s->mcr, 0, sizeof(s->mcr)); 3457 memset(&s->pcr, 0, sizeof(s->pcr)); 3458 memset(&s->rcer, 0, sizeof(s->rcer)); 3459 memset(&s->xcer, 0, sizeof(s->xcer)); 3460 s->tx_req = 0; 3461 s->rx_req = 0; 3462 s->tx_rate = 0; 3463 s->rx_rate = 0; 3464 timer_del(s->source_timer); 3465 timer_del(s->sink_timer); 3466 } 3467 3468 static struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory, 3469 hwaddr base, 3470 qemu_irq txirq, qemu_irq rxirq, 3471 qemu_irq *dma, omap_clk clk) 3472 { 3473 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) 3474 g_malloc0(sizeof(struct omap_mcbsp_s)); 3475 3476 s->txirq = txirq; 3477 s->rxirq = rxirq; 3478 s->txdrq = dma[0]; 3479 s->rxdrq = dma[1]; 3480 s->sink_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_mcbsp_sink_tick, s); 3481 s->source_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_mcbsp_source_tick, s); 3482 omap_mcbsp_reset(s); 3483 3484 memory_region_init_io(&s->iomem, NULL, &omap_mcbsp_ops, s, "omap-mcbsp", 0x800); 3485 memory_region_add_subregion(system_memory, base, &s->iomem); 3486 3487 return s; 3488 } 3489 3490 static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level) 3491 { 3492 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3493 3494 if (s->rx_rate) { 3495 s->rx_req = s->codec->in.len; 3496 omap_mcbsp_rx_newdata(s); 3497 } 3498 } 3499 3500 static void omap_mcbsp_i2s_start(void *opaque, int line, int level) 3501 { 3502 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3503 3504 if (s->tx_rate) { 3505 s->tx_req = s->codec->out.size; 3506 omap_mcbsp_tx_newdata(s); 3507 } 3508 } 3509 3510 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave) 3511 { 3512 s->codec = slave; 3513 slave->rx_swallow = qemu_allocate_irq(omap_mcbsp_i2s_swallow, s, 0); 3514 slave->tx_start = qemu_allocate_irq(omap_mcbsp_i2s_start, s, 0); 3515 } 3516 3517 /* LED Pulse Generators */ 3518 struct omap_lpg_s { 3519 MemoryRegion iomem; 3520 QEMUTimer *tm; 3521 3522 uint8_t control; 3523 uint8_t power; 3524 int64_t on; 3525 int64_t period; 3526 int clk; 3527 int cycle; 3528 }; 3529 3530 static void omap_lpg_tick(void *opaque) 3531 { 3532 struct omap_lpg_s *s = opaque; 3533 3534 if (s->cycle) 3535 timer_mod(s->tm, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->period - s->on); 3536 else 3537 timer_mod(s->tm, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->on); 3538 3539 s->cycle = !s->cycle; 3540 printf("%s: LED is %s\n", __FUNCTION__, s->cycle ? "on" : "off"); 3541 } 3542 3543 static void omap_lpg_update(struct omap_lpg_s *s) 3544 { 3545 int64_t on, period = 1, ticks = 1000; 3546 static const int per[8] = { 1, 2, 4, 8, 12, 16, 20, 24 }; 3547 3548 if (~s->control & (1 << 6)) /* LPGRES */ 3549 on = 0; 3550 else if (s->control & (1 << 7)) /* PERM_ON */ 3551 on = period; 3552 else { 3553 period = muldiv64(ticks, per[s->control & 7], /* PERCTRL */ 3554 256 / 32); 3555 on = (s->clk && s->power) ? muldiv64(ticks, 3556 per[(s->control >> 3) & 7], 256) : 0; /* ONCTRL */ 3557 } 3558 3559 timer_del(s->tm); 3560 if (on == period && s->on < s->period) 3561 printf("%s: LED is on\n", __FUNCTION__); 3562 else if (on == 0 && s->on) 3563 printf("%s: LED is off\n", __FUNCTION__); 3564 else if (on && (on != s->on || period != s->period)) { 3565 s->cycle = 0; 3566 s->on = on; 3567 s->period = period; 3568 omap_lpg_tick(s); 3569 return; 3570 } 3571 3572 s->on = on; 3573 s->period = period; 3574 } 3575 3576 static void omap_lpg_reset(struct omap_lpg_s *s) 3577 { 3578 s->control = 0x00; 3579 s->power = 0x00; 3580 s->clk = 1; 3581 omap_lpg_update(s); 3582 } 3583 3584 static uint64_t omap_lpg_read(void *opaque, hwaddr addr, 3585 unsigned size) 3586 { 3587 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; 3588 int offset = addr & OMAP_MPUI_REG_MASK; 3589 3590 if (size != 1) { 3591 return omap_badwidth_read8(opaque, addr); 3592 } 3593 3594 switch (offset) { 3595 case 0x00: /* LCR */ 3596 return s->control; 3597 3598 case 0x04: /* PMR */ 3599 return s->power; 3600 } 3601 3602 OMAP_BAD_REG(addr); 3603 return 0; 3604 } 3605 3606 static void omap_lpg_write(void *opaque, hwaddr addr, 3607 uint64_t value, unsigned size) 3608 { 3609 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; 3610 int offset = addr & OMAP_MPUI_REG_MASK; 3611 3612 if (size != 1) { 3613 omap_badwidth_write8(opaque, addr, value); 3614 return; 3615 } 3616 3617 switch (offset) { 3618 case 0x00: /* LCR */ 3619 if (~value & (1 << 6)) /* LPGRES */ 3620 omap_lpg_reset(s); 3621 s->control = value & 0xff; 3622 omap_lpg_update(s); 3623 return; 3624 3625 case 0x04: /* PMR */ 3626 s->power = value & 0x01; 3627 omap_lpg_update(s); 3628 return; 3629 3630 default: 3631 OMAP_BAD_REG(addr); 3632 return; 3633 } 3634 } 3635 3636 static const MemoryRegionOps omap_lpg_ops = { 3637 .read = omap_lpg_read, 3638 .write = omap_lpg_write, 3639 .endianness = DEVICE_NATIVE_ENDIAN, 3640 }; 3641 3642 static void omap_lpg_clk_update(void *opaque, int line, int on) 3643 { 3644 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; 3645 3646 s->clk = on; 3647 omap_lpg_update(s); 3648 } 3649 3650 static struct omap_lpg_s *omap_lpg_init(MemoryRegion *system_memory, 3651 hwaddr base, omap_clk clk) 3652 { 3653 struct omap_lpg_s *s = (struct omap_lpg_s *) 3654 g_malloc0(sizeof(struct omap_lpg_s)); 3655 3656 s->tm = timer_new_ms(QEMU_CLOCK_VIRTUAL, omap_lpg_tick, s); 3657 3658 omap_lpg_reset(s); 3659 3660 memory_region_init_io(&s->iomem, NULL, &omap_lpg_ops, s, "omap-lpg", 0x800); 3661 memory_region_add_subregion(system_memory, base, &s->iomem); 3662 3663 omap_clk_adduser(clk, qemu_allocate_irq(omap_lpg_clk_update, s, 0)); 3664 3665 return s; 3666 } 3667 3668 /* MPUI Peripheral Bridge configuration */ 3669 static uint64_t omap_mpui_io_read(void *opaque, hwaddr addr, 3670 unsigned size) 3671 { 3672 if (size != 2) { 3673 return omap_badwidth_read16(opaque, addr); 3674 } 3675 3676 if (addr == OMAP_MPUI_BASE) /* CMR */ 3677 return 0xfe4d; 3678 3679 OMAP_BAD_REG(addr); 3680 return 0; 3681 } 3682 3683 static void omap_mpui_io_write(void *opaque, hwaddr addr, 3684 uint64_t value, unsigned size) 3685 { 3686 /* FIXME: infinite loop */ 3687 omap_badwidth_write16(opaque, addr, value); 3688 } 3689 3690 static const MemoryRegionOps omap_mpui_io_ops = { 3691 .read = omap_mpui_io_read, 3692 .write = omap_mpui_io_write, 3693 .endianness = DEVICE_NATIVE_ENDIAN, 3694 }; 3695 3696 static void omap_setup_mpui_io(MemoryRegion *system_memory, 3697 struct omap_mpu_state_s *mpu) 3698 { 3699 memory_region_init_io(&mpu->mpui_io_iomem, NULL, &omap_mpui_io_ops, mpu, 3700 "omap-mpui-io", 0x7fff); 3701 memory_region_add_subregion(system_memory, OMAP_MPUI_BASE, 3702 &mpu->mpui_io_iomem); 3703 } 3704 3705 /* General chip reset */ 3706 static void omap1_mpu_reset(void *opaque) 3707 { 3708 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; 3709 3710 omap_dma_reset(mpu->dma); 3711 omap_mpu_timer_reset(mpu->timer[0]); 3712 omap_mpu_timer_reset(mpu->timer[1]); 3713 omap_mpu_timer_reset(mpu->timer[2]); 3714 omap_wd_timer_reset(mpu->wdt); 3715 omap_os_timer_reset(mpu->os_timer); 3716 omap_lcdc_reset(mpu->lcd); 3717 omap_ulpd_pm_reset(mpu); 3718 omap_pin_cfg_reset(mpu); 3719 omap_mpui_reset(mpu); 3720 omap_tipb_bridge_reset(mpu->private_tipb); 3721 omap_tipb_bridge_reset(mpu->public_tipb); 3722 omap_dpll_reset(mpu->dpll[0]); 3723 omap_dpll_reset(mpu->dpll[1]); 3724 omap_dpll_reset(mpu->dpll[2]); 3725 omap_uart_reset(mpu->uart[0]); 3726 omap_uart_reset(mpu->uart[1]); 3727 omap_uart_reset(mpu->uart[2]); 3728 omap_mmc_reset(mpu->mmc); 3729 omap_mpuio_reset(mpu->mpuio); 3730 omap_uwire_reset(mpu->microwire); 3731 omap_pwl_reset(mpu->pwl); 3732 omap_pwt_reset(mpu->pwt); 3733 omap_rtc_reset(mpu->rtc); 3734 omap_mcbsp_reset(mpu->mcbsp1); 3735 omap_mcbsp_reset(mpu->mcbsp2); 3736 omap_mcbsp_reset(mpu->mcbsp3); 3737 omap_lpg_reset(mpu->led[0]); 3738 omap_lpg_reset(mpu->led[1]); 3739 omap_clkm_reset(mpu); 3740 cpu_reset(CPU(mpu->cpu)); 3741 } 3742 3743 static const struct omap_map_s { 3744 hwaddr phys_dsp; 3745 hwaddr phys_mpu; 3746 uint32_t size; 3747 const char *name; 3748 } omap15xx_dsp_mm[] = { 3749 /* Strobe 0 */ 3750 { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */ 3751 { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */ 3752 { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */ 3753 { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */ 3754 { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */ 3755 { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */ 3756 { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */ 3757 { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */ 3758 { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */ 3759 { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */ 3760 { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */ 3761 { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */ 3762 { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */ 3763 { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */ 3764 { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */ 3765 { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */ 3766 { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */ 3767 /* Strobe 1 */ 3768 { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */ 3769 3770 { 0 } 3771 }; 3772 3773 static void omap_setup_dsp_mapping(MemoryRegion *system_memory, 3774 const struct omap_map_s *map) 3775 { 3776 MemoryRegion *io; 3777 3778 for (; map->phys_dsp; map ++) { 3779 io = g_new(MemoryRegion, 1); 3780 memory_region_init_alias(io, NULL, map->name, 3781 system_memory, map->phys_mpu, map->size); 3782 memory_region_add_subregion(system_memory, map->phys_dsp, io); 3783 } 3784 } 3785 3786 void omap_mpu_wakeup(void *opaque, int irq, int req) 3787 { 3788 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; 3789 CPUState *cpu = CPU(mpu->cpu); 3790 3791 if (cpu->halted) { 3792 cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB); 3793 } 3794 } 3795 3796 static const struct dma_irq_map omap1_dma_irq_map[] = { 3797 { 0, OMAP_INT_DMA_CH0_6 }, 3798 { 0, OMAP_INT_DMA_CH1_7 }, 3799 { 0, OMAP_INT_DMA_CH2_8 }, 3800 { 0, OMAP_INT_DMA_CH3 }, 3801 { 0, OMAP_INT_DMA_CH4 }, 3802 { 0, OMAP_INT_DMA_CH5 }, 3803 { 1, OMAP_INT_1610_DMA_CH6 }, 3804 { 1, OMAP_INT_1610_DMA_CH7 }, 3805 { 1, OMAP_INT_1610_DMA_CH8 }, 3806 { 1, OMAP_INT_1610_DMA_CH9 }, 3807 { 1, OMAP_INT_1610_DMA_CH10 }, 3808 { 1, OMAP_INT_1610_DMA_CH11 }, 3809 { 1, OMAP_INT_1610_DMA_CH12 }, 3810 { 1, OMAP_INT_1610_DMA_CH13 }, 3811 { 1, OMAP_INT_1610_DMA_CH14 }, 3812 { 1, OMAP_INT_1610_DMA_CH15 } 3813 }; 3814 3815 /* DMA ports for OMAP1 */ 3816 static int omap_validate_emiff_addr(struct omap_mpu_state_s *s, 3817 hwaddr addr) 3818 { 3819 return range_covers_byte(OMAP_EMIFF_BASE, s->sdram_size, addr); 3820 } 3821 3822 static int omap_validate_emifs_addr(struct omap_mpu_state_s *s, 3823 hwaddr addr) 3824 { 3825 return range_covers_byte(OMAP_EMIFS_BASE, OMAP_EMIFF_BASE - OMAP_EMIFS_BASE, 3826 addr); 3827 } 3828 3829 static int omap_validate_imif_addr(struct omap_mpu_state_s *s, 3830 hwaddr addr) 3831 { 3832 return range_covers_byte(OMAP_IMIF_BASE, s->sram_size, addr); 3833 } 3834 3835 static int omap_validate_tipb_addr(struct omap_mpu_state_s *s, 3836 hwaddr addr) 3837 { 3838 return range_covers_byte(0xfffb0000, 0xffff0000 - 0xfffb0000, addr); 3839 } 3840 3841 static int omap_validate_local_addr(struct omap_mpu_state_s *s, 3842 hwaddr addr) 3843 { 3844 return range_covers_byte(OMAP_LOCALBUS_BASE, 0x1000000, addr); 3845 } 3846 3847 static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s, 3848 hwaddr addr) 3849 { 3850 return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr); 3851 } 3852 3853 struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory, 3854 unsigned long sdram_size, 3855 const char *core) 3856 { 3857 int i; 3858 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) 3859 g_malloc0(sizeof(struct omap_mpu_state_s)); 3860 qemu_irq dma_irqs[6]; 3861 DriveInfo *dinfo; 3862 SysBusDevice *busdev; 3863 3864 if (!core) 3865 core = "ti925t"; 3866 3867 /* Core */ 3868 s->mpu_model = omap310; 3869 s->cpu = cpu_arm_init(core); 3870 if (s->cpu == NULL) { 3871 fprintf(stderr, "Unable to find CPU definition\n"); 3872 exit(1); 3873 } 3874 s->sdram_size = sdram_size; 3875 s->sram_size = OMAP15XX_SRAM_SIZE; 3876 3877 s->wakeup = qemu_allocate_irq(omap_mpu_wakeup, s, 0); 3878 3879 /* Clocks */ 3880 omap_clk_init(s); 3881 3882 /* Memory-mapped stuff */ 3883 memory_region_allocate_system_memory(&s->emiff_ram, NULL, "omap1.dram", 3884 s->sdram_size); 3885 memory_region_add_subregion(system_memory, OMAP_EMIFF_BASE, &s->emiff_ram); 3886 memory_region_init_ram(&s->imif_ram, NULL, "omap1.sram", s->sram_size, 3887 &error_abort); 3888 vmstate_register_ram_global(&s->imif_ram); 3889 memory_region_add_subregion(system_memory, OMAP_IMIF_BASE, &s->imif_ram); 3890 3891 omap_clkm_init(system_memory, 0xfffece00, 0xe1008000, s); 3892 3893 s->ih[0] = qdev_create(NULL, "omap-intc"); 3894 qdev_prop_set_uint32(s->ih[0], "size", 0x100); 3895 qdev_prop_set_ptr(s->ih[0], "clk", omap_findclk(s, "arminth_ck")); 3896 qdev_init_nofail(s->ih[0]); 3897 busdev = SYS_BUS_DEVICE(s->ih[0]); 3898 sysbus_connect_irq(busdev, 0, 3899 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ)); 3900 sysbus_connect_irq(busdev, 1, 3901 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ)); 3902 sysbus_mmio_map(busdev, 0, 0xfffecb00); 3903 s->ih[1] = qdev_create(NULL, "omap-intc"); 3904 qdev_prop_set_uint32(s->ih[1], "size", 0x800); 3905 qdev_prop_set_ptr(s->ih[1], "clk", omap_findclk(s, "arminth_ck")); 3906 qdev_init_nofail(s->ih[1]); 3907 busdev = SYS_BUS_DEVICE(s->ih[1]); 3908 sysbus_connect_irq(busdev, 0, 3909 qdev_get_gpio_in(s->ih[0], OMAP_INT_15XX_IH2_IRQ)); 3910 /* The second interrupt controller's FIQ output is not wired up */ 3911 sysbus_mmio_map(busdev, 0, 0xfffe0000); 3912 3913 for (i = 0; i < 6; i++) { 3914 dma_irqs[i] = qdev_get_gpio_in(s->ih[omap1_dma_irq_map[i].ih], 3915 omap1_dma_irq_map[i].intr); 3916 } 3917 s->dma = omap_dma_init(0xfffed800, dma_irqs, system_memory, 3918 qdev_get_gpio_in(s->ih[0], OMAP_INT_DMA_LCD), 3919 s, omap_findclk(s, "dma_ck"), omap_dma_3_1); 3920 3921 s->port[emiff ].addr_valid = omap_validate_emiff_addr; 3922 s->port[emifs ].addr_valid = omap_validate_emifs_addr; 3923 s->port[imif ].addr_valid = omap_validate_imif_addr; 3924 s->port[tipb ].addr_valid = omap_validate_tipb_addr; 3925 s->port[local ].addr_valid = omap_validate_local_addr; 3926 s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr; 3927 3928 /* Register SDRAM and SRAM DMA ports for fast transfers. */ 3929 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->emiff_ram), 3930 OMAP_EMIFF_BASE, s->sdram_size); 3931 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->imif_ram), 3932 OMAP_IMIF_BASE, s->sram_size); 3933 3934 s->timer[0] = omap_mpu_timer_init(system_memory, 0xfffec500, 3935 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER1), 3936 omap_findclk(s, "mputim_ck")); 3937 s->timer[1] = omap_mpu_timer_init(system_memory, 0xfffec600, 3938 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER2), 3939 omap_findclk(s, "mputim_ck")); 3940 s->timer[2] = omap_mpu_timer_init(system_memory, 0xfffec700, 3941 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER3), 3942 omap_findclk(s, "mputim_ck")); 3943 3944 s->wdt = omap_wd_timer_init(system_memory, 0xfffec800, 3945 qdev_get_gpio_in(s->ih[0], OMAP_INT_WD_TIMER), 3946 omap_findclk(s, "armwdt_ck")); 3947 3948 s->os_timer = omap_os_timer_init(system_memory, 0xfffb9000, 3949 qdev_get_gpio_in(s->ih[1], OMAP_INT_OS_TIMER), 3950 omap_findclk(s, "clk32-kHz")); 3951 3952 s->lcd = omap_lcdc_init(system_memory, 0xfffec000, 3953 qdev_get_gpio_in(s->ih[0], OMAP_INT_LCD_CTRL), 3954 omap_dma_get_lcdch(s->dma), 3955 omap_findclk(s, "lcd_ck")); 3956 3957 omap_ulpd_pm_init(system_memory, 0xfffe0800, s); 3958 omap_pin_cfg_init(system_memory, 0xfffe1000, s); 3959 omap_id_init(system_memory, s); 3960 3961 omap_mpui_init(system_memory, 0xfffec900, s); 3962 3963 s->private_tipb = omap_tipb_bridge_init(system_memory, 0xfffeca00, 3964 qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PRIV), 3965 omap_findclk(s, "tipb_ck")); 3966 s->public_tipb = omap_tipb_bridge_init(system_memory, 0xfffed300, 3967 qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PUB), 3968 omap_findclk(s, "tipb_ck")); 3969 3970 omap_tcmi_init(system_memory, 0xfffecc00, s); 3971 3972 s->uart[0] = omap_uart_init(0xfffb0000, 3973 qdev_get_gpio_in(s->ih[1], OMAP_INT_UART1), 3974 omap_findclk(s, "uart1_ck"), 3975 omap_findclk(s, "uart1_ck"), 3976 s->drq[OMAP_DMA_UART1_TX], s->drq[OMAP_DMA_UART1_RX], 3977 "uart1", 3978 serial_hds[0]); 3979 s->uart[1] = omap_uart_init(0xfffb0800, 3980 qdev_get_gpio_in(s->ih[1], OMAP_INT_UART2), 3981 omap_findclk(s, "uart2_ck"), 3982 omap_findclk(s, "uart2_ck"), 3983 s->drq[OMAP_DMA_UART2_TX], s->drq[OMAP_DMA_UART2_RX], 3984 "uart2", 3985 serial_hds[0] ? serial_hds[1] : NULL); 3986 s->uart[2] = omap_uart_init(0xfffb9800, 3987 qdev_get_gpio_in(s->ih[0], OMAP_INT_UART3), 3988 omap_findclk(s, "uart3_ck"), 3989 omap_findclk(s, "uart3_ck"), 3990 s->drq[OMAP_DMA_UART3_TX], s->drq[OMAP_DMA_UART3_RX], 3991 "uart3", 3992 serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL); 3993 3994 s->dpll[0] = omap_dpll_init(system_memory, 0xfffecf00, 3995 omap_findclk(s, "dpll1")); 3996 s->dpll[1] = omap_dpll_init(system_memory, 0xfffed000, 3997 omap_findclk(s, "dpll2")); 3998 s->dpll[2] = omap_dpll_init(system_memory, 0xfffed100, 3999 omap_findclk(s, "dpll3")); 4000 4001 dinfo = drive_get(IF_SD, 0, 0); 4002 if (!dinfo) { 4003 fprintf(stderr, "qemu: missing SecureDigital device\n"); 4004 exit(1); 4005 } 4006 s->mmc = omap_mmc_init(0xfffb7800, system_memory, 4007 blk_by_legacy_dinfo(dinfo), 4008 qdev_get_gpio_in(s->ih[1], OMAP_INT_OQN), 4009 &s->drq[OMAP_DMA_MMC_TX], 4010 omap_findclk(s, "mmc_ck")); 4011 4012 s->mpuio = omap_mpuio_init(system_memory, 0xfffb5000, 4013 qdev_get_gpio_in(s->ih[1], OMAP_INT_KEYBOARD), 4014 qdev_get_gpio_in(s->ih[1], OMAP_INT_MPUIO), 4015 s->wakeup, omap_findclk(s, "clk32-kHz")); 4016 4017 s->gpio = qdev_create(NULL, "omap-gpio"); 4018 qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model); 4019 qdev_prop_set_ptr(s->gpio, "clk", omap_findclk(s, "arm_gpio_ck")); 4020 qdev_init_nofail(s->gpio); 4021 sysbus_connect_irq(SYS_BUS_DEVICE(s->gpio), 0, 4022 qdev_get_gpio_in(s->ih[0], OMAP_INT_GPIO_BANK1)); 4023 sysbus_mmio_map(SYS_BUS_DEVICE(s->gpio), 0, 0xfffce000); 4024 4025 s->microwire = omap_uwire_init(system_memory, 0xfffb3000, 4026 qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireTX), 4027 qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireRX), 4028 s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck")); 4029 4030 s->pwl = omap_pwl_init(system_memory, 0xfffb5800, 4031 omap_findclk(s, "armxor_ck")); 4032 s->pwt = omap_pwt_init(system_memory, 0xfffb6000, 4033 omap_findclk(s, "armxor_ck")); 4034 4035 s->i2c[0] = qdev_create(NULL, "omap_i2c"); 4036 qdev_prop_set_uint8(s->i2c[0], "revision", 0x11); 4037 qdev_prop_set_ptr(s->i2c[0], "fclk", omap_findclk(s, "mpuper_ck")); 4038 qdev_init_nofail(s->i2c[0]); 4039 busdev = SYS_BUS_DEVICE(s->i2c[0]); 4040 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C)); 4041 sysbus_connect_irq(busdev, 1, s->drq[OMAP_DMA_I2C_TX]); 4042 sysbus_connect_irq(busdev, 2, s->drq[OMAP_DMA_I2C_RX]); 4043 sysbus_mmio_map(busdev, 0, 0xfffb3800); 4044 4045 s->rtc = omap_rtc_init(system_memory, 0xfffb4800, 4046 qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_TIMER), 4047 qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_ALARM), 4048 omap_findclk(s, "clk32-kHz")); 4049 4050 s->mcbsp1 = omap_mcbsp_init(system_memory, 0xfffb1800, 4051 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1TX), 4052 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1RX), 4053 &s->drq[OMAP_DMA_MCBSP1_TX], omap_findclk(s, "dspxor_ck")); 4054 s->mcbsp2 = omap_mcbsp_init(system_memory, 0xfffb1000, 4055 qdev_get_gpio_in(s->ih[0], 4056 OMAP_INT_310_McBSP2_TX), 4057 qdev_get_gpio_in(s->ih[0], 4058 OMAP_INT_310_McBSP2_RX), 4059 &s->drq[OMAP_DMA_MCBSP2_TX], omap_findclk(s, "mpuper_ck")); 4060 s->mcbsp3 = omap_mcbsp_init(system_memory, 0xfffb7000, 4061 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3TX), 4062 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3RX), 4063 &s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck")); 4064 4065 s->led[0] = omap_lpg_init(system_memory, 4066 0xfffbd000, omap_findclk(s, "clk32-kHz")); 4067 s->led[1] = omap_lpg_init(system_memory, 4068 0xfffbd800, omap_findclk(s, "clk32-kHz")); 4069 4070 /* Register mappings not currenlty implemented: 4071 * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310) 4072 * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310) 4073 * USB W2FC fffb4000 - fffb47ff 4074 * Camera Interface fffb6800 - fffb6fff 4075 * USB Host fffba000 - fffba7ff 4076 * FAC fffba800 - fffbafff 4077 * HDQ/1-Wire fffbc000 - fffbc7ff 4078 * TIPB switches fffbc800 - fffbcfff 4079 * Mailbox fffcf000 - fffcf7ff 4080 * Local bus IF fffec100 - fffec1ff 4081 * Local bus MMU fffec200 - fffec2ff 4082 * DSP MMU fffed200 - fffed2ff 4083 */ 4084 4085 omap_setup_dsp_mapping(system_memory, omap15xx_dsp_mm); 4086 omap_setup_mpui_io(system_memory, s); 4087 4088 qemu_register_reset(omap1_mpu_reset, s); 4089 4090 return s; 4091 } 4092