1 /* 2 * TI OMAP processors emulation. 3 * 4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 or 9 * (at your option) version 3 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/error-report.h" 22 #include "qapi/error.h" 23 #include "qemu-common.h" 24 #include "cpu.h" 25 #include "hw/boards.h" 26 #include "hw/hw.h" 27 #include "hw/irq.h" 28 #include "hw/arm/boot.h" 29 #include "hw/arm/omap.h" 30 #include "sysemu/sysemu.h" 31 #include "hw/arm/soc_dma.h" 32 #include "sysemu/qtest.h" 33 #include "sysemu/reset.h" 34 #include "qemu/range.h" 35 #include "hw/sysbus.h" 36 #include "qemu/cutils.h" 37 #include "qemu/bcd.h" 38 39 static inline void omap_log_badwidth(const char *funcname, hwaddr addr, int sz) 40 { 41 qemu_log_mask(LOG_GUEST_ERROR, "%s: %d-bit register %#08" HWADDR_PRIx "\n", 42 funcname, 8 * sz, addr); 43 } 44 45 /* Should signal the TCMI/GPMC */ 46 uint32_t omap_badwidth_read8(void *opaque, hwaddr addr) 47 { 48 uint8_t ret; 49 50 omap_log_badwidth(__func__, addr, 1); 51 cpu_physical_memory_read(addr, &ret, 1); 52 return ret; 53 } 54 55 void omap_badwidth_write8(void *opaque, hwaddr addr, 56 uint32_t value) 57 { 58 uint8_t val8 = value; 59 60 omap_log_badwidth(__func__, addr, 1); 61 cpu_physical_memory_write(addr, &val8, 1); 62 } 63 64 uint32_t omap_badwidth_read16(void *opaque, hwaddr addr) 65 { 66 uint16_t ret; 67 68 omap_log_badwidth(__func__, addr, 2); 69 cpu_physical_memory_read(addr, &ret, 2); 70 return ret; 71 } 72 73 void omap_badwidth_write16(void *opaque, hwaddr addr, 74 uint32_t value) 75 { 76 uint16_t val16 = value; 77 78 omap_log_badwidth(__func__, addr, 2); 79 cpu_physical_memory_write(addr, &val16, 2); 80 } 81 82 uint32_t omap_badwidth_read32(void *opaque, hwaddr addr) 83 { 84 uint32_t ret; 85 86 omap_log_badwidth(__func__, addr, 4); 87 cpu_physical_memory_read(addr, &ret, 4); 88 return ret; 89 } 90 91 void omap_badwidth_write32(void *opaque, hwaddr addr, 92 uint32_t value) 93 { 94 omap_log_badwidth(__func__, addr, 4); 95 cpu_physical_memory_write(addr, &value, 4); 96 } 97 98 /* MPU OS timers */ 99 struct omap_mpu_timer_s { 100 MemoryRegion iomem; 101 qemu_irq irq; 102 omap_clk clk; 103 uint32_t val; 104 int64_t time; 105 QEMUTimer *timer; 106 QEMUBH *tick; 107 int64_t rate; 108 int it_ena; 109 110 int enable; 111 int ptv; 112 int ar; 113 int st; 114 uint32_t reset_val; 115 }; 116 117 static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer) 118 { 119 uint64_t distance = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->time; 120 121 if (timer->st && timer->enable && timer->rate) 122 return timer->val - muldiv64(distance >> (timer->ptv + 1), 123 timer->rate, NANOSECONDS_PER_SECOND); 124 else 125 return timer->val; 126 } 127 128 static inline void omap_timer_sync(struct omap_mpu_timer_s *timer) 129 { 130 timer->val = omap_timer_read(timer); 131 timer->time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 132 } 133 134 static inline void omap_timer_update(struct omap_mpu_timer_s *timer) 135 { 136 int64_t expires; 137 138 if (timer->enable && timer->st && timer->rate) { 139 timer->val = timer->reset_val; /* Should skip this on clk enable */ 140 expires = muldiv64((uint64_t) timer->val << (timer->ptv + 1), 141 NANOSECONDS_PER_SECOND, timer->rate); 142 143 /* If timer expiry would be sooner than in about 1 ms and 144 * auto-reload isn't set, then fire immediately. This is a hack 145 * to make systems like PalmOS run in acceptable time. PalmOS 146 * sets the interval to a very low value and polls the status bit 147 * in a busy loop when it wants to sleep just a couple of CPU 148 * ticks. */ 149 if (expires > (NANOSECONDS_PER_SECOND >> 10) || timer->ar) { 150 timer_mod(timer->timer, timer->time + expires); 151 } else { 152 qemu_bh_schedule(timer->tick); 153 } 154 } else 155 timer_del(timer->timer); 156 } 157 158 static void omap_timer_fire(void *opaque) 159 { 160 struct omap_mpu_timer_s *timer = opaque; 161 162 if (!timer->ar) { 163 timer->val = 0; 164 timer->st = 0; 165 } 166 167 if (timer->it_ena) 168 /* Edge-triggered irq */ 169 qemu_irq_pulse(timer->irq); 170 } 171 172 static void omap_timer_tick(void *opaque) 173 { 174 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque; 175 176 omap_timer_sync(timer); 177 omap_timer_fire(timer); 178 omap_timer_update(timer); 179 } 180 181 static void omap_timer_clk_update(void *opaque, int line, int on) 182 { 183 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque; 184 185 omap_timer_sync(timer); 186 timer->rate = on ? omap_clk_getrate(timer->clk) : 0; 187 omap_timer_update(timer); 188 } 189 190 static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer) 191 { 192 omap_clk_adduser(timer->clk, 193 qemu_allocate_irq(omap_timer_clk_update, timer, 0)); 194 timer->rate = omap_clk_getrate(timer->clk); 195 } 196 197 static uint64_t omap_mpu_timer_read(void *opaque, hwaddr addr, 198 unsigned size) 199 { 200 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; 201 202 if (size != 4) { 203 return omap_badwidth_read32(opaque, addr); 204 } 205 206 switch (addr) { 207 case 0x00: /* CNTL_TIMER */ 208 return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st; 209 210 case 0x04: /* LOAD_TIM */ 211 break; 212 213 case 0x08: /* READ_TIM */ 214 return omap_timer_read(s); 215 } 216 217 OMAP_BAD_REG(addr); 218 return 0; 219 } 220 221 static void omap_mpu_timer_write(void *opaque, hwaddr addr, 222 uint64_t value, unsigned size) 223 { 224 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; 225 226 if (size != 4) { 227 omap_badwidth_write32(opaque, addr, value); 228 return; 229 } 230 231 switch (addr) { 232 case 0x00: /* CNTL_TIMER */ 233 omap_timer_sync(s); 234 s->enable = (value >> 5) & 1; 235 s->ptv = (value >> 2) & 7; 236 s->ar = (value >> 1) & 1; 237 s->st = value & 1; 238 omap_timer_update(s); 239 return; 240 241 case 0x04: /* LOAD_TIM */ 242 s->reset_val = value; 243 return; 244 245 case 0x08: /* READ_TIM */ 246 OMAP_RO_REG(addr); 247 break; 248 249 default: 250 OMAP_BAD_REG(addr); 251 } 252 } 253 254 static const MemoryRegionOps omap_mpu_timer_ops = { 255 .read = omap_mpu_timer_read, 256 .write = omap_mpu_timer_write, 257 .endianness = DEVICE_LITTLE_ENDIAN, 258 }; 259 260 static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s) 261 { 262 timer_del(s->timer); 263 s->enable = 0; 264 s->reset_val = 31337; 265 s->val = 0; 266 s->ptv = 0; 267 s->ar = 0; 268 s->st = 0; 269 s->it_ena = 1; 270 } 271 272 static struct omap_mpu_timer_s *omap_mpu_timer_init(MemoryRegion *system_memory, 273 hwaddr base, 274 qemu_irq irq, omap_clk clk) 275 { 276 struct omap_mpu_timer_s *s = g_new0(struct omap_mpu_timer_s, 1); 277 278 s->irq = irq; 279 s->clk = clk; 280 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, s); 281 s->tick = qemu_bh_new(omap_timer_fire, s); 282 omap_mpu_timer_reset(s); 283 omap_timer_clk_setup(s); 284 285 memory_region_init_io(&s->iomem, NULL, &omap_mpu_timer_ops, s, 286 "omap-mpu-timer", 0x100); 287 288 memory_region_add_subregion(system_memory, base, &s->iomem); 289 290 return s; 291 } 292 293 /* Watchdog timer */ 294 struct omap_watchdog_timer_s { 295 struct omap_mpu_timer_s timer; 296 MemoryRegion iomem; 297 uint8_t last_wr; 298 int mode; 299 int free; 300 int reset; 301 }; 302 303 static uint64_t omap_wd_timer_read(void *opaque, hwaddr addr, 304 unsigned size) 305 { 306 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; 307 308 if (size != 2) { 309 return omap_badwidth_read16(opaque, addr); 310 } 311 312 switch (addr) { 313 case 0x00: /* CNTL_TIMER */ 314 return (s->timer.ptv << 9) | (s->timer.ar << 8) | 315 (s->timer.st << 7) | (s->free << 1); 316 317 case 0x04: /* READ_TIMER */ 318 return omap_timer_read(&s->timer); 319 320 case 0x08: /* TIMER_MODE */ 321 return s->mode << 15; 322 } 323 324 OMAP_BAD_REG(addr); 325 return 0; 326 } 327 328 static void omap_wd_timer_write(void *opaque, hwaddr addr, 329 uint64_t value, unsigned size) 330 { 331 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; 332 333 if (size != 2) { 334 omap_badwidth_write16(opaque, addr, value); 335 return; 336 } 337 338 switch (addr) { 339 case 0x00: /* CNTL_TIMER */ 340 omap_timer_sync(&s->timer); 341 s->timer.ptv = (value >> 9) & 7; 342 s->timer.ar = (value >> 8) & 1; 343 s->timer.st = (value >> 7) & 1; 344 s->free = (value >> 1) & 1; 345 omap_timer_update(&s->timer); 346 break; 347 348 case 0x04: /* LOAD_TIMER */ 349 s->timer.reset_val = value & 0xffff; 350 break; 351 352 case 0x08: /* TIMER_MODE */ 353 if (!s->mode && ((value >> 15) & 1)) 354 omap_clk_get(s->timer.clk); 355 s->mode |= (value >> 15) & 1; 356 if (s->last_wr == 0xf5) { 357 if ((value & 0xff) == 0xa0) { 358 if (s->mode) { 359 s->mode = 0; 360 omap_clk_put(s->timer.clk); 361 } 362 } else { 363 /* XXX: on T|E hardware somehow this has no effect, 364 * on Zire 71 it works as specified. */ 365 s->reset = 1; 366 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 367 } 368 } 369 s->last_wr = value & 0xff; 370 break; 371 372 default: 373 OMAP_BAD_REG(addr); 374 } 375 } 376 377 static const MemoryRegionOps omap_wd_timer_ops = { 378 .read = omap_wd_timer_read, 379 .write = omap_wd_timer_write, 380 .endianness = DEVICE_NATIVE_ENDIAN, 381 }; 382 383 static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s) 384 { 385 timer_del(s->timer.timer); 386 if (!s->mode) 387 omap_clk_get(s->timer.clk); 388 s->mode = 1; 389 s->free = 1; 390 s->reset = 0; 391 s->timer.enable = 1; 392 s->timer.it_ena = 1; 393 s->timer.reset_val = 0xffff; 394 s->timer.val = 0; 395 s->timer.st = 0; 396 s->timer.ptv = 0; 397 s->timer.ar = 0; 398 omap_timer_update(&s->timer); 399 } 400 401 static struct omap_watchdog_timer_s *omap_wd_timer_init(MemoryRegion *memory, 402 hwaddr base, 403 qemu_irq irq, omap_clk clk) 404 { 405 struct omap_watchdog_timer_s *s = g_new0(struct omap_watchdog_timer_s, 1); 406 407 s->timer.irq = irq; 408 s->timer.clk = clk; 409 s->timer.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, &s->timer); 410 omap_wd_timer_reset(s); 411 omap_timer_clk_setup(&s->timer); 412 413 memory_region_init_io(&s->iomem, NULL, &omap_wd_timer_ops, s, 414 "omap-wd-timer", 0x100); 415 memory_region_add_subregion(memory, base, &s->iomem); 416 417 return s; 418 } 419 420 /* 32-kHz timer */ 421 struct omap_32khz_timer_s { 422 struct omap_mpu_timer_s timer; 423 MemoryRegion iomem; 424 }; 425 426 static uint64_t omap_os_timer_read(void *opaque, hwaddr addr, 427 unsigned size) 428 { 429 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; 430 int offset = addr & OMAP_MPUI_REG_MASK; 431 432 if (size != 4) { 433 return omap_badwidth_read32(opaque, addr); 434 } 435 436 switch (offset) { 437 case 0x00: /* TVR */ 438 return s->timer.reset_val; 439 440 case 0x04: /* TCR */ 441 return omap_timer_read(&s->timer); 442 443 case 0x08: /* CR */ 444 return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st; 445 446 default: 447 break; 448 } 449 OMAP_BAD_REG(addr); 450 return 0; 451 } 452 453 static void omap_os_timer_write(void *opaque, hwaddr addr, 454 uint64_t value, unsigned size) 455 { 456 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; 457 int offset = addr & OMAP_MPUI_REG_MASK; 458 459 if (size != 4) { 460 omap_badwidth_write32(opaque, addr, value); 461 return; 462 } 463 464 switch (offset) { 465 case 0x00: /* TVR */ 466 s->timer.reset_val = value & 0x00ffffff; 467 break; 468 469 case 0x04: /* TCR */ 470 OMAP_RO_REG(addr); 471 break; 472 473 case 0x08: /* CR */ 474 s->timer.ar = (value >> 3) & 1; 475 s->timer.it_ena = (value >> 2) & 1; 476 if (s->timer.st != (value & 1) || (value & 2)) { 477 omap_timer_sync(&s->timer); 478 s->timer.enable = value & 1; 479 s->timer.st = value & 1; 480 omap_timer_update(&s->timer); 481 } 482 break; 483 484 default: 485 OMAP_BAD_REG(addr); 486 } 487 } 488 489 static const MemoryRegionOps omap_os_timer_ops = { 490 .read = omap_os_timer_read, 491 .write = omap_os_timer_write, 492 .endianness = DEVICE_NATIVE_ENDIAN, 493 }; 494 495 static void omap_os_timer_reset(struct omap_32khz_timer_s *s) 496 { 497 timer_del(s->timer.timer); 498 s->timer.enable = 0; 499 s->timer.it_ena = 0; 500 s->timer.reset_val = 0x00ffffff; 501 s->timer.val = 0; 502 s->timer.st = 0; 503 s->timer.ptv = 0; 504 s->timer.ar = 1; 505 } 506 507 static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory, 508 hwaddr base, 509 qemu_irq irq, omap_clk clk) 510 { 511 struct omap_32khz_timer_s *s = g_new0(struct omap_32khz_timer_s, 1); 512 513 s->timer.irq = irq; 514 s->timer.clk = clk; 515 s->timer.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, &s->timer); 516 omap_os_timer_reset(s); 517 omap_timer_clk_setup(&s->timer); 518 519 memory_region_init_io(&s->iomem, NULL, &omap_os_timer_ops, s, 520 "omap-os-timer", 0x800); 521 memory_region_add_subregion(memory, base, &s->iomem); 522 523 return s; 524 } 525 526 /* Ultra Low-Power Device Module */ 527 static uint64_t omap_ulpd_pm_read(void *opaque, hwaddr addr, 528 unsigned size) 529 { 530 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 531 uint16_t ret; 532 533 if (size != 2) { 534 return omap_badwidth_read16(opaque, addr); 535 } 536 537 switch (addr) { 538 case 0x14: /* IT_STATUS */ 539 ret = s->ulpd_pm_regs[addr >> 2]; 540 s->ulpd_pm_regs[addr >> 2] = 0; 541 qemu_irq_lower(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K)); 542 return ret; 543 544 case 0x18: /* Reserved */ 545 case 0x1c: /* Reserved */ 546 case 0x20: /* Reserved */ 547 case 0x28: /* Reserved */ 548 case 0x2c: /* Reserved */ 549 OMAP_BAD_REG(addr); 550 /* fall through */ 551 case 0x00: /* COUNTER_32_LSB */ 552 case 0x04: /* COUNTER_32_MSB */ 553 case 0x08: /* COUNTER_HIGH_FREQ_LSB */ 554 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ 555 case 0x10: /* GAUGING_CTRL */ 556 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ 557 case 0x30: /* CLOCK_CTRL */ 558 case 0x34: /* SOFT_REQ */ 559 case 0x38: /* COUNTER_32_FIQ */ 560 case 0x3c: /* DPLL_CTRL */ 561 case 0x40: /* STATUS_REQ */ 562 /* XXX: check clk::usecount state for every clock */ 563 case 0x48: /* LOCL_TIME */ 564 case 0x4c: /* APLL_CTRL */ 565 case 0x50: /* POWER_CTRL */ 566 return s->ulpd_pm_regs[addr >> 2]; 567 } 568 569 OMAP_BAD_REG(addr); 570 return 0; 571 } 572 573 static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s, 574 uint16_t diff, uint16_t value) 575 { 576 if (diff & (1 << 4)) /* USB_MCLK_EN */ 577 omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1); 578 if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */ 579 omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1); 580 } 581 582 static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s, 583 uint16_t diff, uint16_t value) 584 { 585 if (diff & (1 << 0)) /* SOFT_DPLL_REQ */ 586 omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1); 587 if (diff & (1 << 1)) /* SOFT_COM_REQ */ 588 omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1); 589 if (diff & (1 << 2)) /* SOFT_SDW_REQ */ 590 omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1); 591 if (diff & (1 << 3)) /* SOFT_USB_REQ */ 592 omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1); 593 } 594 595 static void omap_ulpd_pm_write(void *opaque, hwaddr addr, 596 uint64_t value, unsigned size) 597 { 598 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 599 int64_t now, ticks; 600 int div, mult; 601 static const int bypass_div[4] = { 1, 2, 4, 4 }; 602 uint16_t diff; 603 604 if (size != 2) { 605 omap_badwidth_write16(opaque, addr, value); 606 return; 607 } 608 609 switch (addr) { 610 case 0x00: /* COUNTER_32_LSB */ 611 case 0x04: /* COUNTER_32_MSB */ 612 case 0x08: /* COUNTER_HIGH_FREQ_LSB */ 613 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ 614 case 0x14: /* IT_STATUS */ 615 case 0x40: /* STATUS_REQ */ 616 OMAP_RO_REG(addr); 617 break; 618 619 case 0x10: /* GAUGING_CTRL */ 620 /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */ 621 if ((s->ulpd_pm_regs[addr >> 2] ^ value) & 1) { 622 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 623 624 if (value & 1) 625 s->ulpd_gauge_start = now; 626 else { 627 now -= s->ulpd_gauge_start; 628 629 /* 32-kHz ticks */ 630 ticks = muldiv64(now, 32768, NANOSECONDS_PER_SECOND); 631 s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff; 632 s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff; 633 if (ticks >> 32) /* OVERFLOW_32K */ 634 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2; 635 636 /* High frequency ticks */ 637 ticks = muldiv64(now, 12000000, NANOSECONDS_PER_SECOND); 638 s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff; 639 s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff; 640 if (ticks >> 32) /* OVERFLOW_HI_FREQ */ 641 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1; 642 643 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */ 644 qemu_irq_raise(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K)); 645 } 646 } 647 s->ulpd_pm_regs[addr >> 2] = value; 648 break; 649 650 case 0x18: /* Reserved */ 651 case 0x1c: /* Reserved */ 652 case 0x20: /* Reserved */ 653 case 0x28: /* Reserved */ 654 case 0x2c: /* Reserved */ 655 OMAP_BAD_REG(addr); 656 /* fall through */ 657 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ 658 case 0x38: /* COUNTER_32_FIQ */ 659 case 0x48: /* LOCL_TIME */ 660 case 0x50: /* POWER_CTRL */ 661 s->ulpd_pm_regs[addr >> 2] = value; 662 break; 663 664 case 0x30: /* CLOCK_CTRL */ 665 diff = s->ulpd_pm_regs[addr >> 2] ^ value; 666 s->ulpd_pm_regs[addr >> 2] = value & 0x3f; 667 omap_ulpd_clk_update(s, diff, value); 668 break; 669 670 case 0x34: /* SOFT_REQ */ 671 diff = s->ulpd_pm_regs[addr >> 2] ^ value; 672 s->ulpd_pm_regs[addr >> 2] = value & 0x1f; 673 omap_ulpd_req_update(s, diff, value); 674 break; 675 676 case 0x3c: /* DPLL_CTRL */ 677 /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is 678 * omitted altogether, probably a typo. */ 679 /* This register has identical semantics with DPLL(1:3) control 680 * registers, see omap_dpll_write() */ 681 diff = s->ulpd_pm_regs[addr >> 2] & value; 682 s->ulpd_pm_regs[addr >> 2] = value & 0x2fff; 683 if (diff & (0x3ff << 2)) { 684 if (value & (1 << 4)) { /* PLL_ENABLE */ 685 div = ((value >> 5) & 3) + 1; /* PLL_DIV */ 686 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ 687 } else { 688 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ 689 mult = 1; 690 } 691 omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult); 692 } 693 694 /* Enter the desired mode. */ 695 s->ulpd_pm_regs[addr >> 2] = 696 (s->ulpd_pm_regs[addr >> 2] & 0xfffe) | 697 ((s->ulpd_pm_regs[addr >> 2] >> 4) & 1); 698 699 /* Act as if the lock is restored. */ 700 s->ulpd_pm_regs[addr >> 2] |= 2; 701 break; 702 703 case 0x4c: /* APLL_CTRL */ 704 diff = s->ulpd_pm_regs[addr >> 2] & value; 705 s->ulpd_pm_regs[addr >> 2] = value & 0xf; 706 if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */ 707 omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s, 708 (value & (1 << 0)) ? "apll" : "dpll4")); 709 break; 710 711 default: 712 OMAP_BAD_REG(addr); 713 } 714 } 715 716 static const MemoryRegionOps omap_ulpd_pm_ops = { 717 .read = omap_ulpd_pm_read, 718 .write = omap_ulpd_pm_write, 719 .endianness = DEVICE_NATIVE_ENDIAN, 720 }; 721 722 static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu) 723 { 724 mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001; 725 mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000; 726 mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001; 727 mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000; 728 mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000; 729 mpu->ulpd_pm_regs[0x18 >> 2] = 0x01; 730 mpu->ulpd_pm_regs[0x1c >> 2] = 0x01; 731 mpu->ulpd_pm_regs[0x20 >> 2] = 0x01; 732 mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff; 733 mpu->ulpd_pm_regs[0x28 >> 2] = 0x01; 734 mpu->ulpd_pm_regs[0x2c >> 2] = 0x01; 735 omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000); 736 mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000; 737 omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000); 738 mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000; 739 mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001; 740 mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211; 741 mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */ 742 mpu->ulpd_pm_regs[0x48 >> 2] = 0x960; 743 mpu->ulpd_pm_regs[0x4c >> 2] = 0x08; 744 mpu->ulpd_pm_regs[0x50 >> 2] = 0x08; 745 omap_clk_setrate(omap_findclk(mpu, "dpll4"), 1, 4); 746 omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4")); 747 } 748 749 static void omap_ulpd_pm_init(MemoryRegion *system_memory, 750 hwaddr base, 751 struct omap_mpu_state_s *mpu) 752 { 753 memory_region_init_io(&mpu->ulpd_pm_iomem, NULL, &omap_ulpd_pm_ops, mpu, 754 "omap-ulpd-pm", 0x800); 755 memory_region_add_subregion(system_memory, base, &mpu->ulpd_pm_iomem); 756 omap_ulpd_pm_reset(mpu); 757 } 758 759 /* OMAP Pin Configuration */ 760 static uint64_t omap_pin_cfg_read(void *opaque, hwaddr addr, 761 unsigned size) 762 { 763 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 764 765 if (size != 4) { 766 return omap_badwidth_read32(opaque, addr); 767 } 768 769 switch (addr) { 770 case 0x00: /* FUNC_MUX_CTRL_0 */ 771 case 0x04: /* FUNC_MUX_CTRL_1 */ 772 case 0x08: /* FUNC_MUX_CTRL_2 */ 773 return s->func_mux_ctrl[addr >> 2]; 774 775 case 0x0c: /* COMP_MODE_CTRL_0 */ 776 return s->comp_mode_ctrl[0]; 777 778 case 0x10: /* FUNC_MUX_CTRL_3 */ 779 case 0x14: /* FUNC_MUX_CTRL_4 */ 780 case 0x18: /* FUNC_MUX_CTRL_5 */ 781 case 0x1c: /* FUNC_MUX_CTRL_6 */ 782 case 0x20: /* FUNC_MUX_CTRL_7 */ 783 case 0x24: /* FUNC_MUX_CTRL_8 */ 784 case 0x28: /* FUNC_MUX_CTRL_9 */ 785 case 0x2c: /* FUNC_MUX_CTRL_A */ 786 case 0x30: /* FUNC_MUX_CTRL_B */ 787 case 0x34: /* FUNC_MUX_CTRL_C */ 788 case 0x38: /* FUNC_MUX_CTRL_D */ 789 return s->func_mux_ctrl[(addr >> 2) - 1]; 790 791 case 0x40: /* PULL_DWN_CTRL_0 */ 792 case 0x44: /* PULL_DWN_CTRL_1 */ 793 case 0x48: /* PULL_DWN_CTRL_2 */ 794 case 0x4c: /* PULL_DWN_CTRL_3 */ 795 return s->pull_dwn_ctrl[(addr & 0xf) >> 2]; 796 797 case 0x50: /* GATE_INH_CTRL_0 */ 798 return s->gate_inh_ctrl[0]; 799 800 case 0x60: /* VOLTAGE_CTRL_0 */ 801 return s->voltage_ctrl[0]; 802 803 case 0x70: /* TEST_DBG_CTRL_0 */ 804 return s->test_dbg_ctrl[0]; 805 806 case 0x80: /* MOD_CONF_CTRL_0 */ 807 return s->mod_conf_ctrl[0]; 808 } 809 810 OMAP_BAD_REG(addr); 811 return 0; 812 } 813 814 static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s, 815 uint32_t diff, uint32_t value) 816 { 817 if (s->compat1509) { 818 if (diff & (1 << 9)) /* BLUETOOTH */ 819 omap_clk_onoff(omap_findclk(s, "bt_mclk_out"), 820 (~value >> 9) & 1); 821 if (diff & (1 << 7)) /* USB.CLKO */ 822 omap_clk_onoff(omap_findclk(s, "usb.clko"), 823 (value >> 7) & 1); 824 } 825 } 826 827 static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s, 828 uint32_t diff, uint32_t value) 829 { 830 if (s->compat1509) { 831 if (diff & (1U << 31)) { 832 /* MCBSP3_CLK_HIZ_DI */ 833 omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"), (value >> 31) & 1); 834 } 835 if (diff & (1 << 1)) { 836 /* CLK32K */ 837 omap_clk_onoff(omap_findclk(s, "clk32k_out"), (~value >> 1) & 1); 838 } 839 } 840 } 841 842 static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s, 843 uint32_t diff, uint32_t value) 844 { 845 if (diff & (1U << 31)) { 846 /* CONF_MOD_UART3_CLK_MODE_R */ 847 omap_clk_reparent(omap_findclk(s, "uart3_ck"), 848 omap_findclk(s, ((value >> 31) & 1) ? 849 "ck_48m" : "armper_ck")); 850 } 851 if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */ 852 omap_clk_reparent(omap_findclk(s, "uart2_ck"), 853 omap_findclk(s, ((value >> 30) & 1) ? 854 "ck_48m" : "armper_ck")); 855 if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */ 856 omap_clk_reparent(omap_findclk(s, "uart1_ck"), 857 omap_findclk(s, ((value >> 29) & 1) ? 858 "ck_48m" : "armper_ck")); 859 if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */ 860 omap_clk_reparent(omap_findclk(s, "mmc_ck"), 861 omap_findclk(s, ((value >> 23) & 1) ? 862 "ck_48m" : "armper_ck")); 863 if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */ 864 omap_clk_reparent(omap_findclk(s, "com_mclk_out"), 865 omap_findclk(s, ((value >> 12) & 1) ? 866 "ck_48m" : "armper_ck")); 867 if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */ 868 omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1); 869 } 870 871 static void omap_pin_cfg_write(void *opaque, hwaddr addr, 872 uint64_t value, unsigned size) 873 { 874 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 875 uint32_t diff; 876 877 if (size != 4) { 878 omap_badwidth_write32(opaque, addr, value); 879 return; 880 } 881 882 switch (addr) { 883 case 0x00: /* FUNC_MUX_CTRL_0 */ 884 diff = s->func_mux_ctrl[addr >> 2] ^ value; 885 s->func_mux_ctrl[addr >> 2] = value; 886 omap_pin_funcmux0_update(s, diff, value); 887 return; 888 889 case 0x04: /* FUNC_MUX_CTRL_1 */ 890 diff = s->func_mux_ctrl[addr >> 2] ^ value; 891 s->func_mux_ctrl[addr >> 2] = value; 892 omap_pin_funcmux1_update(s, diff, value); 893 return; 894 895 case 0x08: /* FUNC_MUX_CTRL_2 */ 896 s->func_mux_ctrl[addr >> 2] = value; 897 return; 898 899 case 0x0c: /* COMP_MODE_CTRL_0 */ 900 s->comp_mode_ctrl[0] = value; 901 s->compat1509 = (value != 0x0000eaef); 902 omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]); 903 omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]); 904 return; 905 906 case 0x10: /* FUNC_MUX_CTRL_3 */ 907 case 0x14: /* FUNC_MUX_CTRL_4 */ 908 case 0x18: /* FUNC_MUX_CTRL_5 */ 909 case 0x1c: /* FUNC_MUX_CTRL_6 */ 910 case 0x20: /* FUNC_MUX_CTRL_7 */ 911 case 0x24: /* FUNC_MUX_CTRL_8 */ 912 case 0x28: /* FUNC_MUX_CTRL_9 */ 913 case 0x2c: /* FUNC_MUX_CTRL_A */ 914 case 0x30: /* FUNC_MUX_CTRL_B */ 915 case 0x34: /* FUNC_MUX_CTRL_C */ 916 case 0x38: /* FUNC_MUX_CTRL_D */ 917 s->func_mux_ctrl[(addr >> 2) - 1] = value; 918 return; 919 920 case 0x40: /* PULL_DWN_CTRL_0 */ 921 case 0x44: /* PULL_DWN_CTRL_1 */ 922 case 0x48: /* PULL_DWN_CTRL_2 */ 923 case 0x4c: /* PULL_DWN_CTRL_3 */ 924 s->pull_dwn_ctrl[(addr & 0xf) >> 2] = value; 925 return; 926 927 case 0x50: /* GATE_INH_CTRL_0 */ 928 s->gate_inh_ctrl[0] = value; 929 return; 930 931 case 0x60: /* VOLTAGE_CTRL_0 */ 932 s->voltage_ctrl[0] = value; 933 return; 934 935 case 0x70: /* TEST_DBG_CTRL_0 */ 936 s->test_dbg_ctrl[0] = value; 937 return; 938 939 case 0x80: /* MOD_CONF_CTRL_0 */ 940 diff = s->mod_conf_ctrl[0] ^ value; 941 s->mod_conf_ctrl[0] = value; 942 omap_pin_modconf1_update(s, diff, value); 943 return; 944 945 default: 946 OMAP_BAD_REG(addr); 947 } 948 } 949 950 static const MemoryRegionOps omap_pin_cfg_ops = { 951 .read = omap_pin_cfg_read, 952 .write = omap_pin_cfg_write, 953 .endianness = DEVICE_NATIVE_ENDIAN, 954 }; 955 956 static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu) 957 { 958 /* Start in Compatibility Mode. */ 959 mpu->compat1509 = 1; 960 omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0); 961 omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0); 962 omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0); 963 memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl)); 964 memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl)); 965 memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl)); 966 memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl)); 967 memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl)); 968 memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl)); 969 memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl)); 970 } 971 972 static void omap_pin_cfg_init(MemoryRegion *system_memory, 973 hwaddr base, 974 struct omap_mpu_state_s *mpu) 975 { 976 memory_region_init_io(&mpu->pin_cfg_iomem, NULL, &omap_pin_cfg_ops, mpu, 977 "omap-pin-cfg", 0x800); 978 memory_region_add_subregion(system_memory, base, &mpu->pin_cfg_iomem); 979 omap_pin_cfg_reset(mpu); 980 } 981 982 /* Device Identification, Die Identification */ 983 static uint64_t omap_id_read(void *opaque, hwaddr addr, 984 unsigned size) 985 { 986 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 987 988 if (size != 4) { 989 return omap_badwidth_read32(opaque, addr); 990 } 991 992 switch (addr) { 993 case 0xfffe1800: /* DIE_ID_LSB */ 994 return 0xc9581f0e; 995 case 0xfffe1804: /* DIE_ID_MSB */ 996 return 0xa8858bfa; 997 998 case 0xfffe2000: /* PRODUCT_ID_LSB */ 999 return 0x00aaaafc; 1000 case 0xfffe2004: /* PRODUCT_ID_MSB */ 1001 return 0xcafeb574; 1002 1003 case 0xfffed400: /* JTAG_ID_LSB */ 1004 switch (s->mpu_model) { 1005 case omap310: 1006 return 0x03310315; 1007 case omap1510: 1008 return 0x03310115; 1009 default: 1010 hw_error("%s: bad mpu model\n", __func__); 1011 } 1012 break; 1013 1014 case 0xfffed404: /* JTAG_ID_MSB */ 1015 switch (s->mpu_model) { 1016 case omap310: 1017 return 0xfb57402f; 1018 case omap1510: 1019 return 0xfb47002f; 1020 default: 1021 hw_error("%s: bad mpu model\n", __func__); 1022 } 1023 break; 1024 } 1025 1026 OMAP_BAD_REG(addr); 1027 return 0; 1028 } 1029 1030 static void omap_id_write(void *opaque, hwaddr addr, 1031 uint64_t value, unsigned size) 1032 { 1033 if (size != 4) { 1034 omap_badwidth_write32(opaque, addr, value); 1035 return; 1036 } 1037 1038 OMAP_BAD_REG(addr); 1039 } 1040 1041 static const MemoryRegionOps omap_id_ops = { 1042 .read = omap_id_read, 1043 .write = omap_id_write, 1044 .endianness = DEVICE_NATIVE_ENDIAN, 1045 }; 1046 1047 static void omap_id_init(MemoryRegion *memory, struct omap_mpu_state_s *mpu) 1048 { 1049 memory_region_init_io(&mpu->id_iomem, NULL, &omap_id_ops, mpu, 1050 "omap-id", 0x100000000ULL); 1051 memory_region_init_alias(&mpu->id_iomem_e18, NULL, "omap-id-e18", &mpu->id_iomem, 1052 0xfffe1800, 0x800); 1053 memory_region_add_subregion(memory, 0xfffe1800, &mpu->id_iomem_e18); 1054 memory_region_init_alias(&mpu->id_iomem_ed4, NULL, "omap-id-ed4", &mpu->id_iomem, 1055 0xfffed400, 0x100); 1056 memory_region_add_subregion(memory, 0xfffed400, &mpu->id_iomem_ed4); 1057 if (!cpu_is_omap15xx(mpu)) { 1058 memory_region_init_alias(&mpu->id_iomem_ed4, NULL, "omap-id-e20", 1059 &mpu->id_iomem, 0xfffe2000, 0x800); 1060 memory_region_add_subregion(memory, 0xfffe2000, &mpu->id_iomem_e20); 1061 } 1062 } 1063 1064 /* MPUI Control (Dummy) */ 1065 static uint64_t omap_mpui_read(void *opaque, hwaddr addr, 1066 unsigned size) 1067 { 1068 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1069 1070 if (size != 4) { 1071 return omap_badwidth_read32(opaque, addr); 1072 } 1073 1074 switch (addr) { 1075 case 0x00: /* CTRL */ 1076 return s->mpui_ctrl; 1077 case 0x04: /* DEBUG_ADDR */ 1078 return 0x01ffffff; 1079 case 0x08: /* DEBUG_DATA */ 1080 return 0xffffffff; 1081 case 0x0c: /* DEBUG_FLAG */ 1082 return 0x00000800; 1083 case 0x10: /* STATUS */ 1084 return 0x00000000; 1085 1086 /* Not in OMAP310 */ 1087 case 0x14: /* DSP_STATUS */ 1088 case 0x18: /* DSP_BOOT_CONFIG */ 1089 return 0x00000000; 1090 case 0x1c: /* DSP_MPUI_CONFIG */ 1091 return 0x0000ffff; 1092 } 1093 1094 OMAP_BAD_REG(addr); 1095 return 0; 1096 } 1097 1098 static void omap_mpui_write(void *opaque, hwaddr addr, 1099 uint64_t value, unsigned size) 1100 { 1101 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1102 1103 if (size != 4) { 1104 omap_badwidth_write32(opaque, addr, value); 1105 return; 1106 } 1107 1108 switch (addr) { 1109 case 0x00: /* CTRL */ 1110 s->mpui_ctrl = value & 0x007fffff; 1111 break; 1112 1113 case 0x04: /* DEBUG_ADDR */ 1114 case 0x08: /* DEBUG_DATA */ 1115 case 0x0c: /* DEBUG_FLAG */ 1116 case 0x10: /* STATUS */ 1117 /* Not in OMAP310 */ 1118 case 0x14: /* DSP_STATUS */ 1119 OMAP_RO_REG(addr); 1120 break; 1121 case 0x18: /* DSP_BOOT_CONFIG */ 1122 case 0x1c: /* DSP_MPUI_CONFIG */ 1123 break; 1124 1125 default: 1126 OMAP_BAD_REG(addr); 1127 } 1128 } 1129 1130 static const MemoryRegionOps omap_mpui_ops = { 1131 .read = omap_mpui_read, 1132 .write = omap_mpui_write, 1133 .endianness = DEVICE_NATIVE_ENDIAN, 1134 }; 1135 1136 static void omap_mpui_reset(struct omap_mpu_state_s *s) 1137 { 1138 s->mpui_ctrl = 0x0003ff1b; 1139 } 1140 1141 static void omap_mpui_init(MemoryRegion *memory, hwaddr base, 1142 struct omap_mpu_state_s *mpu) 1143 { 1144 memory_region_init_io(&mpu->mpui_iomem, NULL, &omap_mpui_ops, mpu, 1145 "omap-mpui", 0x100); 1146 memory_region_add_subregion(memory, base, &mpu->mpui_iomem); 1147 1148 omap_mpui_reset(mpu); 1149 } 1150 1151 /* TIPB Bridges */ 1152 struct omap_tipb_bridge_s { 1153 qemu_irq abort; 1154 MemoryRegion iomem; 1155 1156 int width_intr; 1157 uint16_t control; 1158 uint16_t alloc; 1159 uint16_t buffer; 1160 uint16_t enh_control; 1161 }; 1162 1163 static uint64_t omap_tipb_bridge_read(void *opaque, hwaddr addr, 1164 unsigned size) 1165 { 1166 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; 1167 1168 if (size < 2) { 1169 return omap_badwidth_read16(opaque, addr); 1170 } 1171 1172 switch (addr) { 1173 case 0x00: /* TIPB_CNTL */ 1174 return s->control; 1175 case 0x04: /* TIPB_BUS_ALLOC */ 1176 return s->alloc; 1177 case 0x08: /* MPU_TIPB_CNTL */ 1178 return s->buffer; 1179 case 0x0c: /* ENHANCED_TIPB_CNTL */ 1180 return s->enh_control; 1181 case 0x10: /* ADDRESS_DBG */ 1182 case 0x14: /* DATA_DEBUG_LOW */ 1183 case 0x18: /* DATA_DEBUG_HIGH */ 1184 return 0xffff; 1185 case 0x1c: /* DEBUG_CNTR_SIG */ 1186 return 0x00f8; 1187 } 1188 1189 OMAP_BAD_REG(addr); 1190 return 0; 1191 } 1192 1193 static void omap_tipb_bridge_write(void *opaque, hwaddr addr, 1194 uint64_t value, unsigned size) 1195 { 1196 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; 1197 1198 if (size < 2) { 1199 omap_badwidth_write16(opaque, addr, value); 1200 return; 1201 } 1202 1203 switch (addr) { 1204 case 0x00: /* TIPB_CNTL */ 1205 s->control = value & 0xffff; 1206 break; 1207 1208 case 0x04: /* TIPB_BUS_ALLOC */ 1209 s->alloc = value & 0x003f; 1210 break; 1211 1212 case 0x08: /* MPU_TIPB_CNTL */ 1213 s->buffer = value & 0x0003; 1214 break; 1215 1216 case 0x0c: /* ENHANCED_TIPB_CNTL */ 1217 s->width_intr = !(value & 2); 1218 s->enh_control = value & 0x000f; 1219 break; 1220 1221 case 0x10: /* ADDRESS_DBG */ 1222 case 0x14: /* DATA_DEBUG_LOW */ 1223 case 0x18: /* DATA_DEBUG_HIGH */ 1224 case 0x1c: /* DEBUG_CNTR_SIG */ 1225 OMAP_RO_REG(addr); 1226 break; 1227 1228 default: 1229 OMAP_BAD_REG(addr); 1230 } 1231 } 1232 1233 static const MemoryRegionOps omap_tipb_bridge_ops = { 1234 .read = omap_tipb_bridge_read, 1235 .write = omap_tipb_bridge_write, 1236 .endianness = DEVICE_NATIVE_ENDIAN, 1237 }; 1238 1239 static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s) 1240 { 1241 s->control = 0xffff; 1242 s->alloc = 0x0009; 1243 s->buffer = 0x0000; 1244 s->enh_control = 0x000f; 1245 } 1246 1247 static struct omap_tipb_bridge_s *omap_tipb_bridge_init( 1248 MemoryRegion *memory, hwaddr base, 1249 qemu_irq abort_irq, omap_clk clk) 1250 { 1251 struct omap_tipb_bridge_s *s = g_new0(struct omap_tipb_bridge_s, 1); 1252 1253 s->abort = abort_irq; 1254 omap_tipb_bridge_reset(s); 1255 1256 memory_region_init_io(&s->iomem, NULL, &omap_tipb_bridge_ops, s, 1257 "omap-tipb-bridge", 0x100); 1258 memory_region_add_subregion(memory, base, &s->iomem); 1259 1260 return s; 1261 } 1262 1263 /* Dummy Traffic Controller's Memory Interface */ 1264 static uint64_t omap_tcmi_read(void *opaque, hwaddr addr, 1265 unsigned size) 1266 { 1267 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1268 uint32_t ret; 1269 1270 if (size != 4) { 1271 return omap_badwidth_read32(opaque, addr); 1272 } 1273 1274 switch (addr) { 1275 case 0x00: /* IMIF_PRIO */ 1276 case 0x04: /* EMIFS_PRIO */ 1277 case 0x08: /* EMIFF_PRIO */ 1278 case 0x0c: /* EMIFS_CONFIG */ 1279 case 0x10: /* EMIFS_CS0_CONFIG */ 1280 case 0x14: /* EMIFS_CS1_CONFIG */ 1281 case 0x18: /* EMIFS_CS2_CONFIG */ 1282 case 0x1c: /* EMIFS_CS3_CONFIG */ 1283 case 0x24: /* EMIFF_MRS */ 1284 case 0x28: /* TIMEOUT1 */ 1285 case 0x2c: /* TIMEOUT2 */ 1286 case 0x30: /* TIMEOUT3 */ 1287 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ 1288 case 0x40: /* EMIFS_CFG_DYN_WAIT */ 1289 return s->tcmi_regs[addr >> 2]; 1290 1291 case 0x20: /* EMIFF_SDRAM_CONFIG */ 1292 ret = s->tcmi_regs[addr >> 2]; 1293 s->tcmi_regs[addr >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */ 1294 /* XXX: We can try using the VGA_DIRTY flag for this */ 1295 return ret; 1296 } 1297 1298 OMAP_BAD_REG(addr); 1299 return 0; 1300 } 1301 1302 static void omap_tcmi_write(void *opaque, hwaddr addr, 1303 uint64_t value, unsigned size) 1304 { 1305 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1306 1307 if (size != 4) { 1308 omap_badwidth_write32(opaque, addr, value); 1309 return; 1310 } 1311 1312 switch (addr) { 1313 case 0x00: /* IMIF_PRIO */ 1314 case 0x04: /* EMIFS_PRIO */ 1315 case 0x08: /* EMIFF_PRIO */ 1316 case 0x10: /* EMIFS_CS0_CONFIG */ 1317 case 0x14: /* EMIFS_CS1_CONFIG */ 1318 case 0x18: /* EMIFS_CS2_CONFIG */ 1319 case 0x1c: /* EMIFS_CS3_CONFIG */ 1320 case 0x20: /* EMIFF_SDRAM_CONFIG */ 1321 case 0x24: /* EMIFF_MRS */ 1322 case 0x28: /* TIMEOUT1 */ 1323 case 0x2c: /* TIMEOUT2 */ 1324 case 0x30: /* TIMEOUT3 */ 1325 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ 1326 case 0x40: /* EMIFS_CFG_DYN_WAIT */ 1327 s->tcmi_regs[addr >> 2] = value; 1328 break; 1329 case 0x0c: /* EMIFS_CONFIG */ 1330 s->tcmi_regs[addr >> 2] = (value & 0xf) | (1 << 4); 1331 break; 1332 1333 default: 1334 OMAP_BAD_REG(addr); 1335 } 1336 } 1337 1338 static const MemoryRegionOps omap_tcmi_ops = { 1339 .read = omap_tcmi_read, 1340 .write = omap_tcmi_write, 1341 .endianness = DEVICE_NATIVE_ENDIAN, 1342 }; 1343 1344 static void omap_tcmi_reset(struct omap_mpu_state_s *mpu) 1345 { 1346 mpu->tcmi_regs[0x00 >> 2] = 0x00000000; 1347 mpu->tcmi_regs[0x04 >> 2] = 0x00000000; 1348 mpu->tcmi_regs[0x08 >> 2] = 0x00000000; 1349 mpu->tcmi_regs[0x0c >> 2] = 0x00000010; 1350 mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb; 1351 mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb; 1352 mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb; 1353 mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb; 1354 mpu->tcmi_regs[0x20 >> 2] = 0x00618800; 1355 mpu->tcmi_regs[0x24 >> 2] = 0x00000037; 1356 mpu->tcmi_regs[0x28 >> 2] = 0x00000000; 1357 mpu->tcmi_regs[0x2c >> 2] = 0x00000000; 1358 mpu->tcmi_regs[0x30 >> 2] = 0x00000000; 1359 mpu->tcmi_regs[0x3c >> 2] = 0x00000003; 1360 mpu->tcmi_regs[0x40 >> 2] = 0x00000000; 1361 } 1362 1363 static void omap_tcmi_init(MemoryRegion *memory, hwaddr base, 1364 struct omap_mpu_state_s *mpu) 1365 { 1366 memory_region_init_io(&mpu->tcmi_iomem, NULL, &omap_tcmi_ops, mpu, 1367 "omap-tcmi", 0x100); 1368 memory_region_add_subregion(memory, base, &mpu->tcmi_iomem); 1369 omap_tcmi_reset(mpu); 1370 } 1371 1372 /* Digital phase-locked loops control */ 1373 struct dpll_ctl_s { 1374 MemoryRegion iomem; 1375 uint16_t mode; 1376 omap_clk dpll; 1377 }; 1378 1379 static uint64_t omap_dpll_read(void *opaque, hwaddr addr, 1380 unsigned size) 1381 { 1382 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; 1383 1384 if (size != 2) { 1385 return omap_badwidth_read16(opaque, addr); 1386 } 1387 1388 if (addr == 0x00) /* CTL_REG */ 1389 return s->mode; 1390 1391 OMAP_BAD_REG(addr); 1392 return 0; 1393 } 1394 1395 static void omap_dpll_write(void *opaque, hwaddr addr, 1396 uint64_t value, unsigned size) 1397 { 1398 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; 1399 uint16_t diff; 1400 static const int bypass_div[4] = { 1, 2, 4, 4 }; 1401 int div, mult; 1402 1403 if (size != 2) { 1404 omap_badwidth_write16(opaque, addr, value); 1405 return; 1406 } 1407 1408 if (addr == 0x00) { /* CTL_REG */ 1409 /* See omap_ulpd_pm_write() too */ 1410 diff = s->mode & value; 1411 s->mode = value & 0x2fff; 1412 if (diff & (0x3ff << 2)) { 1413 if (value & (1 << 4)) { /* PLL_ENABLE */ 1414 div = ((value >> 5) & 3) + 1; /* PLL_DIV */ 1415 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ 1416 } else { 1417 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ 1418 mult = 1; 1419 } 1420 omap_clk_setrate(s->dpll, div, mult); 1421 } 1422 1423 /* Enter the desired mode. */ 1424 s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1); 1425 1426 /* Act as if the lock is restored. */ 1427 s->mode |= 2; 1428 } else { 1429 OMAP_BAD_REG(addr); 1430 } 1431 } 1432 1433 static const MemoryRegionOps omap_dpll_ops = { 1434 .read = omap_dpll_read, 1435 .write = omap_dpll_write, 1436 .endianness = DEVICE_NATIVE_ENDIAN, 1437 }; 1438 1439 static void omap_dpll_reset(struct dpll_ctl_s *s) 1440 { 1441 s->mode = 0x2002; 1442 omap_clk_setrate(s->dpll, 1, 1); 1443 } 1444 1445 static struct dpll_ctl_s *omap_dpll_init(MemoryRegion *memory, 1446 hwaddr base, omap_clk clk) 1447 { 1448 struct dpll_ctl_s *s = g_malloc0(sizeof(*s)); 1449 memory_region_init_io(&s->iomem, NULL, &omap_dpll_ops, s, "omap-dpll", 0x100); 1450 1451 s->dpll = clk; 1452 omap_dpll_reset(s); 1453 1454 memory_region_add_subregion(memory, base, &s->iomem); 1455 return s; 1456 } 1457 1458 /* MPU Clock/Reset/Power Mode Control */ 1459 static uint64_t omap_clkm_read(void *opaque, hwaddr addr, 1460 unsigned size) 1461 { 1462 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1463 1464 if (size != 2) { 1465 return omap_badwidth_read16(opaque, addr); 1466 } 1467 1468 switch (addr) { 1469 case 0x00: /* ARM_CKCTL */ 1470 return s->clkm.arm_ckctl; 1471 1472 case 0x04: /* ARM_IDLECT1 */ 1473 return s->clkm.arm_idlect1; 1474 1475 case 0x08: /* ARM_IDLECT2 */ 1476 return s->clkm.arm_idlect2; 1477 1478 case 0x0c: /* ARM_EWUPCT */ 1479 return s->clkm.arm_ewupct; 1480 1481 case 0x10: /* ARM_RSTCT1 */ 1482 return s->clkm.arm_rstct1; 1483 1484 case 0x14: /* ARM_RSTCT2 */ 1485 return s->clkm.arm_rstct2; 1486 1487 case 0x18: /* ARM_SYSST */ 1488 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start; 1489 1490 case 0x1c: /* ARM_CKOUT1 */ 1491 return s->clkm.arm_ckout1; 1492 1493 case 0x20: /* ARM_CKOUT2 */ 1494 break; 1495 } 1496 1497 OMAP_BAD_REG(addr); 1498 return 0; 1499 } 1500 1501 static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s, 1502 uint16_t diff, uint16_t value) 1503 { 1504 omap_clk clk; 1505 1506 if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */ 1507 if (value & (1 << 14)) 1508 /* Reserved */; 1509 else { 1510 clk = omap_findclk(s, "arminth_ck"); 1511 omap_clk_reparent(clk, omap_findclk(s, "tc_ck")); 1512 } 1513 } 1514 if (diff & (1 << 12)) { /* ARM_TIMXO */ 1515 clk = omap_findclk(s, "armtim_ck"); 1516 if (value & (1 << 12)) 1517 omap_clk_reparent(clk, omap_findclk(s, "clkin")); 1518 else 1519 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1")); 1520 } 1521 /* XXX: en_dspck */ 1522 if (diff & (3 << 10)) { /* DSPMMUDIV */ 1523 clk = omap_findclk(s, "dspmmu_ck"); 1524 omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1); 1525 } 1526 if (diff & (3 << 8)) { /* TCDIV */ 1527 clk = omap_findclk(s, "tc_ck"); 1528 omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1); 1529 } 1530 if (diff & (3 << 6)) { /* DSPDIV */ 1531 clk = omap_findclk(s, "dsp_ck"); 1532 omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1); 1533 } 1534 if (diff & (3 << 4)) { /* ARMDIV */ 1535 clk = omap_findclk(s, "arm_ck"); 1536 omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1); 1537 } 1538 if (diff & (3 << 2)) { /* LCDDIV */ 1539 clk = omap_findclk(s, "lcd_ck"); 1540 omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1); 1541 } 1542 if (diff & (3 << 0)) { /* PERDIV */ 1543 clk = omap_findclk(s, "armper_ck"); 1544 omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1); 1545 } 1546 } 1547 1548 static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s, 1549 uint16_t diff, uint16_t value) 1550 { 1551 omap_clk clk; 1552 1553 if (value & (1 << 11)) { /* SETARM_IDLE */ 1554 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); 1555 } 1556 if (!(value & (1 << 10))) { /* WKUP_MODE */ 1557 /* XXX: disable wakeup from IRQ */ 1558 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 1559 } 1560 1561 #define SET_CANIDLE(clock, bit) \ 1562 if (diff & (1 << bit)) { \ 1563 clk = omap_findclk(s, clock); \ 1564 omap_clk_canidle(clk, (value >> bit) & 1); \ 1565 } 1566 SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */ 1567 SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */ 1568 SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */ 1569 SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */ 1570 SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */ 1571 SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */ 1572 SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */ 1573 SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */ 1574 SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */ 1575 SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */ 1576 SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */ 1577 SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */ 1578 SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */ 1579 SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */ 1580 } 1581 1582 static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s, 1583 uint16_t diff, uint16_t value) 1584 { 1585 omap_clk clk; 1586 1587 #define SET_ONOFF(clock, bit) \ 1588 if (diff & (1 << bit)) { \ 1589 clk = omap_findclk(s, clock); \ 1590 omap_clk_onoff(clk, (value >> bit) & 1); \ 1591 } 1592 SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */ 1593 SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */ 1594 SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */ 1595 SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */ 1596 SET_ONOFF("lb_ck", 4) /* EN_LBCK */ 1597 SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */ 1598 SET_ONOFF("mpui_ck", 6) /* EN_APICK */ 1599 SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */ 1600 SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */ 1601 SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */ 1602 SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */ 1603 } 1604 1605 static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s, 1606 uint16_t diff, uint16_t value) 1607 { 1608 omap_clk clk; 1609 1610 if (diff & (3 << 4)) { /* TCLKOUT */ 1611 clk = omap_findclk(s, "tclk_out"); 1612 switch ((value >> 4) & 3) { 1613 case 1: 1614 omap_clk_reparent(clk, omap_findclk(s, "ck_gen3")); 1615 omap_clk_onoff(clk, 1); 1616 break; 1617 case 2: 1618 omap_clk_reparent(clk, omap_findclk(s, "tc_ck")); 1619 omap_clk_onoff(clk, 1); 1620 break; 1621 default: 1622 omap_clk_onoff(clk, 0); 1623 } 1624 } 1625 if (diff & (3 << 2)) { /* DCLKOUT */ 1626 clk = omap_findclk(s, "dclk_out"); 1627 switch ((value >> 2) & 3) { 1628 case 0: 1629 omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck")); 1630 break; 1631 case 1: 1632 omap_clk_reparent(clk, omap_findclk(s, "ck_gen2")); 1633 break; 1634 case 2: 1635 omap_clk_reparent(clk, omap_findclk(s, "dsp_ck")); 1636 break; 1637 case 3: 1638 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14")); 1639 break; 1640 } 1641 } 1642 if (diff & (3 << 0)) { /* ACLKOUT */ 1643 clk = omap_findclk(s, "aclk_out"); 1644 switch ((value >> 0) & 3) { 1645 case 1: 1646 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1")); 1647 omap_clk_onoff(clk, 1); 1648 break; 1649 case 2: 1650 omap_clk_reparent(clk, omap_findclk(s, "arm_ck")); 1651 omap_clk_onoff(clk, 1); 1652 break; 1653 case 3: 1654 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14")); 1655 omap_clk_onoff(clk, 1); 1656 break; 1657 default: 1658 omap_clk_onoff(clk, 0); 1659 } 1660 } 1661 } 1662 1663 static void omap_clkm_write(void *opaque, hwaddr addr, 1664 uint64_t value, unsigned size) 1665 { 1666 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1667 uint16_t diff; 1668 omap_clk clk; 1669 static const char *clkschemename[8] = { 1670 "fully synchronous", "fully asynchronous", "synchronous scalable", 1671 "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4", 1672 }; 1673 1674 if (size != 2) { 1675 omap_badwidth_write16(opaque, addr, value); 1676 return; 1677 } 1678 1679 switch (addr) { 1680 case 0x00: /* ARM_CKCTL */ 1681 diff = s->clkm.arm_ckctl ^ value; 1682 s->clkm.arm_ckctl = value & 0x7fff; 1683 omap_clkm_ckctl_update(s, diff, value); 1684 return; 1685 1686 case 0x04: /* ARM_IDLECT1 */ 1687 diff = s->clkm.arm_idlect1 ^ value; 1688 s->clkm.arm_idlect1 = value & 0x0fff; 1689 omap_clkm_idlect1_update(s, diff, value); 1690 return; 1691 1692 case 0x08: /* ARM_IDLECT2 */ 1693 diff = s->clkm.arm_idlect2 ^ value; 1694 s->clkm.arm_idlect2 = value & 0x07ff; 1695 omap_clkm_idlect2_update(s, diff, value); 1696 return; 1697 1698 case 0x0c: /* ARM_EWUPCT */ 1699 s->clkm.arm_ewupct = value & 0x003f; 1700 return; 1701 1702 case 0x10: /* ARM_RSTCT1 */ 1703 diff = s->clkm.arm_rstct1 ^ value; 1704 s->clkm.arm_rstct1 = value & 0x0007; 1705 if (value & 9) { 1706 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 1707 s->clkm.cold_start = 0xa; 1708 } 1709 if (diff & ~value & 4) { /* DSP_RST */ 1710 omap_mpui_reset(s); 1711 omap_tipb_bridge_reset(s->private_tipb); 1712 omap_tipb_bridge_reset(s->public_tipb); 1713 } 1714 if (diff & 2) { /* DSP_EN */ 1715 clk = omap_findclk(s, "dsp_ck"); 1716 omap_clk_canidle(clk, (~value >> 1) & 1); 1717 } 1718 return; 1719 1720 case 0x14: /* ARM_RSTCT2 */ 1721 s->clkm.arm_rstct2 = value & 0x0001; 1722 return; 1723 1724 case 0x18: /* ARM_SYSST */ 1725 if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) { 1726 s->clkm.clocking_scheme = (value >> 11) & 7; 1727 printf("%s: clocking scheme set to %s\n", __func__, 1728 clkschemename[s->clkm.clocking_scheme]); 1729 } 1730 s->clkm.cold_start &= value & 0x3f; 1731 return; 1732 1733 case 0x1c: /* ARM_CKOUT1 */ 1734 diff = s->clkm.arm_ckout1 ^ value; 1735 s->clkm.arm_ckout1 = value & 0x003f; 1736 omap_clkm_ckout1_update(s, diff, value); 1737 return; 1738 1739 case 0x20: /* ARM_CKOUT2 */ 1740 default: 1741 OMAP_BAD_REG(addr); 1742 } 1743 } 1744 1745 static const MemoryRegionOps omap_clkm_ops = { 1746 .read = omap_clkm_read, 1747 .write = omap_clkm_write, 1748 .endianness = DEVICE_NATIVE_ENDIAN, 1749 }; 1750 1751 static uint64_t omap_clkdsp_read(void *opaque, hwaddr addr, 1752 unsigned size) 1753 { 1754 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1755 CPUState *cpu = CPU(s->cpu); 1756 1757 if (size != 2) { 1758 return omap_badwidth_read16(opaque, addr); 1759 } 1760 1761 switch (addr) { 1762 case 0x04: /* DSP_IDLECT1 */ 1763 return s->clkm.dsp_idlect1; 1764 1765 case 0x08: /* DSP_IDLECT2 */ 1766 return s->clkm.dsp_idlect2; 1767 1768 case 0x14: /* DSP_RSTCT2 */ 1769 return s->clkm.dsp_rstct2; 1770 1771 case 0x18: /* DSP_SYSST */ 1772 cpu = CPU(s->cpu); 1773 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start | 1774 (cpu->halted << 6); /* Quite useless... */ 1775 } 1776 1777 OMAP_BAD_REG(addr); 1778 return 0; 1779 } 1780 1781 static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s, 1782 uint16_t diff, uint16_t value) 1783 { 1784 omap_clk clk; 1785 1786 SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */ 1787 } 1788 1789 static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s, 1790 uint16_t diff, uint16_t value) 1791 { 1792 omap_clk clk; 1793 1794 SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */ 1795 } 1796 1797 static void omap_clkdsp_write(void *opaque, hwaddr addr, 1798 uint64_t value, unsigned size) 1799 { 1800 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1801 uint16_t diff; 1802 1803 if (size != 2) { 1804 omap_badwidth_write16(opaque, addr, value); 1805 return; 1806 } 1807 1808 switch (addr) { 1809 case 0x04: /* DSP_IDLECT1 */ 1810 diff = s->clkm.dsp_idlect1 ^ value; 1811 s->clkm.dsp_idlect1 = value & 0x01f7; 1812 omap_clkdsp_idlect1_update(s, diff, value); 1813 break; 1814 1815 case 0x08: /* DSP_IDLECT2 */ 1816 s->clkm.dsp_idlect2 = value & 0x0037; 1817 diff = s->clkm.dsp_idlect1 ^ value; 1818 omap_clkdsp_idlect2_update(s, diff, value); 1819 break; 1820 1821 case 0x14: /* DSP_RSTCT2 */ 1822 s->clkm.dsp_rstct2 = value & 0x0001; 1823 break; 1824 1825 case 0x18: /* DSP_SYSST */ 1826 s->clkm.cold_start &= value & 0x3f; 1827 break; 1828 1829 default: 1830 OMAP_BAD_REG(addr); 1831 } 1832 } 1833 1834 static const MemoryRegionOps omap_clkdsp_ops = { 1835 .read = omap_clkdsp_read, 1836 .write = omap_clkdsp_write, 1837 .endianness = DEVICE_NATIVE_ENDIAN, 1838 }; 1839 1840 static void omap_clkm_reset(struct omap_mpu_state_s *s) 1841 { 1842 if (s->wdt && s->wdt->reset) 1843 s->clkm.cold_start = 0x6; 1844 s->clkm.clocking_scheme = 0; 1845 omap_clkm_ckctl_update(s, ~0, 0x3000); 1846 s->clkm.arm_ckctl = 0x3000; 1847 omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 ^ 0x0400, 0x0400); 1848 s->clkm.arm_idlect1 = 0x0400; 1849 omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 ^ 0x0100, 0x0100); 1850 s->clkm.arm_idlect2 = 0x0100; 1851 s->clkm.arm_ewupct = 0x003f; 1852 s->clkm.arm_rstct1 = 0x0000; 1853 s->clkm.arm_rstct2 = 0x0000; 1854 s->clkm.arm_ckout1 = 0x0015; 1855 s->clkm.dpll1_mode = 0x2002; 1856 omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040); 1857 s->clkm.dsp_idlect1 = 0x0040; 1858 omap_clkdsp_idlect2_update(s, ~0, 0x0000); 1859 s->clkm.dsp_idlect2 = 0x0000; 1860 s->clkm.dsp_rstct2 = 0x0000; 1861 } 1862 1863 static void omap_clkm_init(MemoryRegion *memory, hwaddr mpu_base, 1864 hwaddr dsp_base, struct omap_mpu_state_s *s) 1865 { 1866 memory_region_init_io(&s->clkm_iomem, NULL, &omap_clkm_ops, s, 1867 "omap-clkm", 0x100); 1868 memory_region_init_io(&s->clkdsp_iomem, NULL, &omap_clkdsp_ops, s, 1869 "omap-clkdsp", 0x1000); 1870 1871 s->clkm.arm_idlect1 = 0x03ff; 1872 s->clkm.arm_idlect2 = 0x0100; 1873 s->clkm.dsp_idlect1 = 0x0002; 1874 omap_clkm_reset(s); 1875 s->clkm.cold_start = 0x3a; 1876 1877 memory_region_add_subregion(memory, mpu_base, &s->clkm_iomem); 1878 memory_region_add_subregion(memory, dsp_base, &s->clkdsp_iomem); 1879 } 1880 1881 /* MPU I/O */ 1882 struct omap_mpuio_s { 1883 qemu_irq irq; 1884 qemu_irq kbd_irq; 1885 qemu_irq *in; 1886 qemu_irq handler[16]; 1887 qemu_irq wakeup; 1888 MemoryRegion iomem; 1889 1890 uint16_t inputs; 1891 uint16_t outputs; 1892 uint16_t dir; 1893 uint16_t edge; 1894 uint16_t mask; 1895 uint16_t ints; 1896 1897 uint16_t debounce; 1898 uint16_t latch; 1899 uint8_t event; 1900 1901 uint8_t buttons[5]; 1902 uint8_t row_latch; 1903 uint8_t cols; 1904 int kbd_mask; 1905 int clk; 1906 }; 1907 1908 static void omap_mpuio_set(void *opaque, int line, int level) 1909 { 1910 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; 1911 uint16_t prev = s->inputs; 1912 1913 if (level) 1914 s->inputs |= 1 << line; 1915 else 1916 s->inputs &= ~(1 << line); 1917 1918 if (((1 << line) & s->dir & ~s->mask) && s->clk) { 1919 if ((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) { 1920 s->ints |= 1 << line; 1921 qemu_irq_raise(s->irq); 1922 /* TODO: wakeup */ 1923 } 1924 if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */ 1925 (s->event >> 1) == line) /* PIN_SELECT */ 1926 s->latch = s->inputs; 1927 } 1928 } 1929 1930 static void omap_mpuio_kbd_update(struct omap_mpuio_s *s) 1931 { 1932 int i; 1933 uint8_t *row, rows = 0, cols = ~s->cols; 1934 1935 for (row = s->buttons + 4, i = 1 << 4; i; row --, i >>= 1) 1936 if (*row & cols) 1937 rows |= i; 1938 1939 qemu_set_irq(s->kbd_irq, rows && !s->kbd_mask && s->clk); 1940 s->row_latch = ~rows; 1941 } 1942 1943 static uint64_t omap_mpuio_read(void *opaque, hwaddr addr, 1944 unsigned size) 1945 { 1946 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; 1947 int offset = addr & OMAP_MPUI_REG_MASK; 1948 uint16_t ret; 1949 1950 if (size != 2) { 1951 return omap_badwidth_read16(opaque, addr); 1952 } 1953 1954 switch (offset) { 1955 case 0x00: /* INPUT_LATCH */ 1956 return s->inputs; 1957 1958 case 0x04: /* OUTPUT_REG */ 1959 return s->outputs; 1960 1961 case 0x08: /* IO_CNTL */ 1962 return s->dir; 1963 1964 case 0x10: /* KBR_LATCH */ 1965 return s->row_latch; 1966 1967 case 0x14: /* KBC_REG */ 1968 return s->cols; 1969 1970 case 0x18: /* GPIO_EVENT_MODE_REG */ 1971 return s->event; 1972 1973 case 0x1c: /* GPIO_INT_EDGE_REG */ 1974 return s->edge; 1975 1976 case 0x20: /* KBD_INT */ 1977 return (~s->row_latch & 0x1f) && !s->kbd_mask; 1978 1979 case 0x24: /* GPIO_INT */ 1980 ret = s->ints; 1981 s->ints &= s->mask; 1982 if (ret) 1983 qemu_irq_lower(s->irq); 1984 return ret; 1985 1986 case 0x28: /* KBD_MASKIT */ 1987 return s->kbd_mask; 1988 1989 case 0x2c: /* GPIO_MASKIT */ 1990 return s->mask; 1991 1992 case 0x30: /* GPIO_DEBOUNCING_REG */ 1993 return s->debounce; 1994 1995 case 0x34: /* GPIO_LATCH_REG */ 1996 return s->latch; 1997 } 1998 1999 OMAP_BAD_REG(addr); 2000 return 0; 2001 } 2002 2003 static void omap_mpuio_write(void *opaque, hwaddr addr, 2004 uint64_t value, unsigned size) 2005 { 2006 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; 2007 int offset = addr & OMAP_MPUI_REG_MASK; 2008 uint16_t diff; 2009 int ln; 2010 2011 if (size != 2) { 2012 omap_badwidth_write16(opaque, addr, value); 2013 return; 2014 } 2015 2016 switch (offset) { 2017 case 0x04: /* OUTPUT_REG */ 2018 diff = (s->outputs ^ value) & ~s->dir; 2019 s->outputs = value; 2020 while ((ln = ctz32(diff)) != 32) { 2021 if (s->handler[ln]) 2022 qemu_set_irq(s->handler[ln], (value >> ln) & 1); 2023 diff &= ~(1 << ln); 2024 } 2025 break; 2026 2027 case 0x08: /* IO_CNTL */ 2028 diff = s->outputs & (s->dir ^ value); 2029 s->dir = value; 2030 2031 value = s->outputs & ~s->dir; 2032 while ((ln = ctz32(diff)) != 32) { 2033 if (s->handler[ln]) 2034 qemu_set_irq(s->handler[ln], (value >> ln) & 1); 2035 diff &= ~(1 << ln); 2036 } 2037 break; 2038 2039 case 0x14: /* KBC_REG */ 2040 s->cols = value; 2041 omap_mpuio_kbd_update(s); 2042 break; 2043 2044 case 0x18: /* GPIO_EVENT_MODE_REG */ 2045 s->event = value & 0x1f; 2046 break; 2047 2048 case 0x1c: /* GPIO_INT_EDGE_REG */ 2049 s->edge = value; 2050 break; 2051 2052 case 0x28: /* KBD_MASKIT */ 2053 s->kbd_mask = value & 1; 2054 omap_mpuio_kbd_update(s); 2055 break; 2056 2057 case 0x2c: /* GPIO_MASKIT */ 2058 s->mask = value; 2059 break; 2060 2061 case 0x30: /* GPIO_DEBOUNCING_REG */ 2062 s->debounce = value & 0x1ff; 2063 break; 2064 2065 case 0x00: /* INPUT_LATCH */ 2066 case 0x10: /* KBR_LATCH */ 2067 case 0x20: /* KBD_INT */ 2068 case 0x24: /* GPIO_INT */ 2069 case 0x34: /* GPIO_LATCH_REG */ 2070 OMAP_RO_REG(addr); 2071 return; 2072 2073 default: 2074 OMAP_BAD_REG(addr); 2075 return; 2076 } 2077 } 2078 2079 static const MemoryRegionOps omap_mpuio_ops = { 2080 .read = omap_mpuio_read, 2081 .write = omap_mpuio_write, 2082 .endianness = DEVICE_NATIVE_ENDIAN, 2083 }; 2084 2085 static void omap_mpuio_reset(struct omap_mpuio_s *s) 2086 { 2087 s->inputs = 0; 2088 s->outputs = 0; 2089 s->dir = ~0; 2090 s->event = 0; 2091 s->edge = 0; 2092 s->kbd_mask = 0; 2093 s->mask = 0; 2094 s->debounce = 0; 2095 s->latch = 0; 2096 s->ints = 0; 2097 s->row_latch = 0x1f; 2098 s->clk = 1; 2099 } 2100 2101 static void omap_mpuio_onoff(void *opaque, int line, int on) 2102 { 2103 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; 2104 2105 s->clk = on; 2106 if (on) 2107 omap_mpuio_kbd_update(s); 2108 } 2109 2110 static struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *memory, 2111 hwaddr base, 2112 qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup, 2113 omap_clk clk) 2114 { 2115 struct omap_mpuio_s *s = g_new0(struct omap_mpuio_s, 1); 2116 2117 s->irq = gpio_int; 2118 s->kbd_irq = kbd_int; 2119 s->wakeup = wakeup; 2120 s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16); 2121 omap_mpuio_reset(s); 2122 2123 memory_region_init_io(&s->iomem, NULL, &omap_mpuio_ops, s, 2124 "omap-mpuio", 0x800); 2125 memory_region_add_subregion(memory, base, &s->iomem); 2126 2127 omap_clk_adduser(clk, qemu_allocate_irq(omap_mpuio_onoff, s, 0)); 2128 2129 return s; 2130 } 2131 2132 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s) 2133 { 2134 return s->in; 2135 } 2136 2137 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler) 2138 { 2139 if (line >= 16 || line < 0) 2140 hw_error("%s: No GPIO line %i\n", __func__, line); 2141 s->handler[line] = handler; 2142 } 2143 2144 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down) 2145 { 2146 if (row >= 5 || row < 0) 2147 hw_error("%s: No key %i-%i\n", __func__, col, row); 2148 2149 if (down) 2150 s->buttons[row] |= 1 << col; 2151 else 2152 s->buttons[row] &= ~(1 << col); 2153 2154 omap_mpuio_kbd_update(s); 2155 } 2156 2157 /* MicroWire Interface */ 2158 struct omap_uwire_s { 2159 MemoryRegion iomem; 2160 qemu_irq txirq; 2161 qemu_irq rxirq; 2162 qemu_irq txdrq; 2163 2164 uint16_t txbuf; 2165 uint16_t rxbuf; 2166 uint16_t control; 2167 uint16_t setup[5]; 2168 2169 uWireSlave *chip[4]; 2170 }; 2171 2172 static void omap_uwire_transfer_start(struct omap_uwire_s *s) 2173 { 2174 int chipselect = (s->control >> 10) & 3; /* INDEX */ 2175 uWireSlave *slave = s->chip[chipselect]; 2176 2177 if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */ 2178 if (s->control & (1 << 12)) /* CS_CMD */ 2179 if (slave && slave->send) 2180 slave->send(slave->opaque, 2181 s->txbuf >> (16 - ((s->control >> 5) & 0x1f))); 2182 s->control &= ~(1 << 14); /* CSRB */ 2183 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or 2184 * a DRQ. When is the level IRQ supposed to be reset? */ 2185 } 2186 2187 if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */ 2188 if (s->control & (1 << 12)) /* CS_CMD */ 2189 if (slave && slave->receive) 2190 s->rxbuf = slave->receive(slave->opaque); 2191 s->control |= 1 << 15; /* RDRB */ 2192 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or 2193 * a DRQ. When is the level IRQ supposed to be reset? */ 2194 } 2195 } 2196 2197 static uint64_t omap_uwire_read(void *opaque, hwaddr addr, 2198 unsigned size) 2199 { 2200 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; 2201 int offset = addr & OMAP_MPUI_REG_MASK; 2202 2203 if (size != 2) { 2204 return omap_badwidth_read16(opaque, addr); 2205 } 2206 2207 switch (offset) { 2208 case 0x00: /* RDR */ 2209 s->control &= ~(1 << 15); /* RDRB */ 2210 return s->rxbuf; 2211 2212 case 0x04: /* CSR */ 2213 return s->control; 2214 2215 case 0x08: /* SR1 */ 2216 return s->setup[0]; 2217 case 0x0c: /* SR2 */ 2218 return s->setup[1]; 2219 case 0x10: /* SR3 */ 2220 return s->setup[2]; 2221 case 0x14: /* SR4 */ 2222 return s->setup[3]; 2223 case 0x18: /* SR5 */ 2224 return s->setup[4]; 2225 } 2226 2227 OMAP_BAD_REG(addr); 2228 return 0; 2229 } 2230 2231 static void omap_uwire_write(void *opaque, hwaddr addr, 2232 uint64_t value, unsigned size) 2233 { 2234 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; 2235 int offset = addr & OMAP_MPUI_REG_MASK; 2236 2237 if (size != 2) { 2238 omap_badwidth_write16(opaque, addr, value); 2239 return; 2240 } 2241 2242 switch (offset) { 2243 case 0x00: /* TDR */ 2244 s->txbuf = value; /* TD */ 2245 if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */ 2246 ((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */ 2247 (s->control & (1 << 12)))) { /* CS_CMD */ 2248 s->control |= 1 << 14; /* CSRB */ 2249 omap_uwire_transfer_start(s); 2250 } 2251 break; 2252 2253 case 0x04: /* CSR */ 2254 s->control = value & 0x1fff; 2255 if (value & (1 << 13)) /* START */ 2256 omap_uwire_transfer_start(s); 2257 break; 2258 2259 case 0x08: /* SR1 */ 2260 s->setup[0] = value & 0x003f; 2261 break; 2262 2263 case 0x0c: /* SR2 */ 2264 s->setup[1] = value & 0x0fc0; 2265 break; 2266 2267 case 0x10: /* SR3 */ 2268 s->setup[2] = value & 0x0003; 2269 break; 2270 2271 case 0x14: /* SR4 */ 2272 s->setup[3] = value & 0x0001; 2273 break; 2274 2275 case 0x18: /* SR5 */ 2276 s->setup[4] = value & 0x000f; 2277 break; 2278 2279 default: 2280 OMAP_BAD_REG(addr); 2281 return; 2282 } 2283 } 2284 2285 static const MemoryRegionOps omap_uwire_ops = { 2286 .read = omap_uwire_read, 2287 .write = omap_uwire_write, 2288 .endianness = DEVICE_NATIVE_ENDIAN, 2289 }; 2290 2291 static void omap_uwire_reset(struct omap_uwire_s *s) 2292 { 2293 s->control = 0; 2294 s->setup[0] = 0; 2295 s->setup[1] = 0; 2296 s->setup[2] = 0; 2297 s->setup[3] = 0; 2298 s->setup[4] = 0; 2299 } 2300 2301 static struct omap_uwire_s *omap_uwire_init(MemoryRegion *system_memory, 2302 hwaddr base, 2303 qemu_irq txirq, qemu_irq rxirq, 2304 qemu_irq dma, 2305 omap_clk clk) 2306 { 2307 struct omap_uwire_s *s = g_new0(struct omap_uwire_s, 1); 2308 2309 s->txirq = txirq; 2310 s->rxirq = rxirq; 2311 s->txdrq = dma; 2312 omap_uwire_reset(s); 2313 2314 memory_region_init_io(&s->iomem, NULL, &omap_uwire_ops, s, "omap-uwire", 0x800); 2315 memory_region_add_subregion(system_memory, base, &s->iomem); 2316 2317 return s; 2318 } 2319 2320 void omap_uwire_attach(struct omap_uwire_s *s, 2321 uWireSlave *slave, int chipselect) 2322 { 2323 if (chipselect < 0 || chipselect > 3) { 2324 error_report("%s: Bad chipselect %i", __func__, chipselect); 2325 exit(-1); 2326 } 2327 2328 s->chip[chipselect] = slave; 2329 } 2330 2331 /* Pseudonoise Pulse-Width Light Modulator */ 2332 struct omap_pwl_s { 2333 MemoryRegion iomem; 2334 uint8_t output; 2335 uint8_t level; 2336 uint8_t enable; 2337 int clk; 2338 }; 2339 2340 static void omap_pwl_update(struct omap_pwl_s *s) 2341 { 2342 int output = (s->clk && s->enable) ? s->level : 0; 2343 2344 if (output != s->output) { 2345 s->output = output; 2346 printf("%s: Backlight now at %i/256\n", __func__, output); 2347 } 2348 } 2349 2350 static uint64_t omap_pwl_read(void *opaque, hwaddr addr, 2351 unsigned size) 2352 { 2353 struct omap_pwl_s *s = (struct omap_pwl_s *) opaque; 2354 int offset = addr & OMAP_MPUI_REG_MASK; 2355 2356 if (size != 1) { 2357 return omap_badwidth_read8(opaque, addr); 2358 } 2359 2360 switch (offset) { 2361 case 0x00: /* PWL_LEVEL */ 2362 return s->level; 2363 case 0x04: /* PWL_CTRL */ 2364 return s->enable; 2365 } 2366 OMAP_BAD_REG(addr); 2367 return 0; 2368 } 2369 2370 static void omap_pwl_write(void *opaque, hwaddr addr, 2371 uint64_t value, unsigned size) 2372 { 2373 struct omap_pwl_s *s = (struct omap_pwl_s *) opaque; 2374 int offset = addr & OMAP_MPUI_REG_MASK; 2375 2376 if (size != 1) { 2377 omap_badwidth_write8(opaque, addr, value); 2378 return; 2379 } 2380 2381 switch (offset) { 2382 case 0x00: /* PWL_LEVEL */ 2383 s->level = value; 2384 omap_pwl_update(s); 2385 break; 2386 case 0x04: /* PWL_CTRL */ 2387 s->enable = value & 1; 2388 omap_pwl_update(s); 2389 break; 2390 default: 2391 OMAP_BAD_REG(addr); 2392 return; 2393 } 2394 } 2395 2396 static const MemoryRegionOps omap_pwl_ops = { 2397 .read = omap_pwl_read, 2398 .write = omap_pwl_write, 2399 .endianness = DEVICE_NATIVE_ENDIAN, 2400 }; 2401 2402 static void omap_pwl_reset(struct omap_pwl_s *s) 2403 { 2404 s->output = 0; 2405 s->level = 0; 2406 s->enable = 0; 2407 s->clk = 1; 2408 omap_pwl_update(s); 2409 } 2410 2411 static void omap_pwl_clk_update(void *opaque, int line, int on) 2412 { 2413 struct omap_pwl_s *s = (struct omap_pwl_s *) opaque; 2414 2415 s->clk = on; 2416 omap_pwl_update(s); 2417 } 2418 2419 static struct omap_pwl_s *omap_pwl_init(MemoryRegion *system_memory, 2420 hwaddr base, 2421 omap_clk clk) 2422 { 2423 struct omap_pwl_s *s = g_malloc0(sizeof(*s)); 2424 2425 omap_pwl_reset(s); 2426 2427 memory_region_init_io(&s->iomem, NULL, &omap_pwl_ops, s, 2428 "omap-pwl", 0x800); 2429 memory_region_add_subregion(system_memory, base, &s->iomem); 2430 2431 omap_clk_adduser(clk, qemu_allocate_irq(omap_pwl_clk_update, s, 0)); 2432 return s; 2433 } 2434 2435 /* Pulse-Width Tone module */ 2436 struct omap_pwt_s { 2437 MemoryRegion iomem; 2438 uint8_t frc; 2439 uint8_t vrc; 2440 uint8_t gcr; 2441 omap_clk clk; 2442 }; 2443 2444 static uint64_t omap_pwt_read(void *opaque, hwaddr addr, 2445 unsigned size) 2446 { 2447 struct omap_pwt_s *s = (struct omap_pwt_s *) opaque; 2448 int offset = addr & OMAP_MPUI_REG_MASK; 2449 2450 if (size != 1) { 2451 return omap_badwidth_read8(opaque, addr); 2452 } 2453 2454 switch (offset) { 2455 case 0x00: /* FRC */ 2456 return s->frc; 2457 case 0x04: /* VCR */ 2458 return s->vrc; 2459 case 0x08: /* GCR */ 2460 return s->gcr; 2461 } 2462 OMAP_BAD_REG(addr); 2463 return 0; 2464 } 2465 2466 static void omap_pwt_write(void *opaque, hwaddr addr, 2467 uint64_t value, unsigned size) 2468 { 2469 struct omap_pwt_s *s = (struct omap_pwt_s *) opaque; 2470 int offset = addr & OMAP_MPUI_REG_MASK; 2471 2472 if (size != 1) { 2473 omap_badwidth_write8(opaque, addr, value); 2474 return; 2475 } 2476 2477 switch (offset) { 2478 case 0x00: /* FRC */ 2479 s->frc = value & 0x3f; 2480 break; 2481 case 0x04: /* VRC */ 2482 if ((value ^ s->vrc) & 1) { 2483 if (value & 1) 2484 printf("%s: %iHz buzz on\n", __func__, (int) 2485 /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */ 2486 ((omap_clk_getrate(s->clk) >> 3) / 2487 /* Pre-multiplexer divider */ 2488 ((s->gcr & 2) ? 1 : 154) / 2489 /* Octave multiplexer */ 2490 (2 << (value & 3)) * 2491 /* 101/107 divider */ 2492 ((value & (1 << 2)) ? 101 : 107) * 2493 /* 49/55 divider */ 2494 ((value & (1 << 3)) ? 49 : 55) * 2495 /* 50/63 divider */ 2496 ((value & (1 << 4)) ? 50 : 63) * 2497 /* 80/127 divider */ 2498 ((value & (1 << 5)) ? 80 : 127) / 2499 (107 * 55 * 63 * 127))); 2500 else 2501 printf("%s: silence!\n", __func__); 2502 } 2503 s->vrc = value & 0x7f; 2504 break; 2505 case 0x08: /* GCR */ 2506 s->gcr = value & 3; 2507 break; 2508 default: 2509 OMAP_BAD_REG(addr); 2510 return; 2511 } 2512 } 2513 2514 static const MemoryRegionOps omap_pwt_ops = { 2515 .read =omap_pwt_read, 2516 .write = omap_pwt_write, 2517 .endianness = DEVICE_NATIVE_ENDIAN, 2518 }; 2519 2520 static void omap_pwt_reset(struct omap_pwt_s *s) 2521 { 2522 s->frc = 0; 2523 s->vrc = 0; 2524 s->gcr = 0; 2525 } 2526 2527 static struct omap_pwt_s *omap_pwt_init(MemoryRegion *system_memory, 2528 hwaddr base, 2529 omap_clk clk) 2530 { 2531 struct omap_pwt_s *s = g_malloc0(sizeof(*s)); 2532 s->clk = clk; 2533 omap_pwt_reset(s); 2534 2535 memory_region_init_io(&s->iomem, NULL, &omap_pwt_ops, s, 2536 "omap-pwt", 0x800); 2537 memory_region_add_subregion(system_memory, base, &s->iomem); 2538 return s; 2539 } 2540 2541 /* Real-time Clock module */ 2542 struct omap_rtc_s { 2543 MemoryRegion iomem; 2544 qemu_irq irq; 2545 qemu_irq alarm; 2546 QEMUTimer *clk; 2547 2548 uint8_t interrupts; 2549 uint8_t status; 2550 int16_t comp_reg; 2551 int running; 2552 int pm_am; 2553 int auto_comp; 2554 int round; 2555 struct tm alarm_tm; 2556 time_t alarm_ti; 2557 2558 struct tm current_tm; 2559 time_t ti; 2560 uint64_t tick; 2561 }; 2562 2563 static void omap_rtc_interrupts_update(struct omap_rtc_s *s) 2564 { 2565 /* s->alarm is level-triggered */ 2566 qemu_set_irq(s->alarm, (s->status >> 6) & 1); 2567 } 2568 2569 static void omap_rtc_alarm_update(struct omap_rtc_s *s) 2570 { 2571 s->alarm_ti = mktimegm(&s->alarm_tm); 2572 if (s->alarm_ti == -1) 2573 printf("%s: conversion failed\n", __func__); 2574 } 2575 2576 static uint64_t omap_rtc_read(void *opaque, hwaddr addr, 2577 unsigned size) 2578 { 2579 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; 2580 int offset = addr & OMAP_MPUI_REG_MASK; 2581 uint8_t i; 2582 2583 if (size != 1) { 2584 return omap_badwidth_read8(opaque, addr); 2585 } 2586 2587 switch (offset) { 2588 case 0x00: /* SECONDS_REG */ 2589 return to_bcd(s->current_tm.tm_sec); 2590 2591 case 0x04: /* MINUTES_REG */ 2592 return to_bcd(s->current_tm.tm_min); 2593 2594 case 0x08: /* HOURS_REG */ 2595 if (s->pm_am) 2596 return ((s->current_tm.tm_hour > 11) << 7) | 2597 to_bcd(((s->current_tm.tm_hour - 1) % 12) + 1); 2598 else 2599 return to_bcd(s->current_tm.tm_hour); 2600 2601 case 0x0c: /* DAYS_REG */ 2602 return to_bcd(s->current_tm.tm_mday); 2603 2604 case 0x10: /* MONTHS_REG */ 2605 return to_bcd(s->current_tm.tm_mon + 1); 2606 2607 case 0x14: /* YEARS_REG */ 2608 return to_bcd(s->current_tm.tm_year % 100); 2609 2610 case 0x18: /* WEEK_REG */ 2611 return s->current_tm.tm_wday; 2612 2613 case 0x20: /* ALARM_SECONDS_REG */ 2614 return to_bcd(s->alarm_tm.tm_sec); 2615 2616 case 0x24: /* ALARM_MINUTES_REG */ 2617 return to_bcd(s->alarm_tm.tm_min); 2618 2619 case 0x28: /* ALARM_HOURS_REG */ 2620 if (s->pm_am) 2621 return ((s->alarm_tm.tm_hour > 11) << 7) | 2622 to_bcd(((s->alarm_tm.tm_hour - 1) % 12) + 1); 2623 else 2624 return to_bcd(s->alarm_tm.tm_hour); 2625 2626 case 0x2c: /* ALARM_DAYS_REG */ 2627 return to_bcd(s->alarm_tm.tm_mday); 2628 2629 case 0x30: /* ALARM_MONTHS_REG */ 2630 return to_bcd(s->alarm_tm.tm_mon + 1); 2631 2632 case 0x34: /* ALARM_YEARS_REG */ 2633 return to_bcd(s->alarm_tm.tm_year % 100); 2634 2635 case 0x40: /* RTC_CTRL_REG */ 2636 return (s->pm_am << 3) | (s->auto_comp << 2) | 2637 (s->round << 1) | s->running; 2638 2639 case 0x44: /* RTC_STATUS_REG */ 2640 i = s->status; 2641 s->status &= ~0x3d; 2642 return i; 2643 2644 case 0x48: /* RTC_INTERRUPTS_REG */ 2645 return s->interrupts; 2646 2647 case 0x4c: /* RTC_COMP_LSB_REG */ 2648 return ((uint16_t) s->comp_reg) & 0xff; 2649 2650 case 0x50: /* RTC_COMP_MSB_REG */ 2651 return ((uint16_t) s->comp_reg) >> 8; 2652 } 2653 2654 OMAP_BAD_REG(addr); 2655 return 0; 2656 } 2657 2658 static void omap_rtc_write(void *opaque, hwaddr addr, 2659 uint64_t value, unsigned size) 2660 { 2661 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; 2662 int offset = addr & OMAP_MPUI_REG_MASK; 2663 struct tm new_tm; 2664 time_t ti[2]; 2665 2666 if (size != 1) { 2667 omap_badwidth_write8(opaque, addr, value); 2668 return; 2669 } 2670 2671 switch (offset) { 2672 case 0x00: /* SECONDS_REG */ 2673 #ifdef ALMDEBUG 2674 printf("RTC SEC_REG <-- %02x\n", value); 2675 #endif 2676 s->ti -= s->current_tm.tm_sec; 2677 s->ti += from_bcd(value); 2678 return; 2679 2680 case 0x04: /* MINUTES_REG */ 2681 #ifdef ALMDEBUG 2682 printf("RTC MIN_REG <-- %02x\n", value); 2683 #endif 2684 s->ti -= s->current_tm.tm_min * 60; 2685 s->ti += from_bcd(value) * 60; 2686 return; 2687 2688 case 0x08: /* HOURS_REG */ 2689 #ifdef ALMDEBUG 2690 printf("RTC HRS_REG <-- %02x\n", value); 2691 #endif 2692 s->ti -= s->current_tm.tm_hour * 3600; 2693 if (s->pm_am) { 2694 s->ti += (from_bcd(value & 0x3f) & 12) * 3600; 2695 s->ti += ((value >> 7) & 1) * 43200; 2696 } else 2697 s->ti += from_bcd(value & 0x3f) * 3600; 2698 return; 2699 2700 case 0x0c: /* DAYS_REG */ 2701 #ifdef ALMDEBUG 2702 printf("RTC DAY_REG <-- %02x\n", value); 2703 #endif 2704 s->ti -= s->current_tm.tm_mday * 86400; 2705 s->ti += from_bcd(value) * 86400; 2706 return; 2707 2708 case 0x10: /* MONTHS_REG */ 2709 #ifdef ALMDEBUG 2710 printf("RTC MTH_REG <-- %02x\n", value); 2711 #endif 2712 memcpy(&new_tm, &s->current_tm, sizeof(new_tm)); 2713 new_tm.tm_mon = from_bcd(value); 2714 ti[0] = mktimegm(&s->current_tm); 2715 ti[1] = mktimegm(&new_tm); 2716 2717 if (ti[0] != -1 && ti[1] != -1) { 2718 s->ti -= ti[0]; 2719 s->ti += ti[1]; 2720 } else { 2721 /* A less accurate version */ 2722 s->ti -= s->current_tm.tm_mon * 2592000; 2723 s->ti += from_bcd(value) * 2592000; 2724 } 2725 return; 2726 2727 case 0x14: /* YEARS_REG */ 2728 #ifdef ALMDEBUG 2729 printf("RTC YRS_REG <-- %02x\n", value); 2730 #endif 2731 memcpy(&new_tm, &s->current_tm, sizeof(new_tm)); 2732 new_tm.tm_year += from_bcd(value) - (new_tm.tm_year % 100); 2733 ti[0] = mktimegm(&s->current_tm); 2734 ti[1] = mktimegm(&new_tm); 2735 2736 if (ti[0] != -1 && ti[1] != -1) { 2737 s->ti -= ti[0]; 2738 s->ti += ti[1]; 2739 } else { 2740 /* A less accurate version */ 2741 s->ti -= (time_t)(s->current_tm.tm_year % 100) * 31536000; 2742 s->ti += (time_t)from_bcd(value) * 31536000; 2743 } 2744 return; 2745 2746 case 0x18: /* WEEK_REG */ 2747 return; /* Ignored */ 2748 2749 case 0x20: /* ALARM_SECONDS_REG */ 2750 #ifdef ALMDEBUG 2751 printf("ALM SEC_REG <-- %02x\n", value); 2752 #endif 2753 s->alarm_tm.tm_sec = from_bcd(value); 2754 omap_rtc_alarm_update(s); 2755 return; 2756 2757 case 0x24: /* ALARM_MINUTES_REG */ 2758 #ifdef ALMDEBUG 2759 printf("ALM MIN_REG <-- %02x\n", value); 2760 #endif 2761 s->alarm_tm.tm_min = from_bcd(value); 2762 omap_rtc_alarm_update(s); 2763 return; 2764 2765 case 0x28: /* ALARM_HOURS_REG */ 2766 #ifdef ALMDEBUG 2767 printf("ALM HRS_REG <-- %02x\n", value); 2768 #endif 2769 if (s->pm_am) 2770 s->alarm_tm.tm_hour = 2771 ((from_bcd(value & 0x3f)) % 12) + 2772 ((value >> 7) & 1) * 12; 2773 else 2774 s->alarm_tm.tm_hour = from_bcd(value); 2775 omap_rtc_alarm_update(s); 2776 return; 2777 2778 case 0x2c: /* ALARM_DAYS_REG */ 2779 #ifdef ALMDEBUG 2780 printf("ALM DAY_REG <-- %02x\n", value); 2781 #endif 2782 s->alarm_tm.tm_mday = from_bcd(value); 2783 omap_rtc_alarm_update(s); 2784 return; 2785 2786 case 0x30: /* ALARM_MONTHS_REG */ 2787 #ifdef ALMDEBUG 2788 printf("ALM MON_REG <-- %02x\n", value); 2789 #endif 2790 s->alarm_tm.tm_mon = from_bcd(value); 2791 omap_rtc_alarm_update(s); 2792 return; 2793 2794 case 0x34: /* ALARM_YEARS_REG */ 2795 #ifdef ALMDEBUG 2796 printf("ALM YRS_REG <-- %02x\n", value); 2797 #endif 2798 s->alarm_tm.tm_year = from_bcd(value); 2799 omap_rtc_alarm_update(s); 2800 return; 2801 2802 case 0x40: /* RTC_CTRL_REG */ 2803 #ifdef ALMDEBUG 2804 printf("RTC CONTROL <-- %02x\n", value); 2805 #endif 2806 s->pm_am = (value >> 3) & 1; 2807 s->auto_comp = (value >> 2) & 1; 2808 s->round = (value >> 1) & 1; 2809 s->running = value & 1; 2810 s->status &= 0xfd; 2811 s->status |= s->running << 1; 2812 return; 2813 2814 case 0x44: /* RTC_STATUS_REG */ 2815 #ifdef ALMDEBUG 2816 printf("RTC STATUSL <-- %02x\n", value); 2817 #endif 2818 s->status &= ~((value & 0xc0) ^ 0x80); 2819 omap_rtc_interrupts_update(s); 2820 return; 2821 2822 case 0x48: /* RTC_INTERRUPTS_REG */ 2823 #ifdef ALMDEBUG 2824 printf("RTC INTRS <-- %02x\n", value); 2825 #endif 2826 s->interrupts = value; 2827 return; 2828 2829 case 0x4c: /* RTC_COMP_LSB_REG */ 2830 #ifdef ALMDEBUG 2831 printf("RTC COMPLSB <-- %02x\n", value); 2832 #endif 2833 s->comp_reg &= 0xff00; 2834 s->comp_reg |= 0x00ff & value; 2835 return; 2836 2837 case 0x50: /* RTC_COMP_MSB_REG */ 2838 #ifdef ALMDEBUG 2839 printf("RTC COMPMSB <-- %02x\n", value); 2840 #endif 2841 s->comp_reg &= 0x00ff; 2842 s->comp_reg |= 0xff00 & (value << 8); 2843 return; 2844 2845 default: 2846 OMAP_BAD_REG(addr); 2847 return; 2848 } 2849 } 2850 2851 static const MemoryRegionOps omap_rtc_ops = { 2852 .read = omap_rtc_read, 2853 .write = omap_rtc_write, 2854 .endianness = DEVICE_NATIVE_ENDIAN, 2855 }; 2856 2857 static void omap_rtc_tick(void *opaque) 2858 { 2859 struct omap_rtc_s *s = opaque; 2860 2861 if (s->round) { 2862 /* Round to nearest full minute. */ 2863 if (s->current_tm.tm_sec < 30) 2864 s->ti -= s->current_tm.tm_sec; 2865 else 2866 s->ti += 60 - s->current_tm.tm_sec; 2867 2868 s->round = 0; 2869 } 2870 2871 localtime_r(&s->ti, &s->current_tm); 2872 2873 if ((s->interrupts & 0x08) && s->ti == s->alarm_ti) { 2874 s->status |= 0x40; 2875 omap_rtc_interrupts_update(s); 2876 } 2877 2878 if (s->interrupts & 0x04) 2879 switch (s->interrupts & 3) { 2880 case 0: 2881 s->status |= 0x04; 2882 qemu_irq_pulse(s->irq); 2883 break; 2884 case 1: 2885 if (s->current_tm.tm_sec) 2886 break; 2887 s->status |= 0x08; 2888 qemu_irq_pulse(s->irq); 2889 break; 2890 case 2: 2891 if (s->current_tm.tm_sec || s->current_tm.tm_min) 2892 break; 2893 s->status |= 0x10; 2894 qemu_irq_pulse(s->irq); 2895 break; 2896 case 3: 2897 if (s->current_tm.tm_sec || 2898 s->current_tm.tm_min || s->current_tm.tm_hour) 2899 break; 2900 s->status |= 0x20; 2901 qemu_irq_pulse(s->irq); 2902 break; 2903 } 2904 2905 /* Move on */ 2906 if (s->running) 2907 s->ti ++; 2908 s->tick += 1000; 2909 2910 /* 2911 * Every full hour add a rough approximation of the compensation 2912 * register to the 32kHz Timer (which drives the RTC) value. 2913 */ 2914 if (s->auto_comp && !s->current_tm.tm_sec && !s->current_tm.tm_min) 2915 s->tick += s->comp_reg * 1000 / 32768; 2916 2917 timer_mod(s->clk, s->tick); 2918 } 2919 2920 static void omap_rtc_reset(struct omap_rtc_s *s) 2921 { 2922 struct tm tm; 2923 2924 s->interrupts = 0; 2925 s->comp_reg = 0; 2926 s->running = 0; 2927 s->pm_am = 0; 2928 s->auto_comp = 0; 2929 s->round = 0; 2930 s->tick = qemu_clock_get_ms(rtc_clock); 2931 memset(&s->alarm_tm, 0, sizeof(s->alarm_tm)); 2932 s->alarm_tm.tm_mday = 0x01; 2933 s->status = 1 << 7; 2934 qemu_get_timedate(&tm, 0); 2935 s->ti = mktimegm(&tm); 2936 2937 omap_rtc_alarm_update(s); 2938 omap_rtc_tick(s); 2939 } 2940 2941 static struct omap_rtc_s *omap_rtc_init(MemoryRegion *system_memory, 2942 hwaddr base, 2943 qemu_irq timerirq, qemu_irq alarmirq, 2944 omap_clk clk) 2945 { 2946 struct omap_rtc_s *s = g_new0(struct omap_rtc_s, 1); 2947 2948 s->irq = timerirq; 2949 s->alarm = alarmirq; 2950 s->clk = timer_new_ms(rtc_clock, omap_rtc_tick, s); 2951 2952 omap_rtc_reset(s); 2953 2954 memory_region_init_io(&s->iomem, NULL, &omap_rtc_ops, s, 2955 "omap-rtc", 0x800); 2956 memory_region_add_subregion(system_memory, base, &s->iomem); 2957 2958 return s; 2959 } 2960 2961 /* Multi-channel Buffered Serial Port interfaces */ 2962 struct omap_mcbsp_s { 2963 MemoryRegion iomem; 2964 qemu_irq txirq; 2965 qemu_irq rxirq; 2966 qemu_irq txdrq; 2967 qemu_irq rxdrq; 2968 2969 uint16_t spcr[2]; 2970 uint16_t rcr[2]; 2971 uint16_t xcr[2]; 2972 uint16_t srgr[2]; 2973 uint16_t mcr[2]; 2974 uint16_t pcr; 2975 uint16_t rcer[8]; 2976 uint16_t xcer[8]; 2977 int tx_rate; 2978 int rx_rate; 2979 int tx_req; 2980 int rx_req; 2981 2982 I2SCodec *codec; 2983 QEMUTimer *source_timer; 2984 QEMUTimer *sink_timer; 2985 }; 2986 2987 static void omap_mcbsp_intr_update(struct omap_mcbsp_s *s) 2988 { 2989 int irq; 2990 2991 switch ((s->spcr[0] >> 4) & 3) { /* RINTM */ 2992 case 0: 2993 irq = (s->spcr[0] >> 1) & 1; /* RRDY */ 2994 break; 2995 case 3: 2996 irq = (s->spcr[0] >> 3) & 1; /* RSYNCERR */ 2997 break; 2998 default: 2999 irq = 0; 3000 break; 3001 } 3002 3003 if (irq) 3004 qemu_irq_pulse(s->rxirq); 3005 3006 switch ((s->spcr[1] >> 4) & 3) { /* XINTM */ 3007 case 0: 3008 irq = (s->spcr[1] >> 1) & 1; /* XRDY */ 3009 break; 3010 case 3: 3011 irq = (s->spcr[1] >> 3) & 1; /* XSYNCERR */ 3012 break; 3013 default: 3014 irq = 0; 3015 break; 3016 } 3017 3018 if (irq) 3019 qemu_irq_pulse(s->txirq); 3020 } 3021 3022 static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s) 3023 { 3024 if ((s->spcr[0] >> 1) & 1) /* RRDY */ 3025 s->spcr[0] |= 1 << 2; /* RFULL */ 3026 s->spcr[0] |= 1 << 1; /* RRDY */ 3027 qemu_irq_raise(s->rxdrq); 3028 omap_mcbsp_intr_update(s); 3029 } 3030 3031 static void omap_mcbsp_source_tick(void *opaque) 3032 { 3033 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3034 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 }; 3035 3036 if (!s->rx_rate) 3037 return; 3038 if (s->rx_req) 3039 printf("%s: Rx FIFO overrun\n", __func__); 3040 3041 s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7]; 3042 3043 omap_mcbsp_rx_newdata(s); 3044 timer_mod(s->source_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 3045 NANOSECONDS_PER_SECOND); 3046 } 3047 3048 static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s) 3049 { 3050 if (!s->codec || !s->codec->rts) 3051 omap_mcbsp_source_tick(s); 3052 else if (s->codec->in.len) { 3053 s->rx_req = s->codec->in.len; 3054 omap_mcbsp_rx_newdata(s); 3055 } 3056 } 3057 3058 static void omap_mcbsp_rx_stop(struct omap_mcbsp_s *s) 3059 { 3060 timer_del(s->source_timer); 3061 } 3062 3063 static void omap_mcbsp_rx_done(struct omap_mcbsp_s *s) 3064 { 3065 s->spcr[0] &= ~(1 << 1); /* RRDY */ 3066 qemu_irq_lower(s->rxdrq); 3067 omap_mcbsp_intr_update(s); 3068 } 3069 3070 static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s) 3071 { 3072 s->spcr[1] |= 1 << 1; /* XRDY */ 3073 qemu_irq_raise(s->txdrq); 3074 omap_mcbsp_intr_update(s); 3075 } 3076 3077 static void omap_mcbsp_sink_tick(void *opaque) 3078 { 3079 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3080 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 }; 3081 3082 if (!s->tx_rate) 3083 return; 3084 if (s->tx_req) 3085 printf("%s: Tx FIFO underrun\n", __func__); 3086 3087 s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7]; 3088 3089 omap_mcbsp_tx_newdata(s); 3090 timer_mod(s->sink_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 3091 NANOSECONDS_PER_SECOND); 3092 } 3093 3094 static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s) 3095 { 3096 if (!s->codec || !s->codec->cts) 3097 omap_mcbsp_sink_tick(s); 3098 else if (s->codec->out.size) { 3099 s->tx_req = s->codec->out.size; 3100 omap_mcbsp_tx_newdata(s); 3101 } 3102 } 3103 3104 static void omap_mcbsp_tx_done(struct omap_mcbsp_s *s) 3105 { 3106 s->spcr[1] &= ~(1 << 1); /* XRDY */ 3107 qemu_irq_lower(s->txdrq); 3108 omap_mcbsp_intr_update(s); 3109 if (s->codec && s->codec->cts) 3110 s->codec->tx_swallow(s->codec->opaque); 3111 } 3112 3113 static void omap_mcbsp_tx_stop(struct omap_mcbsp_s *s) 3114 { 3115 s->tx_req = 0; 3116 omap_mcbsp_tx_done(s); 3117 timer_del(s->sink_timer); 3118 } 3119 3120 static void omap_mcbsp_req_update(struct omap_mcbsp_s *s) 3121 { 3122 int prev_rx_rate, prev_tx_rate; 3123 int rx_rate = 0, tx_rate = 0; 3124 int cpu_rate = 1500000; /* XXX */ 3125 3126 /* TODO: check CLKSTP bit */ 3127 if (s->spcr[1] & (1 << 6)) { /* GRST */ 3128 if (s->spcr[0] & (1 << 0)) { /* RRST */ 3129 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ 3130 (s->pcr & (1 << 8))) { /* CLKRM */ 3131 if (~s->pcr & (1 << 7)) /* SCLKME */ 3132 rx_rate = cpu_rate / 3133 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ 3134 } else 3135 if (s->codec) 3136 rx_rate = s->codec->rx_rate; 3137 } 3138 3139 if (s->spcr[1] & (1 << 0)) { /* XRST */ 3140 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ 3141 (s->pcr & (1 << 9))) { /* CLKXM */ 3142 if (~s->pcr & (1 << 7)) /* SCLKME */ 3143 tx_rate = cpu_rate / 3144 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ 3145 } else 3146 if (s->codec) 3147 tx_rate = s->codec->tx_rate; 3148 } 3149 } 3150 prev_tx_rate = s->tx_rate; 3151 prev_rx_rate = s->rx_rate; 3152 s->tx_rate = tx_rate; 3153 s->rx_rate = rx_rate; 3154 3155 if (s->codec) 3156 s->codec->set_rate(s->codec->opaque, rx_rate, tx_rate); 3157 3158 if (!prev_tx_rate && tx_rate) 3159 omap_mcbsp_tx_start(s); 3160 else if (s->tx_rate && !tx_rate) 3161 omap_mcbsp_tx_stop(s); 3162 3163 if (!prev_rx_rate && rx_rate) 3164 omap_mcbsp_rx_start(s); 3165 else if (prev_tx_rate && !tx_rate) 3166 omap_mcbsp_rx_stop(s); 3167 } 3168 3169 static uint64_t omap_mcbsp_read(void *opaque, hwaddr addr, 3170 unsigned size) 3171 { 3172 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3173 int offset = addr & OMAP_MPUI_REG_MASK; 3174 uint16_t ret; 3175 3176 if (size != 2) { 3177 return omap_badwidth_read16(opaque, addr); 3178 } 3179 3180 switch (offset) { 3181 case 0x00: /* DRR2 */ 3182 if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */ 3183 return 0x0000; 3184 /* Fall through. */ 3185 case 0x02: /* DRR1 */ 3186 if (s->rx_req < 2) { 3187 printf("%s: Rx FIFO underrun\n", __func__); 3188 omap_mcbsp_rx_done(s); 3189 } else { 3190 s->tx_req -= 2; 3191 if (s->codec && s->codec->in.len >= 2) { 3192 ret = s->codec->in.fifo[s->codec->in.start ++] << 8; 3193 ret |= s->codec->in.fifo[s->codec->in.start ++]; 3194 s->codec->in.len -= 2; 3195 } else 3196 ret = 0x0000; 3197 if (!s->tx_req) 3198 omap_mcbsp_rx_done(s); 3199 return ret; 3200 } 3201 return 0x0000; 3202 3203 case 0x04: /* DXR2 */ 3204 case 0x06: /* DXR1 */ 3205 return 0x0000; 3206 3207 case 0x08: /* SPCR2 */ 3208 return s->spcr[1]; 3209 case 0x0a: /* SPCR1 */ 3210 return s->spcr[0]; 3211 case 0x0c: /* RCR2 */ 3212 return s->rcr[1]; 3213 case 0x0e: /* RCR1 */ 3214 return s->rcr[0]; 3215 case 0x10: /* XCR2 */ 3216 return s->xcr[1]; 3217 case 0x12: /* XCR1 */ 3218 return s->xcr[0]; 3219 case 0x14: /* SRGR2 */ 3220 return s->srgr[1]; 3221 case 0x16: /* SRGR1 */ 3222 return s->srgr[0]; 3223 case 0x18: /* MCR2 */ 3224 return s->mcr[1]; 3225 case 0x1a: /* MCR1 */ 3226 return s->mcr[0]; 3227 case 0x1c: /* RCERA */ 3228 return s->rcer[0]; 3229 case 0x1e: /* RCERB */ 3230 return s->rcer[1]; 3231 case 0x20: /* XCERA */ 3232 return s->xcer[0]; 3233 case 0x22: /* XCERB */ 3234 return s->xcer[1]; 3235 case 0x24: /* PCR0 */ 3236 return s->pcr; 3237 case 0x26: /* RCERC */ 3238 return s->rcer[2]; 3239 case 0x28: /* RCERD */ 3240 return s->rcer[3]; 3241 case 0x2a: /* XCERC */ 3242 return s->xcer[2]; 3243 case 0x2c: /* XCERD */ 3244 return s->xcer[3]; 3245 case 0x2e: /* RCERE */ 3246 return s->rcer[4]; 3247 case 0x30: /* RCERF */ 3248 return s->rcer[5]; 3249 case 0x32: /* XCERE */ 3250 return s->xcer[4]; 3251 case 0x34: /* XCERF */ 3252 return s->xcer[5]; 3253 case 0x36: /* RCERG */ 3254 return s->rcer[6]; 3255 case 0x38: /* RCERH */ 3256 return s->rcer[7]; 3257 case 0x3a: /* XCERG */ 3258 return s->xcer[6]; 3259 case 0x3c: /* XCERH */ 3260 return s->xcer[7]; 3261 } 3262 3263 OMAP_BAD_REG(addr); 3264 return 0; 3265 } 3266 3267 static void omap_mcbsp_writeh(void *opaque, hwaddr addr, 3268 uint32_t value) 3269 { 3270 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3271 int offset = addr & OMAP_MPUI_REG_MASK; 3272 3273 switch (offset) { 3274 case 0x00: /* DRR2 */ 3275 case 0x02: /* DRR1 */ 3276 OMAP_RO_REG(addr); 3277 return; 3278 3279 case 0x04: /* DXR2 */ 3280 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ 3281 return; 3282 /* Fall through. */ 3283 case 0x06: /* DXR1 */ 3284 if (s->tx_req > 1) { 3285 s->tx_req -= 2; 3286 if (s->codec && s->codec->cts) { 3287 s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff; 3288 s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff; 3289 } 3290 if (s->tx_req < 2) 3291 omap_mcbsp_tx_done(s); 3292 } else 3293 printf("%s: Tx FIFO overrun\n", __func__); 3294 return; 3295 3296 case 0x08: /* SPCR2 */ 3297 s->spcr[1] &= 0x0002; 3298 s->spcr[1] |= 0x03f9 & value; 3299 s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */ 3300 if (~value & 1) /* XRST */ 3301 s->spcr[1] &= ~6; 3302 omap_mcbsp_req_update(s); 3303 return; 3304 case 0x0a: /* SPCR1 */ 3305 s->spcr[0] &= 0x0006; 3306 s->spcr[0] |= 0xf8f9 & value; 3307 if (value & (1 << 15)) /* DLB */ 3308 printf("%s: Digital Loopback mode enable attempt\n", __func__); 3309 if (~value & 1) { /* RRST */ 3310 s->spcr[0] &= ~6; 3311 s->rx_req = 0; 3312 omap_mcbsp_rx_done(s); 3313 } 3314 omap_mcbsp_req_update(s); 3315 return; 3316 3317 case 0x0c: /* RCR2 */ 3318 s->rcr[1] = value & 0xffff; 3319 return; 3320 case 0x0e: /* RCR1 */ 3321 s->rcr[0] = value & 0x7fe0; 3322 return; 3323 case 0x10: /* XCR2 */ 3324 s->xcr[1] = value & 0xffff; 3325 return; 3326 case 0x12: /* XCR1 */ 3327 s->xcr[0] = value & 0x7fe0; 3328 return; 3329 case 0x14: /* SRGR2 */ 3330 s->srgr[1] = value & 0xffff; 3331 omap_mcbsp_req_update(s); 3332 return; 3333 case 0x16: /* SRGR1 */ 3334 s->srgr[0] = value & 0xffff; 3335 omap_mcbsp_req_update(s); 3336 return; 3337 case 0x18: /* MCR2 */ 3338 s->mcr[1] = value & 0x03e3; 3339 if (value & 3) /* XMCM */ 3340 printf("%s: Tx channel selection mode enable attempt\n", __func__); 3341 return; 3342 case 0x1a: /* MCR1 */ 3343 s->mcr[0] = value & 0x03e1; 3344 if (value & 1) /* RMCM */ 3345 printf("%s: Rx channel selection mode enable attempt\n", __func__); 3346 return; 3347 case 0x1c: /* RCERA */ 3348 s->rcer[0] = value & 0xffff; 3349 return; 3350 case 0x1e: /* RCERB */ 3351 s->rcer[1] = value & 0xffff; 3352 return; 3353 case 0x20: /* XCERA */ 3354 s->xcer[0] = value & 0xffff; 3355 return; 3356 case 0x22: /* XCERB */ 3357 s->xcer[1] = value & 0xffff; 3358 return; 3359 case 0x24: /* PCR0 */ 3360 s->pcr = value & 0x7faf; 3361 return; 3362 case 0x26: /* RCERC */ 3363 s->rcer[2] = value & 0xffff; 3364 return; 3365 case 0x28: /* RCERD */ 3366 s->rcer[3] = value & 0xffff; 3367 return; 3368 case 0x2a: /* XCERC */ 3369 s->xcer[2] = value & 0xffff; 3370 return; 3371 case 0x2c: /* XCERD */ 3372 s->xcer[3] = value & 0xffff; 3373 return; 3374 case 0x2e: /* RCERE */ 3375 s->rcer[4] = value & 0xffff; 3376 return; 3377 case 0x30: /* RCERF */ 3378 s->rcer[5] = value & 0xffff; 3379 return; 3380 case 0x32: /* XCERE */ 3381 s->xcer[4] = value & 0xffff; 3382 return; 3383 case 0x34: /* XCERF */ 3384 s->xcer[5] = value & 0xffff; 3385 return; 3386 case 0x36: /* RCERG */ 3387 s->rcer[6] = value & 0xffff; 3388 return; 3389 case 0x38: /* RCERH */ 3390 s->rcer[7] = value & 0xffff; 3391 return; 3392 case 0x3a: /* XCERG */ 3393 s->xcer[6] = value & 0xffff; 3394 return; 3395 case 0x3c: /* XCERH */ 3396 s->xcer[7] = value & 0xffff; 3397 return; 3398 } 3399 3400 OMAP_BAD_REG(addr); 3401 } 3402 3403 static void omap_mcbsp_writew(void *opaque, hwaddr addr, 3404 uint32_t value) 3405 { 3406 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3407 int offset = addr & OMAP_MPUI_REG_MASK; 3408 3409 if (offset == 0x04) { /* DXR */ 3410 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ 3411 return; 3412 if (s->tx_req > 3) { 3413 s->tx_req -= 4; 3414 if (s->codec && s->codec->cts) { 3415 s->codec->out.fifo[s->codec->out.len ++] = 3416 (value >> 24) & 0xff; 3417 s->codec->out.fifo[s->codec->out.len ++] = 3418 (value >> 16) & 0xff; 3419 s->codec->out.fifo[s->codec->out.len ++] = 3420 (value >> 8) & 0xff; 3421 s->codec->out.fifo[s->codec->out.len ++] = 3422 (value >> 0) & 0xff; 3423 } 3424 if (s->tx_req < 4) 3425 omap_mcbsp_tx_done(s); 3426 } else 3427 printf("%s: Tx FIFO overrun\n", __func__); 3428 return; 3429 } 3430 3431 omap_badwidth_write16(opaque, addr, value); 3432 } 3433 3434 static void omap_mcbsp_write(void *opaque, hwaddr addr, 3435 uint64_t value, unsigned size) 3436 { 3437 switch (size) { 3438 case 2: 3439 omap_mcbsp_writeh(opaque, addr, value); 3440 break; 3441 case 4: 3442 omap_mcbsp_writew(opaque, addr, value); 3443 break; 3444 default: 3445 omap_badwidth_write16(opaque, addr, value); 3446 } 3447 } 3448 3449 static const MemoryRegionOps omap_mcbsp_ops = { 3450 .read = omap_mcbsp_read, 3451 .write = omap_mcbsp_write, 3452 .endianness = DEVICE_NATIVE_ENDIAN, 3453 }; 3454 3455 static void omap_mcbsp_reset(struct omap_mcbsp_s *s) 3456 { 3457 memset(&s->spcr, 0, sizeof(s->spcr)); 3458 memset(&s->rcr, 0, sizeof(s->rcr)); 3459 memset(&s->xcr, 0, sizeof(s->xcr)); 3460 s->srgr[0] = 0x0001; 3461 s->srgr[1] = 0x2000; 3462 memset(&s->mcr, 0, sizeof(s->mcr)); 3463 memset(&s->pcr, 0, sizeof(s->pcr)); 3464 memset(&s->rcer, 0, sizeof(s->rcer)); 3465 memset(&s->xcer, 0, sizeof(s->xcer)); 3466 s->tx_req = 0; 3467 s->rx_req = 0; 3468 s->tx_rate = 0; 3469 s->rx_rate = 0; 3470 timer_del(s->source_timer); 3471 timer_del(s->sink_timer); 3472 } 3473 3474 static struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory, 3475 hwaddr base, 3476 qemu_irq txirq, qemu_irq rxirq, 3477 qemu_irq *dma, omap_clk clk) 3478 { 3479 struct omap_mcbsp_s *s = g_new0(struct omap_mcbsp_s, 1); 3480 3481 s->txirq = txirq; 3482 s->rxirq = rxirq; 3483 s->txdrq = dma[0]; 3484 s->rxdrq = dma[1]; 3485 s->sink_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_mcbsp_sink_tick, s); 3486 s->source_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_mcbsp_source_tick, s); 3487 omap_mcbsp_reset(s); 3488 3489 memory_region_init_io(&s->iomem, NULL, &omap_mcbsp_ops, s, "omap-mcbsp", 0x800); 3490 memory_region_add_subregion(system_memory, base, &s->iomem); 3491 3492 return s; 3493 } 3494 3495 static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level) 3496 { 3497 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3498 3499 if (s->rx_rate) { 3500 s->rx_req = s->codec->in.len; 3501 omap_mcbsp_rx_newdata(s); 3502 } 3503 } 3504 3505 static void omap_mcbsp_i2s_start(void *opaque, int line, int level) 3506 { 3507 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3508 3509 if (s->tx_rate) { 3510 s->tx_req = s->codec->out.size; 3511 omap_mcbsp_tx_newdata(s); 3512 } 3513 } 3514 3515 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave) 3516 { 3517 s->codec = slave; 3518 slave->rx_swallow = qemu_allocate_irq(omap_mcbsp_i2s_swallow, s, 0); 3519 slave->tx_start = qemu_allocate_irq(omap_mcbsp_i2s_start, s, 0); 3520 } 3521 3522 /* LED Pulse Generators */ 3523 struct omap_lpg_s { 3524 MemoryRegion iomem; 3525 QEMUTimer *tm; 3526 3527 uint8_t control; 3528 uint8_t power; 3529 int64_t on; 3530 int64_t period; 3531 int clk; 3532 int cycle; 3533 }; 3534 3535 static void omap_lpg_tick(void *opaque) 3536 { 3537 struct omap_lpg_s *s = opaque; 3538 3539 if (s->cycle) 3540 timer_mod(s->tm, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->period - s->on); 3541 else 3542 timer_mod(s->tm, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->on); 3543 3544 s->cycle = !s->cycle; 3545 printf("%s: LED is %s\n", __func__, s->cycle ? "on" : "off"); 3546 } 3547 3548 static void omap_lpg_update(struct omap_lpg_s *s) 3549 { 3550 int64_t on, period = 1, ticks = 1000; 3551 static const int per[8] = { 1, 2, 4, 8, 12, 16, 20, 24 }; 3552 3553 if (~s->control & (1 << 6)) /* LPGRES */ 3554 on = 0; 3555 else if (s->control & (1 << 7)) /* PERM_ON */ 3556 on = period; 3557 else { 3558 period = muldiv64(ticks, per[s->control & 7], /* PERCTRL */ 3559 256 / 32); 3560 on = (s->clk && s->power) ? muldiv64(ticks, 3561 per[(s->control >> 3) & 7], 256) : 0; /* ONCTRL */ 3562 } 3563 3564 timer_del(s->tm); 3565 if (on == period && s->on < s->period) 3566 printf("%s: LED is on\n", __func__); 3567 else if (on == 0 && s->on) 3568 printf("%s: LED is off\n", __func__); 3569 else if (on && (on != s->on || period != s->period)) { 3570 s->cycle = 0; 3571 s->on = on; 3572 s->period = period; 3573 omap_lpg_tick(s); 3574 return; 3575 } 3576 3577 s->on = on; 3578 s->period = period; 3579 } 3580 3581 static void omap_lpg_reset(struct omap_lpg_s *s) 3582 { 3583 s->control = 0x00; 3584 s->power = 0x00; 3585 s->clk = 1; 3586 omap_lpg_update(s); 3587 } 3588 3589 static uint64_t omap_lpg_read(void *opaque, hwaddr addr, 3590 unsigned size) 3591 { 3592 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; 3593 int offset = addr & OMAP_MPUI_REG_MASK; 3594 3595 if (size != 1) { 3596 return omap_badwidth_read8(opaque, addr); 3597 } 3598 3599 switch (offset) { 3600 case 0x00: /* LCR */ 3601 return s->control; 3602 3603 case 0x04: /* PMR */ 3604 return s->power; 3605 } 3606 3607 OMAP_BAD_REG(addr); 3608 return 0; 3609 } 3610 3611 static void omap_lpg_write(void *opaque, hwaddr addr, 3612 uint64_t value, unsigned size) 3613 { 3614 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; 3615 int offset = addr & OMAP_MPUI_REG_MASK; 3616 3617 if (size != 1) { 3618 omap_badwidth_write8(opaque, addr, value); 3619 return; 3620 } 3621 3622 switch (offset) { 3623 case 0x00: /* LCR */ 3624 if (~value & (1 << 6)) /* LPGRES */ 3625 omap_lpg_reset(s); 3626 s->control = value & 0xff; 3627 omap_lpg_update(s); 3628 return; 3629 3630 case 0x04: /* PMR */ 3631 s->power = value & 0x01; 3632 omap_lpg_update(s); 3633 return; 3634 3635 default: 3636 OMAP_BAD_REG(addr); 3637 return; 3638 } 3639 } 3640 3641 static const MemoryRegionOps omap_lpg_ops = { 3642 .read = omap_lpg_read, 3643 .write = omap_lpg_write, 3644 .endianness = DEVICE_NATIVE_ENDIAN, 3645 }; 3646 3647 static void omap_lpg_clk_update(void *opaque, int line, int on) 3648 { 3649 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; 3650 3651 s->clk = on; 3652 omap_lpg_update(s); 3653 } 3654 3655 static struct omap_lpg_s *omap_lpg_init(MemoryRegion *system_memory, 3656 hwaddr base, omap_clk clk) 3657 { 3658 struct omap_lpg_s *s = g_new0(struct omap_lpg_s, 1); 3659 3660 s->tm = timer_new_ms(QEMU_CLOCK_VIRTUAL, omap_lpg_tick, s); 3661 3662 omap_lpg_reset(s); 3663 3664 memory_region_init_io(&s->iomem, NULL, &omap_lpg_ops, s, "omap-lpg", 0x800); 3665 memory_region_add_subregion(system_memory, base, &s->iomem); 3666 3667 omap_clk_adduser(clk, qemu_allocate_irq(omap_lpg_clk_update, s, 0)); 3668 3669 return s; 3670 } 3671 3672 /* MPUI Peripheral Bridge configuration */ 3673 static uint64_t omap_mpui_io_read(void *opaque, hwaddr addr, 3674 unsigned size) 3675 { 3676 if (size != 2) { 3677 return omap_badwidth_read16(opaque, addr); 3678 } 3679 3680 if (addr == OMAP_MPUI_BASE) /* CMR */ 3681 return 0xfe4d; 3682 3683 OMAP_BAD_REG(addr); 3684 return 0; 3685 } 3686 3687 static void omap_mpui_io_write(void *opaque, hwaddr addr, 3688 uint64_t value, unsigned size) 3689 { 3690 /* FIXME: infinite loop */ 3691 omap_badwidth_write16(opaque, addr, value); 3692 } 3693 3694 static const MemoryRegionOps omap_mpui_io_ops = { 3695 .read = omap_mpui_io_read, 3696 .write = omap_mpui_io_write, 3697 .endianness = DEVICE_NATIVE_ENDIAN, 3698 }; 3699 3700 static void omap_setup_mpui_io(MemoryRegion *system_memory, 3701 struct omap_mpu_state_s *mpu) 3702 { 3703 memory_region_init_io(&mpu->mpui_io_iomem, NULL, &omap_mpui_io_ops, mpu, 3704 "omap-mpui-io", 0x7fff); 3705 memory_region_add_subregion(system_memory, OMAP_MPUI_BASE, 3706 &mpu->mpui_io_iomem); 3707 } 3708 3709 /* General chip reset */ 3710 static void omap1_mpu_reset(void *opaque) 3711 { 3712 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; 3713 3714 omap_dma_reset(mpu->dma); 3715 omap_mpu_timer_reset(mpu->timer[0]); 3716 omap_mpu_timer_reset(mpu->timer[1]); 3717 omap_mpu_timer_reset(mpu->timer[2]); 3718 omap_wd_timer_reset(mpu->wdt); 3719 omap_os_timer_reset(mpu->os_timer); 3720 omap_lcdc_reset(mpu->lcd); 3721 omap_ulpd_pm_reset(mpu); 3722 omap_pin_cfg_reset(mpu); 3723 omap_mpui_reset(mpu); 3724 omap_tipb_bridge_reset(mpu->private_tipb); 3725 omap_tipb_bridge_reset(mpu->public_tipb); 3726 omap_dpll_reset(mpu->dpll[0]); 3727 omap_dpll_reset(mpu->dpll[1]); 3728 omap_dpll_reset(mpu->dpll[2]); 3729 omap_uart_reset(mpu->uart[0]); 3730 omap_uart_reset(mpu->uart[1]); 3731 omap_uart_reset(mpu->uart[2]); 3732 omap_mmc_reset(mpu->mmc); 3733 omap_mpuio_reset(mpu->mpuio); 3734 omap_uwire_reset(mpu->microwire); 3735 omap_pwl_reset(mpu->pwl); 3736 omap_pwt_reset(mpu->pwt); 3737 omap_rtc_reset(mpu->rtc); 3738 omap_mcbsp_reset(mpu->mcbsp1); 3739 omap_mcbsp_reset(mpu->mcbsp2); 3740 omap_mcbsp_reset(mpu->mcbsp3); 3741 omap_lpg_reset(mpu->led[0]); 3742 omap_lpg_reset(mpu->led[1]); 3743 omap_clkm_reset(mpu); 3744 cpu_reset(CPU(mpu->cpu)); 3745 } 3746 3747 static const struct omap_map_s { 3748 hwaddr phys_dsp; 3749 hwaddr phys_mpu; 3750 uint32_t size; 3751 const char *name; 3752 } omap15xx_dsp_mm[] = { 3753 /* Strobe 0 */ 3754 { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */ 3755 { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */ 3756 { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */ 3757 { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */ 3758 { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */ 3759 { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */ 3760 { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */ 3761 { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */ 3762 { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */ 3763 { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */ 3764 { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */ 3765 { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */ 3766 { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */ 3767 { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */ 3768 { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */ 3769 { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */ 3770 { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */ 3771 /* Strobe 1 */ 3772 { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */ 3773 3774 { 0 } 3775 }; 3776 3777 static void omap_setup_dsp_mapping(MemoryRegion *system_memory, 3778 const struct omap_map_s *map) 3779 { 3780 MemoryRegion *io; 3781 3782 for (; map->phys_dsp; map ++) { 3783 io = g_new(MemoryRegion, 1); 3784 memory_region_init_alias(io, NULL, map->name, 3785 system_memory, map->phys_mpu, map->size); 3786 memory_region_add_subregion(system_memory, map->phys_dsp, io); 3787 } 3788 } 3789 3790 void omap_mpu_wakeup(void *opaque, int irq, int req) 3791 { 3792 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; 3793 CPUState *cpu = CPU(mpu->cpu); 3794 3795 if (cpu->halted) { 3796 cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB); 3797 } 3798 } 3799 3800 static const struct dma_irq_map omap1_dma_irq_map[] = { 3801 { 0, OMAP_INT_DMA_CH0_6 }, 3802 { 0, OMAP_INT_DMA_CH1_7 }, 3803 { 0, OMAP_INT_DMA_CH2_8 }, 3804 { 0, OMAP_INT_DMA_CH3 }, 3805 { 0, OMAP_INT_DMA_CH4 }, 3806 { 0, OMAP_INT_DMA_CH5 }, 3807 { 1, OMAP_INT_1610_DMA_CH6 }, 3808 { 1, OMAP_INT_1610_DMA_CH7 }, 3809 { 1, OMAP_INT_1610_DMA_CH8 }, 3810 { 1, OMAP_INT_1610_DMA_CH9 }, 3811 { 1, OMAP_INT_1610_DMA_CH10 }, 3812 { 1, OMAP_INT_1610_DMA_CH11 }, 3813 { 1, OMAP_INT_1610_DMA_CH12 }, 3814 { 1, OMAP_INT_1610_DMA_CH13 }, 3815 { 1, OMAP_INT_1610_DMA_CH14 }, 3816 { 1, OMAP_INT_1610_DMA_CH15 } 3817 }; 3818 3819 /* DMA ports for OMAP1 */ 3820 static int omap_validate_emiff_addr(struct omap_mpu_state_s *s, 3821 hwaddr addr) 3822 { 3823 return range_covers_byte(OMAP_EMIFF_BASE, s->sdram_size, addr); 3824 } 3825 3826 static int omap_validate_emifs_addr(struct omap_mpu_state_s *s, 3827 hwaddr addr) 3828 { 3829 return range_covers_byte(OMAP_EMIFS_BASE, OMAP_EMIFF_BASE - OMAP_EMIFS_BASE, 3830 addr); 3831 } 3832 3833 static int omap_validate_imif_addr(struct omap_mpu_state_s *s, 3834 hwaddr addr) 3835 { 3836 return range_covers_byte(OMAP_IMIF_BASE, s->sram_size, addr); 3837 } 3838 3839 static int omap_validate_tipb_addr(struct omap_mpu_state_s *s, 3840 hwaddr addr) 3841 { 3842 return range_covers_byte(0xfffb0000, 0xffff0000 - 0xfffb0000, addr); 3843 } 3844 3845 static int omap_validate_local_addr(struct omap_mpu_state_s *s, 3846 hwaddr addr) 3847 { 3848 return range_covers_byte(OMAP_LOCALBUS_BASE, 0x1000000, addr); 3849 } 3850 3851 static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s, 3852 hwaddr addr) 3853 { 3854 return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr); 3855 } 3856 3857 struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory, 3858 unsigned long sdram_size, 3859 const char *cpu_type) 3860 { 3861 int i; 3862 struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1); 3863 qemu_irq dma_irqs[6]; 3864 DriveInfo *dinfo; 3865 SysBusDevice *busdev; 3866 3867 /* Core */ 3868 s->mpu_model = omap310; 3869 s->cpu = ARM_CPU(cpu_create(cpu_type)); 3870 s->sdram_size = sdram_size; 3871 s->sram_size = OMAP15XX_SRAM_SIZE; 3872 3873 s->wakeup = qemu_allocate_irq(omap_mpu_wakeup, s, 0); 3874 3875 /* Clocks */ 3876 omap_clk_init(s); 3877 3878 /* Memory-mapped stuff */ 3879 memory_region_allocate_system_memory(&s->emiff_ram, NULL, "omap1.dram", 3880 s->sdram_size); 3881 memory_region_add_subregion(system_memory, OMAP_EMIFF_BASE, &s->emiff_ram); 3882 memory_region_init_ram(&s->imif_ram, NULL, "omap1.sram", s->sram_size, 3883 &error_fatal); 3884 memory_region_add_subregion(system_memory, OMAP_IMIF_BASE, &s->imif_ram); 3885 3886 omap_clkm_init(system_memory, 0xfffece00, 0xe1008000, s); 3887 3888 s->ih[0] = qdev_create(NULL, "omap-intc"); 3889 qdev_prop_set_uint32(s->ih[0], "size", 0x100); 3890 qdev_prop_set_ptr(s->ih[0], "clk", omap_findclk(s, "arminth_ck")); 3891 qdev_init_nofail(s->ih[0]); 3892 busdev = SYS_BUS_DEVICE(s->ih[0]); 3893 sysbus_connect_irq(busdev, 0, 3894 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ)); 3895 sysbus_connect_irq(busdev, 1, 3896 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ)); 3897 sysbus_mmio_map(busdev, 0, 0xfffecb00); 3898 s->ih[1] = qdev_create(NULL, "omap-intc"); 3899 qdev_prop_set_uint32(s->ih[1], "size", 0x800); 3900 qdev_prop_set_ptr(s->ih[1], "clk", omap_findclk(s, "arminth_ck")); 3901 qdev_init_nofail(s->ih[1]); 3902 busdev = SYS_BUS_DEVICE(s->ih[1]); 3903 sysbus_connect_irq(busdev, 0, 3904 qdev_get_gpio_in(s->ih[0], OMAP_INT_15XX_IH2_IRQ)); 3905 /* The second interrupt controller's FIQ output is not wired up */ 3906 sysbus_mmio_map(busdev, 0, 0xfffe0000); 3907 3908 for (i = 0; i < 6; i++) { 3909 dma_irqs[i] = qdev_get_gpio_in(s->ih[omap1_dma_irq_map[i].ih], 3910 omap1_dma_irq_map[i].intr); 3911 } 3912 s->dma = omap_dma_init(0xfffed800, dma_irqs, system_memory, 3913 qdev_get_gpio_in(s->ih[0], OMAP_INT_DMA_LCD), 3914 s, omap_findclk(s, "dma_ck"), omap_dma_3_1); 3915 3916 s->port[emiff ].addr_valid = omap_validate_emiff_addr; 3917 s->port[emifs ].addr_valid = omap_validate_emifs_addr; 3918 s->port[imif ].addr_valid = omap_validate_imif_addr; 3919 s->port[tipb ].addr_valid = omap_validate_tipb_addr; 3920 s->port[local ].addr_valid = omap_validate_local_addr; 3921 s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr; 3922 3923 /* Register SDRAM and SRAM DMA ports for fast transfers. */ 3924 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->emiff_ram), 3925 OMAP_EMIFF_BASE, s->sdram_size); 3926 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->imif_ram), 3927 OMAP_IMIF_BASE, s->sram_size); 3928 3929 s->timer[0] = omap_mpu_timer_init(system_memory, 0xfffec500, 3930 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER1), 3931 omap_findclk(s, "mputim_ck")); 3932 s->timer[1] = omap_mpu_timer_init(system_memory, 0xfffec600, 3933 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER2), 3934 omap_findclk(s, "mputim_ck")); 3935 s->timer[2] = omap_mpu_timer_init(system_memory, 0xfffec700, 3936 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER3), 3937 omap_findclk(s, "mputim_ck")); 3938 3939 s->wdt = omap_wd_timer_init(system_memory, 0xfffec800, 3940 qdev_get_gpio_in(s->ih[0], OMAP_INT_WD_TIMER), 3941 omap_findclk(s, "armwdt_ck")); 3942 3943 s->os_timer = omap_os_timer_init(system_memory, 0xfffb9000, 3944 qdev_get_gpio_in(s->ih[1], OMAP_INT_OS_TIMER), 3945 omap_findclk(s, "clk32-kHz")); 3946 3947 s->lcd = omap_lcdc_init(system_memory, 0xfffec000, 3948 qdev_get_gpio_in(s->ih[0], OMAP_INT_LCD_CTRL), 3949 omap_dma_get_lcdch(s->dma), 3950 omap_findclk(s, "lcd_ck")); 3951 3952 omap_ulpd_pm_init(system_memory, 0xfffe0800, s); 3953 omap_pin_cfg_init(system_memory, 0xfffe1000, s); 3954 omap_id_init(system_memory, s); 3955 3956 omap_mpui_init(system_memory, 0xfffec900, s); 3957 3958 s->private_tipb = omap_tipb_bridge_init(system_memory, 0xfffeca00, 3959 qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PRIV), 3960 omap_findclk(s, "tipb_ck")); 3961 s->public_tipb = omap_tipb_bridge_init(system_memory, 0xfffed300, 3962 qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PUB), 3963 omap_findclk(s, "tipb_ck")); 3964 3965 omap_tcmi_init(system_memory, 0xfffecc00, s); 3966 3967 s->uart[0] = omap_uart_init(0xfffb0000, 3968 qdev_get_gpio_in(s->ih[1], OMAP_INT_UART1), 3969 omap_findclk(s, "uart1_ck"), 3970 omap_findclk(s, "uart1_ck"), 3971 s->drq[OMAP_DMA_UART1_TX], s->drq[OMAP_DMA_UART1_RX], 3972 "uart1", 3973 serial_hd(0)); 3974 s->uart[1] = omap_uart_init(0xfffb0800, 3975 qdev_get_gpio_in(s->ih[1], OMAP_INT_UART2), 3976 omap_findclk(s, "uart2_ck"), 3977 omap_findclk(s, "uart2_ck"), 3978 s->drq[OMAP_DMA_UART2_TX], s->drq[OMAP_DMA_UART2_RX], 3979 "uart2", 3980 serial_hd(0) ? serial_hd(1) : NULL); 3981 s->uart[2] = omap_uart_init(0xfffb9800, 3982 qdev_get_gpio_in(s->ih[0], OMAP_INT_UART3), 3983 omap_findclk(s, "uart3_ck"), 3984 omap_findclk(s, "uart3_ck"), 3985 s->drq[OMAP_DMA_UART3_TX], s->drq[OMAP_DMA_UART3_RX], 3986 "uart3", 3987 serial_hd(0) && serial_hd(1) ? serial_hd(2) : NULL); 3988 3989 s->dpll[0] = omap_dpll_init(system_memory, 0xfffecf00, 3990 omap_findclk(s, "dpll1")); 3991 s->dpll[1] = omap_dpll_init(system_memory, 0xfffed000, 3992 omap_findclk(s, "dpll2")); 3993 s->dpll[2] = omap_dpll_init(system_memory, 0xfffed100, 3994 omap_findclk(s, "dpll3")); 3995 3996 dinfo = drive_get(IF_SD, 0, 0); 3997 if (!dinfo && !qtest_enabled()) { 3998 warn_report("missing SecureDigital device"); 3999 } 4000 s->mmc = omap_mmc_init(0xfffb7800, system_memory, 4001 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 4002 qdev_get_gpio_in(s->ih[1], OMAP_INT_OQN), 4003 &s->drq[OMAP_DMA_MMC_TX], 4004 omap_findclk(s, "mmc_ck")); 4005 4006 s->mpuio = omap_mpuio_init(system_memory, 0xfffb5000, 4007 qdev_get_gpio_in(s->ih[1], OMAP_INT_KEYBOARD), 4008 qdev_get_gpio_in(s->ih[1], OMAP_INT_MPUIO), 4009 s->wakeup, omap_findclk(s, "clk32-kHz")); 4010 4011 s->gpio = qdev_create(NULL, "omap-gpio"); 4012 qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model); 4013 qdev_prop_set_ptr(s->gpio, "clk", omap_findclk(s, "arm_gpio_ck")); 4014 qdev_init_nofail(s->gpio); 4015 sysbus_connect_irq(SYS_BUS_DEVICE(s->gpio), 0, 4016 qdev_get_gpio_in(s->ih[0], OMAP_INT_GPIO_BANK1)); 4017 sysbus_mmio_map(SYS_BUS_DEVICE(s->gpio), 0, 0xfffce000); 4018 4019 s->microwire = omap_uwire_init(system_memory, 0xfffb3000, 4020 qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireTX), 4021 qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireRX), 4022 s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck")); 4023 4024 s->pwl = omap_pwl_init(system_memory, 0xfffb5800, 4025 omap_findclk(s, "armxor_ck")); 4026 s->pwt = omap_pwt_init(system_memory, 0xfffb6000, 4027 omap_findclk(s, "armxor_ck")); 4028 4029 s->i2c[0] = qdev_create(NULL, "omap_i2c"); 4030 qdev_prop_set_uint8(s->i2c[0], "revision", 0x11); 4031 qdev_prop_set_ptr(s->i2c[0], "fclk", omap_findclk(s, "mpuper_ck")); 4032 qdev_init_nofail(s->i2c[0]); 4033 busdev = SYS_BUS_DEVICE(s->i2c[0]); 4034 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C)); 4035 sysbus_connect_irq(busdev, 1, s->drq[OMAP_DMA_I2C_TX]); 4036 sysbus_connect_irq(busdev, 2, s->drq[OMAP_DMA_I2C_RX]); 4037 sysbus_mmio_map(busdev, 0, 0xfffb3800); 4038 4039 s->rtc = omap_rtc_init(system_memory, 0xfffb4800, 4040 qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_TIMER), 4041 qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_ALARM), 4042 omap_findclk(s, "clk32-kHz")); 4043 4044 s->mcbsp1 = omap_mcbsp_init(system_memory, 0xfffb1800, 4045 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1TX), 4046 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1RX), 4047 &s->drq[OMAP_DMA_MCBSP1_TX], omap_findclk(s, "dspxor_ck")); 4048 s->mcbsp2 = omap_mcbsp_init(system_memory, 0xfffb1000, 4049 qdev_get_gpio_in(s->ih[0], 4050 OMAP_INT_310_McBSP2_TX), 4051 qdev_get_gpio_in(s->ih[0], 4052 OMAP_INT_310_McBSP2_RX), 4053 &s->drq[OMAP_DMA_MCBSP2_TX], omap_findclk(s, "mpuper_ck")); 4054 s->mcbsp3 = omap_mcbsp_init(system_memory, 0xfffb7000, 4055 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3TX), 4056 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3RX), 4057 &s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck")); 4058 4059 s->led[0] = omap_lpg_init(system_memory, 4060 0xfffbd000, omap_findclk(s, "clk32-kHz")); 4061 s->led[1] = omap_lpg_init(system_memory, 4062 0xfffbd800, omap_findclk(s, "clk32-kHz")); 4063 4064 /* Register mappings not currenlty implemented: 4065 * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310) 4066 * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310) 4067 * USB W2FC fffb4000 - fffb47ff 4068 * Camera Interface fffb6800 - fffb6fff 4069 * USB Host fffba000 - fffba7ff 4070 * FAC fffba800 - fffbafff 4071 * HDQ/1-Wire fffbc000 - fffbc7ff 4072 * TIPB switches fffbc800 - fffbcfff 4073 * Mailbox fffcf000 - fffcf7ff 4074 * Local bus IF fffec100 - fffec1ff 4075 * Local bus MMU fffec200 - fffec2ff 4076 * DSP MMU fffed200 - fffed2ff 4077 */ 4078 4079 omap_setup_dsp_mapping(system_memory, omap15xx_dsp_mm); 4080 omap_setup_mpui_io(system_memory, s); 4081 4082 qemu_register_reset(omap1_mpu_reset, s); 4083 4084 return s; 4085 } 4086