1 /* 2 * TI OMAP processors emulation. 3 * 4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 or 9 * (at your option) version 3 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "qemu-common.h" 23 #include "cpu.h" 24 #include "hw/boards.h" 25 #include "hw/hw.h" 26 #include "hw/arm/arm.h" 27 #include "hw/arm/omap.h" 28 #include "sysemu/sysemu.h" 29 #include "hw/arm/soc_dma.h" 30 #include "sysemu/block-backend.h" 31 #include "sysemu/blockdev.h" 32 #include "qemu/range.h" 33 #include "hw/sysbus.h" 34 #include "qemu/cutils.h" 35 #include "qemu/bcd.h" 36 37 /* Should signal the TCMI/GPMC */ 38 uint32_t omap_badwidth_read8(void *opaque, hwaddr addr) 39 { 40 uint8_t ret; 41 42 OMAP_8B_REG(addr); 43 cpu_physical_memory_read(addr, &ret, 1); 44 return ret; 45 } 46 47 void omap_badwidth_write8(void *opaque, hwaddr addr, 48 uint32_t value) 49 { 50 uint8_t val8 = value; 51 52 OMAP_8B_REG(addr); 53 cpu_physical_memory_write(addr, &val8, 1); 54 } 55 56 uint32_t omap_badwidth_read16(void *opaque, hwaddr addr) 57 { 58 uint16_t ret; 59 60 OMAP_16B_REG(addr); 61 cpu_physical_memory_read(addr, &ret, 2); 62 return ret; 63 } 64 65 void omap_badwidth_write16(void *opaque, hwaddr addr, 66 uint32_t value) 67 { 68 uint16_t val16 = value; 69 70 OMAP_16B_REG(addr); 71 cpu_physical_memory_write(addr, &val16, 2); 72 } 73 74 uint32_t omap_badwidth_read32(void *opaque, hwaddr addr) 75 { 76 uint32_t ret; 77 78 OMAP_32B_REG(addr); 79 cpu_physical_memory_read(addr, &ret, 4); 80 return ret; 81 } 82 83 void omap_badwidth_write32(void *opaque, hwaddr addr, 84 uint32_t value) 85 { 86 OMAP_32B_REG(addr); 87 cpu_physical_memory_write(addr, &value, 4); 88 } 89 90 /* MPU OS timers */ 91 struct omap_mpu_timer_s { 92 MemoryRegion iomem; 93 qemu_irq irq; 94 omap_clk clk; 95 uint32_t val; 96 int64_t time; 97 QEMUTimer *timer; 98 QEMUBH *tick; 99 int64_t rate; 100 int it_ena; 101 102 int enable; 103 int ptv; 104 int ar; 105 int st; 106 uint32_t reset_val; 107 }; 108 109 static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer) 110 { 111 uint64_t distance = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->time; 112 113 if (timer->st && timer->enable && timer->rate) 114 return timer->val - muldiv64(distance >> (timer->ptv + 1), 115 timer->rate, NANOSECONDS_PER_SECOND); 116 else 117 return timer->val; 118 } 119 120 static inline void omap_timer_sync(struct omap_mpu_timer_s *timer) 121 { 122 timer->val = omap_timer_read(timer); 123 timer->time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 124 } 125 126 static inline void omap_timer_update(struct omap_mpu_timer_s *timer) 127 { 128 int64_t expires; 129 130 if (timer->enable && timer->st && timer->rate) { 131 timer->val = timer->reset_val; /* Should skip this on clk enable */ 132 expires = muldiv64((uint64_t) timer->val << (timer->ptv + 1), 133 NANOSECONDS_PER_SECOND, timer->rate); 134 135 /* If timer expiry would be sooner than in about 1 ms and 136 * auto-reload isn't set, then fire immediately. This is a hack 137 * to make systems like PalmOS run in acceptable time. PalmOS 138 * sets the interval to a very low value and polls the status bit 139 * in a busy loop when it wants to sleep just a couple of CPU 140 * ticks. */ 141 if (expires > (NANOSECONDS_PER_SECOND >> 10) || timer->ar) { 142 timer_mod(timer->timer, timer->time + expires); 143 } else { 144 qemu_bh_schedule(timer->tick); 145 } 146 } else 147 timer_del(timer->timer); 148 } 149 150 static void omap_timer_fire(void *opaque) 151 { 152 struct omap_mpu_timer_s *timer = opaque; 153 154 if (!timer->ar) { 155 timer->val = 0; 156 timer->st = 0; 157 } 158 159 if (timer->it_ena) 160 /* Edge-triggered irq */ 161 qemu_irq_pulse(timer->irq); 162 } 163 164 static void omap_timer_tick(void *opaque) 165 { 166 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque; 167 168 omap_timer_sync(timer); 169 omap_timer_fire(timer); 170 omap_timer_update(timer); 171 } 172 173 static void omap_timer_clk_update(void *opaque, int line, int on) 174 { 175 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque; 176 177 omap_timer_sync(timer); 178 timer->rate = on ? omap_clk_getrate(timer->clk) : 0; 179 omap_timer_update(timer); 180 } 181 182 static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer) 183 { 184 omap_clk_adduser(timer->clk, 185 qemu_allocate_irq(omap_timer_clk_update, timer, 0)); 186 timer->rate = omap_clk_getrate(timer->clk); 187 } 188 189 static uint64_t omap_mpu_timer_read(void *opaque, hwaddr addr, 190 unsigned size) 191 { 192 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; 193 194 if (size != 4) { 195 return omap_badwidth_read32(opaque, addr); 196 } 197 198 switch (addr) { 199 case 0x00: /* CNTL_TIMER */ 200 return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st; 201 202 case 0x04: /* LOAD_TIM */ 203 break; 204 205 case 0x08: /* READ_TIM */ 206 return omap_timer_read(s); 207 } 208 209 OMAP_BAD_REG(addr); 210 return 0; 211 } 212 213 static void omap_mpu_timer_write(void *opaque, hwaddr addr, 214 uint64_t value, unsigned size) 215 { 216 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; 217 218 if (size != 4) { 219 omap_badwidth_write32(opaque, addr, value); 220 return; 221 } 222 223 switch (addr) { 224 case 0x00: /* CNTL_TIMER */ 225 omap_timer_sync(s); 226 s->enable = (value >> 5) & 1; 227 s->ptv = (value >> 2) & 7; 228 s->ar = (value >> 1) & 1; 229 s->st = value & 1; 230 omap_timer_update(s); 231 return; 232 233 case 0x04: /* LOAD_TIM */ 234 s->reset_val = value; 235 return; 236 237 case 0x08: /* READ_TIM */ 238 OMAP_RO_REG(addr); 239 break; 240 241 default: 242 OMAP_BAD_REG(addr); 243 } 244 } 245 246 static const MemoryRegionOps omap_mpu_timer_ops = { 247 .read = omap_mpu_timer_read, 248 .write = omap_mpu_timer_write, 249 .endianness = DEVICE_LITTLE_ENDIAN, 250 }; 251 252 static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s) 253 { 254 timer_del(s->timer); 255 s->enable = 0; 256 s->reset_val = 31337; 257 s->val = 0; 258 s->ptv = 0; 259 s->ar = 0; 260 s->st = 0; 261 s->it_ena = 1; 262 } 263 264 static struct omap_mpu_timer_s *omap_mpu_timer_init(MemoryRegion *system_memory, 265 hwaddr base, 266 qemu_irq irq, omap_clk clk) 267 { 268 struct omap_mpu_timer_s *s = g_new0(struct omap_mpu_timer_s, 1); 269 270 s->irq = irq; 271 s->clk = clk; 272 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, s); 273 s->tick = qemu_bh_new(omap_timer_fire, s); 274 omap_mpu_timer_reset(s); 275 omap_timer_clk_setup(s); 276 277 memory_region_init_io(&s->iomem, NULL, &omap_mpu_timer_ops, s, 278 "omap-mpu-timer", 0x100); 279 280 memory_region_add_subregion(system_memory, base, &s->iomem); 281 282 return s; 283 } 284 285 /* Watchdog timer */ 286 struct omap_watchdog_timer_s { 287 struct omap_mpu_timer_s timer; 288 MemoryRegion iomem; 289 uint8_t last_wr; 290 int mode; 291 int free; 292 int reset; 293 }; 294 295 static uint64_t omap_wd_timer_read(void *opaque, hwaddr addr, 296 unsigned size) 297 { 298 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; 299 300 if (size != 2) { 301 return omap_badwidth_read16(opaque, addr); 302 } 303 304 switch (addr) { 305 case 0x00: /* CNTL_TIMER */ 306 return (s->timer.ptv << 9) | (s->timer.ar << 8) | 307 (s->timer.st << 7) | (s->free << 1); 308 309 case 0x04: /* READ_TIMER */ 310 return omap_timer_read(&s->timer); 311 312 case 0x08: /* TIMER_MODE */ 313 return s->mode << 15; 314 } 315 316 OMAP_BAD_REG(addr); 317 return 0; 318 } 319 320 static void omap_wd_timer_write(void *opaque, hwaddr addr, 321 uint64_t value, unsigned size) 322 { 323 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; 324 325 if (size != 2) { 326 omap_badwidth_write16(opaque, addr, value); 327 return; 328 } 329 330 switch (addr) { 331 case 0x00: /* CNTL_TIMER */ 332 omap_timer_sync(&s->timer); 333 s->timer.ptv = (value >> 9) & 7; 334 s->timer.ar = (value >> 8) & 1; 335 s->timer.st = (value >> 7) & 1; 336 s->free = (value >> 1) & 1; 337 omap_timer_update(&s->timer); 338 break; 339 340 case 0x04: /* LOAD_TIMER */ 341 s->timer.reset_val = value & 0xffff; 342 break; 343 344 case 0x08: /* TIMER_MODE */ 345 if (!s->mode && ((value >> 15) & 1)) 346 omap_clk_get(s->timer.clk); 347 s->mode |= (value >> 15) & 1; 348 if (s->last_wr == 0xf5) { 349 if ((value & 0xff) == 0xa0) { 350 if (s->mode) { 351 s->mode = 0; 352 omap_clk_put(s->timer.clk); 353 } 354 } else { 355 /* XXX: on T|E hardware somehow this has no effect, 356 * on Zire 71 it works as specified. */ 357 s->reset = 1; 358 qemu_system_reset_request(); 359 } 360 } 361 s->last_wr = value & 0xff; 362 break; 363 364 default: 365 OMAP_BAD_REG(addr); 366 } 367 } 368 369 static const MemoryRegionOps omap_wd_timer_ops = { 370 .read = omap_wd_timer_read, 371 .write = omap_wd_timer_write, 372 .endianness = DEVICE_NATIVE_ENDIAN, 373 }; 374 375 static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s) 376 { 377 timer_del(s->timer.timer); 378 if (!s->mode) 379 omap_clk_get(s->timer.clk); 380 s->mode = 1; 381 s->free = 1; 382 s->reset = 0; 383 s->timer.enable = 1; 384 s->timer.it_ena = 1; 385 s->timer.reset_val = 0xffff; 386 s->timer.val = 0; 387 s->timer.st = 0; 388 s->timer.ptv = 0; 389 s->timer.ar = 0; 390 omap_timer_update(&s->timer); 391 } 392 393 static struct omap_watchdog_timer_s *omap_wd_timer_init(MemoryRegion *memory, 394 hwaddr base, 395 qemu_irq irq, omap_clk clk) 396 { 397 struct omap_watchdog_timer_s *s = g_new0(struct omap_watchdog_timer_s, 1); 398 399 s->timer.irq = irq; 400 s->timer.clk = clk; 401 s->timer.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, &s->timer); 402 omap_wd_timer_reset(s); 403 omap_timer_clk_setup(&s->timer); 404 405 memory_region_init_io(&s->iomem, NULL, &omap_wd_timer_ops, s, 406 "omap-wd-timer", 0x100); 407 memory_region_add_subregion(memory, base, &s->iomem); 408 409 return s; 410 } 411 412 /* 32-kHz timer */ 413 struct omap_32khz_timer_s { 414 struct omap_mpu_timer_s timer; 415 MemoryRegion iomem; 416 }; 417 418 static uint64_t omap_os_timer_read(void *opaque, hwaddr addr, 419 unsigned size) 420 { 421 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; 422 int offset = addr & OMAP_MPUI_REG_MASK; 423 424 if (size != 4) { 425 return omap_badwidth_read32(opaque, addr); 426 } 427 428 switch (offset) { 429 case 0x00: /* TVR */ 430 return s->timer.reset_val; 431 432 case 0x04: /* TCR */ 433 return omap_timer_read(&s->timer); 434 435 case 0x08: /* CR */ 436 return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st; 437 438 default: 439 break; 440 } 441 OMAP_BAD_REG(addr); 442 return 0; 443 } 444 445 static void omap_os_timer_write(void *opaque, hwaddr addr, 446 uint64_t value, unsigned size) 447 { 448 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; 449 int offset = addr & OMAP_MPUI_REG_MASK; 450 451 if (size != 4) { 452 omap_badwidth_write32(opaque, addr, value); 453 return; 454 } 455 456 switch (offset) { 457 case 0x00: /* TVR */ 458 s->timer.reset_val = value & 0x00ffffff; 459 break; 460 461 case 0x04: /* TCR */ 462 OMAP_RO_REG(addr); 463 break; 464 465 case 0x08: /* CR */ 466 s->timer.ar = (value >> 3) & 1; 467 s->timer.it_ena = (value >> 2) & 1; 468 if (s->timer.st != (value & 1) || (value & 2)) { 469 omap_timer_sync(&s->timer); 470 s->timer.enable = value & 1; 471 s->timer.st = value & 1; 472 omap_timer_update(&s->timer); 473 } 474 break; 475 476 default: 477 OMAP_BAD_REG(addr); 478 } 479 } 480 481 static const MemoryRegionOps omap_os_timer_ops = { 482 .read = omap_os_timer_read, 483 .write = omap_os_timer_write, 484 .endianness = DEVICE_NATIVE_ENDIAN, 485 }; 486 487 static void omap_os_timer_reset(struct omap_32khz_timer_s *s) 488 { 489 timer_del(s->timer.timer); 490 s->timer.enable = 0; 491 s->timer.it_ena = 0; 492 s->timer.reset_val = 0x00ffffff; 493 s->timer.val = 0; 494 s->timer.st = 0; 495 s->timer.ptv = 0; 496 s->timer.ar = 1; 497 } 498 499 static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory, 500 hwaddr base, 501 qemu_irq irq, omap_clk clk) 502 { 503 struct omap_32khz_timer_s *s = g_new0(struct omap_32khz_timer_s, 1); 504 505 s->timer.irq = irq; 506 s->timer.clk = clk; 507 s->timer.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, &s->timer); 508 omap_os_timer_reset(s); 509 omap_timer_clk_setup(&s->timer); 510 511 memory_region_init_io(&s->iomem, NULL, &omap_os_timer_ops, s, 512 "omap-os-timer", 0x800); 513 memory_region_add_subregion(memory, base, &s->iomem); 514 515 return s; 516 } 517 518 /* Ultra Low-Power Device Module */ 519 static uint64_t omap_ulpd_pm_read(void *opaque, hwaddr addr, 520 unsigned size) 521 { 522 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 523 uint16_t ret; 524 525 if (size != 2) { 526 return omap_badwidth_read16(opaque, addr); 527 } 528 529 switch (addr) { 530 case 0x14: /* IT_STATUS */ 531 ret = s->ulpd_pm_regs[addr >> 2]; 532 s->ulpd_pm_regs[addr >> 2] = 0; 533 qemu_irq_lower(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K)); 534 return ret; 535 536 case 0x18: /* Reserved */ 537 case 0x1c: /* Reserved */ 538 case 0x20: /* Reserved */ 539 case 0x28: /* Reserved */ 540 case 0x2c: /* Reserved */ 541 OMAP_BAD_REG(addr); 542 /* fall through */ 543 case 0x00: /* COUNTER_32_LSB */ 544 case 0x04: /* COUNTER_32_MSB */ 545 case 0x08: /* COUNTER_HIGH_FREQ_LSB */ 546 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ 547 case 0x10: /* GAUGING_CTRL */ 548 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ 549 case 0x30: /* CLOCK_CTRL */ 550 case 0x34: /* SOFT_REQ */ 551 case 0x38: /* COUNTER_32_FIQ */ 552 case 0x3c: /* DPLL_CTRL */ 553 case 0x40: /* STATUS_REQ */ 554 /* XXX: check clk::usecount state for every clock */ 555 case 0x48: /* LOCL_TIME */ 556 case 0x4c: /* APLL_CTRL */ 557 case 0x50: /* POWER_CTRL */ 558 return s->ulpd_pm_regs[addr >> 2]; 559 } 560 561 OMAP_BAD_REG(addr); 562 return 0; 563 } 564 565 static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s, 566 uint16_t diff, uint16_t value) 567 { 568 if (diff & (1 << 4)) /* USB_MCLK_EN */ 569 omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1); 570 if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */ 571 omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1); 572 } 573 574 static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s, 575 uint16_t diff, uint16_t value) 576 { 577 if (diff & (1 << 0)) /* SOFT_DPLL_REQ */ 578 omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1); 579 if (diff & (1 << 1)) /* SOFT_COM_REQ */ 580 omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1); 581 if (diff & (1 << 2)) /* SOFT_SDW_REQ */ 582 omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1); 583 if (diff & (1 << 3)) /* SOFT_USB_REQ */ 584 omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1); 585 } 586 587 static void omap_ulpd_pm_write(void *opaque, hwaddr addr, 588 uint64_t value, unsigned size) 589 { 590 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 591 int64_t now, ticks; 592 int div, mult; 593 static const int bypass_div[4] = { 1, 2, 4, 4 }; 594 uint16_t diff; 595 596 if (size != 2) { 597 omap_badwidth_write16(opaque, addr, value); 598 return; 599 } 600 601 switch (addr) { 602 case 0x00: /* COUNTER_32_LSB */ 603 case 0x04: /* COUNTER_32_MSB */ 604 case 0x08: /* COUNTER_HIGH_FREQ_LSB */ 605 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ 606 case 0x14: /* IT_STATUS */ 607 case 0x40: /* STATUS_REQ */ 608 OMAP_RO_REG(addr); 609 break; 610 611 case 0x10: /* GAUGING_CTRL */ 612 /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */ 613 if ((s->ulpd_pm_regs[addr >> 2] ^ value) & 1) { 614 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 615 616 if (value & 1) 617 s->ulpd_gauge_start = now; 618 else { 619 now -= s->ulpd_gauge_start; 620 621 /* 32-kHz ticks */ 622 ticks = muldiv64(now, 32768, NANOSECONDS_PER_SECOND); 623 s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff; 624 s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff; 625 if (ticks >> 32) /* OVERFLOW_32K */ 626 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2; 627 628 /* High frequency ticks */ 629 ticks = muldiv64(now, 12000000, NANOSECONDS_PER_SECOND); 630 s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff; 631 s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff; 632 if (ticks >> 32) /* OVERFLOW_HI_FREQ */ 633 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1; 634 635 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */ 636 qemu_irq_raise(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K)); 637 } 638 } 639 s->ulpd_pm_regs[addr >> 2] = value; 640 break; 641 642 case 0x18: /* Reserved */ 643 case 0x1c: /* Reserved */ 644 case 0x20: /* Reserved */ 645 case 0x28: /* Reserved */ 646 case 0x2c: /* Reserved */ 647 OMAP_BAD_REG(addr); 648 /* fall through */ 649 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ 650 case 0x38: /* COUNTER_32_FIQ */ 651 case 0x48: /* LOCL_TIME */ 652 case 0x50: /* POWER_CTRL */ 653 s->ulpd_pm_regs[addr >> 2] = value; 654 break; 655 656 case 0x30: /* CLOCK_CTRL */ 657 diff = s->ulpd_pm_regs[addr >> 2] ^ value; 658 s->ulpd_pm_regs[addr >> 2] = value & 0x3f; 659 omap_ulpd_clk_update(s, diff, value); 660 break; 661 662 case 0x34: /* SOFT_REQ */ 663 diff = s->ulpd_pm_regs[addr >> 2] ^ value; 664 s->ulpd_pm_regs[addr >> 2] = value & 0x1f; 665 omap_ulpd_req_update(s, diff, value); 666 break; 667 668 case 0x3c: /* DPLL_CTRL */ 669 /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is 670 * omitted altogether, probably a typo. */ 671 /* This register has identical semantics with DPLL(1:3) control 672 * registers, see omap_dpll_write() */ 673 diff = s->ulpd_pm_regs[addr >> 2] & value; 674 s->ulpd_pm_regs[addr >> 2] = value & 0x2fff; 675 if (diff & (0x3ff << 2)) { 676 if (value & (1 << 4)) { /* PLL_ENABLE */ 677 div = ((value >> 5) & 3) + 1; /* PLL_DIV */ 678 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ 679 } else { 680 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ 681 mult = 1; 682 } 683 omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult); 684 } 685 686 /* Enter the desired mode. */ 687 s->ulpd_pm_regs[addr >> 2] = 688 (s->ulpd_pm_regs[addr >> 2] & 0xfffe) | 689 ((s->ulpd_pm_regs[addr >> 2] >> 4) & 1); 690 691 /* Act as if the lock is restored. */ 692 s->ulpd_pm_regs[addr >> 2] |= 2; 693 break; 694 695 case 0x4c: /* APLL_CTRL */ 696 diff = s->ulpd_pm_regs[addr >> 2] & value; 697 s->ulpd_pm_regs[addr >> 2] = value & 0xf; 698 if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */ 699 omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s, 700 (value & (1 << 0)) ? "apll" : "dpll4")); 701 break; 702 703 default: 704 OMAP_BAD_REG(addr); 705 } 706 } 707 708 static const MemoryRegionOps omap_ulpd_pm_ops = { 709 .read = omap_ulpd_pm_read, 710 .write = omap_ulpd_pm_write, 711 .endianness = DEVICE_NATIVE_ENDIAN, 712 }; 713 714 static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu) 715 { 716 mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001; 717 mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000; 718 mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001; 719 mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000; 720 mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000; 721 mpu->ulpd_pm_regs[0x18 >> 2] = 0x01; 722 mpu->ulpd_pm_regs[0x1c >> 2] = 0x01; 723 mpu->ulpd_pm_regs[0x20 >> 2] = 0x01; 724 mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff; 725 mpu->ulpd_pm_regs[0x28 >> 2] = 0x01; 726 mpu->ulpd_pm_regs[0x2c >> 2] = 0x01; 727 omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000); 728 mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000; 729 omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000); 730 mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000; 731 mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001; 732 mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211; 733 mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */ 734 mpu->ulpd_pm_regs[0x48 >> 2] = 0x960; 735 mpu->ulpd_pm_regs[0x4c >> 2] = 0x08; 736 mpu->ulpd_pm_regs[0x50 >> 2] = 0x08; 737 omap_clk_setrate(omap_findclk(mpu, "dpll4"), 1, 4); 738 omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4")); 739 } 740 741 static void omap_ulpd_pm_init(MemoryRegion *system_memory, 742 hwaddr base, 743 struct omap_mpu_state_s *mpu) 744 { 745 memory_region_init_io(&mpu->ulpd_pm_iomem, NULL, &omap_ulpd_pm_ops, mpu, 746 "omap-ulpd-pm", 0x800); 747 memory_region_add_subregion(system_memory, base, &mpu->ulpd_pm_iomem); 748 omap_ulpd_pm_reset(mpu); 749 } 750 751 /* OMAP Pin Configuration */ 752 static uint64_t omap_pin_cfg_read(void *opaque, hwaddr addr, 753 unsigned size) 754 { 755 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 756 757 if (size != 4) { 758 return omap_badwidth_read32(opaque, addr); 759 } 760 761 switch (addr) { 762 case 0x00: /* FUNC_MUX_CTRL_0 */ 763 case 0x04: /* FUNC_MUX_CTRL_1 */ 764 case 0x08: /* FUNC_MUX_CTRL_2 */ 765 return s->func_mux_ctrl[addr >> 2]; 766 767 case 0x0c: /* COMP_MODE_CTRL_0 */ 768 return s->comp_mode_ctrl[0]; 769 770 case 0x10: /* FUNC_MUX_CTRL_3 */ 771 case 0x14: /* FUNC_MUX_CTRL_4 */ 772 case 0x18: /* FUNC_MUX_CTRL_5 */ 773 case 0x1c: /* FUNC_MUX_CTRL_6 */ 774 case 0x20: /* FUNC_MUX_CTRL_7 */ 775 case 0x24: /* FUNC_MUX_CTRL_8 */ 776 case 0x28: /* FUNC_MUX_CTRL_9 */ 777 case 0x2c: /* FUNC_MUX_CTRL_A */ 778 case 0x30: /* FUNC_MUX_CTRL_B */ 779 case 0x34: /* FUNC_MUX_CTRL_C */ 780 case 0x38: /* FUNC_MUX_CTRL_D */ 781 return s->func_mux_ctrl[(addr >> 2) - 1]; 782 783 case 0x40: /* PULL_DWN_CTRL_0 */ 784 case 0x44: /* PULL_DWN_CTRL_1 */ 785 case 0x48: /* PULL_DWN_CTRL_2 */ 786 case 0x4c: /* PULL_DWN_CTRL_3 */ 787 return s->pull_dwn_ctrl[(addr & 0xf) >> 2]; 788 789 case 0x50: /* GATE_INH_CTRL_0 */ 790 return s->gate_inh_ctrl[0]; 791 792 case 0x60: /* VOLTAGE_CTRL_0 */ 793 return s->voltage_ctrl[0]; 794 795 case 0x70: /* TEST_DBG_CTRL_0 */ 796 return s->test_dbg_ctrl[0]; 797 798 case 0x80: /* MOD_CONF_CTRL_0 */ 799 return s->mod_conf_ctrl[0]; 800 } 801 802 OMAP_BAD_REG(addr); 803 return 0; 804 } 805 806 static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s, 807 uint32_t diff, uint32_t value) 808 { 809 if (s->compat1509) { 810 if (diff & (1 << 9)) /* BLUETOOTH */ 811 omap_clk_onoff(omap_findclk(s, "bt_mclk_out"), 812 (~value >> 9) & 1); 813 if (diff & (1 << 7)) /* USB.CLKO */ 814 omap_clk_onoff(omap_findclk(s, "usb.clko"), 815 (value >> 7) & 1); 816 } 817 } 818 819 static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s, 820 uint32_t diff, uint32_t value) 821 { 822 if (s->compat1509) { 823 if (diff & (1U << 31)) { 824 /* MCBSP3_CLK_HIZ_DI */ 825 omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"), (value >> 31) & 1); 826 } 827 if (diff & (1 << 1)) { 828 /* CLK32K */ 829 omap_clk_onoff(omap_findclk(s, "clk32k_out"), (~value >> 1) & 1); 830 } 831 } 832 } 833 834 static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s, 835 uint32_t diff, uint32_t value) 836 { 837 if (diff & (1U << 31)) { 838 /* CONF_MOD_UART3_CLK_MODE_R */ 839 omap_clk_reparent(omap_findclk(s, "uart3_ck"), 840 omap_findclk(s, ((value >> 31) & 1) ? 841 "ck_48m" : "armper_ck")); 842 } 843 if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */ 844 omap_clk_reparent(omap_findclk(s, "uart2_ck"), 845 omap_findclk(s, ((value >> 30) & 1) ? 846 "ck_48m" : "armper_ck")); 847 if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */ 848 omap_clk_reparent(omap_findclk(s, "uart1_ck"), 849 omap_findclk(s, ((value >> 29) & 1) ? 850 "ck_48m" : "armper_ck")); 851 if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */ 852 omap_clk_reparent(omap_findclk(s, "mmc_ck"), 853 omap_findclk(s, ((value >> 23) & 1) ? 854 "ck_48m" : "armper_ck")); 855 if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */ 856 omap_clk_reparent(omap_findclk(s, "com_mclk_out"), 857 omap_findclk(s, ((value >> 12) & 1) ? 858 "ck_48m" : "armper_ck")); 859 if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */ 860 omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1); 861 } 862 863 static void omap_pin_cfg_write(void *opaque, hwaddr addr, 864 uint64_t value, unsigned size) 865 { 866 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 867 uint32_t diff; 868 869 if (size != 4) { 870 omap_badwidth_write32(opaque, addr, value); 871 return; 872 } 873 874 switch (addr) { 875 case 0x00: /* FUNC_MUX_CTRL_0 */ 876 diff = s->func_mux_ctrl[addr >> 2] ^ value; 877 s->func_mux_ctrl[addr >> 2] = value; 878 omap_pin_funcmux0_update(s, diff, value); 879 return; 880 881 case 0x04: /* FUNC_MUX_CTRL_1 */ 882 diff = s->func_mux_ctrl[addr >> 2] ^ value; 883 s->func_mux_ctrl[addr >> 2] = value; 884 omap_pin_funcmux1_update(s, diff, value); 885 return; 886 887 case 0x08: /* FUNC_MUX_CTRL_2 */ 888 s->func_mux_ctrl[addr >> 2] = value; 889 return; 890 891 case 0x0c: /* COMP_MODE_CTRL_0 */ 892 s->comp_mode_ctrl[0] = value; 893 s->compat1509 = (value != 0x0000eaef); 894 omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]); 895 omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]); 896 return; 897 898 case 0x10: /* FUNC_MUX_CTRL_3 */ 899 case 0x14: /* FUNC_MUX_CTRL_4 */ 900 case 0x18: /* FUNC_MUX_CTRL_5 */ 901 case 0x1c: /* FUNC_MUX_CTRL_6 */ 902 case 0x20: /* FUNC_MUX_CTRL_7 */ 903 case 0x24: /* FUNC_MUX_CTRL_8 */ 904 case 0x28: /* FUNC_MUX_CTRL_9 */ 905 case 0x2c: /* FUNC_MUX_CTRL_A */ 906 case 0x30: /* FUNC_MUX_CTRL_B */ 907 case 0x34: /* FUNC_MUX_CTRL_C */ 908 case 0x38: /* FUNC_MUX_CTRL_D */ 909 s->func_mux_ctrl[(addr >> 2) - 1] = value; 910 return; 911 912 case 0x40: /* PULL_DWN_CTRL_0 */ 913 case 0x44: /* PULL_DWN_CTRL_1 */ 914 case 0x48: /* PULL_DWN_CTRL_2 */ 915 case 0x4c: /* PULL_DWN_CTRL_3 */ 916 s->pull_dwn_ctrl[(addr & 0xf) >> 2] = value; 917 return; 918 919 case 0x50: /* GATE_INH_CTRL_0 */ 920 s->gate_inh_ctrl[0] = value; 921 return; 922 923 case 0x60: /* VOLTAGE_CTRL_0 */ 924 s->voltage_ctrl[0] = value; 925 return; 926 927 case 0x70: /* TEST_DBG_CTRL_0 */ 928 s->test_dbg_ctrl[0] = value; 929 return; 930 931 case 0x80: /* MOD_CONF_CTRL_0 */ 932 diff = s->mod_conf_ctrl[0] ^ value; 933 s->mod_conf_ctrl[0] = value; 934 omap_pin_modconf1_update(s, diff, value); 935 return; 936 937 default: 938 OMAP_BAD_REG(addr); 939 } 940 } 941 942 static const MemoryRegionOps omap_pin_cfg_ops = { 943 .read = omap_pin_cfg_read, 944 .write = omap_pin_cfg_write, 945 .endianness = DEVICE_NATIVE_ENDIAN, 946 }; 947 948 static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu) 949 { 950 /* Start in Compatibility Mode. */ 951 mpu->compat1509 = 1; 952 omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0); 953 omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0); 954 omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0); 955 memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl)); 956 memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl)); 957 memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl)); 958 memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl)); 959 memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl)); 960 memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl)); 961 memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl)); 962 } 963 964 static void omap_pin_cfg_init(MemoryRegion *system_memory, 965 hwaddr base, 966 struct omap_mpu_state_s *mpu) 967 { 968 memory_region_init_io(&mpu->pin_cfg_iomem, NULL, &omap_pin_cfg_ops, mpu, 969 "omap-pin-cfg", 0x800); 970 memory_region_add_subregion(system_memory, base, &mpu->pin_cfg_iomem); 971 omap_pin_cfg_reset(mpu); 972 } 973 974 /* Device Identification, Die Identification */ 975 static uint64_t omap_id_read(void *opaque, hwaddr addr, 976 unsigned size) 977 { 978 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 979 980 if (size != 4) { 981 return omap_badwidth_read32(opaque, addr); 982 } 983 984 switch (addr) { 985 case 0xfffe1800: /* DIE_ID_LSB */ 986 return 0xc9581f0e; 987 case 0xfffe1804: /* DIE_ID_MSB */ 988 return 0xa8858bfa; 989 990 case 0xfffe2000: /* PRODUCT_ID_LSB */ 991 return 0x00aaaafc; 992 case 0xfffe2004: /* PRODUCT_ID_MSB */ 993 return 0xcafeb574; 994 995 case 0xfffed400: /* JTAG_ID_LSB */ 996 switch (s->mpu_model) { 997 case omap310: 998 return 0x03310315; 999 case omap1510: 1000 return 0x03310115; 1001 default: 1002 hw_error("%s: bad mpu model\n", __FUNCTION__); 1003 } 1004 break; 1005 1006 case 0xfffed404: /* JTAG_ID_MSB */ 1007 switch (s->mpu_model) { 1008 case omap310: 1009 return 0xfb57402f; 1010 case omap1510: 1011 return 0xfb47002f; 1012 default: 1013 hw_error("%s: bad mpu model\n", __FUNCTION__); 1014 } 1015 break; 1016 } 1017 1018 OMAP_BAD_REG(addr); 1019 return 0; 1020 } 1021 1022 static void omap_id_write(void *opaque, hwaddr addr, 1023 uint64_t value, unsigned size) 1024 { 1025 if (size != 4) { 1026 omap_badwidth_write32(opaque, addr, value); 1027 return; 1028 } 1029 1030 OMAP_BAD_REG(addr); 1031 } 1032 1033 static const MemoryRegionOps omap_id_ops = { 1034 .read = omap_id_read, 1035 .write = omap_id_write, 1036 .endianness = DEVICE_NATIVE_ENDIAN, 1037 }; 1038 1039 static void omap_id_init(MemoryRegion *memory, struct omap_mpu_state_s *mpu) 1040 { 1041 memory_region_init_io(&mpu->id_iomem, NULL, &omap_id_ops, mpu, 1042 "omap-id", 0x100000000ULL); 1043 memory_region_init_alias(&mpu->id_iomem_e18, NULL, "omap-id-e18", &mpu->id_iomem, 1044 0xfffe1800, 0x800); 1045 memory_region_add_subregion(memory, 0xfffe1800, &mpu->id_iomem_e18); 1046 memory_region_init_alias(&mpu->id_iomem_ed4, NULL, "omap-id-ed4", &mpu->id_iomem, 1047 0xfffed400, 0x100); 1048 memory_region_add_subregion(memory, 0xfffed400, &mpu->id_iomem_ed4); 1049 if (!cpu_is_omap15xx(mpu)) { 1050 memory_region_init_alias(&mpu->id_iomem_ed4, NULL, "omap-id-e20", 1051 &mpu->id_iomem, 0xfffe2000, 0x800); 1052 memory_region_add_subregion(memory, 0xfffe2000, &mpu->id_iomem_e20); 1053 } 1054 } 1055 1056 /* MPUI Control (Dummy) */ 1057 static uint64_t omap_mpui_read(void *opaque, hwaddr addr, 1058 unsigned size) 1059 { 1060 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1061 1062 if (size != 4) { 1063 return omap_badwidth_read32(opaque, addr); 1064 } 1065 1066 switch (addr) { 1067 case 0x00: /* CTRL */ 1068 return s->mpui_ctrl; 1069 case 0x04: /* DEBUG_ADDR */ 1070 return 0x01ffffff; 1071 case 0x08: /* DEBUG_DATA */ 1072 return 0xffffffff; 1073 case 0x0c: /* DEBUG_FLAG */ 1074 return 0x00000800; 1075 case 0x10: /* STATUS */ 1076 return 0x00000000; 1077 1078 /* Not in OMAP310 */ 1079 case 0x14: /* DSP_STATUS */ 1080 case 0x18: /* DSP_BOOT_CONFIG */ 1081 return 0x00000000; 1082 case 0x1c: /* DSP_MPUI_CONFIG */ 1083 return 0x0000ffff; 1084 } 1085 1086 OMAP_BAD_REG(addr); 1087 return 0; 1088 } 1089 1090 static void omap_mpui_write(void *opaque, hwaddr addr, 1091 uint64_t value, unsigned size) 1092 { 1093 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1094 1095 if (size != 4) { 1096 omap_badwidth_write32(opaque, addr, value); 1097 return; 1098 } 1099 1100 switch (addr) { 1101 case 0x00: /* CTRL */ 1102 s->mpui_ctrl = value & 0x007fffff; 1103 break; 1104 1105 case 0x04: /* DEBUG_ADDR */ 1106 case 0x08: /* DEBUG_DATA */ 1107 case 0x0c: /* DEBUG_FLAG */ 1108 case 0x10: /* STATUS */ 1109 /* Not in OMAP310 */ 1110 case 0x14: /* DSP_STATUS */ 1111 OMAP_RO_REG(addr); 1112 break; 1113 case 0x18: /* DSP_BOOT_CONFIG */ 1114 case 0x1c: /* DSP_MPUI_CONFIG */ 1115 break; 1116 1117 default: 1118 OMAP_BAD_REG(addr); 1119 } 1120 } 1121 1122 static const MemoryRegionOps omap_mpui_ops = { 1123 .read = omap_mpui_read, 1124 .write = omap_mpui_write, 1125 .endianness = DEVICE_NATIVE_ENDIAN, 1126 }; 1127 1128 static void omap_mpui_reset(struct omap_mpu_state_s *s) 1129 { 1130 s->mpui_ctrl = 0x0003ff1b; 1131 } 1132 1133 static void omap_mpui_init(MemoryRegion *memory, hwaddr base, 1134 struct omap_mpu_state_s *mpu) 1135 { 1136 memory_region_init_io(&mpu->mpui_iomem, NULL, &omap_mpui_ops, mpu, 1137 "omap-mpui", 0x100); 1138 memory_region_add_subregion(memory, base, &mpu->mpui_iomem); 1139 1140 omap_mpui_reset(mpu); 1141 } 1142 1143 /* TIPB Bridges */ 1144 struct omap_tipb_bridge_s { 1145 qemu_irq abort; 1146 MemoryRegion iomem; 1147 1148 int width_intr; 1149 uint16_t control; 1150 uint16_t alloc; 1151 uint16_t buffer; 1152 uint16_t enh_control; 1153 }; 1154 1155 static uint64_t omap_tipb_bridge_read(void *opaque, hwaddr addr, 1156 unsigned size) 1157 { 1158 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; 1159 1160 if (size < 2) { 1161 return omap_badwidth_read16(opaque, addr); 1162 } 1163 1164 switch (addr) { 1165 case 0x00: /* TIPB_CNTL */ 1166 return s->control; 1167 case 0x04: /* TIPB_BUS_ALLOC */ 1168 return s->alloc; 1169 case 0x08: /* MPU_TIPB_CNTL */ 1170 return s->buffer; 1171 case 0x0c: /* ENHANCED_TIPB_CNTL */ 1172 return s->enh_control; 1173 case 0x10: /* ADDRESS_DBG */ 1174 case 0x14: /* DATA_DEBUG_LOW */ 1175 case 0x18: /* DATA_DEBUG_HIGH */ 1176 return 0xffff; 1177 case 0x1c: /* DEBUG_CNTR_SIG */ 1178 return 0x00f8; 1179 } 1180 1181 OMAP_BAD_REG(addr); 1182 return 0; 1183 } 1184 1185 static void omap_tipb_bridge_write(void *opaque, hwaddr addr, 1186 uint64_t value, unsigned size) 1187 { 1188 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; 1189 1190 if (size < 2) { 1191 omap_badwidth_write16(opaque, addr, value); 1192 return; 1193 } 1194 1195 switch (addr) { 1196 case 0x00: /* TIPB_CNTL */ 1197 s->control = value & 0xffff; 1198 break; 1199 1200 case 0x04: /* TIPB_BUS_ALLOC */ 1201 s->alloc = value & 0x003f; 1202 break; 1203 1204 case 0x08: /* MPU_TIPB_CNTL */ 1205 s->buffer = value & 0x0003; 1206 break; 1207 1208 case 0x0c: /* ENHANCED_TIPB_CNTL */ 1209 s->width_intr = !(value & 2); 1210 s->enh_control = value & 0x000f; 1211 break; 1212 1213 case 0x10: /* ADDRESS_DBG */ 1214 case 0x14: /* DATA_DEBUG_LOW */ 1215 case 0x18: /* DATA_DEBUG_HIGH */ 1216 case 0x1c: /* DEBUG_CNTR_SIG */ 1217 OMAP_RO_REG(addr); 1218 break; 1219 1220 default: 1221 OMAP_BAD_REG(addr); 1222 } 1223 } 1224 1225 static const MemoryRegionOps omap_tipb_bridge_ops = { 1226 .read = omap_tipb_bridge_read, 1227 .write = omap_tipb_bridge_write, 1228 .endianness = DEVICE_NATIVE_ENDIAN, 1229 }; 1230 1231 static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s) 1232 { 1233 s->control = 0xffff; 1234 s->alloc = 0x0009; 1235 s->buffer = 0x0000; 1236 s->enh_control = 0x000f; 1237 } 1238 1239 static struct omap_tipb_bridge_s *omap_tipb_bridge_init( 1240 MemoryRegion *memory, hwaddr base, 1241 qemu_irq abort_irq, omap_clk clk) 1242 { 1243 struct omap_tipb_bridge_s *s = g_new0(struct omap_tipb_bridge_s, 1); 1244 1245 s->abort = abort_irq; 1246 omap_tipb_bridge_reset(s); 1247 1248 memory_region_init_io(&s->iomem, NULL, &omap_tipb_bridge_ops, s, 1249 "omap-tipb-bridge", 0x100); 1250 memory_region_add_subregion(memory, base, &s->iomem); 1251 1252 return s; 1253 } 1254 1255 /* Dummy Traffic Controller's Memory Interface */ 1256 static uint64_t omap_tcmi_read(void *opaque, hwaddr addr, 1257 unsigned size) 1258 { 1259 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1260 uint32_t ret; 1261 1262 if (size != 4) { 1263 return omap_badwidth_read32(opaque, addr); 1264 } 1265 1266 switch (addr) { 1267 case 0x00: /* IMIF_PRIO */ 1268 case 0x04: /* EMIFS_PRIO */ 1269 case 0x08: /* EMIFF_PRIO */ 1270 case 0x0c: /* EMIFS_CONFIG */ 1271 case 0x10: /* EMIFS_CS0_CONFIG */ 1272 case 0x14: /* EMIFS_CS1_CONFIG */ 1273 case 0x18: /* EMIFS_CS2_CONFIG */ 1274 case 0x1c: /* EMIFS_CS3_CONFIG */ 1275 case 0x24: /* EMIFF_MRS */ 1276 case 0x28: /* TIMEOUT1 */ 1277 case 0x2c: /* TIMEOUT2 */ 1278 case 0x30: /* TIMEOUT3 */ 1279 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ 1280 case 0x40: /* EMIFS_CFG_DYN_WAIT */ 1281 return s->tcmi_regs[addr >> 2]; 1282 1283 case 0x20: /* EMIFF_SDRAM_CONFIG */ 1284 ret = s->tcmi_regs[addr >> 2]; 1285 s->tcmi_regs[addr >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */ 1286 /* XXX: We can try using the VGA_DIRTY flag for this */ 1287 return ret; 1288 } 1289 1290 OMAP_BAD_REG(addr); 1291 return 0; 1292 } 1293 1294 static void omap_tcmi_write(void *opaque, hwaddr addr, 1295 uint64_t value, unsigned size) 1296 { 1297 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1298 1299 if (size != 4) { 1300 omap_badwidth_write32(opaque, addr, value); 1301 return; 1302 } 1303 1304 switch (addr) { 1305 case 0x00: /* IMIF_PRIO */ 1306 case 0x04: /* EMIFS_PRIO */ 1307 case 0x08: /* EMIFF_PRIO */ 1308 case 0x10: /* EMIFS_CS0_CONFIG */ 1309 case 0x14: /* EMIFS_CS1_CONFIG */ 1310 case 0x18: /* EMIFS_CS2_CONFIG */ 1311 case 0x1c: /* EMIFS_CS3_CONFIG */ 1312 case 0x20: /* EMIFF_SDRAM_CONFIG */ 1313 case 0x24: /* EMIFF_MRS */ 1314 case 0x28: /* TIMEOUT1 */ 1315 case 0x2c: /* TIMEOUT2 */ 1316 case 0x30: /* TIMEOUT3 */ 1317 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ 1318 case 0x40: /* EMIFS_CFG_DYN_WAIT */ 1319 s->tcmi_regs[addr >> 2] = value; 1320 break; 1321 case 0x0c: /* EMIFS_CONFIG */ 1322 s->tcmi_regs[addr >> 2] = (value & 0xf) | (1 << 4); 1323 break; 1324 1325 default: 1326 OMAP_BAD_REG(addr); 1327 } 1328 } 1329 1330 static const MemoryRegionOps omap_tcmi_ops = { 1331 .read = omap_tcmi_read, 1332 .write = omap_tcmi_write, 1333 .endianness = DEVICE_NATIVE_ENDIAN, 1334 }; 1335 1336 static void omap_tcmi_reset(struct omap_mpu_state_s *mpu) 1337 { 1338 mpu->tcmi_regs[0x00 >> 2] = 0x00000000; 1339 mpu->tcmi_regs[0x04 >> 2] = 0x00000000; 1340 mpu->tcmi_regs[0x08 >> 2] = 0x00000000; 1341 mpu->tcmi_regs[0x0c >> 2] = 0x00000010; 1342 mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb; 1343 mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb; 1344 mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb; 1345 mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb; 1346 mpu->tcmi_regs[0x20 >> 2] = 0x00618800; 1347 mpu->tcmi_regs[0x24 >> 2] = 0x00000037; 1348 mpu->tcmi_regs[0x28 >> 2] = 0x00000000; 1349 mpu->tcmi_regs[0x2c >> 2] = 0x00000000; 1350 mpu->tcmi_regs[0x30 >> 2] = 0x00000000; 1351 mpu->tcmi_regs[0x3c >> 2] = 0x00000003; 1352 mpu->tcmi_regs[0x40 >> 2] = 0x00000000; 1353 } 1354 1355 static void omap_tcmi_init(MemoryRegion *memory, hwaddr base, 1356 struct omap_mpu_state_s *mpu) 1357 { 1358 memory_region_init_io(&mpu->tcmi_iomem, NULL, &omap_tcmi_ops, mpu, 1359 "omap-tcmi", 0x100); 1360 memory_region_add_subregion(memory, base, &mpu->tcmi_iomem); 1361 omap_tcmi_reset(mpu); 1362 } 1363 1364 /* Digital phase-locked loops control */ 1365 struct dpll_ctl_s { 1366 MemoryRegion iomem; 1367 uint16_t mode; 1368 omap_clk dpll; 1369 }; 1370 1371 static uint64_t omap_dpll_read(void *opaque, hwaddr addr, 1372 unsigned size) 1373 { 1374 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; 1375 1376 if (size != 2) { 1377 return omap_badwidth_read16(opaque, addr); 1378 } 1379 1380 if (addr == 0x00) /* CTL_REG */ 1381 return s->mode; 1382 1383 OMAP_BAD_REG(addr); 1384 return 0; 1385 } 1386 1387 static void omap_dpll_write(void *opaque, hwaddr addr, 1388 uint64_t value, unsigned size) 1389 { 1390 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; 1391 uint16_t diff; 1392 static const int bypass_div[4] = { 1, 2, 4, 4 }; 1393 int div, mult; 1394 1395 if (size != 2) { 1396 omap_badwidth_write16(opaque, addr, value); 1397 return; 1398 } 1399 1400 if (addr == 0x00) { /* CTL_REG */ 1401 /* See omap_ulpd_pm_write() too */ 1402 diff = s->mode & value; 1403 s->mode = value & 0x2fff; 1404 if (diff & (0x3ff << 2)) { 1405 if (value & (1 << 4)) { /* PLL_ENABLE */ 1406 div = ((value >> 5) & 3) + 1; /* PLL_DIV */ 1407 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ 1408 } else { 1409 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ 1410 mult = 1; 1411 } 1412 omap_clk_setrate(s->dpll, div, mult); 1413 } 1414 1415 /* Enter the desired mode. */ 1416 s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1); 1417 1418 /* Act as if the lock is restored. */ 1419 s->mode |= 2; 1420 } else { 1421 OMAP_BAD_REG(addr); 1422 } 1423 } 1424 1425 static const MemoryRegionOps omap_dpll_ops = { 1426 .read = omap_dpll_read, 1427 .write = omap_dpll_write, 1428 .endianness = DEVICE_NATIVE_ENDIAN, 1429 }; 1430 1431 static void omap_dpll_reset(struct dpll_ctl_s *s) 1432 { 1433 s->mode = 0x2002; 1434 omap_clk_setrate(s->dpll, 1, 1); 1435 } 1436 1437 static struct dpll_ctl_s *omap_dpll_init(MemoryRegion *memory, 1438 hwaddr base, omap_clk clk) 1439 { 1440 struct dpll_ctl_s *s = g_malloc0(sizeof(*s)); 1441 memory_region_init_io(&s->iomem, NULL, &omap_dpll_ops, s, "omap-dpll", 0x100); 1442 1443 s->dpll = clk; 1444 omap_dpll_reset(s); 1445 1446 memory_region_add_subregion(memory, base, &s->iomem); 1447 return s; 1448 } 1449 1450 /* MPU Clock/Reset/Power Mode Control */ 1451 static uint64_t omap_clkm_read(void *opaque, hwaddr addr, 1452 unsigned size) 1453 { 1454 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1455 1456 if (size != 2) { 1457 return omap_badwidth_read16(opaque, addr); 1458 } 1459 1460 switch (addr) { 1461 case 0x00: /* ARM_CKCTL */ 1462 return s->clkm.arm_ckctl; 1463 1464 case 0x04: /* ARM_IDLECT1 */ 1465 return s->clkm.arm_idlect1; 1466 1467 case 0x08: /* ARM_IDLECT2 */ 1468 return s->clkm.arm_idlect2; 1469 1470 case 0x0c: /* ARM_EWUPCT */ 1471 return s->clkm.arm_ewupct; 1472 1473 case 0x10: /* ARM_RSTCT1 */ 1474 return s->clkm.arm_rstct1; 1475 1476 case 0x14: /* ARM_RSTCT2 */ 1477 return s->clkm.arm_rstct2; 1478 1479 case 0x18: /* ARM_SYSST */ 1480 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start; 1481 1482 case 0x1c: /* ARM_CKOUT1 */ 1483 return s->clkm.arm_ckout1; 1484 1485 case 0x20: /* ARM_CKOUT2 */ 1486 break; 1487 } 1488 1489 OMAP_BAD_REG(addr); 1490 return 0; 1491 } 1492 1493 static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s, 1494 uint16_t diff, uint16_t value) 1495 { 1496 omap_clk clk; 1497 1498 if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */ 1499 if (value & (1 << 14)) 1500 /* Reserved */; 1501 else { 1502 clk = omap_findclk(s, "arminth_ck"); 1503 omap_clk_reparent(clk, omap_findclk(s, "tc_ck")); 1504 } 1505 } 1506 if (diff & (1 << 12)) { /* ARM_TIMXO */ 1507 clk = omap_findclk(s, "armtim_ck"); 1508 if (value & (1 << 12)) 1509 omap_clk_reparent(clk, omap_findclk(s, "clkin")); 1510 else 1511 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1")); 1512 } 1513 /* XXX: en_dspck */ 1514 if (diff & (3 << 10)) { /* DSPMMUDIV */ 1515 clk = omap_findclk(s, "dspmmu_ck"); 1516 omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1); 1517 } 1518 if (diff & (3 << 8)) { /* TCDIV */ 1519 clk = omap_findclk(s, "tc_ck"); 1520 omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1); 1521 } 1522 if (diff & (3 << 6)) { /* DSPDIV */ 1523 clk = omap_findclk(s, "dsp_ck"); 1524 omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1); 1525 } 1526 if (diff & (3 << 4)) { /* ARMDIV */ 1527 clk = omap_findclk(s, "arm_ck"); 1528 omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1); 1529 } 1530 if (diff & (3 << 2)) { /* LCDDIV */ 1531 clk = omap_findclk(s, "lcd_ck"); 1532 omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1); 1533 } 1534 if (diff & (3 << 0)) { /* PERDIV */ 1535 clk = omap_findclk(s, "armper_ck"); 1536 omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1); 1537 } 1538 } 1539 1540 static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s, 1541 uint16_t diff, uint16_t value) 1542 { 1543 omap_clk clk; 1544 1545 if (value & (1 << 11)) { /* SETARM_IDLE */ 1546 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); 1547 } 1548 if (!(value & (1 << 10))) /* WKUP_MODE */ 1549 qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */ 1550 1551 #define SET_CANIDLE(clock, bit) \ 1552 if (diff & (1 << bit)) { \ 1553 clk = omap_findclk(s, clock); \ 1554 omap_clk_canidle(clk, (value >> bit) & 1); \ 1555 } 1556 SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */ 1557 SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */ 1558 SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */ 1559 SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */ 1560 SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */ 1561 SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */ 1562 SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */ 1563 SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */ 1564 SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */ 1565 SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */ 1566 SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */ 1567 SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */ 1568 SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */ 1569 SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */ 1570 } 1571 1572 static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s, 1573 uint16_t diff, uint16_t value) 1574 { 1575 omap_clk clk; 1576 1577 #define SET_ONOFF(clock, bit) \ 1578 if (diff & (1 << bit)) { \ 1579 clk = omap_findclk(s, clock); \ 1580 omap_clk_onoff(clk, (value >> bit) & 1); \ 1581 } 1582 SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */ 1583 SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */ 1584 SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */ 1585 SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */ 1586 SET_ONOFF("lb_ck", 4) /* EN_LBCK */ 1587 SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */ 1588 SET_ONOFF("mpui_ck", 6) /* EN_APICK */ 1589 SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */ 1590 SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */ 1591 SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */ 1592 SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */ 1593 } 1594 1595 static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s, 1596 uint16_t diff, uint16_t value) 1597 { 1598 omap_clk clk; 1599 1600 if (diff & (3 << 4)) { /* TCLKOUT */ 1601 clk = omap_findclk(s, "tclk_out"); 1602 switch ((value >> 4) & 3) { 1603 case 1: 1604 omap_clk_reparent(clk, omap_findclk(s, "ck_gen3")); 1605 omap_clk_onoff(clk, 1); 1606 break; 1607 case 2: 1608 omap_clk_reparent(clk, omap_findclk(s, "tc_ck")); 1609 omap_clk_onoff(clk, 1); 1610 break; 1611 default: 1612 omap_clk_onoff(clk, 0); 1613 } 1614 } 1615 if (diff & (3 << 2)) { /* DCLKOUT */ 1616 clk = omap_findclk(s, "dclk_out"); 1617 switch ((value >> 2) & 3) { 1618 case 0: 1619 omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck")); 1620 break; 1621 case 1: 1622 omap_clk_reparent(clk, omap_findclk(s, "ck_gen2")); 1623 break; 1624 case 2: 1625 omap_clk_reparent(clk, omap_findclk(s, "dsp_ck")); 1626 break; 1627 case 3: 1628 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14")); 1629 break; 1630 } 1631 } 1632 if (diff & (3 << 0)) { /* ACLKOUT */ 1633 clk = omap_findclk(s, "aclk_out"); 1634 switch ((value >> 0) & 3) { 1635 case 1: 1636 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1")); 1637 omap_clk_onoff(clk, 1); 1638 break; 1639 case 2: 1640 omap_clk_reparent(clk, omap_findclk(s, "arm_ck")); 1641 omap_clk_onoff(clk, 1); 1642 break; 1643 case 3: 1644 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14")); 1645 omap_clk_onoff(clk, 1); 1646 break; 1647 default: 1648 omap_clk_onoff(clk, 0); 1649 } 1650 } 1651 } 1652 1653 static void omap_clkm_write(void *opaque, hwaddr addr, 1654 uint64_t value, unsigned size) 1655 { 1656 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1657 uint16_t diff; 1658 omap_clk clk; 1659 static const char *clkschemename[8] = { 1660 "fully synchronous", "fully asynchronous", "synchronous scalable", 1661 "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4", 1662 }; 1663 1664 if (size != 2) { 1665 omap_badwidth_write16(opaque, addr, value); 1666 return; 1667 } 1668 1669 switch (addr) { 1670 case 0x00: /* ARM_CKCTL */ 1671 diff = s->clkm.arm_ckctl ^ value; 1672 s->clkm.arm_ckctl = value & 0x7fff; 1673 omap_clkm_ckctl_update(s, diff, value); 1674 return; 1675 1676 case 0x04: /* ARM_IDLECT1 */ 1677 diff = s->clkm.arm_idlect1 ^ value; 1678 s->clkm.arm_idlect1 = value & 0x0fff; 1679 omap_clkm_idlect1_update(s, diff, value); 1680 return; 1681 1682 case 0x08: /* ARM_IDLECT2 */ 1683 diff = s->clkm.arm_idlect2 ^ value; 1684 s->clkm.arm_idlect2 = value & 0x07ff; 1685 omap_clkm_idlect2_update(s, diff, value); 1686 return; 1687 1688 case 0x0c: /* ARM_EWUPCT */ 1689 s->clkm.arm_ewupct = value & 0x003f; 1690 return; 1691 1692 case 0x10: /* ARM_RSTCT1 */ 1693 diff = s->clkm.arm_rstct1 ^ value; 1694 s->clkm.arm_rstct1 = value & 0x0007; 1695 if (value & 9) { 1696 qemu_system_reset_request(); 1697 s->clkm.cold_start = 0xa; 1698 } 1699 if (diff & ~value & 4) { /* DSP_RST */ 1700 omap_mpui_reset(s); 1701 omap_tipb_bridge_reset(s->private_tipb); 1702 omap_tipb_bridge_reset(s->public_tipb); 1703 } 1704 if (diff & 2) { /* DSP_EN */ 1705 clk = omap_findclk(s, "dsp_ck"); 1706 omap_clk_canidle(clk, (~value >> 1) & 1); 1707 } 1708 return; 1709 1710 case 0x14: /* ARM_RSTCT2 */ 1711 s->clkm.arm_rstct2 = value & 0x0001; 1712 return; 1713 1714 case 0x18: /* ARM_SYSST */ 1715 if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) { 1716 s->clkm.clocking_scheme = (value >> 11) & 7; 1717 printf("%s: clocking scheme set to %s\n", __FUNCTION__, 1718 clkschemename[s->clkm.clocking_scheme]); 1719 } 1720 s->clkm.cold_start &= value & 0x3f; 1721 return; 1722 1723 case 0x1c: /* ARM_CKOUT1 */ 1724 diff = s->clkm.arm_ckout1 ^ value; 1725 s->clkm.arm_ckout1 = value & 0x003f; 1726 omap_clkm_ckout1_update(s, diff, value); 1727 return; 1728 1729 case 0x20: /* ARM_CKOUT2 */ 1730 default: 1731 OMAP_BAD_REG(addr); 1732 } 1733 } 1734 1735 static const MemoryRegionOps omap_clkm_ops = { 1736 .read = omap_clkm_read, 1737 .write = omap_clkm_write, 1738 .endianness = DEVICE_NATIVE_ENDIAN, 1739 }; 1740 1741 static uint64_t omap_clkdsp_read(void *opaque, hwaddr addr, 1742 unsigned size) 1743 { 1744 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1745 CPUState *cpu = CPU(s->cpu); 1746 1747 if (size != 2) { 1748 return omap_badwidth_read16(opaque, addr); 1749 } 1750 1751 switch (addr) { 1752 case 0x04: /* DSP_IDLECT1 */ 1753 return s->clkm.dsp_idlect1; 1754 1755 case 0x08: /* DSP_IDLECT2 */ 1756 return s->clkm.dsp_idlect2; 1757 1758 case 0x14: /* DSP_RSTCT2 */ 1759 return s->clkm.dsp_rstct2; 1760 1761 case 0x18: /* DSP_SYSST */ 1762 cpu = CPU(s->cpu); 1763 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start | 1764 (cpu->halted << 6); /* Quite useless... */ 1765 } 1766 1767 OMAP_BAD_REG(addr); 1768 return 0; 1769 } 1770 1771 static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s, 1772 uint16_t diff, uint16_t value) 1773 { 1774 omap_clk clk; 1775 1776 SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */ 1777 } 1778 1779 static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s, 1780 uint16_t diff, uint16_t value) 1781 { 1782 omap_clk clk; 1783 1784 SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */ 1785 } 1786 1787 static void omap_clkdsp_write(void *opaque, hwaddr addr, 1788 uint64_t value, unsigned size) 1789 { 1790 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1791 uint16_t diff; 1792 1793 if (size != 2) { 1794 omap_badwidth_write16(opaque, addr, value); 1795 return; 1796 } 1797 1798 switch (addr) { 1799 case 0x04: /* DSP_IDLECT1 */ 1800 diff = s->clkm.dsp_idlect1 ^ value; 1801 s->clkm.dsp_idlect1 = value & 0x01f7; 1802 omap_clkdsp_idlect1_update(s, diff, value); 1803 break; 1804 1805 case 0x08: /* DSP_IDLECT2 */ 1806 s->clkm.dsp_idlect2 = value & 0x0037; 1807 diff = s->clkm.dsp_idlect1 ^ value; 1808 omap_clkdsp_idlect2_update(s, diff, value); 1809 break; 1810 1811 case 0x14: /* DSP_RSTCT2 */ 1812 s->clkm.dsp_rstct2 = value & 0x0001; 1813 break; 1814 1815 case 0x18: /* DSP_SYSST */ 1816 s->clkm.cold_start &= value & 0x3f; 1817 break; 1818 1819 default: 1820 OMAP_BAD_REG(addr); 1821 } 1822 } 1823 1824 static const MemoryRegionOps omap_clkdsp_ops = { 1825 .read = omap_clkdsp_read, 1826 .write = omap_clkdsp_write, 1827 .endianness = DEVICE_NATIVE_ENDIAN, 1828 }; 1829 1830 static void omap_clkm_reset(struct omap_mpu_state_s *s) 1831 { 1832 if (s->wdt && s->wdt->reset) 1833 s->clkm.cold_start = 0x6; 1834 s->clkm.clocking_scheme = 0; 1835 omap_clkm_ckctl_update(s, ~0, 0x3000); 1836 s->clkm.arm_ckctl = 0x3000; 1837 omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 ^ 0x0400, 0x0400); 1838 s->clkm.arm_idlect1 = 0x0400; 1839 omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 ^ 0x0100, 0x0100); 1840 s->clkm.arm_idlect2 = 0x0100; 1841 s->clkm.arm_ewupct = 0x003f; 1842 s->clkm.arm_rstct1 = 0x0000; 1843 s->clkm.arm_rstct2 = 0x0000; 1844 s->clkm.arm_ckout1 = 0x0015; 1845 s->clkm.dpll1_mode = 0x2002; 1846 omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040); 1847 s->clkm.dsp_idlect1 = 0x0040; 1848 omap_clkdsp_idlect2_update(s, ~0, 0x0000); 1849 s->clkm.dsp_idlect2 = 0x0000; 1850 s->clkm.dsp_rstct2 = 0x0000; 1851 } 1852 1853 static void omap_clkm_init(MemoryRegion *memory, hwaddr mpu_base, 1854 hwaddr dsp_base, struct omap_mpu_state_s *s) 1855 { 1856 memory_region_init_io(&s->clkm_iomem, NULL, &omap_clkm_ops, s, 1857 "omap-clkm", 0x100); 1858 memory_region_init_io(&s->clkdsp_iomem, NULL, &omap_clkdsp_ops, s, 1859 "omap-clkdsp", 0x1000); 1860 1861 s->clkm.arm_idlect1 = 0x03ff; 1862 s->clkm.arm_idlect2 = 0x0100; 1863 s->clkm.dsp_idlect1 = 0x0002; 1864 omap_clkm_reset(s); 1865 s->clkm.cold_start = 0x3a; 1866 1867 memory_region_add_subregion(memory, mpu_base, &s->clkm_iomem); 1868 memory_region_add_subregion(memory, dsp_base, &s->clkdsp_iomem); 1869 } 1870 1871 /* MPU I/O */ 1872 struct omap_mpuio_s { 1873 qemu_irq irq; 1874 qemu_irq kbd_irq; 1875 qemu_irq *in; 1876 qemu_irq handler[16]; 1877 qemu_irq wakeup; 1878 MemoryRegion iomem; 1879 1880 uint16_t inputs; 1881 uint16_t outputs; 1882 uint16_t dir; 1883 uint16_t edge; 1884 uint16_t mask; 1885 uint16_t ints; 1886 1887 uint16_t debounce; 1888 uint16_t latch; 1889 uint8_t event; 1890 1891 uint8_t buttons[5]; 1892 uint8_t row_latch; 1893 uint8_t cols; 1894 int kbd_mask; 1895 int clk; 1896 }; 1897 1898 static void omap_mpuio_set(void *opaque, int line, int level) 1899 { 1900 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; 1901 uint16_t prev = s->inputs; 1902 1903 if (level) 1904 s->inputs |= 1 << line; 1905 else 1906 s->inputs &= ~(1 << line); 1907 1908 if (((1 << line) & s->dir & ~s->mask) && s->clk) { 1909 if ((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) { 1910 s->ints |= 1 << line; 1911 qemu_irq_raise(s->irq); 1912 /* TODO: wakeup */ 1913 } 1914 if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */ 1915 (s->event >> 1) == line) /* PIN_SELECT */ 1916 s->latch = s->inputs; 1917 } 1918 } 1919 1920 static void omap_mpuio_kbd_update(struct omap_mpuio_s *s) 1921 { 1922 int i; 1923 uint8_t *row, rows = 0, cols = ~s->cols; 1924 1925 for (row = s->buttons + 4, i = 1 << 4; i; row --, i >>= 1) 1926 if (*row & cols) 1927 rows |= i; 1928 1929 qemu_set_irq(s->kbd_irq, rows && !s->kbd_mask && s->clk); 1930 s->row_latch = ~rows; 1931 } 1932 1933 static uint64_t omap_mpuio_read(void *opaque, hwaddr addr, 1934 unsigned size) 1935 { 1936 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; 1937 int offset = addr & OMAP_MPUI_REG_MASK; 1938 uint16_t ret; 1939 1940 if (size != 2) { 1941 return omap_badwidth_read16(opaque, addr); 1942 } 1943 1944 switch (offset) { 1945 case 0x00: /* INPUT_LATCH */ 1946 return s->inputs; 1947 1948 case 0x04: /* OUTPUT_REG */ 1949 return s->outputs; 1950 1951 case 0x08: /* IO_CNTL */ 1952 return s->dir; 1953 1954 case 0x10: /* KBR_LATCH */ 1955 return s->row_latch; 1956 1957 case 0x14: /* KBC_REG */ 1958 return s->cols; 1959 1960 case 0x18: /* GPIO_EVENT_MODE_REG */ 1961 return s->event; 1962 1963 case 0x1c: /* GPIO_INT_EDGE_REG */ 1964 return s->edge; 1965 1966 case 0x20: /* KBD_INT */ 1967 return (~s->row_latch & 0x1f) && !s->kbd_mask; 1968 1969 case 0x24: /* GPIO_INT */ 1970 ret = s->ints; 1971 s->ints &= s->mask; 1972 if (ret) 1973 qemu_irq_lower(s->irq); 1974 return ret; 1975 1976 case 0x28: /* KBD_MASKIT */ 1977 return s->kbd_mask; 1978 1979 case 0x2c: /* GPIO_MASKIT */ 1980 return s->mask; 1981 1982 case 0x30: /* GPIO_DEBOUNCING_REG */ 1983 return s->debounce; 1984 1985 case 0x34: /* GPIO_LATCH_REG */ 1986 return s->latch; 1987 } 1988 1989 OMAP_BAD_REG(addr); 1990 return 0; 1991 } 1992 1993 static void omap_mpuio_write(void *opaque, hwaddr addr, 1994 uint64_t value, unsigned size) 1995 { 1996 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; 1997 int offset = addr & OMAP_MPUI_REG_MASK; 1998 uint16_t diff; 1999 int ln; 2000 2001 if (size != 2) { 2002 omap_badwidth_write16(opaque, addr, value); 2003 return; 2004 } 2005 2006 switch (offset) { 2007 case 0x04: /* OUTPUT_REG */ 2008 diff = (s->outputs ^ value) & ~s->dir; 2009 s->outputs = value; 2010 while ((ln = ctz32(diff)) != 32) { 2011 if (s->handler[ln]) 2012 qemu_set_irq(s->handler[ln], (value >> ln) & 1); 2013 diff &= ~(1 << ln); 2014 } 2015 break; 2016 2017 case 0x08: /* IO_CNTL */ 2018 diff = s->outputs & (s->dir ^ value); 2019 s->dir = value; 2020 2021 value = s->outputs & ~s->dir; 2022 while ((ln = ctz32(diff)) != 32) { 2023 if (s->handler[ln]) 2024 qemu_set_irq(s->handler[ln], (value >> ln) & 1); 2025 diff &= ~(1 << ln); 2026 } 2027 break; 2028 2029 case 0x14: /* KBC_REG */ 2030 s->cols = value; 2031 omap_mpuio_kbd_update(s); 2032 break; 2033 2034 case 0x18: /* GPIO_EVENT_MODE_REG */ 2035 s->event = value & 0x1f; 2036 break; 2037 2038 case 0x1c: /* GPIO_INT_EDGE_REG */ 2039 s->edge = value; 2040 break; 2041 2042 case 0x28: /* KBD_MASKIT */ 2043 s->kbd_mask = value & 1; 2044 omap_mpuio_kbd_update(s); 2045 break; 2046 2047 case 0x2c: /* GPIO_MASKIT */ 2048 s->mask = value; 2049 break; 2050 2051 case 0x30: /* GPIO_DEBOUNCING_REG */ 2052 s->debounce = value & 0x1ff; 2053 break; 2054 2055 case 0x00: /* INPUT_LATCH */ 2056 case 0x10: /* KBR_LATCH */ 2057 case 0x20: /* KBD_INT */ 2058 case 0x24: /* GPIO_INT */ 2059 case 0x34: /* GPIO_LATCH_REG */ 2060 OMAP_RO_REG(addr); 2061 return; 2062 2063 default: 2064 OMAP_BAD_REG(addr); 2065 return; 2066 } 2067 } 2068 2069 static const MemoryRegionOps omap_mpuio_ops = { 2070 .read = omap_mpuio_read, 2071 .write = omap_mpuio_write, 2072 .endianness = DEVICE_NATIVE_ENDIAN, 2073 }; 2074 2075 static void omap_mpuio_reset(struct omap_mpuio_s *s) 2076 { 2077 s->inputs = 0; 2078 s->outputs = 0; 2079 s->dir = ~0; 2080 s->event = 0; 2081 s->edge = 0; 2082 s->kbd_mask = 0; 2083 s->mask = 0; 2084 s->debounce = 0; 2085 s->latch = 0; 2086 s->ints = 0; 2087 s->row_latch = 0x1f; 2088 s->clk = 1; 2089 } 2090 2091 static void omap_mpuio_onoff(void *opaque, int line, int on) 2092 { 2093 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; 2094 2095 s->clk = on; 2096 if (on) 2097 omap_mpuio_kbd_update(s); 2098 } 2099 2100 static struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *memory, 2101 hwaddr base, 2102 qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup, 2103 omap_clk clk) 2104 { 2105 struct omap_mpuio_s *s = g_new0(struct omap_mpuio_s, 1); 2106 2107 s->irq = gpio_int; 2108 s->kbd_irq = kbd_int; 2109 s->wakeup = wakeup; 2110 s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16); 2111 omap_mpuio_reset(s); 2112 2113 memory_region_init_io(&s->iomem, NULL, &omap_mpuio_ops, s, 2114 "omap-mpuio", 0x800); 2115 memory_region_add_subregion(memory, base, &s->iomem); 2116 2117 omap_clk_adduser(clk, qemu_allocate_irq(omap_mpuio_onoff, s, 0)); 2118 2119 return s; 2120 } 2121 2122 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s) 2123 { 2124 return s->in; 2125 } 2126 2127 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler) 2128 { 2129 if (line >= 16 || line < 0) 2130 hw_error("%s: No GPIO line %i\n", __FUNCTION__, line); 2131 s->handler[line] = handler; 2132 } 2133 2134 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down) 2135 { 2136 if (row >= 5 || row < 0) 2137 hw_error("%s: No key %i-%i\n", __FUNCTION__, col, row); 2138 2139 if (down) 2140 s->buttons[row] |= 1 << col; 2141 else 2142 s->buttons[row] &= ~(1 << col); 2143 2144 omap_mpuio_kbd_update(s); 2145 } 2146 2147 /* MicroWire Interface */ 2148 struct omap_uwire_s { 2149 MemoryRegion iomem; 2150 qemu_irq txirq; 2151 qemu_irq rxirq; 2152 qemu_irq txdrq; 2153 2154 uint16_t txbuf; 2155 uint16_t rxbuf; 2156 uint16_t control; 2157 uint16_t setup[5]; 2158 2159 uWireSlave *chip[4]; 2160 }; 2161 2162 static void omap_uwire_transfer_start(struct omap_uwire_s *s) 2163 { 2164 int chipselect = (s->control >> 10) & 3; /* INDEX */ 2165 uWireSlave *slave = s->chip[chipselect]; 2166 2167 if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */ 2168 if (s->control & (1 << 12)) /* CS_CMD */ 2169 if (slave && slave->send) 2170 slave->send(slave->opaque, 2171 s->txbuf >> (16 - ((s->control >> 5) & 0x1f))); 2172 s->control &= ~(1 << 14); /* CSRB */ 2173 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or 2174 * a DRQ. When is the level IRQ supposed to be reset? */ 2175 } 2176 2177 if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */ 2178 if (s->control & (1 << 12)) /* CS_CMD */ 2179 if (slave && slave->receive) 2180 s->rxbuf = slave->receive(slave->opaque); 2181 s->control |= 1 << 15; /* RDRB */ 2182 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or 2183 * a DRQ. When is the level IRQ supposed to be reset? */ 2184 } 2185 } 2186 2187 static uint64_t omap_uwire_read(void *opaque, hwaddr addr, 2188 unsigned size) 2189 { 2190 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; 2191 int offset = addr & OMAP_MPUI_REG_MASK; 2192 2193 if (size != 2) { 2194 return omap_badwidth_read16(opaque, addr); 2195 } 2196 2197 switch (offset) { 2198 case 0x00: /* RDR */ 2199 s->control &= ~(1 << 15); /* RDRB */ 2200 return s->rxbuf; 2201 2202 case 0x04: /* CSR */ 2203 return s->control; 2204 2205 case 0x08: /* SR1 */ 2206 return s->setup[0]; 2207 case 0x0c: /* SR2 */ 2208 return s->setup[1]; 2209 case 0x10: /* SR3 */ 2210 return s->setup[2]; 2211 case 0x14: /* SR4 */ 2212 return s->setup[3]; 2213 case 0x18: /* SR5 */ 2214 return s->setup[4]; 2215 } 2216 2217 OMAP_BAD_REG(addr); 2218 return 0; 2219 } 2220 2221 static void omap_uwire_write(void *opaque, hwaddr addr, 2222 uint64_t value, unsigned size) 2223 { 2224 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; 2225 int offset = addr & OMAP_MPUI_REG_MASK; 2226 2227 if (size != 2) { 2228 omap_badwidth_write16(opaque, addr, value); 2229 return; 2230 } 2231 2232 switch (offset) { 2233 case 0x00: /* TDR */ 2234 s->txbuf = value; /* TD */ 2235 if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */ 2236 ((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */ 2237 (s->control & (1 << 12)))) { /* CS_CMD */ 2238 s->control |= 1 << 14; /* CSRB */ 2239 omap_uwire_transfer_start(s); 2240 } 2241 break; 2242 2243 case 0x04: /* CSR */ 2244 s->control = value & 0x1fff; 2245 if (value & (1 << 13)) /* START */ 2246 omap_uwire_transfer_start(s); 2247 break; 2248 2249 case 0x08: /* SR1 */ 2250 s->setup[0] = value & 0x003f; 2251 break; 2252 2253 case 0x0c: /* SR2 */ 2254 s->setup[1] = value & 0x0fc0; 2255 break; 2256 2257 case 0x10: /* SR3 */ 2258 s->setup[2] = value & 0x0003; 2259 break; 2260 2261 case 0x14: /* SR4 */ 2262 s->setup[3] = value & 0x0001; 2263 break; 2264 2265 case 0x18: /* SR5 */ 2266 s->setup[4] = value & 0x000f; 2267 break; 2268 2269 default: 2270 OMAP_BAD_REG(addr); 2271 return; 2272 } 2273 } 2274 2275 static const MemoryRegionOps omap_uwire_ops = { 2276 .read = omap_uwire_read, 2277 .write = omap_uwire_write, 2278 .endianness = DEVICE_NATIVE_ENDIAN, 2279 }; 2280 2281 static void omap_uwire_reset(struct omap_uwire_s *s) 2282 { 2283 s->control = 0; 2284 s->setup[0] = 0; 2285 s->setup[1] = 0; 2286 s->setup[2] = 0; 2287 s->setup[3] = 0; 2288 s->setup[4] = 0; 2289 } 2290 2291 static struct omap_uwire_s *omap_uwire_init(MemoryRegion *system_memory, 2292 hwaddr base, 2293 qemu_irq txirq, qemu_irq rxirq, 2294 qemu_irq dma, 2295 omap_clk clk) 2296 { 2297 struct omap_uwire_s *s = g_new0(struct omap_uwire_s, 1); 2298 2299 s->txirq = txirq; 2300 s->rxirq = rxirq; 2301 s->txdrq = dma; 2302 omap_uwire_reset(s); 2303 2304 memory_region_init_io(&s->iomem, NULL, &omap_uwire_ops, s, "omap-uwire", 0x800); 2305 memory_region_add_subregion(system_memory, base, &s->iomem); 2306 2307 return s; 2308 } 2309 2310 void omap_uwire_attach(struct omap_uwire_s *s, 2311 uWireSlave *slave, int chipselect) 2312 { 2313 if (chipselect < 0 || chipselect > 3) { 2314 fprintf(stderr, "%s: Bad chipselect %i\n", __FUNCTION__, chipselect); 2315 exit(-1); 2316 } 2317 2318 s->chip[chipselect] = slave; 2319 } 2320 2321 /* Pseudonoise Pulse-Width Light Modulator */ 2322 struct omap_pwl_s { 2323 MemoryRegion iomem; 2324 uint8_t output; 2325 uint8_t level; 2326 uint8_t enable; 2327 int clk; 2328 }; 2329 2330 static void omap_pwl_update(struct omap_pwl_s *s) 2331 { 2332 int output = (s->clk && s->enable) ? s->level : 0; 2333 2334 if (output != s->output) { 2335 s->output = output; 2336 printf("%s: Backlight now at %i/256\n", __FUNCTION__, output); 2337 } 2338 } 2339 2340 static uint64_t omap_pwl_read(void *opaque, hwaddr addr, 2341 unsigned size) 2342 { 2343 struct omap_pwl_s *s = (struct omap_pwl_s *) opaque; 2344 int offset = addr & OMAP_MPUI_REG_MASK; 2345 2346 if (size != 1) { 2347 return omap_badwidth_read8(opaque, addr); 2348 } 2349 2350 switch (offset) { 2351 case 0x00: /* PWL_LEVEL */ 2352 return s->level; 2353 case 0x04: /* PWL_CTRL */ 2354 return s->enable; 2355 } 2356 OMAP_BAD_REG(addr); 2357 return 0; 2358 } 2359 2360 static void omap_pwl_write(void *opaque, hwaddr addr, 2361 uint64_t value, unsigned size) 2362 { 2363 struct omap_pwl_s *s = (struct omap_pwl_s *) opaque; 2364 int offset = addr & OMAP_MPUI_REG_MASK; 2365 2366 if (size != 1) { 2367 omap_badwidth_write8(opaque, addr, value); 2368 return; 2369 } 2370 2371 switch (offset) { 2372 case 0x00: /* PWL_LEVEL */ 2373 s->level = value; 2374 omap_pwl_update(s); 2375 break; 2376 case 0x04: /* PWL_CTRL */ 2377 s->enable = value & 1; 2378 omap_pwl_update(s); 2379 break; 2380 default: 2381 OMAP_BAD_REG(addr); 2382 return; 2383 } 2384 } 2385 2386 static const MemoryRegionOps omap_pwl_ops = { 2387 .read = omap_pwl_read, 2388 .write = omap_pwl_write, 2389 .endianness = DEVICE_NATIVE_ENDIAN, 2390 }; 2391 2392 static void omap_pwl_reset(struct omap_pwl_s *s) 2393 { 2394 s->output = 0; 2395 s->level = 0; 2396 s->enable = 0; 2397 s->clk = 1; 2398 omap_pwl_update(s); 2399 } 2400 2401 static void omap_pwl_clk_update(void *opaque, int line, int on) 2402 { 2403 struct omap_pwl_s *s = (struct omap_pwl_s *) opaque; 2404 2405 s->clk = on; 2406 omap_pwl_update(s); 2407 } 2408 2409 static struct omap_pwl_s *omap_pwl_init(MemoryRegion *system_memory, 2410 hwaddr base, 2411 omap_clk clk) 2412 { 2413 struct omap_pwl_s *s = g_malloc0(sizeof(*s)); 2414 2415 omap_pwl_reset(s); 2416 2417 memory_region_init_io(&s->iomem, NULL, &omap_pwl_ops, s, 2418 "omap-pwl", 0x800); 2419 memory_region_add_subregion(system_memory, base, &s->iomem); 2420 2421 omap_clk_adduser(clk, qemu_allocate_irq(omap_pwl_clk_update, s, 0)); 2422 return s; 2423 } 2424 2425 /* Pulse-Width Tone module */ 2426 struct omap_pwt_s { 2427 MemoryRegion iomem; 2428 uint8_t frc; 2429 uint8_t vrc; 2430 uint8_t gcr; 2431 omap_clk clk; 2432 }; 2433 2434 static uint64_t omap_pwt_read(void *opaque, hwaddr addr, 2435 unsigned size) 2436 { 2437 struct omap_pwt_s *s = (struct omap_pwt_s *) opaque; 2438 int offset = addr & OMAP_MPUI_REG_MASK; 2439 2440 if (size != 1) { 2441 return omap_badwidth_read8(opaque, addr); 2442 } 2443 2444 switch (offset) { 2445 case 0x00: /* FRC */ 2446 return s->frc; 2447 case 0x04: /* VCR */ 2448 return s->vrc; 2449 case 0x08: /* GCR */ 2450 return s->gcr; 2451 } 2452 OMAP_BAD_REG(addr); 2453 return 0; 2454 } 2455 2456 static void omap_pwt_write(void *opaque, hwaddr addr, 2457 uint64_t value, unsigned size) 2458 { 2459 struct omap_pwt_s *s = (struct omap_pwt_s *) opaque; 2460 int offset = addr & OMAP_MPUI_REG_MASK; 2461 2462 if (size != 1) { 2463 omap_badwidth_write8(opaque, addr, value); 2464 return; 2465 } 2466 2467 switch (offset) { 2468 case 0x00: /* FRC */ 2469 s->frc = value & 0x3f; 2470 break; 2471 case 0x04: /* VRC */ 2472 if ((value ^ s->vrc) & 1) { 2473 if (value & 1) 2474 printf("%s: %iHz buzz on\n", __FUNCTION__, (int) 2475 /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */ 2476 ((omap_clk_getrate(s->clk) >> 3) / 2477 /* Pre-multiplexer divider */ 2478 ((s->gcr & 2) ? 1 : 154) / 2479 /* Octave multiplexer */ 2480 (2 << (value & 3)) * 2481 /* 101/107 divider */ 2482 ((value & (1 << 2)) ? 101 : 107) * 2483 /* 49/55 divider */ 2484 ((value & (1 << 3)) ? 49 : 55) * 2485 /* 50/63 divider */ 2486 ((value & (1 << 4)) ? 50 : 63) * 2487 /* 80/127 divider */ 2488 ((value & (1 << 5)) ? 80 : 127) / 2489 (107 * 55 * 63 * 127))); 2490 else 2491 printf("%s: silence!\n", __FUNCTION__); 2492 } 2493 s->vrc = value & 0x7f; 2494 break; 2495 case 0x08: /* GCR */ 2496 s->gcr = value & 3; 2497 break; 2498 default: 2499 OMAP_BAD_REG(addr); 2500 return; 2501 } 2502 } 2503 2504 static const MemoryRegionOps omap_pwt_ops = { 2505 .read =omap_pwt_read, 2506 .write = omap_pwt_write, 2507 .endianness = DEVICE_NATIVE_ENDIAN, 2508 }; 2509 2510 static void omap_pwt_reset(struct omap_pwt_s *s) 2511 { 2512 s->frc = 0; 2513 s->vrc = 0; 2514 s->gcr = 0; 2515 } 2516 2517 static struct omap_pwt_s *omap_pwt_init(MemoryRegion *system_memory, 2518 hwaddr base, 2519 omap_clk clk) 2520 { 2521 struct omap_pwt_s *s = g_malloc0(sizeof(*s)); 2522 s->clk = clk; 2523 omap_pwt_reset(s); 2524 2525 memory_region_init_io(&s->iomem, NULL, &omap_pwt_ops, s, 2526 "omap-pwt", 0x800); 2527 memory_region_add_subregion(system_memory, base, &s->iomem); 2528 return s; 2529 } 2530 2531 /* Real-time Clock module */ 2532 struct omap_rtc_s { 2533 MemoryRegion iomem; 2534 qemu_irq irq; 2535 qemu_irq alarm; 2536 QEMUTimer *clk; 2537 2538 uint8_t interrupts; 2539 uint8_t status; 2540 int16_t comp_reg; 2541 int running; 2542 int pm_am; 2543 int auto_comp; 2544 int round; 2545 struct tm alarm_tm; 2546 time_t alarm_ti; 2547 2548 struct tm current_tm; 2549 time_t ti; 2550 uint64_t tick; 2551 }; 2552 2553 static void omap_rtc_interrupts_update(struct omap_rtc_s *s) 2554 { 2555 /* s->alarm is level-triggered */ 2556 qemu_set_irq(s->alarm, (s->status >> 6) & 1); 2557 } 2558 2559 static void omap_rtc_alarm_update(struct omap_rtc_s *s) 2560 { 2561 s->alarm_ti = mktimegm(&s->alarm_tm); 2562 if (s->alarm_ti == -1) 2563 printf("%s: conversion failed\n", __FUNCTION__); 2564 } 2565 2566 static uint64_t omap_rtc_read(void *opaque, hwaddr addr, 2567 unsigned size) 2568 { 2569 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; 2570 int offset = addr & OMAP_MPUI_REG_MASK; 2571 uint8_t i; 2572 2573 if (size != 1) { 2574 return omap_badwidth_read8(opaque, addr); 2575 } 2576 2577 switch (offset) { 2578 case 0x00: /* SECONDS_REG */ 2579 return to_bcd(s->current_tm.tm_sec); 2580 2581 case 0x04: /* MINUTES_REG */ 2582 return to_bcd(s->current_tm.tm_min); 2583 2584 case 0x08: /* HOURS_REG */ 2585 if (s->pm_am) 2586 return ((s->current_tm.tm_hour > 11) << 7) | 2587 to_bcd(((s->current_tm.tm_hour - 1) % 12) + 1); 2588 else 2589 return to_bcd(s->current_tm.tm_hour); 2590 2591 case 0x0c: /* DAYS_REG */ 2592 return to_bcd(s->current_tm.tm_mday); 2593 2594 case 0x10: /* MONTHS_REG */ 2595 return to_bcd(s->current_tm.tm_mon + 1); 2596 2597 case 0x14: /* YEARS_REG */ 2598 return to_bcd(s->current_tm.tm_year % 100); 2599 2600 case 0x18: /* WEEK_REG */ 2601 return s->current_tm.tm_wday; 2602 2603 case 0x20: /* ALARM_SECONDS_REG */ 2604 return to_bcd(s->alarm_tm.tm_sec); 2605 2606 case 0x24: /* ALARM_MINUTES_REG */ 2607 return to_bcd(s->alarm_tm.tm_min); 2608 2609 case 0x28: /* ALARM_HOURS_REG */ 2610 if (s->pm_am) 2611 return ((s->alarm_tm.tm_hour > 11) << 7) | 2612 to_bcd(((s->alarm_tm.tm_hour - 1) % 12) + 1); 2613 else 2614 return to_bcd(s->alarm_tm.tm_hour); 2615 2616 case 0x2c: /* ALARM_DAYS_REG */ 2617 return to_bcd(s->alarm_tm.tm_mday); 2618 2619 case 0x30: /* ALARM_MONTHS_REG */ 2620 return to_bcd(s->alarm_tm.tm_mon + 1); 2621 2622 case 0x34: /* ALARM_YEARS_REG */ 2623 return to_bcd(s->alarm_tm.tm_year % 100); 2624 2625 case 0x40: /* RTC_CTRL_REG */ 2626 return (s->pm_am << 3) | (s->auto_comp << 2) | 2627 (s->round << 1) | s->running; 2628 2629 case 0x44: /* RTC_STATUS_REG */ 2630 i = s->status; 2631 s->status &= ~0x3d; 2632 return i; 2633 2634 case 0x48: /* RTC_INTERRUPTS_REG */ 2635 return s->interrupts; 2636 2637 case 0x4c: /* RTC_COMP_LSB_REG */ 2638 return ((uint16_t) s->comp_reg) & 0xff; 2639 2640 case 0x50: /* RTC_COMP_MSB_REG */ 2641 return ((uint16_t) s->comp_reg) >> 8; 2642 } 2643 2644 OMAP_BAD_REG(addr); 2645 return 0; 2646 } 2647 2648 static void omap_rtc_write(void *opaque, hwaddr addr, 2649 uint64_t value, unsigned size) 2650 { 2651 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; 2652 int offset = addr & OMAP_MPUI_REG_MASK; 2653 struct tm new_tm; 2654 time_t ti[2]; 2655 2656 if (size != 1) { 2657 omap_badwidth_write8(opaque, addr, value); 2658 return; 2659 } 2660 2661 switch (offset) { 2662 case 0x00: /* SECONDS_REG */ 2663 #ifdef ALMDEBUG 2664 printf("RTC SEC_REG <-- %02x\n", value); 2665 #endif 2666 s->ti -= s->current_tm.tm_sec; 2667 s->ti += from_bcd(value); 2668 return; 2669 2670 case 0x04: /* MINUTES_REG */ 2671 #ifdef ALMDEBUG 2672 printf("RTC MIN_REG <-- %02x\n", value); 2673 #endif 2674 s->ti -= s->current_tm.tm_min * 60; 2675 s->ti += from_bcd(value) * 60; 2676 return; 2677 2678 case 0x08: /* HOURS_REG */ 2679 #ifdef ALMDEBUG 2680 printf("RTC HRS_REG <-- %02x\n", value); 2681 #endif 2682 s->ti -= s->current_tm.tm_hour * 3600; 2683 if (s->pm_am) { 2684 s->ti += (from_bcd(value & 0x3f) & 12) * 3600; 2685 s->ti += ((value >> 7) & 1) * 43200; 2686 } else 2687 s->ti += from_bcd(value & 0x3f) * 3600; 2688 return; 2689 2690 case 0x0c: /* DAYS_REG */ 2691 #ifdef ALMDEBUG 2692 printf("RTC DAY_REG <-- %02x\n", value); 2693 #endif 2694 s->ti -= s->current_tm.tm_mday * 86400; 2695 s->ti += from_bcd(value) * 86400; 2696 return; 2697 2698 case 0x10: /* MONTHS_REG */ 2699 #ifdef ALMDEBUG 2700 printf("RTC MTH_REG <-- %02x\n", value); 2701 #endif 2702 memcpy(&new_tm, &s->current_tm, sizeof(new_tm)); 2703 new_tm.tm_mon = from_bcd(value); 2704 ti[0] = mktimegm(&s->current_tm); 2705 ti[1] = mktimegm(&new_tm); 2706 2707 if (ti[0] != -1 && ti[1] != -1) { 2708 s->ti -= ti[0]; 2709 s->ti += ti[1]; 2710 } else { 2711 /* A less accurate version */ 2712 s->ti -= s->current_tm.tm_mon * 2592000; 2713 s->ti += from_bcd(value) * 2592000; 2714 } 2715 return; 2716 2717 case 0x14: /* YEARS_REG */ 2718 #ifdef ALMDEBUG 2719 printf("RTC YRS_REG <-- %02x\n", value); 2720 #endif 2721 memcpy(&new_tm, &s->current_tm, sizeof(new_tm)); 2722 new_tm.tm_year += from_bcd(value) - (new_tm.tm_year % 100); 2723 ti[0] = mktimegm(&s->current_tm); 2724 ti[1] = mktimegm(&new_tm); 2725 2726 if (ti[0] != -1 && ti[1] != -1) { 2727 s->ti -= ti[0]; 2728 s->ti += ti[1]; 2729 } else { 2730 /* A less accurate version */ 2731 s->ti -= (time_t)(s->current_tm.tm_year % 100) * 31536000; 2732 s->ti += (time_t)from_bcd(value) * 31536000; 2733 } 2734 return; 2735 2736 case 0x18: /* WEEK_REG */ 2737 return; /* Ignored */ 2738 2739 case 0x20: /* ALARM_SECONDS_REG */ 2740 #ifdef ALMDEBUG 2741 printf("ALM SEC_REG <-- %02x\n", value); 2742 #endif 2743 s->alarm_tm.tm_sec = from_bcd(value); 2744 omap_rtc_alarm_update(s); 2745 return; 2746 2747 case 0x24: /* ALARM_MINUTES_REG */ 2748 #ifdef ALMDEBUG 2749 printf("ALM MIN_REG <-- %02x\n", value); 2750 #endif 2751 s->alarm_tm.tm_min = from_bcd(value); 2752 omap_rtc_alarm_update(s); 2753 return; 2754 2755 case 0x28: /* ALARM_HOURS_REG */ 2756 #ifdef ALMDEBUG 2757 printf("ALM HRS_REG <-- %02x\n", value); 2758 #endif 2759 if (s->pm_am) 2760 s->alarm_tm.tm_hour = 2761 ((from_bcd(value & 0x3f)) % 12) + 2762 ((value >> 7) & 1) * 12; 2763 else 2764 s->alarm_tm.tm_hour = from_bcd(value); 2765 omap_rtc_alarm_update(s); 2766 return; 2767 2768 case 0x2c: /* ALARM_DAYS_REG */ 2769 #ifdef ALMDEBUG 2770 printf("ALM DAY_REG <-- %02x\n", value); 2771 #endif 2772 s->alarm_tm.tm_mday = from_bcd(value); 2773 omap_rtc_alarm_update(s); 2774 return; 2775 2776 case 0x30: /* ALARM_MONTHS_REG */ 2777 #ifdef ALMDEBUG 2778 printf("ALM MON_REG <-- %02x\n", value); 2779 #endif 2780 s->alarm_tm.tm_mon = from_bcd(value); 2781 omap_rtc_alarm_update(s); 2782 return; 2783 2784 case 0x34: /* ALARM_YEARS_REG */ 2785 #ifdef ALMDEBUG 2786 printf("ALM YRS_REG <-- %02x\n", value); 2787 #endif 2788 s->alarm_tm.tm_year = from_bcd(value); 2789 omap_rtc_alarm_update(s); 2790 return; 2791 2792 case 0x40: /* RTC_CTRL_REG */ 2793 #ifdef ALMDEBUG 2794 printf("RTC CONTROL <-- %02x\n", value); 2795 #endif 2796 s->pm_am = (value >> 3) & 1; 2797 s->auto_comp = (value >> 2) & 1; 2798 s->round = (value >> 1) & 1; 2799 s->running = value & 1; 2800 s->status &= 0xfd; 2801 s->status |= s->running << 1; 2802 return; 2803 2804 case 0x44: /* RTC_STATUS_REG */ 2805 #ifdef ALMDEBUG 2806 printf("RTC STATUSL <-- %02x\n", value); 2807 #endif 2808 s->status &= ~((value & 0xc0) ^ 0x80); 2809 omap_rtc_interrupts_update(s); 2810 return; 2811 2812 case 0x48: /* RTC_INTERRUPTS_REG */ 2813 #ifdef ALMDEBUG 2814 printf("RTC INTRS <-- %02x\n", value); 2815 #endif 2816 s->interrupts = value; 2817 return; 2818 2819 case 0x4c: /* RTC_COMP_LSB_REG */ 2820 #ifdef ALMDEBUG 2821 printf("RTC COMPLSB <-- %02x\n", value); 2822 #endif 2823 s->comp_reg &= 0xff00; 2824 s->comp_reg |= 0x00ff & value; 2825 return; 2826 2827 case 0x50: /* RTC_COMP_MSB_REG */ 2828 #ifdef ALMDEBUG 2829 printf("RTC COMPMSB <-- %02x\n", value); 2830 #endif 2831 s->comp_reg &= 0x00ff; 2832 s->comp_reg |= 0xff00 & (value << 8); 2833 return; 2834 2835 default: 2836 OMAP_BAD_REG(addr); 2837 return; 2838 } 2839 } 2840 2841 static const MemoryRegionOps omap_rtc_ops = { 2842 .read = omap_rtc_read, 2843 .write = omap_rtc_write, 2844 .endianness = DEVICE_NATIVE_ENDIAN, 2845 }; 2846 2847 static void omap_rtc_tick(void *opaque) 2848 { 2849 struct omap_rtc_s *s = opaque; 2850 2851 if (s->round) { 2852 /* Round to nearest full minute. */ 2853 if (s->current_tm.tm_sec < 30) 2854 s->ti -= s->current_tm.tm_sec; 2855 else 2856 s->ti += 60 - s->current_tm.tm_sec; 2857 2858 s->round = 0; 2859 } 2860 2861 localtime_r(&s->ti, &s->current_tm); 2862 2863 if ((s->interrupts & 0x08) && s->ti == s->alarm_ti) { 2864 s->status |= 0x40; 2865 omap_rtc_interrupts_update(s); 2866 } 2867 2868 if (s->interrupts & 0x04) 2869 switch (s->interrupts & 3) { 2870 case 0: 2871 s->status |= 0x04; 2872 qemu_irq_pulse(s->irq); 2873 break; 2874 case 1: 2875 if (s->current_tm.tm_sec) 2876 break; 2877 s->status |= 0x08; 2878 qemu_irq_pulse(s->irq); 2879 break; 2880 case 2: 2881 if (s->current_tm.tm_sec || s->current_tm.tm_min) 2882 break; 2883 s->status |= 0x10; 2884 qemu_irq_pulse(s->irq); 2885 break; 2886 case 3: 2887 if (s->current_tm.tm_sec || 2888 s->current_tm.tm_min || s->current_tm.tm_hour) 2889 break; 2890 s->status |= 0x20; 2891 qemu_irq_pulse(s->irq); 2892 break; 2893 } 2894 2895 /* Move on */ 2896 if (s->running) 2897 s->ti ++; 2898 s->tick += 1000; 2899 2900 /* 2901 * Every full hour add a rough approximation of the compensation 2902 * register to the 32kHz Timer (which drives the RTC) value. 2903 */ 2904 if (s->auto_comp && !s->current_tm.tm_sec && !s->current_tm.tm_min) 2905 s->tick += s->comp_reg * 1000 / 32768; 2906 2907 timer_mod(s->clk, s->tick); 2908 } 2909 2910 static void omap_rtc_reset(struct omap_rtc_s *s) 2911 { 2912 struct tm tm; 2913 2914 s->interrupts = 0; 2915 s->comp_reg = 0; 2916 s->running = 0; 2917 s->pm_am = 0; 2918 s->auto_comp = 0; 2919 s->round = 0; 2920 s->tick = qemu_clock_get_ms(rtc_clock); 2921 memset(&s->alarm_tm, 0, sizeof(s->alarm_tm)); 2922 s->alarm_tm.tm_mday = 0x01; 2923 s->status = 1 << 7; 2924 qemu_get_timedate(&tm, 0); 2925 s->ti = mktimegm(&tm); 2926 2927 omap_rtc_alarm_update(s); 2928 omap_rtc_tick(s); 2929 } 2930 2931 static struct omap_rtc_s *omap_rtc_init(MemoryRegion *system_memory, 2932 hwaddr base, 2933 qemu_irq timerirq, qemu_irq alarmirq, 2934 omap_clk clk) 2935 { 2936 struct omap_rtc_s *s = g_new0(struct omap_rtc_s, 1); 2937 2938 s->irq = timerirq; 2939 s->alarm = alarmirq; 2940 s->clk = timer_new_ms(rtc_clock, omap_rtc_tick, s); 2941 2942 omap_rtc_reset(s); 2943 2944 memory_region_init_io(&s->iomem, NULL, &omap_rtc_ops, s, 2945 "omap-rtc", 0x800); 2946 memory_region_add_subregion(system_memory, base, &s->iomem); 2947 2948 return s; 2949 } 2950 2951 /* Multi-channel Buffered Serial Port interfaces */ 2952 struct omap_mcbsp_s { 2953 MemoryRegion iomem; 2954 qemu_irq txirq; 2955 qemu_irq rxirq; 2956 qemu_irq txdrq; 2957 qemu_irq rxdrq; 2958 2959 uint16_t spcr[2]; 2960 uint16_t rcr[2]; 2961 uint16_t xcr[2]; 2962 uint16_t srgr[2]; 2963 uint16_t mcr[2]; 2964 uint16_t pcr; 2965 uint16_t rcer[8]; 2966 uint16_t xcer[8]; 2967 int tx_rate; 2968 int rx_rate; 2969 int tx_req; 2970 int rx_req; 2971 2972 I2SCodec *codec; 2973 QEMUTimer *source_timer; 2974 QEMUTimer *sink_timer; 2975 }; 2976 2977 static void omap_mcbsp_intr_update(struct omap_mcbsp_s *s) 2978 { 2979 int irq; 2980 2981 switch ((s->spcr[0] >> 4) & 3) { /* RINTM */ 2982 case 0: 2983 irq = (s->spcr[0] >> 1) & 1; /* RRDY */ 2984 break; 2985 case 3: 2986 irq = (s->spcr[0] >> 3) & 1; /* RSYNCERR */ 2987 break; 2988 default: 2989 irq = 0; 2990 break; 2991 } 2992 2993 if (irq) 2994 qemu_irq_pulse(s->rxirq); 2995 2996 switch ((s->spcr[1] >> 4) & 3) { /* XINTM */ 2997 case 0: 2998 irq = (s->spcr[1] >> 1) & 1; /* XRDY */ 2999 break; 3000 case 3: 3001 irq = (s->spcr[1] >> 3) & 1; /* XSYNCERR */ 3002 break; 3003 default: 3004 irq = 0; 3005 break; 3006 } 3007 3008 if (irq) 3009 qemu_irq_pulse(s->txirq); 3010 } 3011 3012 static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s) 3013 { 3014 if ((s->spcr[0] >> 1) & 1) /* RRDY */ 3015 s->spcr[0] |= 1 << 2; /* RFULL */ 3016 s->spcr[0] |= 1 << 1; /* RRDY */ 3017 qemu_irq_raise(s->rxdrq); 3018 omap_mcbsp_intr_update(s); 3019 } 3020 3021 static void omap_mcbsp_source_tick(void *opaque) 3022 { 3023 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3024 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 }; 3025 3026 if (!s->rx_rate) 3027 return; 3028 if (s->rx_req) 3029 printf("%s: Rx FIFO overrun\n", __FUNCTION__); 3030 3031 s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7]; 3032 3033 omap_mcbsp_rx_newdata(s); 3034 timer_mod(s->source_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 3035 NANOSECONDS_PER_SECOND); 3036 } 3037 3038 static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s) 3039 { 3040 if (!s->codec || !s->codec->rts) 3041 omap_mcbsp_source_tick(s); 3042 else if (s->codec->in.len) { 3043 s->rx_req = s->codec->in.len; 3044 omap_mcbsp_rx_newdata(s); 3045 } 3046 } 3047 3048 static void omap_mcbsp_rx_stop(struct omap_mcbsp_s *s) 3049 { 3050 timer_del(s->source_timer); 3051 } 3052 3053 static void omap_mcbsp_rx_done(struct omap_mcbsp_s *s) 3054 { 3055 s->spcr[0] &= ~(1 << 1); /* RRDY */ 3056 qemu_irq_lower(s->rxdrq); 3057 omap_mcbsp_intr_update(s); 3058 } 3059 3060 static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s) 3061 { 3062 s->spcr[1] |= 1 << 1; /* XRDY */ 3063 qemu_irq_raise(s->txdrq); 3064 omap_mcbsp_intr_update(s); 3065 } 3066 3067 static void omap_mcbsp_sink_tick(void *opaque) 3068 { 3069 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3070 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 }; 3071 3072 if (!s->tx_rate) 3073 return; 3074 if (s->tx_req) 3075 printf("%s: Tx FIFO underrun\n", __FUNCTION__); 3076 3077 s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7]; 3078 3079 omap_mcbsp_tx_newdata(s); 3080 timer_mod(s->sink_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 3081 NANOSECONDS_PER_SECOND); 3082 } 3083 3084 static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s) 3085 { 3086 if (!s->codec || !s->codec->cts) 3087 omap_mcbsp_sink_tick(s); 3088 else if (s->codec->out.size) { 3089 s->tx_req = s->codec->out.size; 3090 omap_mcbsp_tx_newdata(s); 3091 } 3092 } 3093 3094 static void omap_mcbsp_tx_done(struct omap_mcbsp_s *s) 3095 { 3096 s->spcr[1] &= ~(1 << 1); /* XRDY */ 3097 qemu_irq_lower(s->txdrq); 3098 omap_mcbsp_intr_update(s); 3099 if (s->codec && s->codec->cts) 3100 s->codec->tx_swallow(s->codec->opaque); 3101 } 3102 3103 static void omap_mcbsp_tx_stop(struct omap_mcbsp_s *s) 3104 { 3105 s->tx_req = 0; 3106 omap_mcbsp_tx_done(s); 3107 timer_del(s->sink_timer); 3108 } 3109 3110 static void omap_mcbsp_req_update(struct omap_mcbsp_s *s) 3111 { 3112 int prev_rx_rate, prev_tx_rate; 3113 int rx_rate = 0, tx_rate = 0; 3114 int cpu_rate = 1500000; /* XXX */ 3115 3116 /* TODO: check CLKSTP bit */ 3117 if (s->spcr[1] & (1 << 6)) { /* GRST */ 3118 if (s->spcr[0] & (1 << 0)) { /* RRST */ 3119 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ 3120 (s->pcr & (1 << 8))) { /* CLKRM */ 3121 if (~s->pcr & (1 << 7)) /* SCLKME */ 3122 rx_rate = cpu_rate / 3123 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ 3124 } else 3125 if (s->codec) 3126 rx_rate = s->codec->rx_rate; 3127 } 3128 3129 if (s->spcr[1] & (1 << 0)) { /* XRST */ 3130 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ 3131 (s->pcr & (1 << 9))) { /* CLKXM */ 3132 if (~s->pcr & (1 << 7)) /* SCLKME */ 3133 tx_rate = cpu_rate / 3134 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ 3135 } else 3136 if (s->codec) 3137 tx_rate = s->codec->tx_rate; 3138 } 3139 } 3140 prev_tx_rate = s->tx_rate; 3141 prev_rx_rate = s->rx_rate; 3142 s->tx_rate = tx_rate; 3143 s->rx_rate = rx_rate; 3144 3145 if (s->codec) 3146 s->codec->set_rate(s->codec->opaque, rx_rate, tx_rate); 3147 3148 if (!prev_tx_rate && tx_rate) 3149 omap_mcbsp_tx_start(s); 3150 else if (s->tx_rate && !tx_rate) 3151 omap_mcbsp_tx_stop(s); 3152 3153 if (!prev_rx_rate && rx_rate) 3154 omap_mcbsp_rx_start(s); 3155 else if (prev_tx_rate && !tx_rate) 3156 omap_mcbsp_rx_stop(s); 3157 } 3158 3159 static uint64_t omap_mcbsp_read(void *opaque, hwaddr addr, 3160 unsigned size) 3161 { 3162 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3163 int offset = addr & OMAP_MPUI_REG_MASK; 3164 uint16_t ret; 3165 3166 if (size != 2) { 3167 return omap_badwidth_read16(opaque, addr); 3168 } 3169 3170 switch (offset) { 3171 case 0x00: /* DRR2 */ 3172 if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */ 3173 return 0x0000; 3174 /* Fall through. */ 3175 case 0x02: /* DRR1 */ 3176 if (s->rx_req < 2) { 3177 printf("%s: Rx FIFO underrun\n", __FUNCTION__); 3178 omap_mcbsp_rx_done(s); 3179 } else { 3180 s->tx_req -= 2; 3181 if (s->codec && s->codec->in.len >= 2) { 3182 ret = s->codec->in.fifo[s->codec->in.start ++] << 8; 3183 ret |= s->codec->in.fifo[s->codec->in.start ++]; 3184 s->codec->in.len -= 2; 3185 } else 3186 ret = 0x0000; 3187 if (!s->tx_req) 3188 omap_mcbsp_rx_done(s); 3189 return ret; 3190 } 3191 return 0x0000; 3192 3193 case 0x04: /* DXR2 */ 3194 case 0x06: /* DXR1 */ 3195 return 0x0000; 3196 3197 case 0x08: /* SPCR2 */ 3198 return s->spcr[1]; 3199 case 0x0a: /* SPCR1 */ 3200 return s->spcr[0]; 3201 case 0x0c: /* RCR2 */ 3202 return s->rcr[1]; 3203 case 0x0e: /* RCR1 */ 3204 return s->rcr[0]; 3205 case 0x10: /* XCR2 */ 3206 return s->xcr[1]; 3207 case 0x12: /* XCR1 */ 3208 return s->xcr[0]; 3209 case 0x14: /* SRGR2 */ 3210 return s->srgr[1]; 3211 case 0x16: /* SRGR1 */ 3212 return s->srgr[0]; 3213 case 0x18: /* MCR2 */ 3214 return s->mcr[1]; 3215 case 0x1a: /* MCR1 */ 3216 return s->mcr[0]; 3217 case 0x1c: /* RCERA */ 3218 return s->rcer[0]; 3219 case 0x1e: /* RCERB */ 3220 return s->rcer[1]; 3221 case 0x20: /* XCERA */ 3222 return s->xcer[0]; 3223 case 0x22: /* XCERB */ 3224 return s->xcer[1]; 3225 case 0x24: /* PCR0 */ 3226 return s->pcr; 3227 case 0x26: /* RCERC */ 3228 return s->rcer[2]; 3229 case 0x28: /* RCERD */ 3230 return s->rcer[3]; 3231 case 0x2a: /* XCERC */ 3232 return s->xcer[2]; 3233 case 0x2c: /* XCERD */ 3234 return s->xcer[3]; 3235 case 0x2e: /* RCERE */ 3236 return s->rcer[4]; 3237 case 0x30: /* RCERF */ 3238 return s->rcer[5]; 3239 case 0x32: /* XCERE */ 3240 return s->xcer[4]; 3241 case 0x34: /* XCERF */ 3242 return s->xcer[5]; 3243 case 0x36: /* RCERG */ 3244 return s->rcer[6]; 3245 case 0x38: /* RCERH */ 3246 return s->rcer[7]; 3247 case 0x3a: /* XCERG */ 3248 return s->xcer[6]; 3249 case 0x3c: /* XCERH */ 3250 return s->xcer[7]; 3251 } 3252 3253 OMAP_BAD_REG(addr); 3254 return 0; 3255 } 3256 3257 static void omap_mcbsp_writeh(void *opaque, hwaddr addr, 3258 uint32_t value) 3259 { 3260 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3261 int offset = addr & OMAP_MPUI_REG_MASK; 3262 3263 switch (offset) { 3264 case 0x00: /* DRR2 */ 3265 case 0x02: /* DRR1 */ 3266 OMAP_RO_REG(addr); 3267 return; 3268 3269 case 0x04: /* DXR2 */ 3270 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ 3271 return; 3272 /* Fall through. */ 3273 case 0x06: /* DXR1 */ 3274 if (s->tx_req > 1) { 3275 s->tx_req -= 2; 3276 if (s->codec && s->codec->cts) { 3277 s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff; 3278 s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff; 3279 } 3280 if (s->tx_req < 2) 3281 omap_mcbsp_tx_done(s); 3282 } else 3283 printf("%s: Tx FIFO overrun\n", __FUNCTION__); 3284 return; 3285 3286 case 0x08: /* SPCR2 */ 3287 s->spcr[1] &= 0x0002; 3288 s->spcr[1] |= 0x03f9 & value; 3289 s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */ 3290 if (~value & 1) /* XRST */ 3291 s->spcr[1] &= ~6; 3292 omap_mcbsp_req_update(s); 3293 return; 3294 case 0x0a: /* SPCR1 */ 3295 s->spcr[0] &= 0x0006; 3296 s->spcr[0] |= 0xf8f9 & value; 3297 if (value & (1 << 15)) /* DLB */ 3298 printf("%s: Digital Loopback mode enable attempt\n", __FUNCTION__); 3299 if (~value & 1) { /* RRST */ 3300 s->spcr[0] &= ~6; 3301 s->rx_req = 0; 3302 omap_mcbsp_rx_done(s); 3303 } 3304 omap_mcbsp_req_update(s); 3305 return; 3306 3307 case 0x0c: /* RCR2 */ 3308 s->rcr[1] = value & 0xffff; 3309 return; 3310 case 0x0e: /* RCR1 */ 3311 s->rcr[0] = value & 0x7fe0; 3312 return; 3313 case 0x10: /* XCR2 */ 3314 s->xcr[1] = value & 0xffff; 3315 return; 3316 case 0x12: /* XCR1 */ 3317 s->xcr[0] = value & 0x7fe0; 3318 return; 3319 case 0x14: /* SRGR2 */ 3320 s->srgr[1] = value & 0xffff; 3321 omap_mcbsp_req_update(s); 3322 return; 3323 case 0x16: /* SRGR1 */ 3324 s->srgr[0] = value & 0xffff; 3325 omap_mcbsp_req_update(s); 3326 return; 3327 case 0x18: /* MCR2 */ 3328 s->mcr[1] = value & 0x03e3; 3329 if (value & 3) /* XMCM */ 3330 printf("%s: Tx channel selection mode enable attempt\n", 3331 __FUNCTION__); 3332 return; 3333 case 0x1a: /* MCR1 */ 3334 s->mcr[0] = value & 0x03e1; 3335 if (value & 1) /* RMCM */ 3336 printf("%s: Rx channel selection mode enable attempt\n", 3337 __FUNCTION__); 3338 return; 3339 case 0x1c: /* RCERA */ 3340 s->rcer[0] = value & 0xffff; 3341 return; 3342 case 0x1e: /* RCERB */ 3343 s->rcer[1] = value & 0xffff; 3344 return; 3345 case 0x20: /* XCERA */ 3346 s->xcer[0] = value & 0xffff; 3347 return; 3348 case 0x22: /* XCERB */ 3349 s->xcer[1] = value & 0xffff; 3350 return; 3351 case 0x24: /* PCR0 */ 3352 s->pcr = value & 0x7faf; 3353 return; 3354 case 0x26: /* RCERC */ 3355 s->rcer[2] = value & 0xffff; 3356 return; 3357 case 0x28: /* RCERD */ 3358 s->rcer[3] = value & 0xffff; 3359 return; 3360 case 0x2a: /* XCERC */ 3361 s->xcer[2] = value & 0xffff; 3362 return; 3363 case 0x2c: /* XCERD */ 3364 s->xcer[3] = value & 0xffff; 3365 return; 3366 case 0x2e: /* RCERE */ 3367 s->rcer[4] = value & 0xffff; 3368 return; 3369 case 0x30: /* RCERF */ 3370 s->rcer[5] = value & 0xffff; 3371 return; 3372 case 0x32: /* XCERE */ 3373 s->xcer[4] = value & 0xffff; 3374 return; 3375 case 0x34: /* XCERF */ 3376 s->xcer[5] = value & 0xffff; 3377 return; 3378 case 0x36: /* RCERG */ 3379 s->rcer[6] = value & 0xffff; 3380 return; 3381 case 0x38: /* RCERH */ 3382 s->rcer[7] = value & 0xffff; 3383 return; 3384 case 0x3a: /* XCERG */ 3385 s->xcer[6] = value & 0xffff; 3386 return; 3387 case 0x3c: /* XCERH */ 3388 s->xcer[7] = value & 0xffff; 3389 return; 3390 } 3391 3392 OMAP_BAD_REG(addr); 3393 } 3394 3395 static void omap_mcbsp_writew(void *opaque, hwaddr addr, 3396 uint32_t value) 3397 { 3398 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3399 int offset = addr & OMAP_MPUI_REG_MASK; 3400 3401 if (offset == 0x04) { /* DXR */ 3402 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ 3403 return; 3404 if (s->tx_req > 3) { 3405 s->tx_req -= 4; 3406 if (s->codec && s->codec->cts) { 3407 s->codec->out.fifo[s->codec->out.len ++] = 3408 (value >> 24) & 0xff; 3409 s->codec->out.fifo[s->codec->out.len ++] = 3410 (value >> 16) & 0xff; 3411 s->codec->out.fifo[s->codec->out.len ++] = 3412 (value >> 8) & 0xff; 3413 s->codec->out.fifo[s->codec->out.len ++] = 3414 (value >> 0) & 0xff; 3415 } 3416 if (s->tx_req < 4) 3417 omap_mcbsp_tx_done(s); 3418 } else 3419 printf("%s: Tx FIFO overrun\n", __FUNCTION__); 3420 return; 3421 } 3422 3423 omap_badwidth_write16(opaque, addr, value); 3424 } 3425 3426 static void omap_mcbsp_write(void *opaque, hwaddr addr, 3427 uint64_t value, unsigned size) 3428 { 3429 switch (size) { 3430 case 2: 3431 omap_mcbsp_writeh(opaque, addr, value); 3432 break; 3433 case 4: 3434 omap_mcbsp_writew(opaque, addr, value); 3435 break; 3436 default: 3437 omap_badwidth_write16(opaque, addr, value); 3438 } 3439 } 3440 3441 static const MemoryRegionOps omap_mcbsp_ops = { 3442 .read = omap_mcbsp_read, 3443 .write = omap_mcbsp_write, 3444 .endianness = DEVICE_NATIVE_ENDIAN, 3445 }; 3446 3447 static void omap_mcbsp_reset(struct omap_mcbsp_s *s) 3448 { 3449 memset(&s->spcr, 0, sizeof(s->spcr)); 3450 memset(&s->rcr, 0, sizeof(s->rcr)); 3451 memset(&s->xcr, 0, sizeof(s->xcr)); 3452 s->srgr[0] = 0x0001; 3453 s->srgr[1] = 0x2000; 3454 memset(&s->mcr, 0, sizeof(s->mcr)); 3455 memset(&s->pcr, 0, sizeof(s->pcr)); 3456 memset(&s->rcer, 0, sizeof(s->rcer)); 3457 memset(&s->xcer, 0, sizeof(s->xcer)); 3458 s->tx_req = 0; 3459 s->rx_req = 0; 3460 s->tx_rate = 0; 3461 s->rx_rate = 0; 3462 timer_del(s->source_timer); 3463 timer_del(s->sink_timer); 3464 } 3465 3466 static struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory, 3467 hwaddr base, 3468 qemu_irq txirq, qemu_irq rxirq, 3469 qemu_irq *dma, omap_clk clk) 3470 { 3471 struct omap_mcbsp_s *s = g_new0(struct omap_mcbsp_s, 1); 3472 3473 s->txirq = txirq; 3474 s->rxirq = rxirq; 3475 s->txdrq = dma[0]; 3476 s->rxdrq = dma[1]; 3477 s->sink_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_mcbsp_sink_tick, s); 3478 s->source_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_mcbsp_source_tick, s); 3479 omap_mcbsp_reset(s); 3480 3481 memory_region_init_io(&s->iomem, NULL, &omap_mcbsp_ops, s, "omap-mcbsp", 0x800); 3482 memory_region_add_subregion(system_memory, base, &s->iomem); 3483 3484 return s; 3485 } 3486 3487 static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level) 3488 { 3489 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3490 3491 if (s->rx_rate) { 3492 s->rx_req = s->codec->in.len; 3493 omap_mcbsp_rx_newdata(s); 3494 } 3495 } 3496 3497 static void omap_mcbsp_i2s_start(void *opaque, int line, int level) 3498 { 3499 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3500 3501 if (s->tx_rate) { 3502 s->tx_req = s->codec->out.size; 3503 omap_mcbsp_tx_newdata(s); 3504 } 3505 } 3506 3507 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave) 3508 { 3509 s->codec = slave; 3510 slave->rx_swallow = qemu_allocate_irq(omap_mcbsp_i2s_swallow, s, 0); 3511 slave->tx_start = qemu_allocate_irq(omap_mcbsp_i2s_start, s, 0); 3512 } 3513 3514 /* LED Pulse Generators */ 3515 struct omap_lpg_s { 3516 MemoryRegion iomem; 3517 QEMUTimer *tm; 3518 3519 uint8_t control; 3520 uint8_t power; 3521 int64_t on; 3522 int64_t period; 3523 int clk; 3524 int cycle; 3525 }; 3526 3527 static void omap_lpg_tick(void *opaque) 3528 { 3529 struct omap_lpg_s *s = opaque; 3530 3531 if (s->cycle) 3532 timer_mod(s->tm, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->period - s->on); 3533 else 3534 timer_mod(s->tm, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->on); 3535 3536 s->cycle = !s->cycle; 3537 printf("%s: LED is %s\n", __FUNCTION__, s->cycle ? "on" : "off"); 3538 } 3539 3540 static void omap_lpg_update(struct omap_lpg_s *s) 3541 { 3542 int64_t on, period = 1, ticks = 1000; 3543 static const int per[8] = { 1, 2, 4, 8, 12, 16, 20, 24 }; 3544 3545 if (~s->control & (1 << 6)) /* LPGRES */ 3546 on = 0; 3547 else if (s->control & (1 << 7)) /* PERM_ON */ 3548 on = period; 3549 else { 3550 period = muldiv64(ticks, per[s->control & 7], /* PERCTRL */ 3551 256 / 32); 3552 on = (s->clk && s->power) ? muldiv64(ticks, 3553 per[(s->control >> 3) & 7], 256) : 0; /* ONCTRL */ 3554 } 3555 3556 timer_del(s->tm); 3557 if (on == period && s->on < s->period) 3558 printf("%s: LED is on\n", __FUNCTION__); 3559 else if (on == 0 && s->on) 3560 printf("%s: LED is off\n", __FUNCTION__); 3561 else if (on && (on != s->on || period != s->period)) { 3562 s->cycle = 0; 3563 s->on = on; 3564 s->period = period; 3565 omap_lpg_tick(s); 3566 return; 3567 } 3568 3569 s->on = on; 3570 s->period = period; 3571 } 3572 3573 static void omap_lpg_reset(struct omap_lpg_s *s) 3574 { 3575 s->control = 0x00; 3576 s->power = 0x00; 3577 s->clk = 1; 3578 omap_lpg_update(s); 3579 } 3580 3581 static uint64_t omap_lpg_read(void *opaque, hwaddr addr, 3582 unsigned size) 3583 { 3584 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; 3585 int offset = addr & OMAP_MPUI_REG_MASK; 3586 3587 if (size != 1) { 3588 return omap_badwidth_read8(opaque, addr); 3589 } 3590 3591 switch (offset) { 3592 case 0x00: /* LCR */ 3593 return s->control; 3594 3595 case 0x04: /* PMR */ 3596 return s->power; 3597 } 3598 3599 OMAP_BAD_REG(addr); 3600 return 0; 3601 } 3602 3603 static void omap_lpg_write(void *opaque, hwaddr addr, 3604 uint64_t value, unsigned size) 3605 { 3606 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; 3607 int offset = addr & OMAP_MPUI_REG_MASK; 3608 3609 if (size != 1) { 3610 omap_badwidth_write8(opaque, addr, value); 3611 return; 3612 } 3613 3614 switch (offset) { 3615 case 0x00: /* LCR */ 3616 if (~value & (1 << 6)) /* LPGRES */ 3617 omap_lpg_reset(s); 3618 s->control = value & 0xff; 3619 omap_lpg_update(s); 3620 return; 3621 3622 case 0x04: /* PMR */ 3623 s->power = value & 0x01; 3624 omap_lpg_update(s); 3625 return; 3626 3627 default: 3628 OMAP_BAD_REG(addr); 3629 return; 3630 } 3631 } 3632 3633 static const MemoryRegionOps omap_lpg_ops = { 3634 .read = omap_lpg_read, 3635 .write = omap_lpg_write, 3636 .endianness = DEVICE_NATIVE_ENDIAN, 3637 }; 3638 3639 static void omap_lpg_clk_update(void *opaque, int line, int on) 3640 { 3641 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; 3642 3643 s->clk = on; 3644 omap_lpg_update(s); 3645 } 3646 3647 static struct omap_lpg_s *omap_lpg_init(MemoryRegion *system_memory, 3648 hwaddr base, omap_clk clk) 3649 { 3650 struct omap_lpg_s *s = g_new0(struct omap_lpg_s, 1); 3651 3652 s->tm = timer_new_ms(QEMU_CLOCK_VIRTUAL, omap_lpg_tick, s); 3653 3654 omap_lpg_reset(s); 3655 3656 memory_region_init_io(&s->iomem, NULL, &omap_lpg_ops, s, "omap-lpg", 0x800); 3657 memory_region_add_subregion(system_memory, base, &s->iomem); 3658 3659 omap_clk_adduser(clk, qemu_allocate_irq(omap_lpg_clk_update, s, 0)); 3660 3661 return s; 3662 } 3663 3664 /* MPUI Peripheral Bridge configuration */ 3665 static uint64_t omap_mpui_io_read(void *opaque, hwaddr addr, 3666 unsigned size) 3667 { 3668 if (size != 2) { 3669 return omap_badwidth_read16(opaque, addr); 3670 } 3671 3672 if (addr == OMAP_MPUI_BASE) /* CMR */ 3673 return 0xfe4d; 3674 3675 OMAP_BAD_REG(addr); 3676 return 0; 3677 } 3678 3679 static void omap_mpui_io_write(void *opaque, hwaddr addr, 3680 uint64_t value, unsigned size) 3681 { 3682 /* FIXME: infinite loop */ 3683 omap_badwidth_write16(opaque, addr, value); 3684 } 3685 3686 static const MemoryRegionOps omap_mpui_io_ops = { 3687 .read = omap_mpui_io_read, 3688 .write = omap_mpui_io_write, 3689 .endianness = DEVICE_NATIVE_ENDIAN, 3690 }; 3691 3692 static void omap_setup_mpui_io(MemoryRegion *system_memory, 3693 struct omap_mpu_state_s *mpu) 3694 { 3695 memory_region_init_io(&mpu->mpui_io_iomem, NULL, &omap_mpui_io_ops, mpu, 3696 "omap-mpui-io", 0x7fff); 3697 memory_region_add_subregion(system_memory, OMAP_MPUI_BASE, 3698 &mpu->mpui_io_iomem); 3699 } 3700 3701 /* General chip reset */ 3702 static void omap1_mpu_reset(void *opaque) 3703 { 3704 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; 3705 3706 omap_dma_reset(mpu->dma); 3707 omap_mpu_timer_reset(mpu->timer[0]); 3708 omap_mpu_timer_reset(mpu->timer[1]); 3709 omap_mpu_timer_reset(mpu->timer[2]); 3710 omap_wd_timer_reset(mpu->wdt); 3711 omap_os_timer_reset(mpu->os_timer); 3712 omap_lcdc_reset(mpu->lcd); 3713 omap_ulpd_pm_reset(mpu); 3714 omap_pin_cfg_reset(mpu); 3715 omap_mpui_reset(mpu); 3716 omap_tipb_bridge_reset(mpu->private_tipb); 3717 omap_tipb_bridge_reset(mpu->public_tipb); 3718 omap_dpll_reset(mpu->dpll[0]); 3719 omap_dpll_reset(mpu->dpll[1]); 3720 omap_dpll_reset(mpu->dpll[2]); 3721 omap_uart_reset(mpu->uart[0]); 3722 omap_uart_reset(mpu->uart[1]); 3723 omap_uart_reset(mpu->uart[2]); 3724 omap_mmc_reset(mpu->mmc); 3725 omap_mpuio_reset(mpu->mpuio); 3726 omap_uwire_reset(mpu->microwire); 3727 omap_pwl_reset(mpu->pwl); 3728 omap_pwt_reset(mpu->pwt); 3729 omap_rtc_reset(mpu->rtc); 3730 omap_mcbsp_reset(mpu->mcbsp1); 3731 omap_mcbsp_reset(mpu->mcbsp2); 3732 omap_mcbsp_reset(mpu->mcbsp3); 3733 omap_lpg_reset(mpu->led[0]); 3734 omap_lpg_reset(mpu->led[1]); 3735 omap_clkm_reset(mpu); 3736 cpu_reset(CPU(mpu->cpu)); 3737 } 3738 3739 static const struct omap_map_s { 3740 hwaddr phys_dsp; 3741 hwaddr phys_mpu; 3742 uint32_t size; 3743 const char *name; 3744 } omap15xx_dsp_mm[] = { 3745 /* Strobe 0 */ 3746 { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */ 3747 { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */ 3748 { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */ 3749 { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */ 3750 { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */ 3751 { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */ 3752 { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */ 3753 { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */ 3754 { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */ 3755 { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */ 3756 { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */ 3757 { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */ 3758 { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */ 3759 { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */ 3760 { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */ 3761 { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */ 3762 { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */ 3763 /* Strobe 1 */ 3764 { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */ 3765 3766 { 0 } 3767 }; 3768 3769 static void omap_setup_dsp_mapping(MemoryRegion *system_memory, 3770 const struct omap_map_s *map) 3771 { 3772 MemoryRegion *io; 3773 3774 for (; map->phys_dsp; map ++) { 3775 io = g_new(MemoryRegion, 1); 3776 memory_region_init_alias(io, NULL, map->name, 3777 system_memory, map->phys_mpu, map->size); 3778 memory_region_add_subregion(system_memory, map->phys_dsp, io); 3779 } 3780 } 3781 3782 void omap_mpu_wakeup(void *opaque, int irq, int req) 3783 { 3784 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; 3785 CPUState *cpu = CPU(mpu->cpu); 3786 3787 if (cpu->halted) { 3788 cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB); 3789 } 3790 } 3791 3792 static const struct dma_irq_map omap1_dma_irq_map[] = { 3793 { 0, OMAP_INT_DMA_CH0_6 }, 3794 { 0, OMAP_INT_DMA_CH1_7 }, 3795 { 0, OMAP_INT_DMA_CH2_8 }, 3796 { 0, OMAP_INT_DMA_CH3 }, 3797 { 0, OMAP_INT_DMA_CH4 }, 3798 { 0, OMAP_INT_DMA_CH5 }, 3799 { 1, OMAP_INT_1610_DMA_CH6 }, 3800 { 1, OMAP_INT_1610_DMA_CH7 }, 3801 { 1, OMAP_INT_1610_DMA_CH8 }, 3802 { 1, OMAP_INT_1610_DMA_CH9 }, 3803 { 1, OMAP_INT_1610_DMA_CH10 }, 3804 { 1, OMAP_INT_1610_DMA_CH11 }, 3805 { 1, OMAP_INT_1610_DMA_CH12 }, 3806 { 1, OMAP_INT_1610_DMA_CH13 }, 3807 { 1, OMAP_INT_1610_DMA_CH14 }, 3808 { 1, OMAP_INT_1610_DMA_CH15 } 3809 }; 3810 3811 /* DMA ports for OMAP1 */ 3812 static int omap_validate_emiff_addr(struct omap_mpu_state_s *s, 3813 hwaddr addr) 3814 { 3815 return range_covers_byte(OMAP_EMIFF_BASE, s->sdram_size, addr); 3816 } 3817 3818 static int omap_validate_emifs_addr(struct omap_mpu_state_s *s, 3819 hwaddr addr) 3820 { 3821 return range_covers_byte(OMAP_EMIFS_BASE, OMAP_EMIFF_BASE - OMAP_EMIFS_BASE, 3822 addr); 3823 } 3824 3825 static int omap_validate_imif_addr(struct omap_mpu_state_s *s, 3826 hwaddr addr) 3827 { 3828 return range_covers_byte(OMAP_IMIF_BASE, s->sram_size, addr); 3829 } 3830 3831 static int omap_validate_tipb_addr(struct omap_mpu_state_s *s, 3832 hwaddr addr) 3833 { 3834 return range_covers_byte(0xfffb0000, 0xffff0000 - 0xfffb0000, addr); 3835 } 3836 3837 static int omap_validate_local_addr(struct omap_mpu_state_s *s, 3838 hwaddr addr) 3839 { 3840 return range_covers_byte(OMAP_LOCALBUS_BASE, 0x1000000, addr); 3841 } 3842 3843 static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s, 3844 hwaddr addr) 3845 { 3846 return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr); 3847 } 3848 3849 struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory, 3850 unsigned long sdram_size, 3851 const char *core) 3852 { 3853 int i; 3854 struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1); 3855 qemu_irq dma_irqs[6]; 3856 DriveInfo *dinfo; 3857 SysBusDevice *busdev; 3858 3859 if (!core) 3860 core = "ti925t"; 3861 3862 /* Core */ 3863 s->mpu_model = omap310; 3864 s->cpu = cpu_arm_init(core); 3865 if (s->cpu == NULL) { 3866 fprintf(stderr, "Unable to find CPU definition\n"); 3867 exit(1); 3868 } 3869 s->sdram_size = sdram_size; 3870 s->sram_size = OMAP15XX_SRAM_SIZE; 3871 3872 s->wakeup = qemu_allocate_irq(omap_mpu_wakeup, s, 0); 3873 3874 /* Clocks */ 3875 omap_clk_init(s); 3876 3877 /* Memory-mapped stuff */ 3878 memory_region_allocate_system_memory(&s->emiff_ram, NULL, "omap1.dram", 3879 s->sdram_size); 3880 memory_region_add_subregion(system_memory, OMAP_EMIFF_BASE, &s->emiff_ram); 3881 memory_region_init_ram(&s->imif_ram, NULL, "omap1.sram", s->sram_size, 3882 &error_fatal); 3883 vmstate_register_ram_global(&s->imif_ram); 3884 memory_region_add_subregion(system_memory, OMAP_IMIF_BASE, &s->imif_ram); 3885 3886 omap_clkm_init(system_memory, 0xfffece00, 0xe1008000, s); 3887 3888 s->ih[0] = qdev_create(NULL, "omap-intc"); 3889 qdev_prop_set_uint32(s->ih[0], "size", 0x100); 3890 qdev_prop_set_ptr(s->ih[0], "clk", omap_findclk(s, "arminth_ck")); 3891 qdev_init_nofail(s->ih[0]); 3892 busdev = SYS_BUS_DEVICE(s->ih[0]); 3893 sysbus_connect_irq(busdev, 0, 3894 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ)); 3895 sysbus_connect_irq(busdev, 1, 3896 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ)); 3897 sysbus_mmio_map(busdev, 0, 0xfffecb00); 3898 s->ih[1] = qdev_create(NULL, "omap-intc"); 3899 qdev_prop_set_uint32(s->ih[1], "size", 0x800); 3900 qdev_prop_set_ptr(s->ih[1], "clk", omap_findclk(s, "arminth_ck")); 3901 qdev_init_nofail(s->ih[1]); 3902 busdev = SYS_BUS_DEVICE(s->ih[1]); 3903 sysbus_connect_irq(busdev, 0, 3904 qdev_get_gpio_in(s->ih[0], OMAP_INT_15XX_IH2_IRQ)); 3905 /* The second interrupt controller's FIQ output is not wired up */ 3906 sysbus_mmio_map(busdev, 0, 0xfffe0000); 3907 3908 for (i = 0; i < 6; i++) { 3909 dma_irqs[i] = qdev_get_gpio_in(s->ih[omap1_dma_irq_map[i].ih], 3910 omap1_dma_irq_map[i].intr); 3911 } 3912 s->dma = omap_dma_init(0xfffed800, dma_irqs, system_memory, 3913 qdev_get_gpio_in(s->ih[0], OMAP_INT_DMA_LCD), 3914 s, omap_findclk(s, "dma_ck"), omap_dma_3_1); 3915 3916 s->port[emiff ].addr_valid = omap_validate_emiff_addr; 3917 s->port[emifs ].addr_valid = omap_validate_emifs_addr; 3918 s->port[imif ].addr_valid = omap_validate_imif_addr; 3919 s->port[tipb ].addr_valid = omap_validate_tipb_addr; 3920 s->port[local ].addr_valid = omap_validate_local_addr; 3921 s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr; 3922 3923 /* Register SDRAM and SRAM DMA ports for fast transfers. */ 3924 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->emiff_ram), 3925 OMAP_EMIFF_BASE, s->sdram_size); 3926 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->imif_ram), 3927 OMAP_IMIF_BASE, s->sram_size); 3928 3929 s->timer[0] = omap_mpu_timer_init(system_memory, 0xfffec500, 3930 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER1), 3931 omap_findclk(s, "mputim_ck")); 3932 s->timer[1] = omap_mpu_timer_init(system_memory, 0xfffec600, 3933 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER2), 3934 omap_findclk(s, "mputim_ck")); 3935 s->timer[2] = omap_mpu_timer_init(system_memory, 0xfffec700, 3936 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER3), 3937 omap_findclk(s, "mputim_ck")); 3938 3939 s->wdt = omap_wd_timer_init(system_memory, 0xfffec800, 3940 qdev_get_gpio_in(s->ih[0], OMAP_INT_WD_TIMER), 3941 omap_findclk(s, "armwdt_ck")); 3942 3943 s->os_timer = omap_os_timer_init(system_memory, 0xfffb9000, 3944 qdev_get_gpio_in(s->ih[1], OMAP_INT_OS_TIMER), 3945 omap_findclk(s, "clk32-kHz")); 3946 3947 s->lcd = omap_lcdc_init(system_memory, 0xfffec000, 3948 qdev_get_gpio_in(s->ih[0], OMAP_INT_LCD_CTRL), 3949 omap_dma_get_lcdch(s->dma), 3950 omap_findclk(s, "lcd_ck")); 3951 3952 omap_ulpd_pm_init(system_memory, 0xfffe0800, s); 3953 omap_pin_cfg_init(system_memory, 0xfffe1000, s); 3954 omap_id_init(system_memory, s); 3955 3956 omap_mpui_init(system_memory, 0xfffec900, s); 3957 3958 s->private_tipb = omap_tipb_bridge_init(system_memory, 0xfffeca00, 3959 qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PRIV), 3960 omap_findclk(s, "tipb_ck")); 3961 s->public_tipb = omap_tipb_bridge_init(system_memory, 0xfffed300, 3962 qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PUB), 3963 omap_findclk(s, "tipb_ck")); 3964 3965 omap_tcmi_init(system_memory, 0xfffecc00, s); 3966 3967 s->uart[0] = omap_uart_init(0xfffb0000, 3968 qdev_get_gpio_in(s->ih[1], OMAP_INT_UART1), 3969 omap_findclk(s, "uart1_ck"), 3970 omap_findclk(s, "uart1_ck"), 3971 s->drq[OMAP_DMA_UART1_TX], s->drq[OMAP_DMA_UART1_RX], 3972 "uart1", 3973 serial_hds[0]); 3974 s->uart[1] = omap_uart_init(0xfffb0800, 3975 qdev_get_gpio_in(s->ih[1], OMAP_INT_UART2), 3976 omap_findclk(s, "uart2_ck"), 3977 omap_findclk(s, "uart2_ck"), 3978 s->drq[OMAP_DMA_UART2_TX], s->drq[OMAP_DMA_UART2_RX], 3979 "uart2", 3980 serial_hds[0] ? serial_hds[1] : NULL); 3981 s->uart[2] = omap_uart_init(0xfffb9800, 3982 qdev_get_gpio_in(s->ih[0], OMAP_INT_UART3), 3983 omap_findclk(s, "uart3_ck"), 3984 omap_findclk(s, "uart3_ck"), 3985 s->drq[OMAP_DMA_UART3_TX], s->drq[OMAP_DMA_UART3_RX], 3986 "uart3", 3987 serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL); 3988 3989 s->dpll[0] = omap_dpll_init(system_memory, 0xfffecf00, 3990 omap_findclk(s, "dpll1")); 3991 s->dpll[1] = omap_dpll_init(system_memory, 0xfffed000, 3992 omap_findclk(s, "dpll2")); 3993 s->dpll[2] = omap_dpll_init(system_memory, 0xfffed100, 3994 omap_findclk(s, "dpll3")); 3995 3996 dinfo = drive_get(IF_SD, 0, 0); 3997 if (!dinfo) { 3998 fprintf(stderr, "qemu: missing SecureDigital device\n"); 3999 exit(1); 4000 } 4001 s->mmc = omap_mmc_init(0xfffb7800, system_memory, 4002 blk_by_legacy_dinfo(dinfo), 4003 qdev_get_gpio_in(s->ih[1], OMAP_INT_OQN), 4004 &s->drq[OMAP_DMA_MMC_TX], 4005 omap_findclk(s, "mmc_ck")); 4006 4007 s->mpuio = omap_mpuio_init(system_memory, 0xfffb5000, 4008 qdev_get_gpio_in(s->ih[1], OMAP_INT_KEYBOARD), 4009 qdev_get_gpio_in(s->ih[1], OMAP_INT_MPUIO), 4010 s->wakeup, omap_findclk(s, "clk32-kHz")); 4011 4012 s->gpio = qdev_create(NULL, "omap-gpio"); 4013 qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model); 4014 qdev_prop_set_ptr(s->gpio, "clk", omap_findclk(s, "arm_gpio_ck")); 4015 qdev_init_nofail(s->gpio); 4016 sysbus_connect_irq(SYS_BUS_DEVICE(s->gpio), 0, 4017 qdev_get_gpio_in(s->ih[0], OMAP_INT_GPIO_BANK1)); 4018 sysbus_mmio_map(SYS_BUS_DEVICE(s->gpio), 0, 0xfffce000); 4019 4020 s->microwire = omap_uwire_init(system_memory, 0xfffb3000, 4021 qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireTX), 4022 qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireRX), 4023 s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck")); 4024 4025 s->pwl = omap_pwl_init(system_memory, 0xfffb5800, 4026 omap_findclk(s, "armxor_ck")); 4027 s->pwt = omap_pwt_init(system_memory, 0xfffb6000, 4028 omap_findclk(s, "armxor_ck")); 4029 4030 s->i2c[0] = qdev_create(NULL, "omap_i2c"); 4031 qdev_prop_set_uint8(s->i2c[0], "revision", 0x11); 4032 qdev_prop_set_ptr(s->i2c[0], "fclk", omap_findclk(s, "mpuper_ck")); 4033 qdev_init_nofail(s->i2c[0]); 4034 busdev = SYS_BUS_DEVICE(s->i2c[0]); 4035 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C)); 4036 sysbus_connect_irq(busdev, 1, s->drq[OMAP_DMA_I2C_TX]); 4037 sysbus_connect_irq(busdev, 2, s->drq[OMAP_DMA_I2C_RX]); 4038 sysbus_mmio_map(busdev, 0, 0xfffb3800); 4039 4040 s->rtc = omap_rtc_init(system_memory, 0xfffb4800, 4041 qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_TIMER), 4042 qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_ALARM), 4043 omap_findclk(s, "clk32-kHz")); 4044 4045 s->mcbsp1 = omap_mcbsp_init(system_memory, 0xfffb1800, 4046 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1TX), 4047 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1RX), 4048 &s->drq[OMAP_DMA_MCBSP1_TX], omap_findclk(s, "dspxor_ck")); 4049 s->mcbsp2 = omap_mcbsp_init(system_memory, 0xfffb1000, 4050 qdev_get_gpio_in(s->ih[0], 4051 OMAP_INT_310_McBSP2_TX), 4052 qdev_get_gpio_in(s->ih[0], 4053 OMAP_INT_310_McBSP2_RX), 4054 &s->drq[OMAP_DMA_MCBSP2_TX], omap_findclk(s, "mpuper_ck")); 4055 s->mcbsp3 = omap_mcbsp_init(system_memory, 0xfffb7000, 4056 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3TX), 4057 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3RX), 4058 &s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck")); 4059 4060 s->led[0] = omap_lpg_init(system_memory, 4061 0xfffbd000, omap_findclk(s, "clk32-kHz")); 4062 s->led[1] = omap_lpg_init(system_memory, 4063 0xfffbd800, omap_findclk(s, "clk32-kHz")); 4064 4065 /* Register mappings not currenlty implemented: 4066 * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310) 4067 * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310) 4068 * USB W2FC fffb4000 - fffb47ff 4069 * Camera Interface fffb6800 - fffb6fff 4070 * USB Host fffba000 - fffba7ff 4071 * FAC fffba800 - fffbafff 4072 * HDQ/1-Wire fffbc000 - fffbc7ff 4073 * TIPB switches fffbc800 - fffbcfff 4074 * Mailbox fffcf000 - fffcf7ff 4075 * Local bus IF fffec100 - fffec1ff 4076 * Local bus MMU fffec200 - fffec2ff 4077 * DSP MMU fffed200 - fffed2ff 4078 */ 4079 4080 omap_setup_dsp_mapping(system_memory, omap15xx_dsp_mm); 4081 omap_setup_mpui_io(system_memory, s); 4082 4083 qemu_register_reset(omap1_mpu_reset, s); 4084 4085 return s; 4086 } 4087