1 /* 2 * TI OMAP processors emulation. 3 * 4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 or 9 * (at your option) version 3 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "hw/boards.h" 23 #include "hw/hw.h" 24 #include "hw/arm/arm.h" 25 #include "hw/arm/omap.h" 26 #include "sysemu/sysemu.h" 27 #include "hw/arm/soc_dma.h" 28 #include "sysemu/block-backend.h" 29 #include "sysemu/blockdev.h" 30 #include "qemu/range.h" 31 #include "hw/sysbus.h" 32 33 /* Should signal the TCMI/GPMC */ 34 uint32_t omap_badwidth_read8(void *opaque, hwaddr addr) 35 { 36 uint8_t ret; 37 38 OMAP_8B_REG(addr); 39 cpu_physical_memory_read(addr, &ret, 1); 40 return ret; 41 } 42 43 void omap_badwidth_write8(void *opaque, hwaddr addr, 44 uint32_t value) 45 { 46 uint8_t val8 = value; 47 48 OMAP_8B_REG(addr); 49 cpu_physical_memory_write(addr, &val8, 1); 50 } 51 52 uint32_t omap_badwidth_read16(void *opaque, hwaddr addr) 53 { 54 uint16_t ret; 55 56 OMAP_16B_REG(addr); 57 cpu_physical_memory_read(addr, &ret, 2); 58 return ret; 59 } 60 61 void omap_badwidth_write16(void *opaque, hwaddr addr, 62 uint32_t value) 63 { 64 uint16_t val16 = value; 65 66 OMAP_16B_REG(addr); 67 cpu_physical_memory_write(addr, &val16, 2); 68 } 69 70 uint32_t omap_badwidth_read32(void *opaque, hwaddr addr) 71 { 72 uint32_t ret; 73 74 OMAP_32B_REG(addr); 75 cpu_physical_memory_read(addr, &ret, 4); 76 return ret; 77 } 78 79 void omap_badwidth_write32(void *opaque, hwaddr addr, 80 uint32_t value) 81 { 82 OMAP_32B_REG(addr); 83 cpu_physical_memory_write(addr, &value, 4); 84 } 85 86 /* MPU OS timers */ 87 struct omap_mpu_timer_s { 88 MemoryRegion iomem; 89 qemu_irq irq; 90 omap_clk clk; 91 uint32_t val; 92 int64_t time; 93 QEMUTimer *timer; 94 QEMUBH *tick; 95 int64_t rate; 96 int it_ena; 97 98 int enable; 99 int ptv; 100 int ar; 101 int st; 102 uint32_t reset_val; 103 }; 104 105 static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer) 106 { 107 uint64_t distance = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->time; 108 109 if (timer->st && timer->enable && timer->rate) 110 return timer->val - muldiv64(distance >> (timer->ptv + 1), 111 timer->rate, get_ticks_per_sec()); 112 else 113 return timer->val; 114 } 115 116 static inline void omap_timer_sync(struct omap_mpu_timer_s *timer) 117 { 118 timer->val = omap_timer_read(timer); 119 timer->time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 120 } 121 122 static inline void omap_timer_update(struct omap_mpu_timer_s *timer) 123 { 124 int64_t expires; 125 126 if (timer->enable && timer->st && timer->rate) { 127 timer->val = timer->reset_val; /* Should skip this on clk enable */ 128 expires = muldiv64((uint64_t) timer->val << (timer->ptv + 1), 129 get_ticks_per_sec(), timer->rate); 130 131 /* If timer expiry would be sooner than in about 1 ms and 132 * auto-reload isn't set, then fire immediately. This is a hack 133 * to make systems like PalmOS run in acceptable time. PalmOS 134 * sets the interval to a very low value and polls the status bit 135 * in a busy loop when it wants to sleep just a couple of CPU 136 * ticks. */ 137 if (expires > (get_ticks_per_sec() >> 10) || timer->ar) 138 timer_mod(timer->timer, timer->time + expires); 139 else 140 qemu_bh_schedule(timer->tick); 141 } else 142 timer_del(timer->timer); 143 } 144 145 static void omap_timer_fire(void *opaque) 146 { 147 struct omap_mpu_timer_s *timer = opaque; 148 149 if (!timer->ar) { 150 timer->val = 0; 151 timer->st = 0; 152 } 153 154 if (timer->it_ena) 155 /* Edge-triggered irq */ 156 qemu_irq_pulse(timer->irq); 157 } 158 159 static void omap_timer_tick(void *opaque) 160 { 161 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque; 162 163 omap_timer_sync(timer); 164 omap_timer_fire(timer); 165 omap_timer_update(timer); 166 } 167 168 static void omap_timer_clk_update(void *opaque, int line, int on) 169 { 170 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque; 171 172 omap_timer_sync(timer); 173 timer->rate = on ? omap_clk_getrate(timer->clk) : 0; 174 omap_timer_update(timer); 175 } 176 177 static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer) 178 { 179 omap_clk_adduser(timer->clk, 180 qemu_allocate_irq(omap_timer_clk_update, timer, 0)); 181 timer->rate = omap_clk_getrate(timer->clk); 182 } 183 184 static uint64_t omap_mpu_timer_read(void *opaque, hwaddr addr, 185 unsigned size) 186 { 187 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; 188 189 if (size != 4) { 190 return omap_badwidth_read32(opaque, addr); 191 } 192 193 switch (addr) { 194 case 0x00: /* CNTL_TIMER */ 195 return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st; 196 197 case 0x04: /* LOAD_TIM */ 198 break; 199 200 case 0x08: /* READ_TIM */ 201 return omap_timer_read(s); 202 } 203 204 OMAP_BAD_REG(addr); 205 return 0; 206 } 207 208 static void omap_mpu_timer_write(void *opaque, hwaddr addr, 209 uint64_t value, unsigned size) 210 { 211 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; 212 213 if (size != 4) { 214 omap_badwidth_write32(opaque, addr, value); 215 return; 216 } 217 218 switch (addr) { 219 case 0x00: /* CNTL_TIMER */ 220 omap_timer_sync(s); 221 s->enable = (value >> 5) & 1; 222 s->ptv = (value >> 2) & 7; 223 s->ar = (value >> 1) & 1; 224 s->st = value & 1; 225 omap_timer_update(s); 226 return; 227 228 case 0x04: /* LOAD_TIM */ 229 s->reset_val = value; 230 return; 231 232 case 0x08: /* READ_TIM */ 233 OMAP_RO_REG(addr); 234 break; 235 236 default: 237 OMAP_BAD_REG(addr); 238 } 239 } 240 241 static const MemoryRegionOps omap_mpu_timer_ops = { 242 .read = omap_mpu_timer_read, 243 .write = omap_mpu_timer_write, 244 .endianness = DEVICE_LITTLE_ENDIAN, 245 }; 246 247 static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s) 248 { 249 timer_del(s->timer); 250 s->enable = 0; 251 s->reset_val = 31337; 252 s->val = 0; 253 s->ptv = 0; 254 s->ar = 0; 255 s->st = 0; 256 s->it_ena = 1; 257 } 258 259 static struct omap_mpu_timer_s *omap_mpu_timer_init(MemoryRegion *system_memory, 260 hwaddr base, 261 qemu_irq irq, omap_clk clk) 262 { 263 struct omap_mpu_timer_s *s = g_new0(struct omap_mpu_timer_s, 1); 264 265 s->irq = irq; 266 s->clk = clk; 267 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, s); 268 s->tick = qemu_bh_new(omap_timer_fire, s); 269 omap_mpu_timer_reset(s); 270 omap_timer_clk_setup(s); 271 272 memory_region_init_io(&s->iomem, NULL, &omap_mpu_timer_ops, s, 273 "omap-mpu-timer", 0x100); 274 275 memory_region_add_subregion(system_memory, base, &s->iomem); 276 277 return s; 278 } 279 280 /* Watchdog timer */ 281 struct omap_watchdog_timer_s { 282 struct omap_mpu_timer_s timer; 283 MemoryRegion iomem; 284 uint8_t last_wr; 285 int mode; 286 int free; 287 int reset; 288 }; 289 290 static uint64_t omap_wd_timer_read(void *opaque, hwaddr addr, 291 unsigned size) 292 { 293 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; 294 295 if (size != 2) { 296 return omap_badwidth_read16(opaque, addr); 297 } 298 299 switch (addr) { 300 case 0x00: /* CNTL_TIMER */ 301 return (s->timer.ptv << 9) | (s->timer.ar << 8) | 302 (s->timer.st << 7) | (s->free << 1); 303 304 case 0x04: /* READ_TIMER */ 305 return omap_timer_read(&s->timer); 306 307 case 0x08: /* TIMER_MODE */ 308 return s->mode << 15; 309 } 310 311 OMAP_BAD_REG(addr); 312 return 0; 313 } 314 315 static void omap_wd_timer_write(void *opaque, hwaddr addr, 316 uint64_t value, unsigned size) 317 { 318 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; 319 320 if (size != 2) { 321 omap_badwidth_write16(opaque, addr, value); 322 return; 323 } 324 325 switch (addr) { 326 case 0x00: /* CNTL_TIMER */ 327 omap_timer_sync(&s->timer); 328 s->timer.ptv = (value >> 9) & 7; 329 s->timer.ar = (value >> 8) & 1; 330 s->timer.st = (value >> 7) & 1; 331 s->free = (value >> 1) & 1; 332 omap_timer_update(&s->timer); 333 break; 334 335 case 0x04: /* LOAD_TIMER */ 336 s->timer.reset_val = value & 0xffff; 337 break; 338 339 case 0x08: /* TIMER_MODE */ 340 if (!s->mode && ((value >> 15) & 1)) 341 omap_clk_get(s->timer.clk); 342 s->mode |= (value >> 15) & 1; 343 if (s->last_wr == 0xf5) { 344 if ((value & 0xff) == 0xa0) { 345 if (s->mode) { 346 s->mode = 0; 347 omap_clk_put(s->timer.clk); 348 } 349 } else { 350 /* XXX: on T|E hardware somehow this has no effect, 351 * on Zire 71 it works as specified. */ 352 s->reset = 1; 353 qemu_system_reset_request(); 354 } 355 } 356 s->last_wr = value & 0xff; 357 break; 358 359 default: 360 OMAP_BAD_REG(addr); 361 } 362 } 363 364 static const MemoryRegionOps omap_wd_timer_ops = { 365 .read = omap_wd_timer_read, 366 .write = omap_wd_timer_write, 367 .endianness = DEVICE_NATIVE_ENDIAN, 368 }; 369 370 static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s) 371 { 372 timer_del(s->timer.timer); 373 if (!s->mode) 374 omap_clk_get(s->timer.clk); 375 s->mode = 1; 376 s->free = 1; 377 s->reset = 0; 378 s->timer.enable = 1; 379 s->timer.it_ena = 1; 380 s->timer.reset_val = 0xffff; 381 s->timer.val = 0; 382 s->timer.st = 0; 383 s->timer.ptv = 0; 384 s->timer.ar = 0; 385 omap_timer_update(&s->timer); 386 } 387 388 static struct omap_watchdog_timer_s *omap_wd_timer_init(MemoryRegion *memory, 389 hwaddr base, 390 qemu_irq irq, omap_clk clk) 391 { 392 struct omap_watchdog_timer_s *s = g_new0(struct omap_watchdog_timer_s, 1); 393 394 s->timer.irq = irq; 395 s->timer.clk = clk; 396 s->timer.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, &s->timer); 397 omap_wd_timer_reset(s); 398 omap_timer_clk_setup(&s->timer); 399 400 memory_region_init_io(&s->iomem, NULL, &omap_wd_timer_ops, s, 401 "omap-wd-timer", 0x100); 402 memory_region_add_subregion(memory, base, &s->iomem); 403 404 return s; 405 } 406 407 /* 32-kHz timer */ 408 struct omap_32khz_timer_s { 409 struct omap_mpu_timer_s timer; 410 MemoryRegion iomem; 411 }; 412 413 static uint64_t omap_os_timer_read(void *opaque, hwaddr addr, 414 unsigned size) 415 { 416 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; 417 int offset = addr & OMAP_MPUI_REG_MASK; 418 419 if (size != 4) { 420 return omap_badwidth_read32(opaque, addr); 421 } 422 423 switch (offset) { 424 case 0x00: /* TVR */ 425 return s->timer.reset_val; 426 427 case 0x04: /* TCR */ 428 return omap_timer_read(&s->timer); 429 430 case 0x08: /* CR */ 431 return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st; 432 433 default: 434 break; 435 } 436 OMAP_BAD_REG(addr); 437 return 0; 438 } 439 440 static void omap_os_timer_write(void *opaque, hwaddr addr, 441 uint64_t value, unsigned size) 442 { 443 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; 444 int offset = addr & OMAP_MPUI_REG_MASK; 445 446 if (size != 4) { 447 omap_badwidth_write32(opaque, addr, value); 448 return; 449 } 450 451 switch (offset) { 452 case 0x00: /* TVR */ 453 s->timer.reset_val = value & 0x00ffffff; 454 break; 455 456 case 0x04: /* TCR */ 457 OMAP_RO_REG(addr); 458 break; 459 460 case 0x08: /* CR */ 461 s->timer.ar = (value >> 3) & 1; 462 s->timer.it_ena = (value >> 2) & 1; 463 if (s->timer.st != (value & 1) || (value & 2)) { 464 omap_timer_sync(&s->timer); 465 s->timer.enable = value & 1; 466 s->timer.st = value & 1; 467 omap_timer_update(&s->timer); 468 } 469 break; 470 471 default: 472 OMAP_BAD_REG(addr); 473 } 474 } 475 476 static const MemoryRegionOps omap_os_timer_ops = { 477 .read = omap_os_timer_read, 478 .write = omap_os_timer_write, 479 .endianness = DEVICE_NATIVE_ENDIAN, 480 }; 481 482 static void omap_os_timer_reset(struct omap_32khz_timer_s *s) 483 { 484 timer_del(s->timer.timer); 485 s->timer.enable = 0; 486 s->timer.it_ena = 0; 487 s->timer.reset_val = 0x00ffffff; 488 s->timer.val = 0; 489 s->timer.st = 0; 490 s->timer.ptv = 0; 491 s->timer.ar = 1; 492 } 493 494 static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory, 495 hwaddr base, 496 qemu_irq irq, omap_clk clk) 497 { 498 struct omap_32khz_timer_s *s = g_new0(struct omap_32khz_timer_s, 1); 499 500 s->timer.irq = irq; 501 s->timer.clk = clk; 502 s->timer.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, &s->timer); 503 omap_os_timer_reset(s); 504 omap_timer_clk_setup(&s->timer); 505 506 memory_region_init_io(&s->iomem, NULL, &omap_os_timer_ops, s, 507 "omap-os-timer", 0x800); 508 memory_region_add_subregion(memory, base, &s->iomem); 509 510 return s; 511 } 512 513 /* Ultra Low-Power Device Module */ 514 static uint64_t omap_ulpd_pm_read(void *opaque, hwaddr addr, 515 unsigned size) 516 { 517 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 518 uint16_t ret; 519 520 if (size != 2) { 521 return omap_badwidth_read16(opaque, addr); 522 } 523 524 switch (addr) { 525 case 0x14: /* IT_STATUS */ 526 ret = s->ulpd_pm_regs[addr >> 2]; 527 s->ulpd_pm_regs[addr >> 2] = 0; 528 qemu_irq_lower(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K)); 529 return ret; 530 531 case 0x18: /* Reserved */ 532 case 0x1c: /* Reserved */ 533 case 0x20: /* Reserved */ 534 case 0x28: /* Reserved */ 535 case 0x2c: /* Reserved */ 536 OMAP_BAD_REG(addr); 537 /* fall through */ 538 case 0x00: /* COUNTER_32_LSB */ 539 case 0x04: /* COUNTER_32_MSB */ 540 case 0x08: /* COUNTER_HIGH_FREQ_LSB */ 541 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ 542 case 0x10: /* GAUGING_CTRL */ 543 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ 544 case 0x30: /* CLOCK_CTRL */ 545 case 0x34: /* SOFT_REQ */ 546 case 0x38: /* COUNTER_32_FIQ */ 547 case 0x3c: /* DPLL_CTRL */ 548 case 0x40: /* STATUS_REQ */ 549 /* XXX: check clk::usecount state for every clock */ 550 case 0x48: /* LOCL_TIME */ 551 case 0x4c: /* APLL_CTRL */ 552 case 0x50: /* POWER_CTRL */ 553 return s->ulpd_pm_regs[addr >> 2]; 554 } 555 556 OMAP_BAD_REG(addr); 557 return 0; 558 } 559 560 static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s, 561 uint16_t diff, uint16_t value) 562 { 563 if (diff & (1 << 4)) /* USB_MCLK_EN */ 564 omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1); 565 if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */ 566 omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1); 567 } 568 569 static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s, 570 uint16_t diff, uint16_t value) 571 { 572 if (diff & (1 << 0)) /* SOFT_DPLL_REQ */ 573 omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1); 574 if (diff & (1 << 1)) /* SOFT_COM_REQ */ 575 omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1); 576 if (diff & (1 << 2)) /* SOFT_SDW_REQ */ 577 omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1); 578 if (diff & (1 << 3)) /* SOFT_USB_REQ */ 579 omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1); 580 } 581 582 static void omap_ulpd_pm_write(void *opaque, hwaddr addr, 583 uint64_t value, unsigned size) 584 { 585 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 586 int64_t now, ticks; 587 int div, mult; 588 static const int bypass_div[4] = { 1, 2, 4, 4 }; 589 uint16_t diff; 590 591 if (size != 2) { 592 omap_badwidth_write16(opaque, addr, value); 593 return; 594 } 595 596 switch (addr) { 597 case 0x00: /* COUNTER_32_LSB */ 598 case 0x04: /* COUNTER_32_MSB */ 599 case 0x08: /* COUNTER_HIGH_FREQ_LSB */ 600 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ 601 case 0x14: /* IT_STATUS */ 602 case 0x40: /* STATUS_REQ */ 603 OMAP_RO_REG(addr); 604 break; 605 606 case 0x10: /* GAUGING_CTRL */ 607 /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */ 608 if ((s->ulpd_pm_regs[addr >> 2] ^ value) & 1) { 609 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 610 611 if (value & 1) 612 s->ulpd_gauge_start = now; 613 else { 614 now -= s->ulpd_gauge_start; 615 616 /* 32-kHz ticks */ 617 ticks = muldiv64(now, 32768, get_ticks_per_sec()); 618 s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff; 619 s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff; 620 if (ticks >> 32) /* OVERFLOW_32K */ 621 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2; 622 623 /* High frequency ticks */ 624 ticks = muldiv64(now, 12000000, get_ticks_per_sec()); 625 s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff; 626 s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff; 627 if (ticks >> 32) /* OVERFLOW_HI_FREQ */ 628 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1; 629 630 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */ 631 qemu_irq_raise(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K)); 632 } 633 } 634 s->ulpd_pm_regs[addr >> 2] = value; 635 break; 636 637 case 0x18: /* Reserved */ 638 case 0x1c: /* Reserved */ 639 case 0x20: /* Reserved */ 640 case 0x28: /* Reserved */ 641 case 0x2c: /* Reserved */ 642 OMAP_BAD_REG(addr); 643 /* fall through */ 644 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ 645 case 0x38: /* COUNTER_32_FIQ */ 646 case 0x48: /* LOCL_TIME */ 647 case 0x50: /* POWER_CTRL */ 648 s->ulpd_pm_regs[addr >> 2] = value; 649 break; 650 651 case 0x30: /* CLOCK_CTRL */ 652 diff = s->ulpd_pm_regs[addr >> 2] ^ value; 653 s->ulpd_pm_regs[addr >> 2] = value & 0x3f; 654 omap_ulpd_clk_update(s, diff, value); 655 break; 656 657 case 0x34: /* SOFT_REQ */ 658 diff = s->ulpd_pm_regs[addr >> 2] ^ value; 659 s->ulpd_pm_regs[addr >> 2] = value & 0x1f; 660 omap_ulpd_req_update(s, diff, value); 661 break; 662 663 case 0x3c: /* DPLL_CTRL */ 664 /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is 665 * omitted altogether, probably a typo. */ 666 /* This register has identical semantics with DPLL(1:3) control 667 * registers, see omap_dpll_write() */ 668 diff = s->ulpd_pm_regs[addr >> 2] & value; 669 s->ulpd_pm_regs[addr >> 2] = value & 0x2fff; 670 if (diff & (0x3ff << 2)) { 671 if (value & (1 << 4)) { /* PLL_ENABLE */ 672 div = ((value >> 5) & 3) + 1; /* PLL_DIV */ 673 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ 674 } else { 675 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ 676 mult = 1; 677 } 678 omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult); 679 } 680 681 /* Enter the desired mode. */ 682 s->ulpd_pm_regs[addr >> 2] = 683 (s->ulpd_pm_regs[addr >> 2] & 0xfffe) | 684 ((s->ulpd_pm_regs[addr >> 2] >> 4) & 1); 685 686 /* Act as if the lock is restored. */ 687 s->ulpd_pm_regs[addr >> 2] |= 2; 688 break; 689 690 case 0x4c: /* APLL_CTRL */ 691 diff = s->ulpd_pm_regs[addr >> 2] & value; 692 s->ulpd_pm_regs[addr >> 2] = value & 0xf; 693 if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */ 694 omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s, 695 (value & (1 << 0)) ? "apll" : "dpll4")); 696 break; 697 698 default: 699 OMAP_BAD_REG(addr); 700 } 701 } 702 703 static const MemoryRegionOps omap_ulpd_pm_ops = { 704 .read = omap_ulpd_pm_read, 705 .write = omap_ulpd_pm_write, 706 .endianness = DEVICE_NATIVE_ENDIAN, 707 }; 708 709 static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu) 710 { 711 mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001; 712 mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000; 713 mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001; 714 mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000; 715 mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000; 716 mpu->ulpd_pm_regs[0x18 >> 2] = 0x01; 717 mpu->ulpd_pm_regs[0x1c >> 2] = 0x01; 718 mpu->ulpd_pm_regs[0x20 >> 2] = 0x01; 719 mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff; 720 mpu->ulpd_pm_regs[0x28 >> 2] = 0x01; 721 mpu->ulpd_pm_regs[0x2c >> 2] = 0x01; 722 omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000); 723 mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000; 724 omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000); 725 mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000; 726 mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001; 727 mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211; 728 mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */ 729 mpu->ulpd_pm_regs[0x48 >> 2] = 0x960; 730 mpu->ulpd_pm_regs[0x4c >> 2] = 0x08; 731 mpu->ulpd_pm_regs[0x50 >> 2] = 0x08; 732 omap_clk_setrate(omap_findclk(mpu, "dpll4"), 1, 4); 733 omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4")); 734 } 735 736 static void omap_ulpd_pm_init(MemoryRegion *system_memory, 737 hwaddr base, 738 struct omap_mpu_state_s *mpu) 739 { 740 memory_region_init_io(&mpu->ulpd_pm_iomem, NULL, &omap_ulpd_pm_ops, mpu, 741 "omap-ulpd-pm", 0x800); 742 memory_region_add_subregion(system_memory, base, &mpu->ulpd_pm_iomem); 743 omap_ulpd_pm_reset(mpu); 744 } 745 746 /* OMAP Pin Configuration */ 747 static uint64_t omap_pin_cfg_read(void *opaque, hwaddr addr, 748 unsigned size) 749 { 750 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 751 752 if (size != 4) { 753 return omap_badwidth_read32(opaque, addr); 754 } 755 756 switch (addr) { 757 case 0x00: /* FUNC_MUX_CTRL_0 */ 758 case 0x04: /* FUNC_MUX_CTRL_1 */ 759 case 0x08: /* FUNC_MUX_CTRL_2 */ 760 return s->func_mux_ctrl[addr >> 2]; 761 762 case 0x0c: /* COMP_MODE_CTRL_0 */ 763 return s->comp_mode_ctrl[0]; 764 765 case 0x10: /* FUNC_MUX_CTRL_3 */ 766 case 0x14: /* FUNC_MUX_CTRL_4 */ 767 case 0x18: /* FUNC_MUX_CTRL_5 */ 768 case 0x1c: /* FUNC_MUX_CTRL_6 */ 769 case 0x20: /* FUNC_MUX_CTRL_7 */ 770 case 0x24: /* FUNC_MUX_CTRL_8 */ 771 case 0x28: /* FUNC_MUX_CTRL_9 */ 772 case 0x2c: /* FUNC_MUX_CTRL_A */ 773 case 0x30: /* FUNC_MUX_CTRL_B */ 774 case 0x34: /* FUNC_MUX_CTRL_C */ 775 case 0x38: /* FUNC_MUX_CTRL_D */ 776 return s->func_mux_ctrl[(addr >> 2) - 1]; 777 778 case 0x40: /* PULL_DWN_CTRL_0 */ 779 case 0x44: /* PULL_DWN_CTRL_1 */ 780 case 0x48: /* PULL_DWN_CTRL_2 */ 781 case 0x4c: /* PULL_DWN_CTRL_3 */ 782 return s->pull_dwn_ctrl[(addr & 0xf) >> 2]; 783 784 case 0x50: /* GATE_INH_CTRL_0 */ 785 return s->gate_inh_ctrl[0]; 786 787 case 0x60: /* VOLTAGE_CTRL_0 */ 788 return s->voltage_ctrl[0]; 789 790 case 0x70: /* TEST_DBG_CTRL_0 */ 791 return s->test_dbg_ctrl[0]; 792 793 case 0x80: /* MOD_CONF_CTRL_0 */ 794 return s->mod_conf_ctrl[0]; 795 } 796 797 OMAP_BAD_REG(addr); 798 return 0; 799 } 800 801 static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s, 802 uint32_t diff, uint32_t value) 803 { 804 if (s->compat1509) { 805 if (diff & (1 << 9)) /* BLUETOOTH */ 806 omap_clk_onoff(omap_findclk(s, "bt_mclk_out"), 807 (~value >> 9) & 1); 808 if (diff & (1 << 7)) /* USB.CLKO */ 809 omap_clk_onoff(omap_findclk(s, "usb.clko"), 810 (value >> 7) & 1); 811 } 812 } 813 814 static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s, 815 uint32_t diff, uint32_t value) 816 { 817 if (s->compat1509) { 818 if (diff & (1U << 31)) { 819 /* MCBSP3_CLK_HIZ_DI */ 820 omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"), (value >> 31) & 1); 821 } 822 if (diff & (1 << 1)) { 823 /* CLK32K */ 824 omap_clk_onoff(omap_findclk(s, "clk32k_out"), (~value >> 1) & 1); 825 } 826 } 827 } 828 829 static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s, 830 uint32_t diff, uint32_t value) 831 { 832 if (diff & (1U << 31)) { 833 /* CONF_MOD_UART3_CLK_MODE_R */ 834 omap_clk_reparent(omap_findclk(s, "uart3_ck"), 835 omap_findclk(s, ((value >> 31) & 1) ? 836 "ck_48m" : "armper_ck")); 837 } 838 if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */ 839 omap_clk_reparent(omap_findclk(s, "uart2_ck"), 840 omap_findclk(s, ((value >> 30) & 1) ? 841 "ck_48m" : "armper_ck")); 842 if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */ 843 omap_clk_reparent(omap_findclk(s, "uart1_ck"), 844 omap_findclk(s, ((value >> 29) & 1) ? 845 "ck_48m" : "armper_ck")); 846 if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */ 847 omap_clk_reparent(omap_findclk(s, "mmc_ck"), 848 omap_findclk(s, ((value >> 23) & 1) ? 849 "ck_48m" : "armper_ck")); 850 if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */ 851 omap_clk_reparent(omap_findclk(s, "com_mclk_out"), 852 omap_findclk(s, ((value >> 12) & 1) ? 853 "ck_48m" : "armper_ck")); 854 if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */ 855 omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1); 856 } 857 858 static void omap_pin_cfg_write(void *opaque, hwaddr addr, 859 uint64_t value, unsigned size) 860 { 861 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 862 uint32_t diff; 863 864 if (size != 4) { 865 omap_badwidth_write32(opaque, addr, value); 866 return; 867 } 868 869 switch (addr) { 870 case 0x00: /* FUNC_MUX_CTRL_0 */ 871 diff = s->func_mux_ctrl[addr >> 2] ^ value; 872 s->func_mux_ctrl[addr >> 2] = value; 873 omap_pin_funcmux0_update(s, diff, value); 874 return; 875 876 case 0x04: /* FUNC_MUX_CTRL_1 */ 877 diff = s->func_mux_ctrl[addr >> 2] ^ value; 878 s->func_mux_ctrl[addr >> 2] = value; 879 omap_pin_funcmux1_update(s, diff, value); 880 return; 881 882 case 0x08: /* FUNC_MUX_CTRL_2 */ 883 s->func_mux_ctrl[addr >> 2] = value; 884 return; 885 886 case 0x0c: /* COMP_MODE_CTRL_0 */ 887 s->comp_mode_ctrl[0] = value; 888 s->compat1509 = (value != 0x0000eaef); 889 omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]); 890 omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]); 891 return; 892 893 case 0x10: /* FUNC_MUX_CTRL_3 */ 894 case 0x14: /* FUNC_MUX_CTRL_4 */ 895 case 0x18: /* FUNC_MUX_CTRL_5 */ 896 case 0x1c: /* FUNC_MUX_CTRL_6 */ 897 case 0x20: /* FUNC_MUX_CTRL_7 */ 898 case 0x24: /* FUNC_MUX_CTRL_8 */ 899 case 0x28: /* FUNC_MUX_CTRL_9 */ 900 case 0x2c: /* FUNC_MUX_CTRL_A */ 901 case 0x30: /* FUNC_MUX_CTRL_B */ 902 case 0x34: /* FUNC_MUX_CTRL_C */ 903 case 0x38: /* FUNC_MUX_CTRL_D */ 904 s->func_mux_ctrl[(addr >> 2) - 1] = value; 905 return; 906 907 case 0x40: /* PULL_DWN_CTRL_0 */ 908 case 0x44: /* PULL_DWN_CTRL_1 */ 909 case 0x48: /* PULL_DWN_CTRL_2 */ 910 case 0x4c: /* PULL_DWN_CTRL_3 */ 911 s->pull_dwn_ctrl[(addr & 0xf) >> 2] = value; 912 return; 913 914 case 0x50: /* GATE_INH_CTRL_0 */ 915 s->gate_inh_ctrl[0] = value; 916 return; 917 918 case 0x60: /* VOLTAGE_CTRL_0 */ 919 s->voltage_ctrl[0] = value; 920 return; 921 922 case 0x70: /* TEST_DBG_CTRL_0 */ 923 s->test_dbg_ctrl[0] = value; 924 return; 925 926 case 0x80: /* MOD_CONF_CTRL_0 */ 927 diff = s->mod_conf_ctrl[0] ^ value; 928 s->mod_conf_ctrl[0] = value; 929 omap_pin_modconf1_update(s, diff, value); 930 return; 931 932 default: 933 OMAP_BAD_REG(addr); 934 } 935 } 936 937 static const MemoryRegionOps omap_pin_cfg_ops = { 938 .read = omap_pin_cfg_read, 939 .write = omap_pin_cfg_write, 940 .endianness = DEVICE_NATIVE_ENDIAN, 941 }; 942 943 static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu) 944 { 945 /* Start in Compatibility Mode. */ 946 mpu->compat1509 = 1; 947 omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0); 948 omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0); 949 omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0); 950 memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl)); 951 memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl)); 952 memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl)); 953 memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl)); 954 memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl)); 955 memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl)); 956 memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl)); 957 } 958 959 static void omap_pin_cfg_init(MemoryRegion *system_memory, 960 hwaddr base, 961 struct omap_mpu_state_s *mpu) 962 { 963 memory_region_init_io(&mpu->pin_cfg_iomem, NULL, &omap_pin_cfg_ops, mpu, 964 "omap-pin-cfg", 0x800); 965 memory_region_add_subregion(system_memory, base, &mpu->pin_cfg_iomem); 966 omap_pin_cfg_reset(mpu); 967 } 968 969 /* Device Identification, Die Identification */ 970 static uint64_t omap_id_read(void *opaque, hwaddr addr, 971 unsigned size) 972 { 973 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 974 975 if (size != 4) { 976 return omap_badwidth_read32(opaque, addr); 977 } 978 979 switch (addr) { 980 case 0xfffe1800: /* DIE_ID_LSB */ 981 return 0xc9581f0e; 982 case 0xfffe1804: /* DIE_ID_MSB */ 983 return 0xa8858bfa; 984 985 case 0xfffe2000: /* PRODUCT_ID_LSB */ 986 return 0x00aaaafc; 987 case 0xfffe2004: /* PRODUCT_ID_MSB */ 988 return 0xcafeb574; 989 990 case 0xfffed400: /* JTAG_ID_LSB */ 991 switch (s->mpu_model) { 992 case omap310: 993 return 0x03310315; 994 case omap1510: 995 return 0x03310115; 996 default: 997 hw_error("%s: bad mpu model\n", __FUNCTION__); 998 } 999 break; 1000 1001 case 0xfffed404: /* JTAG_ID_MSB */ 1002 switch (s->mpu_model) { 1003 case omap310: 1004 return 0xfb57402f; 1005 case omap1510: 1006 return 0xfb47002f; 1007 default: 1008 hw_error("%s: bad mpu model\n", __FUNCTION__); 1009 } 1010 break; 1011 } 1012 1013 OMAP_BAD_REG(addr); 1014 return 0; 1015 } 1016 1017 static void omap_id_write(void *opaque, hwaddr addr, 1018 uint64_t value, unsigned size) 1019 { 1020 if (size != 4) { 1021 omap_badwidth_write32(opaque, addr, value); 1022 return; 1023 } 1024 1025 OMAP_BAD_REG(addr); 1026 } 1027 1028 static const MemoryRegionOps omap_id_ops = { 1029 .read = omap_id_read, 1030 .write = omap_id_write, 1031 .endianness = DEVICE_NATIVE_ENDIAN, 1032 }; 1033 1034 static void omap_id_init(MemoryRegion *memory, struct omap_mpu_state_s *mpu) 1035 { 1036 memory_region_init_io(&mpu->id_iomem, NULL, &omap_id_ops, mpu, 1037 "omap-id", 0x100000000ULL); 1038 memory_region_init_alias(&mpu->id_iomem_e18, NULL, "omap-id-e18", &mpu->id_iomem, 1039 0xfffe1800, 0x800); 1040 memory_region_add_subregion(memory, 0xfffe1800, &mpu->id_iomem_e18); 1041 memory_region_init_alias(&mpu->id_iomem_ed4, NULL, "omap-id-ed4", &mpu->id_iomem, 1042 0xfffed400, 0x100); 1043 memory_region_add_subregion(memory, 0xfffed400, &mpu->id_iomem_ed4); 1044 if (!cpu_is_omap15xx(mpu)) { 1045 memory_region_init_alias(&mpu->id_iomem_ed4, NULL, "omap-id-e20", 1046 &mpu->id_iomem, 0xfffe2000, 0x800); 1047 memory_region_add_subregion(memory, 0xfffe2000, &mpu->id_iomem_e20); 1048 } 1049 } 1050 1051 /* MPUI Control (Dummy) */ 1052 static uint64_t omap_mpui_read(void *opaque, hwaddr addr, 1053 unsigned size) 1054 { 1055 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1056 1057 if (size != 4) { 1058 return omap_badwidth_read32(opaque, addr); 1059 } 1060 1061 switch (addr) { 1062 case 0x00: /* CTRL */ 1063 return s->mpui_ctrl; 1064 case 0x04: /* DEBUG_ADDR */ 1065 return 0x01ffffff; 1066 case 0x08: /* DEBUG_DATA */ 1067 return 0xffffffff; 1068 case 0x0c: /* DEBUG_FLAG */ 1069 return 0x00000800; 1070 case 0x10: /* STATUS */ 1071 return 0x00000000; 1072 1073 /* Not in OMAP310 */ 1074 case 0x14: /* DSP_STATUS */ 1075 case 0x18: /* DSP_BOOT_CONFIG */ 1076 return 0x00000000; 1077 case 0x1c: /* DSP_MPUI_CONFIG */ 1078 return 0x0000ffff; 1079 } 1080 1081 OMAP_BAD_REG(addr); 1082 return 0; 1083 } 1084 1085 static void omap_mpui_write(void *opaque, hwaddr addr, 1086 uint64_t value, unsigned size) 1087 { 1088 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1089 1090 if (size != 4) { 1091 omap_badwidth_write32(opaque, addr, value); 1092 return; 1093 } 1094 1095 switch (addr) { 1096 case 0x00: /* CTRL */ 1097 s->mpui_ctrl = value & 0x007fffff; 1098 break; 1099 1100 case 0x04: /* DEBUG_ADDR */ 1101 case 0x08: /* DEBUG_DATA */ 1102 case 0x0c: /* DEBUG_FLAG */ 1103 case 0x10: /* STATUS */ 1104 /* Not in OMAP310 */ 1105 case 0x14: /* DSP_STATUS */ 1106 OMAP_RO_REG(addr); 1107 break; 1108 case 0x18: /* DSP_BOOT_CONFIG */ 1109 case 0x1c: /* DSP_MPUI_CONFIG */ 1110 break; 1111 1112 default: 1113 OMAP_BAD_REG(addr); 1114 } 1115 } 1116 1117 static const MemoryRegionOps omap_mpui_ops = { 1118 .read = omap_mpui_read, 1119 .write = omap_mpui_write, 1120 .endianness = DEVICE_NATIVE_ENDIAN, 1121 }; 1122 1123 static void omap_mpui_reset(struct omap_mpu_state_s *s) 1124 { 1125 s->mpui_ctrl = 0x0003ff1b; 1126 } 1127 1128 static void omap_mpui_init(MemoryRegion *memory, hwaddr base, 1129 struct omap_mpu_state_s *mpu) 1130 { 1131 memory_region_init_io(&mpu->mpui_iomem, NULL, &omap_mpui_ops, mpu, 1132 "omap-mpui", 0x100); 1133 memory_region_add_subregion(memory, base, &mpu->mpui_iomem); 1134 1135 omap_mpui_reset(mpu); 1136 } 1137 1138 /* TIPB Bridges */ 1139 struct omap_tipb_bridge_s { 1140 qemu_irq abort; 1141 MemoryRegion iomem; 1142 1143 int width_intr; 1144 uint16_t control; 1145 uint16_t alloc; 1146 uint16_t buffer; 1147 uint16_t enh_control; 1148 }; 1149 1150 static uint64_t omap_tipb_bridge_read(void *opaque, hwaddr addr, 1151 unsigned size) 1152 { 1153 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; 1154 1155 if (size < 2) { 1156 return omap_badwidth_read16(opaque, addr); 1157 } 1158 1159 switch (addr) { 1160 case 0x00: /* TIPB_CNTL */ 1161 return s->control; 1162 case 0x04: /* TIPB_BUS_ALLOC */ 1163 return s->alloc; 1164 case 0x08: /* MPU_TIPB_CNTL */ 1165 return s->buffer; 1166 case 0x0c: /* ENHANCED_TIPB_CNTL */ 1167 return s->enh_control; 1168 case 0x10: /* ADDRESS_DBG */ 1169 case 0x14: /* DATA_DEBUG_LOW */ 1170 case 0x18: /* DATA_DEBUG_HIGH */ 1171 return 0xffff; 1172 case 0x1c: /* DEBUG_CNTR_SIG */ 1173 return 0x00f8; 1174 } 1175 1176 OMAP_BAD_REG(addr); 1177 return 0; 1178 } 1179 1180 static void omap_tipb_bridge_write(void *opaque, hwaddr addr, 1181 uint64_t value, unsigned size) 1182 { 1183 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; 1184 1185 if (size < 2) { 1186 omap_badwidth_write16(opaque, addr, value); 1187 return; 1188 } 1189 1190 switch (addr) { 1191 case 0x00: /* TIPB_CNTL */ 1192 s->control = value & 0xffff; 1193 break; 1194 1195 case 0x04: /* TIPB_BUS_ALLOC */ 1196 s->alloc = value & 0x003f; 1197 break; 1198 1199 case 0x08: /* MPU_TIPB_CNTL */ 1200 s->buffer = value & 0x0003; 1201 break; 1202 1203 case 0x0c: /* ENHANCED_TIPB_CNTL */ 1204 s->width_intr = !(value & 2); 1205 s->enh_control = value & 0x000f; 1206 break; 1207 1208 case 0x10: /* ADDRESS_DBG */ 1209 case 0x14: /* DATA_DEBUG_LOW */ 1210 case 0x18: /* DATA_DEBUG_HIGH */ 1211 case 0x1c: /* DEBUG_CNTR_SIG */ 1212 OMAP_RO_REG(addr); 1213 break; 1214 1215 default: 1216 OMAP_BAD_REG(addr); 1217 } 1218 } 1219 1220 static const MemoryRegionOps omap_tipb_bridge_ops = { 1221 .read = omap_tipb_bridge_read, 1222 .write = omap_tipb_bridge_write, 1223 .endianness = DEVICE_NATIVE_ENDIAN, 1224 }; 1225 1226 static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s) 1227 { 1228 s->control = 0xffff; 1229 s->alloc = 0x0009; 1230 s->buffer = 0x0000; 1231 s->enh_control = 0x000f; 1232 } 1233 1234 static struct omap_tipb_bridge_s *omap_tipb_bridge_init( 1235 MemoryRegion *memory, hwaddr base, 1236 qemu_irq abort_irq, omap_clk clk) 1237 { 1238 struct omap_tipb_bridge_s *s = g_new0(struct omap_tipb_bridge_s, 1); 1239 1240 s->abort = abort_irq; 1241 omap_tipb_bridge_reset(s); 1242 1243 memory_region_init_io(&s->iomem, NULL, &omap_tipb_bridge_ops, s, 1244 "omap-tipb-bridge", 0x100); 1245 memory_region_add_subregion(memory, base, &s->iomem); 1246 1247 return s; 1248 } 1249 1250 /* Dummy Traffic Controller's Memory Interface */ 1251 static uint64_t omap_tcmi_read(void *opaque, hwaddr addr, 1252 unsigned size) 1253 { 1254 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1255 uint32_t ret; 1256 1257 if (size != 4) { 1258 return omap_badwidth_read32(opaque, addr); 1259 } 1260 1261 switch (addr) { 1262 case 0x00: /* IMIF_PRIO */ 1263 case 0x04: /* EMIFS_PRIO */ 1264 case 0x08: /* EMIFF_PRIO */ 1265 case 0x0c: /* EMIFS_CONFIG */ 1266 case 0x10: /* EMIFS_CS0_CONFIG */ 1267 case 0x14: /* EMIFS_CS1_CONFIG */ 1268 case 0x18: /* EMIFS_CS2_CONFIG */ 1269 case 0x1c: /* EMIFS_CS3_CONFIG */ 1270 case 0x24: /* EMIFF_MRS */ 1271 case 0x28: /* TIMEOUT1 */ 1272 case 0x2c: /* TIMEOUT2 */ 1273 case 0x30: /* TIMEOUT3 */ 1274 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ 1275 case 0x40: /* EMIFS_CFG_DYN_WAIT */ 1276 return s->tcmi_regs[addr >> 2]; 1277 1278 case 0x20: /* EMIFF_SDRAM_CONFIG */ 1279 ret = s->tcmi_regs[addr >> 2]; 1280 s->tcmi_regs[addr >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */ 1281 /* XXX: We can try using the VGA_DIRTY flag for this */ 1282 return ret; 1283 } 1284 1285 OMAP_BAD_REG(addr); 1286 return 0; 1287 } 1288 1289 static void omap_tcmi_write(void *opaque, hwaddr addr, 1290 uint64_t value, unsigned size) 1291 { 1292 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1293 1294 if (size != 4) { 1295 omap_badwidth_write32(opaque, addr, value); 1296 return; 1297 } 1298 1299 switch (addr) { 1300 case 0x00: /* IMIF_PRIO */ 1301 case 0x04: /* EMIFS_PRIO */ 1302 case 0x08: /* EMIFF_PRIO */ 1303 case 0x10: /* EMIFS_CS0_CONFIG */ 1304 case 0x14: /* EMIFS_CS1_CONFIG */ 1305 case 0x18: /* EMIFS_CS2_CONFIG */ 1306 case 0x1c: /* EMIFS_CS3_CONFIG */ 1307 case 0x20: /* EMIFF_SDRAM_CONFIG */ 1308 case 0x24: /* EMIFF_MRS */ 1309 case 0x28: /* TIMEOUT1 */ 1310 case 0x2c: /* TIMEOUT2 */ 1311 case 0x30: /* TIMEOUT3 */ 1312 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ 1313 case 0x40: /* EMIFS_CFG_DYN_WAIT */ 1314 s->tcmi_regs[addr >> 2] = value; 1315 break; 1316 case 0x0c: /* EMIFS_CONFIG */ 1317 s->tcmi_regs[addr >> 2] = (value & 0xf) | (1 << 4); 1318 break; 1319 1320 default: 1321 OMAP_BAD_REG(addr); 1322 } 1323 } 1324 1325 static const MemoryRegionOps omap_tcmi_ops = { 1326 .read = omap_tcmi_read, 1327 .write = omap_tcmi_write, 1328 .endianness = DEVICE_NATIVE_ENDIAN, 1329 }; 1330 1331 static void omap_tcmi_reset(struct omap_mpu_state_s *mpu) 1332 { 1333 mpu->tcmi_regs[0x00 >> 2] = 0x00000000; 1334 mpu->tcmi_regs[0x04 >> 2] = 0x00000000; 1335 mpu->tcmi_regs[0x08 >> 2] = 0x00000000; 1336 mpu->tcmi_regs[0x0c >> 2] = 0x00000010; 1337 mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb; 1338 mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb; 1339 mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb; 1340 mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb; 1341 mpu->tcmi_regs[0x20 >> 2] = 0x00618800; 1342 mpu->tcmi_regs[0x24 >> 2] = 0x00000037; 1343 mpu->tcmi_regs[0x28 >> 2] = 0x00000000; 1344 mpu->tcmi_regs[0x2c >> 2] = 0x00000000; 1345 mpu->tcmi_regs[0x30 >> 2] = 0x00000000; 1346 mpu->tcmi_regs[0x3c >> 2] = 0x00000003; 1347 mpu->tcmi_regs[0x40 >> 2] = 0x00000000; 1348 } 1349 1350 static void omap_tcmi_init(MemoryRegion *memory, hwaddr base, 1351 struct omap_mpu_state_s *mpu) 1352 { 1353 memory_region_init_io(&mpu->tcmi_iomem, NULL, &omap_tcmi_ops, mpu, 1354 "omap-tcmi", 0x100); 1355 memory_region_add_subregion(memory, base, &mpu->tcmi_iomem); 1356 omap_tcmi_reset(mpu); 1357 } 1358 1359 /* Digital phase-locked loops control */ 1360 struct dpll_ctl_s { 1361 MemoryRegion iomem; 1362 uint16_t mode; 1363 omap_clk dpll; 1364 }; 1365 1366 static uint64_t omap_dpll_read(void *opaque, hwaddr addr, 1367 unsigned size) 1368 { 1369 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; 1370 1371 if (size != 2) { 1372 return omap_badwidth_read16(opaque, addr); 1373 } 1374 1375 if (addr == 0x00) /* CTL_REG */ 1376 return s->mode; 1377 1378 OMAP_BAD_REG(addr); 1379 return 0; 1380 } 1381 1382 static void omap_dpll_write(void *opaque, hwaddr addr, 1383 uint64_t value, unsigned size) 1384 { 1385 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; 1386 uint16_t diff; 1387 static const int bypass_div[4] = { 1, 2, 4, 4 }; 1388 int div, mult; 1389 1390 if (size != 2) { 1391 omap_badwidth_write16(opaque, addr, value); 1392 return; 1393 } 1394 1395 if (addr == 0x00) { /* CTL_REG */ 1396 /* See omap_ulpd_pm_write() too */ 1397 diff = s->mode & value; 1398 s->mode = value & 0x2fff; 1399 if (diff & (0x3ff << 2)) { 1400 if (value & (1 << 4)) { /* PLL_ENABLE */ 1401 div = ((value >> 5) & 3) + 1; /* PLL_DIV */ 1402 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ 1403 } else { 1404 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ 1405 mult = 1; 1406 } 1407 omap_clk_setrate(s->dpll, div, mult); 1408 } 1409 1410 /* Enter the desired mode. */ 1411 s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1); 1412 1413 /* Act as if the lock is restored. */ 1414 s->mode |= 2; 1415 } else { 1416 OMAP_BAD_REG(addr); 1417 } 1418 } 1419 1420 static const MemoryRegionOps omap_dpll_ops = { 1421 .read = omap_dpll_read, 1422 .write = omap_dpll_write, 1423 .endianness = DEVICE_NATIVE_ENDIAN, 1424 }; 1425 1426 static void omap_dpll_reset(struct dpll_ctl_s *s) 1427 { 1428 s->mode = 0x2002; 1429 omap_clk_setrate(s->dpll, 1, 1); 1430 } 1431 1432 static struct dpll_ctl_s *omap_dpll_init(MemoryRegion *memory, 1433 hwaddr base, omap_clk clk) 1434 { 1435 struct dpll_ctl_s *s = g_malloc0(sizeof(*s)); 1436 memory_region_init_io(&s->iomem, NULL, &omap_dpll_ops, s, "omap-dpll", 0x100); 1437 1438 s->dpll = clk; 1439 omap_dpll_reset(s); 1440 1441 memory_region_add_subregion(memory, base, &s->iomem); 1442 return s; 1443 } 1444 1445 /* MPU Clock/Reset/Power Mode Control */ 1446 static uint64_t omap_clkm_read(void *opaque, hwaddr addr, 1447 unsigned size) 1448 { 1449 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1450 1451 if (size != 2) { 1452 return omap_badwidth_read16(opaque, addr); 1453 } 1454 1455 switch (addr) { 1456 case 0x00: /* ARM_CKCTL */ 1457 return s->clkm.arm_ckctl; 1458 1459 case 0x04: /* ARM_IDLECT1 */ 1460 return s->clkm.arm_idlect1; 1461 1462 case 0x08: /* ARM_IDLECT2 */ 1463 return s->clkm.arm_idlect2; 1464 1465 case 0x0c: /* ARM_EWUPCT */ 1466 return s->clkm.arm_ewupct; 1467 1468 case 0x10: /* ARM_RSTCT1 */ 1469 return s->clkm.arm_rstct1; 1470 1471 case 0x14: /* ARM_RSTCT2 */ 1472 return s->clkm.arm_rstct2; 1473 1474 case 0x18: /* ARM_SYSST */ 1475 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start; 1476 1477 case 0x1c: /* ARM_CKOUT1 */ 1478 return s->clkm.arm_ckout1; 1479 1480 case 0x20: /* ARM_CKOUT2 */ 1481 break; 1482 } 1483 1484 OMAP_BAD_REG(addr); 1485 return 0; 1486 } 1487 1488 static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s, 1489 uint16_t diff, uint16_t value) 1490 { 1491 omap_clk clk; 1492 1493 if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */ 1494 if (value & (1 << 14)) 1495 /* Reserved */; 1496 else { 1497 clk = omap_findclk(s, "arminth_ck"); 1498 omap_clk_reparent(clk, omap_findclk(s, "tc_ck")); 1499 } 1500 } 1501 if (diff & (1 << 12)) { /* ARM_TIMXO */ 1502 clk = omap_findclk(s, "armtim_ck"); 1503 if (value & (1 << 12)) 1504 omap_clk_reparent(clk, omap_findclk(s, "clkin")); 1505 else 1506 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1")); 1507 } 1508 /* XXX: en_dspck */ 1509 if (diff & (3 << 10)) { /* DSPMMUDIV */ 1510 clk = omap_findclk(s, "dspmmu_ck"); 1511 omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1); 1512 } 1513 if (diff & (3 << 8)) { /* TCDIV */ 1514 clk = omap_findclk(s, "tc_ck"); 1515 omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1); 1516 } 1517 if (diff & (3 << 6)) { /* DSPDIV */ 1518 clk = omap_findclk(s, "dsp_ck"); 1519 omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1); 1520 } 1521 if (diff & (3 << 4)) { /* ARMDIV */ 1522 clk = omap_findclk(s, "arm_ck"); 1523 omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1); 1524 } 1525 if (diff & (3 << 2)) { /* LCDDIV */ 1526 clk = omap_findclk(s, "lcd_ck"); 1527 omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1); 1528 } 1529 if (diff & (3 << 0)) { /* PERDIV */ 1530 clk = omap_findclk(s, "armper_ck"); 1531 omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1); 1532 } 1533 } 1534 1535 static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s, 1536 uint16_t diff, uint16_t value) 1537 { 1538 omap_clk clk; 1539 1540 if (value & (1 << 11)) { /* SETARM_IDLE */ 1541 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); 1542 } 1543 if (!(value & (1 << 10))) /* WKUP_MODE */ 1544 qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */ 1545 1546 #define SET_CANIDLE(clock, bit) \ 1547 if (diff & (1 << bit)) { \ 1548 clk = omap_findclk(s, clock); \ 1549 omap_clk_canidle(clk, (value >> bit) & 1); \ 1550 } 1551 SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */ 1552 SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */ 1553 SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */ 1554 SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */ 1555 SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */ 1556 SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */ 1557 SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */ 1558 SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */ 1559 SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */ 1560 SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */ 1561 SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */ 1562 SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */ 1563 SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */ 1564 SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */ 1565 } 1566 1567 static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s, 1568 uint16_t diff, uint16_t value) 1569 { 1570 omap_clk clk; 1571 1572 #define SET_ONOFF(clock, bit) \ 1573 if (diff & (1 << bit)) { \ 1574 clk = omap_findclk(s, clock); \ 1575 omap_clk_onoff(clk, (value >> bit) & 1); \ 1576 } 1577 SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */ 1578 SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */ 1579 SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */ 1580 SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */ 1581 SET_ONOFF("lb_ck", 4) /* EN_LBCK */ 1582 SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */ 1583 SET_ONOFF("mpui_ck", 6) /* EN_APICK */ 1584 SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */ 1585 SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */ 1586 SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */ 1587 SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */ 1588 } 1589 1590 static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s, 1591 uint16_t diff, uint16_t value) 1592 { 1593 omap_clk clk; 1594 1595 if (diff & (3 << 4)) { /* TCLKOUT */ 1596 clk = omap_findclk(s, "tclk_out"); 1597 switch ((value >> 4) & 3) { 1598 case 1: 1599 omap_clk_reparent(clk, omap_findclk(s, "ck_gen3")); 1600 omap_clk_onoff(clk, 1); 1601 break; 1602 case 2: 1603 omap_clk_reparent(clk, omap_findclk(s, "tc_ck")); 1604 omap_clk_onoff(clk, 1); 1605 break; 1606 default: 1607 omap_clk_onoff(clk, 0); 1608 } 1609 } 1610 if (diff & (3 << 2)) { /* DCLKOUT */ 1611 clk = omap_findclk(s, "dclk_out"); 1612 switch ((value >> 2) & 3) { 1613 case 0: 1614 omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck")); 1615 break; 1616 case 1: 1617 omap_clk_reparent(clk, omap_findclk(s, "ck_gen2")); 1618 break; 1619 case 2: 1620 omap_clk_reparent(clk, omap_findclk(s, "dsp_ck")); 1621 break; 1622 case 3: 1623 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14")); 1624 break; 1625 } 1626 } 1627 if (diff & (3 << 0)) { /* ACLKOUT */ 1628 clk = omap_findclk(s, "aclk_out"); 1629 switch ((value >> 0) & 3) { 1630 case 1: 1631 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1")); 1632 omap_clk_onoff(clk, 1); 1633 break; 1634 case 2: 1635 omap_clk_reparent(clk, omap_findclk(s, "arm_ck")); 1636 omap_clk_onoff(clk, 1); 1637 break; 1638 case 3: 1639 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14")); 1640 omap_clk_onoff(clk, 1); 1641 break; 1642 default: 1643 omap_clk_onoff(clk, 0); 1644 } 1645 } 1646 } 1647 1648 static void omap_clkm_write(void *opaque, hwaddr addr, 1649 uint64_t value, unsigned size) 1650 { 1651 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1652 uint16_t diff; 1653 omap_clk clk; 1654 static const char *clkschemename[8] = { 1655 "fully synchronous", "fully asynchronous", "synchronous scalable", 1656 "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4", 1657 }; 1658 1659 if (size != 2) { 1660 omap_badwidth_write16(opaque, addr, value); 1661 return; 1662 } 1663 1664 switch (addr) { 1665 case 0x00: /* ARM_CKCTL */ 1666 diff = s->clkm.arm_ckctl ^ value; 1667 s->clkm.arm_ckctl = value & 0x7fff; 1668 omap_clkm_ckctl_update(s, diff, value); 1669 return; 1670 1671 case 0x04: /* ARM_IDLECT1 */ 1672 diff = s->clkm.arm_idlect1 ^ value; 1673 s->clkm.arm_idlect1 = value & 0x0fff; 1674 omap_clkm_idlect1_update(s, diff, value); 1675 return; 1676 1677 case 0x08: /* ARM_IDLECT2 */ 1678 diff = s->clkm.arm_idlect2 ^ value; 1679 s->clkm.arm_idlect2 = value & 0x07ff; 1680 omap_clkm_idlect2_update(s, diff, value); 1681 return; 1682 1683 case 0x0c: /* ARM_EWUPCT */ 1684 s->clkm.arm_ewupct = value & 0x003f; 1685 return; 1686 1687 case 0x10: /* ARM_RSTCT1 */ 1688 diff = s->clkm.arm_rstct1 ^ value; 1689 s->clkm.arm_rstct1 = value & 0x0007; 1690 if (value & 9) { 1691 qemu_system_reset_request(); 1692 s->clkm.cold_start = 0xa; 1693 } 1694 if (diff & ~value & 4) { /* DSP_RST */ 1695 omap_mpui_reset(s); 1696 omap_tipb_bridge_reset(s->private_tipb); 1697 omap_tipb_bridge_reset(s->public_tipb); 1698 } 1699 if (diff & 2) { /* DSP_EN */ 1700 clk = omap_findclk(s, "dsp_ck"); 1701 omap_clk_canidle(clk, (~value >> 1) & 1); 1702 } 1703 return; 1704 1705 case 0x14: /* ARM_RSTCT2 */ 1706 s->clkm.arm_rstct2 = value & 0x0001; 1707 return; 1708 1709 case 0x18: /* ARM_SYSST */ 1710 if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) { 1711 s->clkm.clocking_scheme = (value >> 11) & 7; 1712 printf("%s: clocking scheme set to %s\n", __FUNCTION__, 1713 clkschemename[s->clkm.clocking_scheme]); 1714 } 1715 s->clkm.cold_start &= value & 0x3f; 1716 return; 1717 1718 case 0x1c: /* ARM_CKOUT1 */ 1719 diff = s->clkm.arm_ckout1 ^ value; 1720 s->clkm.arm_ckout1 = value & 0x003f; 1721 omap_clkm_ckout1_update(s, diff, value); 1722 return; 1723 1724 case 0x20: /* ARM_CKOUT2 */ 1725 default: 1726 OMAP_BAD_REG(addr); 1727 } 1728 } 1729 1730 static const MemoryRegionOps omap_clkm_ops = { 1731 .read = omap_clkm_read, 1732 .write = omap_clkm_write, 1733 .endianness = DEVICE_NATIVE_ENDIAN, 1734 }; 1735 1736 static uint64_t omap_clkdsp_read(void *opaque, hwaddr addr, 1737 unsigned size) 1738 { 1739 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1740 CPUState *cpu = CPU(s->cpu); 1741 1742 if (size != 2) { 1743 return omap_badwidth_read16(opaque, addr); 1744 } 1745 1746 switch (addr) { 1747 case 0x04: /* DSP_IDLECT1 */ 1748 return s->clkm.dsp_idlect1; 1749 1750 case 0x08: /* DSP_IDLECT2 */ 1751 return s->clkm.dsp_idlect2; 1752 1753 case 0x14: /* DSP_RSTCT2 */ 1754 return s->clkm.dsp_rstct2; 1755 1756 case 0x18: /* DSP_SYSST */ 1757 cpu = CPU(s->cpu); 1758 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start | 1759 (cpu->halted << 6); /* Quite useless... */ 1760 } 1761 1762 OMAP_BAD_REG(addr); 1763 return 0; 1764 } 1765 1766 static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s, 1767 uint16_t diff, uint16_t value) 1768 { 1769 omap_clk clk; 1770 1771 SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */ 1772 } 1773 1774 static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s, 1775 uint16_t diff, uint16_t value) 1776 { 1777 omap_clk clk; 1778 1779 SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */ 1780 } 1781 1782 static void omap_clkdsp_write(void *opaque, hwaddr addr, 1783 uint64_t value, unsigned size) 1784 { 1785 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1786 uint16_t diff; 1787 1788 if (size != 2) { 1789 omap_badwidth_write16(opaque, addr, value); 1790 return; 1791 } 1792 1793 switch (addr) { 1794 case 0x04: /* DSP_IDLECT1 */ 1795 diff = s->clkm.dsp_idlect1 ^ value; 1796 s->clkm.dsp_idlect1 = value & 0x01f7; 1797 omap_clkdsp_idlect1_update(s, diff, value); 1798 break; 1799 1800 case 0x08: /* DSP_IDLECT2 */ 1801 s->clkm.dsp_idlect2 = value & 0x0037; 1802 diff = s->clkm.dsp_idlect1 ^ value; 1803 omap_clkdsp_idlect2_update(s, diff, value); 1804 break; 1805 1806 case 0x14: /* DSP_RSTCT2 */ 1807 s->clkm.dsp_rstct2 = value & 0x0001; 1808 break; 1809 1810 case 0x18: /* DSP_SYSST */ 1811 s->clkm.cold_start &= value & 0x3f; 1812 break; 1813 1814 default: 1815 OMAP_BAD_REG(addr); 1816 } 1817 } 1818 1819 static const MemoryRegionOps omap_clkdsp_ops = { 1820 .read = omap_clkdsp_read, 1821 .write = omap_clkdsp_write, 1822 .endianness = DEVICE_NATIVE_ENDIAN, 1823 }; 1824 1825 static void omap_clkm_reset(struct omap_mpu_state_s *s) 1826 { 1827 if (s->wdt && s->wdt->reset) 1828 s->clkm.cold_start = 0x6; 1829 s->clkm.clocking_scheme = 0; 1830 omap_clkm_ckctl_update(s, ~0, 0x3000); 1831 s->clkm.arm_ckctl = 0x3000; 1832 omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 ^ 0x0400, 0x0400); 1833 s->clkm.arm_idlect1 = 0x0400; 1834 omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 ^ 0x0100, 0x0100); 1835 s->clkm.arm_idlect2 = 0x0100; 1836 s->clkm.arm_ewupct = 0x003f; 1837 s->clkm.arm_rstct1 = 0x0000; 1838 s->clkm.arm_rstct2 = 0x0000; 1839 s->clkm.arm_ckout1 = 0x0015; 1840 s->clkm.dpll1_mode = 0x2002; 1841 omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040); 1842 s->clkm.dsp_idlect1 = 0x0040; 1843 omap_clkdsp_idlect2_update(s, ~0, 0x0000); 1844 s->clkm.dsp_idlect2 = 0x0000; 1845 s->clkm.dsp_rstct2 = 0x0000; 1846 } 1847 1848 static void omap_clkm_init(MemoryRegion *memory, hwaddr mpu_base, 1849 hwaddr dsp_base, struct omap_mpu_state_s *s) 1850 { 1851 memory_region_init_io(&s->clkm_iomem, NULL, &omap_clkm_ops, s, 1852 "omap-clkm", 0x100); 1853 memory_region_init_io(&s->clkdsp_iomem, NULL, &omap_clkdsp_ops, s, 1854 "omap-clkdsp", 0x1000); 1855 1856 s->clkm.arm_idlect1 = 0x03ff; 1857 s->clkm.arm_idlect2 = 0x0100; 1858 s->clkm.dsp_idlect1 = 0x0002; 1859 omap_clkm_reset(s); 1860 s->clkm.cold_start = 0x3a; 1861 1862 memory_region_add_subregion(memory, mpu_base, &s->clkm_iomem); 1863 memory_region_add_subregion(memory, dsp_base, &s->clkdsp_iomem); 1864 } 1865 1866 /* MPU I/O */ 1867 struct omap_mpuio_s { 1868 qemu_irq irq; 1869 qemu_irq kbd_irq; 1870 qemu_irq *in; 1871 qemu_irq handler[16]; 1872 qemu_irq wakeup; 1873 MemoryRegion iomem; 1874 1875 uint16_t inputs; 1876 uint16_t outputs; 1877 uint16_t dir; 1878 uint16_t edge; 1879 uint16_t mask; 1880 uint16_t ints; 1881 1882 uint16_t debounce; 1883 uint16_t latch; 1884 uint8_t event; 1885 1886 uint8_t buttons[5]; 1887 uint8_t row_latch; 1888 uint8_t cols; 1889 int kbd_mask; 1890 int clk; 1891 }; 1892 1893 static void omap_mpuio_set(void *opaque, int line, int level) 1894 { 1895 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; 1896 uint16_t prev = s->inputs; 1897 1898 if (level) 1899 s->inputs |= 1 << line; 1900 else 1901 s->inputs &= ~(1 << line); 1902 1903 if (((1 << line) & s->dir & ~s->mask) && s->clk) { 1904 if ((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) { 1905 s->ints |= 1 << line; 1906 qemu_irq_raise(s->irq); 1907 /* TODO: wakeup */ 1908 } 1909 if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */ 1910 (s->event >> 1) == line) /* PIN_SELECT */ 1911 s->latch = s->inputs; 1912 } 1913 } 1914 1915 static void omap_mpuio_kbd_update(struct omap_mpuio_s *s) 1916 { 1917 int i; 1918 uint8_t *row, rows = 0, cols = ~s->cols; 1919 1920 for (row = s->buttons + 4, i = 1 << 4; i; row --, i >>= 1) 1921 if (*row & cols) 1922 rows |= i; 1923 1924 qemu_set_irq(s->kbd_irq, rows && !s->kbd_mask && s->clk); 1925 s->row_latch = ~rows; 1926 } 1927 1928 static uint64_t omap_mpuio_read(void *opaque, hwaddr addr, 1929 unsigned size) 1930 { 1931 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; 1932 int offset = addr & OMAP_MPUI_REG_MASK; 1933 uint16_t ret; 1934 1935 if (size != 2) { 1936 return omap_badwidth_read16(opaque, addr); 1937 } 1938 1939 switch (offset) { 1940 case 0x00: /* INPUT_LATCH */ 1941 return s->inputs; 1942 1943 case 0x04: /* OUTPUT_REG */ 1944 return s->outputs; 1945 1946 case 0x08: /* IO_CNTL */ 1947 return s->dir; 1948 1949 case 0x10: /* KBR_LATCH */ 1950 return s->row_latch; 1951 1952 case 0x14: /* KBC_REG */ 1953 return s->cols; 1954 1955 case 0x18: /* GPIO_EVENT_MODE_REG */ 1956 return s->event; 1957 1958 case 0x1c: /* GPIO_INT_EDGE_REG */ 1959 return s->edge; 1960 1961 case 0x20: /* KBD_INT */ 1962 return (~s->row_latch & 0x1f) && !s->kbd_mask; 1963 1964 case 0x24: /* GPIO_INT */ 1965 ret = s->ints; 1966 s->ints &= s->mask; 1967 if (ret) 1968 qemu_irq_lower(s->irq); 1969 return ret; 1970 1971 case 0x28: /* KBD_MASKIT */ 1972 return s->kbd_mask; 1973 1974 case 0x2c: /* GPIO_MASKIT */ 1975 return s->mask; 1976 1977 case 0x30: /* GPIO_DEBOUNCING_REG */ 1978 return s->debounce; 1979 1980 case 0x34: /* GPIO_LATCH_REG */ 1981 return s->latch; 1982 } 1983 1984 OMAP_BAD_REG(addr); 1985 return 0; 1986 } 1987 1988 static void omap_mpuio_write(void *opaque, hwaddr addr, 1989 uint64_t value, unsigned size) 1990 { 1991 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; 1992 int offset = addr & OMAP_MPUI_REG_MASK; 1993 uint16_t diff; 1994 int ln; 1995 1996 if (size != 2) { 1997 omap_badwidth_write16(opaque, addr, value); 1998 return; 1999 } 2000 2001 switch (offset) { 2002 case 0x04: /* OUTPUT_REG */ 2003 diff = (s->outputs ^ value) & ~s->dir; 2004 s->outputs = value; 2005 while ((ln = ctz32(diff)) != 32) { 2006 if (s->handler[ln]) 2007 qemu_set_irq(s->handler[ln], (value >> ln) & 1); 2008 diff &= ~(1 << ln); 2009 } 2010 break; 2011 2012 case 0x08: /* IO_CNTL */ 2013 diff = s->outputs & (s->dir ^ value); 2014 s->dir = value; 2015 2016 value = s->outputs & ~s->dir; 2017 while ((ln = ctz32(diff)) != 32) { 2018 if (s->handler[ln]) 2019 qemu_set_irq(s->handler[ln], (value >> ln) & 1); 2020 diff &= ~(1 << ln); 2021 } 2022 break; 2023 2024 case 0x14: /* KBC_REG */ 2025 s->cols = value; 2026 omap_mpuio_kbd_update(s); 2027 break; 2028 2029 case 0x18: /* GPIO_EVENT_MODE_REG */ 2030 s->event = value & 0x1f; 2031 break; 2032 2033 case 0x1c: /* GPIO_INT_EDGE_REG */ 2034 s->edge = value; 2035 break; 2036 2037 case 0x28: /* KBD_MASKIT */ 2038 s->kbd_mask = value & 1; 2039 omap_mpuio_kbd_update(s); 2040 break; 2041 2042 case 0x2c: /* GPIO_MASKIT */ 2043 s->mask = value; 2044 break; 2045 2046 case 0x30: /* GPIO_DEBOUNCING_REG */ 2047 s->debounce = value & 0x1ff; 2048 break; 2049 2050 case 0x00: /* INPUT_LATCH */ 2051 case 0x10: /* KBR_LATCH */ 2052 case 0x20: /* KBD_INT */ 2053 case 0x24: /* GPIO_INT */ 2054 case 0x34: /* GPIO_LATCH_REG */ 2055 OMAP_RO_REG(addr); 2056 return; 2057 2058 default: 2059 OMAP_BAD_REG(addr); 2060 return; 2061 } 2062 } 2063 2064 static const MemoryRegionOps omap_mpuio_ops = { 2065 .read = omap_mpuio_read, 2066 .write = omap_mpuio_write, 2067 .endianness = DEVICE_NATIVE_ENDIAN, 2068 }; 2069 2070 static void omap_mpuio_reset(struct omap_mpuio_s *s) 2071 { 2072 s->inputs = 0; 2073 s->outputs = 0; 2074 s->dir = ~0; 2075 s->event = 0; 2076 s->edge = 0; 2077 s->kbd_mask = 0; 2078 s->mask = 0; 2079 s->debounce = 0; 2080 s->latch = 0; 2081 s->ints = 0; 2082 s->row_latch = 0x1f; 2083 s->clk = 1; 2084 } 2085 2086 static void omap_mpuio_onoff(void *opaque, int line, int on) 2087 { 2088 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; 2089 2090 s->clk = on; 2091 if (on) 2092 omap_mpuio_kbd_update(s); 2093 } 2094 2095 static struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *memory, 2096 hwaddr base, 2097 qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup, 2098 omap_clk clk) 2099 { 2100 struct omap_mpuio_s *s = g_new0(struct omap_mpuio_s, 1); 2101 2102 s->irq = gpio_int; 2103 s->kbd_irq = kbd_int; 2104 s->wakeup = wakeup; 2105 s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16); 2106 omap_mpuio_reset(s); 2107 2108 memory_region_init_io(&s->iomem, NULL, &omap_mpuio_ops, s, 2109 "omap-mpuio", 0x800); 2110 memory_region_add_subregion(memory, base, &s->iomem); 2111 2112 omap_clk_adduser(clk, qemu_allocate_irq(omap_mpuio_onoff, s, 0)); 2113 2114 return s; 2115 } 2116 2117 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s) 2118 { 2119 return s->in; 2120 } 2121 2122 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler) 2123 { 2124 if (line >= 16 || line < 0) 2125 hw_error("%s: No GPIO line %i\n", __FUNCTION__, line); 2126 s->handler[line] = handler; 2127 } 2128 2129 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down) 2130 { 2131 if (row >= 5 || row < 0) 2132 hw_error("%s: No key %i-%i\n", __FUNCTION__, col, row); 2133 2134 if (down) 2135 s->buttons[row] |= 1 << col; 2136 else 2137 s->buttons[row] &= ~(1 << col); 2138 2139 omap_mpuio_kbd_update(s); 2140 } 2141 2142 /* MicroWire Interface */ 2143 struct omap_uwire_s { 2144 MemoryRegion iomem; 2145 qemu_irq txirq; 2146 qemu_irq rxirq; 2147 qemu_irq txdrq; 2148 2149 uint16_t txbuf; 2150 uint16_t rxbuf; 2151 uint16_t control; 2152 uint16_t setup[5]; 2153 2154 uWireSlave *chip[4]; 2155 }; 2156 2157 static void omap_uwire_transfer_start(struct omap_uwire_s *s) 2158 { 2159 int chipselect = (s->control >> 10) & 3; /* INDEX */ 2160 uWireSlave *slave = s->chip[chipselect]; 2161 2162 if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */ 2163 if (s->control & (1 << 12)) /* CS_CMD */ 2164 if (slave && slave->send) 2165 slave->send(slave->opaque, 2166 s->txbuf >> (16 - ((s->control >> 5) & 0x1f))); 2167 s->control &= ~(1 << 14); /* CSRB */ 2168 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or 2169 * a DRQ. When is the level IRQ supposed to be reset? */ 2170 } 2171 2172 if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */ 2173 if (s->control & (1 << 12)) /* CS_CMD */ 2174 if (slave && slave->receive) 2175 s->rxbuf = slave->receive(slave->opaque); 2176 s->control |= 1 << 15; /* RDRB */ 2177 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or 2178 * a DRQ. When is the level IRQ supposed to be reset? */ 2179 } 2180 } 2181 2182 static uint64_t omap_uwire_read(void *opaque, hwaddr addr, 2183 unsigned size) 2184 { 2185 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; 2186 int offset = addr & OMAP_MPUI_REG_MASK; 2187 2188 if (size != 2) { 2189 return omap_badwidth_read16(opaque, addr); 2190 } 2191 2192 switch (offset) { 2193 case 0x00: /* RDR */ 2194 s->control &= ~(1 << 15); /* RDRB */ 2195 return s->rxbuf; 2196 2197 case 0x04: /* CSR */ 2198 return s->control; 2199 2200 case 0x08: /* SR1 */ 2201 return s->setup[0]; 2202 case 0x0c: /* SR2 */ 2203 return s->setup[1]; 2204 case 0x10: /* SR3 */ 2205 return s->setup[2]; 2206 case 0x14: /* SR4 */ 2207 return s->setup[3]; 2208 case 0x18: /* SR5 */ 2209 return s->setup[4]; 2210 } 2211 2212 OMAP_BAD_REG(addr); 2213 return 0; 2214 } 2215 2216 static void omap_uwire_write(void *opaque, hwaddr addr, 2217 uint64_t value, unsigned size) 2218 { 2219 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; 2220 int offset = addr & OMAP_MPUI_REG_MASK; 2221 2222 if (size != 2) { 2223 omap_badwidth_write16(opaque, addr, value); 2224 return; 2225 } 2226 2227 switch (offset) { 2228 case 0x00: /* TDR */ 2229 s->txbuf = value; /* TD */ 2230 if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */ 2231 ((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */ 2232 (s->control & (1 << 12)))) { /* CS_CMD */ 2233 s->control |= 1 << 14; /* CSRB */ 2234 omap_uwire_transfer_start(s); 2235 } 2236 break; 2237 2238 case 0x04: /* CSR */ 2239 s->control = value & 0x1fff; 2240 if (value & (1 << 13)) /* START */ 2241 omap_uwire_transfer_start(s); 2242 break; 2243 2244 case 0x08: /* SR1 */ 2245 s->setup[0] = value & 0x003f; 2246 break; 2247 2248 case 0x0c: /* SR2 */ 2249 s->setup[1] = value & 0x0fc0; 2250 break; 2251 2252 case 0x10: /* SR3 */ 2253 s->setup[2] = value & 0x0003; 2254 break; 2255 2256 case 0x14: /* SR4 */ 2257 s->setup[3] = value & 0x0001; 2258 break; 2259 2260 case 0x18: /* SR5 */ 2261 s->setup[4] = value & 0x000f; 2262 break; 2263 2264 default: 2265 OMAP_BAD_REG(addr); 2266 return; 2267 } 2268 } 2269 2270 static const MemoryRegionOps omap_uwire_ops = { 2271 .read = omap_uwire_read, 2272 .write = omap_uwire_write, 2273 .endianness = DEVICE_NATIVE_ENDIAN, 2274 }; 2275 2276 static void omap_uwire_reset(struct omap_uwire_s *s) 2277 { 2278 s->control = 0; 2279 s->setup[0] = 0; 2280 s->setup[1] = 0; 2281 s->setup[2] = 0; 2282 s->setup[3] = 0; 2283 s->setup[4] = 0; 2284 } 2285 2286 static struct omap_uwire_s *omap_uwire_init(MemoryRegion *system_memory, 2287 hwaddr base, 2288 qemu_irq txirq, qemu_irq rxirq, 2289 qemu_irq dma, 2290 omap_clk clk) 2291 { 2292 struct omap_uwire_s *s = g_new0(struct omap_uwire_s, 1); 2293 2294 s->txirq = txirq; 2295 s->rxirq = rxirq; 2296 s->txdrq = dma; 2297 omap_uwire_reset(s); 2298 2299 memory_region_init_io(&s->iomem, NULL, &omap_uwire_ops, s, "omap-uwire", 0x800); 2300 memory_region_add_subregion(system_memory, base, &s->iomem); 2301 2302 return s; 2303 } 2304 2305 void omap_uwire_attach(struct omap_uwire_s *s, 2306 uWireSlave *slave, int chipselect) 2307 { 2308 if (chipselect < 0 || chipselect > 3) { 2309 fprintf(stderr, "%s: Bad chipselect %i\n", __FUNCTION__, chipselect); 2310 exit(-1); 2311 } 2312 2313 s->chip[chipselect] = slave; 2314 } 2315 2316 /* Pseudonoise Pulse-Width Light Modulator */ 2317 struct omap_pwl_s { 2318 MemoryRegion iomem; 2319 uint8_t output; 2320 uint8_t level; 2321 uint8_t enable; 2322 int clk; 2323 }; 2324 2325 static void omap_pwl_update(struct omap_pwl_s *s) 2326 { 2327 int output = (s->clk && s->enable) ? s->level : 0; 2328 2329 if (output != s->output) { 2330 s->output = output; 2331 printf("%s: Backlight now at %i/256\n", __FUNCTION__, output); 2332 } 2333 } 2334 2335 static uint64_t omap_pwl_read(void *opaque, hwaddr addr, 2336 unsigned size) 2337 { 2338 struct omap_pwl_s *s = (struct omap_pwl_s *) opaque; 2339 int offset = addr & OMAP_MPUI_REG_MASK; 2340 2341 if (size != 1) { 2342 return omap_badwidth_read8(opaque, addr); 2343 } 2344 2345 switch (offset) { 2346 case 0x00: /* PWL_LEVEL */ 2347 return s->level; 2348 case 0x04: /* PWL_CTRL */ 2349 return s->enable; 2350 } 2351 OMAP_BAD_REG(addr); 2352 return 0; 2353 } 2354 2355 static void omap_pwl_write(void *opaque, hwaddr addr, 2356 uint64_t value, unsigned size) 2357 { 2358 struct omap_pwl_s *s = (struct omap_pwl_s *) opaque; 2359 int offset = addr & OMAP_MPUI_REG_MASK; 2360 2361 if (size != 1) { 2362 omap_badwidth_write8(opaque, addr, value); 2363 return; 2364 } 2365 2366 switch (offset) { 2367 case 0x00: /* PWL_LEVEL */ 2368 s->level = value; 2369 omap_pwl_update(s); 2370 break; 2371 case 0x04: /* PWL_CTRL */ 2372 s->enable = value & 1; 2373 omap_pwl_update(s); 2374 break; 2375 default: 2376 OMAP_BAD_REG(addr); 2377 return; 2378 } 2379 } 2380 2381 static const MemoryRegionOps omap_pwl_ops = { 2382 .read = omap_pwl_read, 2383 .write = omap_pwl_write, 2384 .endianness = DEVICE_NATIVE_ENDIAN, 2385 }; 2386 2387 static void omap_pwl_reset(struct omap_pwl_s *s) 2388 { 2389 s->output = 0; 2390 s->level = 0; 2391 s->enable = 0; 2392 s->clk = 1; 2393 omap_pwl_update(s); 2394 } 2395 2396 static void omap_pwl_clk_update(void *opaque, int line, int on) 2397 { 2398 struct omap_pwl_s *s = (struct omap_pwl_s *) opaque; 2399 2400 s->clk = on; 2401 omap_pwl_update(s); 2402 } 2403 2404 static struct omap_pwl_s *omap_pwl_init(MemoryRegion *system_memory, 2405 hwaddr base, 2406 omap_clk clk) 2407 { 2408 struct omap_pwl_s *s = g_malloc0(sizeof(*s)); 2409 2410 omap_pwl_reset(s); 2411 2412 memory_region_init_io(&s->iomem, NULL, &omap_pwl_ops, s, 2413 "omap-pwl", 0x800); 2414 memory_region_add_subregion(system_memory, base, &s->iomem); 2415 2416 omap_clk_adduser(clk, qemu_allocate_irq(omap_pwl_clk_update, s, 0)); 2417 return s; 2418 } 2419 2420 /* Pulse-Width Tone module */ 2421 struct omap_pwt_s { 2422 MemoryRegion iomem; 2423 uint8_t frc; 2424 uint8_t vrc; 2425 uint8_t gcr; 2426 omap_clk clk; 2427 }; 2428 2429 static uint64_t omap_pwt_read(void *opaque, hwaddr addr, 2430 unsigned size) 2431 { 2432 struct omap_pwt_s *s = (struct omap_pwt_s *) opaque; 2433 int offset = addr & OMAP_MPUI_REG_MASK; 2434 2435 if (size != 1) { 2436 return omap_badwidth_read8(opaque, addr); 2437 } 2438 2439 switch (offset) { 2440 case 0x00: /* FRC */ 2441 return s->frc; 2442 case 0x04: /* VCR */ 2443 return s->vrc; 2444 case 0x08: /* GCR */ 2445 return s->gcr; 2446 } 2447 OMAP_BAD_REG(addr); 2448 return 0; 2449 } 2450 2451 static void omap_pwt_write(void *opaque, hwaddr addr, 2452 uint64_t value, unsigned size) 2453 { 2454 struct omap_pwt_s *s = (struct omap_pwt_s *) opaque; 2455 int offset = addr & OMAP_MPUI_REG_MASK; 2456 2457 if (size != 1) { 2458 omap_badwidth_write8(opaque, addr, value); 2459 return; 2460 } 2461 2462 switch (offset) { 2463 case 0x00: /* FRC */ 2464 s->frc = value & 0x3f; 2465 break; 2466 case 0x04: /* VRC */ 2467 if ((value ^ s->vrc) & 1) { 2468 if (value & 1) 2469 printf("%s: %iHz buzz on\n", __FUNCTION__, (int) 2470 /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */ 2471 ((omap_clk_getrate(s->clk) >> 3) / 2472 /* Pre-multiplexer divider */ 2473 ((s->gcr & 2) ? 1 : 154) / 2474 /* Octave multiplexer */ 2475 (2 << (value & 3)) * 2476 /* 101/107 divider */ 2477 ((value & (1 << 2)) ? 101 : 107) * 2478 /* 49/55 divider */ 2479 ((value & (1 << 3)) ? 49 : 55) * 2480 /* 50/63 divider */ 2481 ((value & (1 << 4)) ? 50 : 63) * 2482 /* 80/127 divider */ 2483 ((value & (1 << 5)) ? 80 : 127) / 2484 (107 * 55 * 63 * 127))); 2485 else 2486 printf("%s: silence!\n", __FUNCTION__); 2487 } 2488 s->vrc = value & 0x7f; 2489 break; 2490 case 0x08: /* GCR */ 2491 s->gcr = value & 3; 2492 break; 2493 default: 2494 OMAP_BAD_REG(addr); 2495 return; 2496 } 2497 } 2498 2499 static const MemoryRegionOps omap_pwt_ops = { 2500 .read =omap_pwt_read, 2501 .write = omap_pwt_write, 2502 .endianness = DEVICE_NATIVE_ENDIAN, 2503 }; 2504 2505 static void omap_pwt_reset(struct omap_pwt_s *s) 2506 { 2507 s->frc = 0; 2508 s->vrc = 0; 2509 s->gcr = 0; 2510 } 2511 2512 static struct omap_pwt_s *omap_pwt_init(MemoryRegion *system_memory, 2513 hwaddr base, 2514 omap_clk clk) 2515 { 2516 struct omap_pwt_s *s = g_malloc0(sizeof(*s)); 2517 s->clk = clk; 2518 omap_pwt_reset(s); 2519 2520 memory_region_init_io(&s->iomem, NULL, &omap_pwt_ops, s, 2521 "omap-pwt", 0x800); 2522 memory_region_add_subregion(system_memory, base, &s->iomem); 2523 return s; 2524 } 2525 2526 /* Real-time Clock module */ 2527 struct omap_rtc_s { 2528 MemoryRegion iomem; 2529 qemu_irq irq; 2530 qemu_irq alarm; 2531 QEMUTimer *clk; 2532 2533 uint8_t interrupts; 2534 uint8_t status; 2535 int16_t comp_reg; 2536 int running; 2537 int pm_am; 2538 int auto_comp; 2539 int round; 2540 struct tm alarm_tm; 2541 time_t alarm_ti; 2542 2543 struct tm current_tm; 2544 time_t ti; 2545 uint64_t tick; 2546 }; 2547 2548 static void omap_rtc_interrupts_update(struct omap_rtc_s *s) 2549 { 2550 /* s->alarm is level-triggered */ 2551 qemu_set_irq(s->alarm, (s->status >> 6) & 1); 2552 } 2553 2554 static void omap_rtc_alarm_update(struct omap_rtc_s *s) 2555 { 2556 s->alarm_ti = mktimegm(&s->alarm_tm); 2557 if (s->alarm_ti == -1) 2558 printf("%s: conversion failed\n", __FUNCTION__); 2559 } 2560 2561 static uint64_t omap_rtc_read(void *opaque, hwaddr addr, 2562 unsigned size) 2563 { 2564 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; 2565 int offset = addr & OMAP_MPUI_REG_MASK; 2566 uint8_t i; 2567 2568 if (size != 1) { 2569 return omap_badwidth_read8(opaque, addr); 2570 } 2571 2572 switch (offset) { 2573 case 0x00: /* SECONDS_REG */ 2574 return to_bcd(s->current_tm.tm_sec); 2575 2576 case 0x04: /* MINUTES_REG */ 2577 return to_bcd(s->current_tm.tm_min); 2578 2579 case 0x08: /* HOURS_REG */ 2580 if (s->pm_am) 2581 return ((s->current_tm.tm_hour > 11) << 7) | 2582 to_bcd(((s->current_tm.tm_hour - 1) % 12) + 1); 2583 else 2584 return to_bcd(s->current_tm.tm_hour); 2585 2586 case 0x0c: /* DAYS_REG */ 2587 return to_bcd(s->current_tm.tm_mday); 2588 2589 case 0x10: /* MONTHS_REG */ 2590 return to_bcd(s->current_tm.tm_mon + 1); 2591 2592 case 0x14: /* YEARS_REG */ 2593 return to_bcd(s->current_tm.tm_year % 100); 2594 2595 case 0x18: /* WEEK_REG */ 2596 return s->current_tm.tm_wday; 2597 2598 case 0x20: /* ALARM_SECONDS_REG */ 2599 return to_bcd(s->alarm_tm.tm_sec); 2600 2601 case 0x24: /* ALARM_MINUTES_REG */ 2602 return to_bcd(s->alarm_tm.tm_min); 2603 2604 case 0x28: /* ALARM_HOURS_REG */ 2605 if (s->pm_am) 2606 return ((s->alarm_tm.tm_hour > 11) << 7) | 2607 to_bcd(((s->alarm_tm.tm_hour - 1) % 12) + 1); 2608 else 2609 return to_bcd(s->alarm_tm.tm_hour); 2610 2611 case 0x2c: /* ALARM_DAYS_REG */ 2612 return to_bcd(s->alarm_tm.tm_mday); 2613 2614 case 0x30: /* ALARM_MONTHS_REG */ 2615 return to_bcd(s->alarm_tm.tm_mon + 1); 2616 2617 case 0x34: /* ALARM_YEARS_REG */ 2618 return to_bcd(s->alarm_tm.tm_year % 100); 2619 2620 case 0x40: /* RTC_CTRL_REG */ 2621 return (s->pm_am << 3) | (s->auto_comp << 2) | 2622 (s->round << 1) | s->running; 2623 2624 case 0x44: /* RTC_STATUS_REG */ 2625 i = s->status; 2626 s->status &= ~0x3d; 2627 return i; 2628 2629 case 0x48: /* RTC_INTERRUPTS_REG */ 2630 return s->interrupts; 2631 2632 case 0x4c: /* RTC_COMP_LSB_REG */ 2633 return ((uint16_t) s->comp_reg) & 0xff; 2634 2635 case 0x50: /* RTC_COMP_MSB_REG */ 2636 return ((uint16_t) s->comp_reg) >> 8; 2637 } 2638 2639 OMAP_BAD_REG(addr); 2640 return 0; 2641 } 2642 2643 static void omap_rtc_write(void *opaque, hwaddr addr, 2644 uint64_t value, unsigned size) 2645 { 2646 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; 2647 int offset = addr & OMAP_MPUI_REG_MASK; 2648 struct tm new_tm; 2649 time_t ti[2]; 2650 2651 if (size != 1) { 2652 omap_badwidth_write8(opaque, addr, value); 2653 return; 2654 } 2655 2656 switch (offset) { 2657 case 0x00: /* SECONDS_REG */ 2658 #ifdef ALMDEBUG 2659 printf("RTC SEC_REG <-- %02x\n", value); 2660 #endif 2661 s->ti -= s->current_tm.tm_sec; 2662 s->ti += from_bcd(value); 2663 return; 2664 2665 case 0x04: /* MINUTES_REG */ 2666 #ifdef ALMDEBUG 2667 printf("RTC MIN_REG <-- %02x\n", value); 2668 #endif 2669 s->ti -= s->current_tm.tm_min * 60; 2670 s->ti += from_bcd(value) * 60; 2671 return; 2672 2673 case 0x08: /* HOURS_REG */ 2674 #ifdef ALMDEBUG 2675 printf("RTC HRS_REG <-- %02x\n", value); 2676 #endif 2677 s->ti -= s->current_tm.tm_hour * 3600; 2678 if (s->pm_am) { 2679 s->ti += (from_bcd(value & 0x3f) & 12) * 3600; 2680 s->ti += ((value >> 7) & 1) * 43200; 2681 } else 2682 s->ti += from_bcd(value & 0x3f) * 3600; 2683 return; 2684 2685 case 0x0c: /* DAYS_REG */ 2686 #ifdef ALMDEBUG 2687 printf("RTC DAY_REG <-- %02x\n", value); 2688 #endif 2689 s->ti -= s->current_tm.tm_mday * 86400; 2690 s->ti += from_bcd(value) * 86400; 2691 return; 2692 2693 case 0x10: /* MONTHS_REG */ 2694 #ifdef ALMDEBUG 2695 printf("RTC MTH_REG <-- %02x\n", value); 2696 #endif 2697 memcpy(&new_tm, &s->current_tm, sizeof(new_tm)); 2698 new_tm.tm_mon = from_bcd(value); 2699 ti[0] = mktimegm(&s->current_tm); 2700 ti[1] = mktimegm(&new_tm); 2701 2702 if (ti[0] != -1 && ti[1] != -1) { 2703 s->ti -= ti[0]; 2704 s->ti += ti[1]; 2705 } else { 2706 /* A less accurate version */ 2707 s->ti -= s->current_tm.tm_mon * 2592000; 2708 s->ti += from_bcd(value) * 2592000; 2709 } 2710 return; 2711 2712 case 0x14: /* YEARS_REG */ 2713 #ifdef ALMDEBUG 2714 printf("RTC YRS_REG <-- %02x\n", value); 2715 #endif 2716 memcpy(&new_tm, &s->current_tm, sizeof(new_tm)); 2717 new_tm.tm_year += from_bcd(value) - (new_tm.tm_year % 100); 2718 ti[0] = mktimegm(&s->current_tm); 2719 ti[1] = mktimegm(&new_tm); 2720 2721 if (ti[0] != -1 && ti[1] != -1) { 2722 s->ti -= ti[0]; 2723 s->ti += ti[1]; 2724 } else { 2725 /* A less accurate version */ 2726 s->ti -= (time_t)(s->current_tm.tm_year % 100) * 31536000; 2727 s->ti += (time_t)from_bcd(value) * 31536000; 2728 } 2729 return; 2730 2731 case 0x18: /* WEEK_REG */ 2732 return; /* Ignored */ 2733 2734 case 0x20: /* ALARM_SECONDS_REG */ 2735 #ifdef ALMDEBUG 2736 printf("ALM SEC_REG <-- %02x\n", value); 2737 #endif 2738 s->alarm_tm.tm_sec = from_bcd(value); 2739 omap_rtc_alarm_update(s); 2740 return; 2741 2742 case 0x24: /* ALARM_MINUTES_REG */ 2743 #ifdef ALMDEBUG 2744 printf("ALM MIN_REG <-- %02x\n", value); 2745 #endif 2746 s->alarm_tm.tm_min = from_bcd(value); 2747 omap_rtc_alarm_update(s); 2748 return; 2749 2750 case 0x28: /* ALARM_HOURS_REG */ 2751 #ifdef ALMDEBUG 2752 printf("ALM HRS_REG <-- %02x\n", value); 2753 #endif 2754 if (s->pm_am) 2755 s->alarm_tm.tm_hour = 2756 ((from_bcd(value & 0x3f)) % 12) + 2757 ((value >> 7) & 1) * 12; 2758 else 2759 s->alarm_tm.tm_hour = from_bcd(value); 2760 omap_rtc_alarm_update(s); 2761 return; 2762 2763 case 0x2c: /* ALARM_DAYS_REG */ 2764 #ifdef ALMDEBUG 2765 printf("ALM DAY_REG <-- %02x\n", value); 2766 #endif 2767 s->alarm_tm.tm_mday = from_bcd(value); 2768 omap_rtc_alarm_update(s); 2769 return; 2770 2771 case 0x30: /* ALARM_MONTHS_REG */ 2772 #ifdef ALMDEBUG 2773 printf("ALM MON_REG <-- %02x\n", value); 2774 #endif 2775 s->alarm_tm.tm_mon = from_bcd(value); 2776 omap_rtc_alarm_update(s); 2777 return; 2778 2779 case 0x34: /* ALARM_YEARS_REG */ 2780 #ifdef ALMDEBUG 2781 printf("ALM YRS_REG <-- %02x\n", value); 2782 #endif 2783 s->alarm_tm.tm_year = from_bcd(value); 2784 omap_rtc_alarm_update(s); 2785 return; 2786 2787 case 0x40: /* RTC_CTRL_REG */ 2788 #ifdef ALMDEBUG 2789 printf("RTC CONTROL <-- %02x\n", value); 2790 #endif 2791 s->pm_am = (value >> 3) & 1; 2792 s->auto_comp = (value >> 2) & 1; 2793 s->round = (value >> 1) & 1; 2794 s->running = value & 1; 2795 s->status &= 0xfd; 2796 s->status |= s->running << 1; 2797 return; 2798 2799 case 0x44: /* RTC_STATUS_REG */ 2800 #ifdef ALMDEBUG 2801 printf("RTC STATUSL <-- %02x\n", value); 2802 #endif 2803 s->status &= ~((value & 0xc0) ^ 0x80); 2804 omap_rtc_interrupts_update(s); 2805 return; 2806 2807 case 0x48: /* RTC_INTERRUPTS_REG */ 2808 #ifdef ALMDEBUG 2809 printf("RTC INTRS <-- %02x\n", value); 2810 #endif 2811 s->interrupts = value; 2812 return; 2813 2814 case 0x4c: /* RTC_COMP_LSB_REG */ 2815 #ifdef ALMDEBUG 2816 printf("RTC COMPLSB <-- %02x\n", value); 2817 #endif 2818 s->comp_reg &= 0xff00; 2819 s->comp_reg |= 0x00ff & value; 2820 return; 2821 2822 case 0x50: /* RTC_COMP_MSB_REG */ 2823 #ifdef ALMDEBUG 2824 printf("RTC COMPMSB <-- %02x\n", value); 2825 #endif 2826 s->comp_reg &= 0x00ff; 2827 s->comp_reg |= 0xff00 & (value << 8); 2828 return; 2829 2830 default: 2831 OMAP_BAD_REG(addr); 2832 return; 2833 } 2834 } 2835 2836 static const MemoryRegionOps omap_rtc_ops = { 2837 .read = omap_rtc_read, 2838 .write = omap_rtc_write, 2839 .endianness = DEVICE_NATIVE_ENDIAN, 2840 }; 2841 2842 static void omap_rtc_tick(void *opaque) 2843 { 2844 struct omap_rtc_s *s = opaque; 2845 2846 if (s->round) { 2847 /* Round to nearest full minute. */ 2848 if (s->current_tm.tm_sec < 30) 2849 s->ti -= s->current_tm.tm_sec; 2850 else 2851 s->ti += 60 - s->current_tm.tm_sec; 2852 2853 s->round = 0; 2854 } 2855 2856 localtime_r(&s->ti, &s->current_tm); 2857 2858 if ((s->interrupts & 0x08) && s->ti == s->alarm_ti) { 2859 s->status |= 0x40; 2860 omap_rtc_interrupts_update(s); 2861 } 2862 2863 if (s->interrupts & 0x04) 2864 switch (s->interrupts & 3) { 2865 case 0: 2866 s->status |= 0x04; 2867 qemu_irq_pulse(s->irq); 2868 break; 2869 case 1: 2870 if (s->current_tm.tm_sec) 2871 break; 2872 s->status |= 0x08; 2873 qemu_irq_pulse(s->irq); 2874 break; 2875 case 2: 2876 if (s->current_tm.tm_sec || s->current_tm.tm_min) 2877 break; 2878 s->status |= 0x10; 2879 qemu_irq_pulse(s->irq); 2880 break; 2881 case 3: 2882 if (s->current_tm.tm_sec || 2883 s->current_tm.tm_min || s->current_tm.tm_hour) 2884 break; 2885 s->status |= 0x20; 2886 qemu_irq_pulse(s->irq); 2887 break; 2888 } 2889 2890 /* Move on */ 2891 if (s->running) 2892 s->ti ++; 2893 s->tick += 1000; 2894 2895 /* 2896 * Every full hour add a rough approximation of the compensation 2897 * register to the 32kHz Timer (which drives the RTC) value. 2898 */ 2899 if (s->auto_comp && !s->current_tm.tm_sec && !s->current_tm.tm_min) 2900 s->tick += s->comp_reg * 1000 / 32768; 2901 2902 timer_mod(s->clk, s->tick); 2903 } 2904 2905 static void omap_rtc_reset(struct omap_rtc_s *s) 2906 { 2907 struct tm tm; 2908 2909 s->interrupts = 0; 2910 s->comp_reg = 0; 2911 s->running = 0; 2912 s->pm_am = 0; 2913 s->auto_comp = 0; 2914 s->round = 0; 2915 s->tick = qemu_clock_get_ms(rtc_clock); 2916 memset(&s->alarm_tm, 0, sizeof(s->alarm_tm)); 2917 s->alarm_tm.tm_mday = 0x01; 2918 s->status = 1 << 7; 2919 qemu_get_timedate(&tm, 0); 2920 s->ti = mktimegm(&tm); 2921 2922 omap_rtc_alarm_update(s); 2923 omap_rtc_tick(s); 2924 } 2925 2926 static struct omap_rtc_s *omap_rtc_init(MemoryRegion *system_memory, 2927 hwaddr base, 2928 qemu_irq timerirq, qemu_irq alarmirq, 2929 omap_clk clk) 2930 { 2931 struct omap_rtc_s *s = g_new0(struct omap_rtc_s, 1); 2932 2933 s->irq = timerirq; 2934 s->alarm = alarmirq; 2935 s->clk = timer_new_ms(rtc_clock, omap_rtc_tick, s); 2936 2937 omap_rtc_reset(s); 2938 2939 memory_region_init_io(&s->iomem, NULL, &omap_rtc_ops, s, 2940 "omap-rtc", 0x800); 2941 memory_region_add_subregion(system_memory, base, &s->iomem); 2942 2943 return s; 2944 } 2945 2946 /* Multi-channel Buffered Serial Port interfaces */ 2947 struct omap_mcbsp_s { 2948 MemoryRegion iomem; 2949 qemu_irq txirq; 2950 qemu_irq rxirq; 2951 qemu_irq txdrq; 2952 qemu_irq rxdrq; 2953 2954 uint16_t spcr[2]; 2955 uint16_t rcr[2]; 2956 uint16_t xcr[2]; 2957 uint16_t srgr[2]; 2958 uint16_t mcr[2]; 2959 uint16_t pcr; 2960 uint16_t rcer[8]; 2961 uint16_t xcer[8]; 2962 int tx_rate; 2963 int rx_rate; 2964 int tx_req; 2965 int rx_req; 2966 2967 I2SCodec *codec; 2968 QEMUTimer *source_timer; 2969 QEMUTimer *sink_timer; 2970 }; 2971 2972 static void omap_mcbsp_intr_update(struct omap_mcbsp_s *s) 2973 { 2974 int irq; 2975 2976 switch ((s->spcr[0] >> 4) & 3) { /* RINTM */ 2977 case 0: 2978 irq = (s->spcr[0] >> 1) & 1; /* RRDY */ 2979 break; 2980 case 3: 2981 irq = (s->spcr[0] >> 3) & 1; /* RSYNCERR */ 2982 break; 2983 default: 2984 irq = 0; 2985 break; 2986 } 2987 2988 if (irq) 2989 qemu_irq_pulse(s->rxirq); 2990 2991 switch ((s->spcr[1] >> 4) & 3) { /* XINTM */ 2992 case 0: 2993 irq = (s->spcr[1] >> 1) & 1; /* XRDY */ 2994 break; 2995 case 3: 2996 irq = (s->spcr[1] >> 3) & 1; /* XSYNCERR */ 2997 break; 2998 default: 2999 irq = 0; 3000 break; 3001 } 3002 3003 if (irq) 3004 qemu_irq_pulse(s->txirq); 3005 } 3006 3007 static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s) 3008 { 3009 if ((s->spcr[0] >> 1) & 1) /* RRDY */ 3010 s->spcr[0] |= 1 << 2; /* RFULL */ 3011 s->spcr[0] |= 1 << 1; /* RRDY */ 3012 qemu_irq_raise(s->rxdrq); 3013 omap_mcbsp_intr_update(s); 3014 } 3015 3016 static void omap_mcbsp_source_tick(void *opaque) 3017 { 3018 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3019 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 }; 3020 3021 if (!s->rx_rate) 3022 return; 3023 if (s->rx_req) 3024 printf("%s: Rx FIFO overrun\n", __FUNCTION__); 3025 3026 s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7]; 3027 3028 omap_mcbsp_rx_newdata(s); 3029 timer_mod(s->source_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 3030 get_ticks_per_sec()); 3031 } 3032 3033 static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s) 3034 { 3035 if (!s->codec || !s->codec->rts) 3036 omap_mcbsp_source_tick(s); 3037 else if (s->codec->in.len) { 3038 s->rx_req = s->codec->in.len; 3039 omap_mcbsp_rx_newdata(s); 3040 } 3041 } 3042 3043 static void omap_mcbsp_rx_stop(struct omap_mcbsp_s *s) 3044 { 3045 timer_del(s->source_timer); 3046 } 3047 3048 static void omap_mcbsp_rx_done(struct omap_mcbsp_s *s) 3049 { 3050 s->spcr[0] &= ~(1 << 1); /* RRDY */ 3051 qemu_irq_lower(s->rxdrq); 3052 omap_mcbsp_intr_update(s); 3053 } 3054 3055 static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s) 3056 { 3057 s->spcr[1] |= 1 << 1; /* XRDY */ 3058 qemu_irq_raise(s->txdrq); 3059 omap_mcbsp_intr_update(s); 3060 } 3061 3062 static void omap_mcbsp_sink_tick(void *opaque) 3063 { 3064 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3065 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 }; 3066 3067 if (!s->tx_rate) 3068 return; 3069 if (s->tx_req) 3070 printf("%s: Tx FIFO underrun\n", __FUNCTION__); 3071 3072 s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7]; 3073 3074 omap_mcbsp_tx_newdata(s); 3075 timer_mod(s->sink_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 3076 get_ticks_per_sec()); 3077 } 3078 3079 static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s) 3080 { 3081 if (!s->codec || !s->codec->cts) 3082 omap_mcbsp_sink_tick(s); 3083 else if (s->codec->out.size) { 3084 s->tx_req = s->codec->out.size; 3085 omap_mcbsp_tx_newdata(s); 3086 } 3087 } 3088 3089 static void omap_mcbsp_tx_done(struct omap_mcbsp_s *s) 3090 { 3091 s->spcr[1] &= ~(1 << 1); /* XRDY */ 3092 qemu_irq_lower(s->txdrq); 3093 omap_mcbsp_intr_update(s); 3094 if (s->codec && s->codec->cts) 3095 s->codec->tx_swallow(s->codec->opaque); 3096 } 3097 3098 static void omap_mcbsp_tx_stop(struct omap_mcbsp_s *s) 3099 { 3100 s->tx_req = 0; 3101 omap_mcbsp_tx_done(s); 3102 timer_del(s->sink_timer); 3103 } 3104 3105 static void omap_mcbsp_req_update(struct omap_mcbsp_s *s) 3106 { 3107 int prev_rx_rate, prev_tx_rate; 3108 int rx_rate = 0, tx_rate = 0; 3109 int cpu_rate = 1500000; /* XXX */ 3110 3111 /* TODO: check CLKSTP bit */ 3112 if (s->spcr[1] & (1 << 6)) { /* GRST */ 3113 if (s->spcr[0] & (1 << 0)) { /* RRST */ 3114 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ 3115 (s->pcr & (1 << 8))) { /* CLKRM */ 3116 if (~s->pcr & (1 << 7)) /* SCLKME */ 3117 rx_rate = cpu_rate / 3118 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ 3119 } else 3120 if (s->codec) 3121 rx_rate = s->codec->rx_rate; 3122 } 3123 3124 if (s->spcr[1] & (1 << 0)) { /* XRST */ 3125 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ 3126 (s->pcr & (1 << 9))) { /* CLKXM */ 3127 if (~s->pcr & (1 << 7)) /* SCLKME */ 3128 tx_rate = cpu_rate / 3129 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ 3130 } else 3131 if (s->codec) 3132 tx_rate = s->codec->tx_rate; 3133 } 3134 } 3135 prev_tx_rate = s->tx_rate; 3136 prev_rx_rate = s->rx_rate; 3137 s->tx_rate = tx_rate; 3138 s->rx_rate = rx_rate; 3139 3140 if (s->codec) 3141 s->codec->set_rate(s->codec->opaque, rx_rate, tx_rate); 3142 3143 if (!prev_tx_rate && tx_rate) 3144 omap_mcbsp_tx_start(s); 3145 else if (s->tx_rate && !tx_rate) 3146 omap_mcbsp_tx_stop(s); 3147 3148 if (!prev_rx_rate && rx_rate) 3149 omap_mcbsp_rx_start(s); 3150 else if (prev_tx_rate && !tx_rate) 3151 omap_mcbsp_rx_stop(s); 3152 } 3153 3154 static uint64_t omap_mcbsp_read(void *opaque, hwaddr addr, 3155 unsigned size) 3156 { 3157 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3158 int offset = addr & OMAP_MPUI_REG_MASK; 3159 uint16_t ret; 3160 3161 if (size != 2) { 3162 return omap_badwidth_read16(opaque, addr); 3163 } 3164 3165 switch (offset) { 3166 case 0x00: /* DRR2 */ 3167 if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */ 3168 return 0x0000; 3169 /* Fall through. */ 3170 case 0x02: /* DRR1 */ 3171 if (s->rx_req < 2) { 3172 printf("%s: Rx FIFO underrun\n", __FUNCTION__); 3173 omap_mcbsp_rx_done(s); 3174 } else { 3175 s->tx_req -= 2; 3176 if (s->codec && s->codec->in.len >= 2) { 3177 ret = s->codec->in.fifo[s->codec->in.start ++] << 8; 3178 ret |= s->codec->in.fifo[s->codec->in.start ++]; 3179 s->codec->in.len -= 2; 3180 } else 3181 ret = 0x0000; 3182 if (!s->tx_req) 3183 omap_mcbsp_rx_done(s); 3184 return ret; 3185 } 3186 return 0x0000; 3187 3188 case 0x04: /* DXR2 */ 3189 case 0x06: /* DXR1 */ 3190 return 0x0000; 3191 3192 case 0x08: /* SPCR2 */ 3193 return s->spcr[1]; 3194 case 0x0a: /* SPCR1 */ 3195 return s->spcr[0]; 3196 case 0x0c: /* RCR2 */ 3197 return s->rcr[1]; 3198 case 0x0e: /* RCR1 */ 3199 return s->rcr[0]; 3200 case 0x10: /* XCR2 */ 3201 return s->xcr[1]; 3202 case 0x12: /* XCR1 */ 3203 return s->xcr[0]; 3204 case 0x14: /* SRGR2 */ 3205 return s->srgr[1]; 3206 case 0x16: /* SRGR1 */ 3207 return s->srgr[0]; 3208 case 0x18: /* MCR2 */ 3209 return s->mcr[1]; 3210 case 0x1a: /* MCR1 */ 3211 return s->mcr[0]; 3212 case 0x1c: /* RCERA */ 3213 return s->rcer[0]; 3214 case 0x1e: /* RCERB */ 3215 return s->rcer[1]; 3216 case 0x20: /* XCERA */ 3217 return s->xcer[0]; 3218 case 0x22: /* XCERB */ 3219 return s->xcer[1]; 3220 case 0x24: /* PCR0 */ 3221 return s->pcr; 3222 case 0x26: /* RCERC */ 3223 return s->rcer[2]; 3224 case 0x28: /* RCERD */ 3225 return s->rcer[3]; 3226 case 0x2a: /* XCERC */ 3227 return s->xcer[2]; 3228 case 0x2c: /* XCERD */ 3229 return s->xcer[3]; 3230 case 0x2e: /* RCERE */ 3231 return s->rcer[4]; 3232 case 0x30: /* RCERF */ 3233 return s->rcer[5]; 3234 case 0x32: /* XCERE */ 3235 return s->xcer[4]; 3236 case 0x34: /* XCERF */ 3237 return s->xcer[5]; 3238 case 0x36: /* RCERG */ 3239 return s->rcer[6]; 3240 case 0x38: /* RCERH */ 3241 return s->rcer[7]; 3242 case 0x3a: /* XCERG */ 3243 return s->xcer[6]; 3244 case 0x3c: /* XCERH */ 3245 return s->xcer[7]; 3246 } 3247 3248 OMAP_BAD_REG(addr); 3249 return 0; 3250 } 3251 3252 static void omap_mcbsp_writeh(void *opaque, hwaddr addr, 3253 uint32_t value) 3254 { 3255 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3256 int offset = addr & OMAP_MPUI_REG_MASK; 3257 3258 switch (offset) { 3259 case 0x00: /* DRR2 */ 3260 case 0x02: /* DRR1 */ 3261 OMAP_RO_REG(addr); 3262 return; 3263 3264 case 0x04: /* DXR2 */ 3265 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ 3266 return; 3267 /* Fall through. */ 3268 case 0x06: /* DXR1 */ 3269 if (s->tx_req > 1) { 3270 s->tx_req -= 2; 3271 if (s->codec && s->codec->cts) { 3272 s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff; 3273 s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff; 3274 } 3275 if (s->tx_req < 2) 3276 omap_mcbsp_tx_done(s); 3277 } else 3278 printf("%s: Tx FIFO overrun\n", __FUNCTION__); 3279 return; 3280 3281 case 0x08: /* SPCR2 */ 3282 s->spcr[1] &= 0x0002; 3283 s->spcr[1] |= 0x03f9 & value; 3284 s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */ 3285 if (~value & 1) /* XRST */ 3286 s->spcr[1] &= ~6; 3287 omap_mcbsp_req_update(s); 3288 return; 3289 case 0x0a: /* SPCR1 */ 3290 s->spcr[0] &= 0x0006; 3291 s->spcr[0] |= 0xf8f9 & value; 3292 if (value & (1 << 15)) /* DLB */ 3293 printf("%s: Digital Loopback mode enable attempt\n", __FUNCTION__); 3294 if (~value & 1) { /* RRST */ 3295 s->spcr[0] &= ~6; 3296 s->rx_req = 0; 3297 omap_mcbsp_rx_done(s); 3298 } 3299 omap_mcbsp_req_update(s); 3300 return; 3301 3302 case 0x0c: /* RCR2 */ 3303 s->rcr[1] = value & 0xffff; 3304 return; 3305 case 0x0e: /* RCR1 */ 3306 s->rcr[0] = value & 0x7fe0; 3307 return; 3308 case 0x10: /* XCR2 */ 3309 s->xcr[1] = value & 0xffff; 3310 return; 3311 case 0x12: /* XCR1 */ 3312 s->xcr[0] = value & 0x7fe0; 3313 return; 3314 case 0x14: /* SRGR2 */ 3315 s->srgr[1] = value & 0xffff; 3316 omap_mcbsp_req_update(s); 3317 return; 3318 case 0x16: /* SRGR1 */ 3319 s->srgr[0] = value & 0xffff; 3320 omap_mcbsp_req_update(s); 3321 return; 3322 case 0x18: /* MCR2 */ 3323 s->mcr[1] = value & 0x03e3; 3324 if (value & 3) /* XMCM */ 3325 printf("%s: Tx channel selection mode enable attempt\n", 3326 __FUNCTION__); 3327 return; 3328 case 0x1a: /* MCR1 */ 3329 s->mcr[0] = value & 0x03e1; 3330 if (value & 1) /* RMCM */ 3331 printf("%s: Rx channel selection mode enable attempt\n", 3332 __FUNCTION__); 3333 return; 3334 case 0x1c: /* RCERA */ 3335 s->rcer[0] = value & 0xffff; 3336 return; 3337 case 0x1e: /* RCERB */ 3338 s->rcer[1] = value & 0xffff; 3339 return; 3340 case 0x20: /* XCERA */ 3341 s->xcer[0] = value & 0xffff; 3342 return; 3343 case 0x22: /* XCERB */ 3344 s->xcer[1] = value & 0xffff; 3345 return; 3346 case 0x24: /* PCR0 */ 3347 s->pcr = value & 0x7faf; 3348 return; 3349 case 0x26: /* RCERC */ 3350 s->rcer[2] = value & 0xffff; 3351 return; 3352 case 0x28: /* RCERD */ 3353 s->rcer[3] = value & 0xffff; 3354 return; 3355 case 0x2a: /* XCERC */ 3356 s->xcer[2] = value & 0xffff; 3357 return; 3358 case 0x2c: /* XCERD */ 3359 s->xcer[3] = value & 0xffff; 3360 return; 3361 case 0x2e: /* RCERE */ 3362 s->rcer[4] = value & 0xffff; 3363 return; 3364 case 0x30: /* RCERF */ 3365 s->rcer[5] = value & 0xffff; 3366 return; 3367 case 0x32: /* XCERE */ 3368 s->xcer[4] = value & 0xffff; 3369 return; 3370 case 0x34: /* XCERF */ 3371 s->xcer[5] = value & 0xffff; 3372 return; 3373 case 0x36: /* RCERG */ 3374 s->rcer[6] = value & 0xffff; 3375 return; 3376 case 0x38: /* RCERH */ 3377 s->rcer[7] = value & 0xffff; 3378 return; 3379 case 0x3a: /* XCERG */ 3380 s->xcer[6] = value & 0xffff; 3381 return; 3382 case 0x3c: /* XCERH */ 3383 s->xcer[7] = value & 0xffff; 3384 return; 3385 } 3386 3387 OMAP_BAD_REG(addr); 3388 } 3389 3390 static void omap_mcbsp_writew(void *opaque, hwaddr addr, 3391 uint32_t value) 3392 { 3393 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3394 int offset = addr & OMAP_MPUI_REG_MASK; 3395 3396 if (offset == 0x04) { /* DXR */ 3397 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ 3398 return; 3399 if (s->tx_req > 3) { 3400 s->tx_req -= 4; 3401 if (s->codec && s->codec->cts) { 3402 s->codec->out.fifo[s->codec->out.len ++] = 3403 (value >> 24) & 0xff; 3404 s->codec->out.fifo[s->codec->out.len ++] = 3405 (value >> 16) & 0xff; 3406 s->codec->out.fifo[s->codec->out.len ++] = 3407 (value >> 8) & 0xff; 3408 s->codec->out.fifo[s->codec->out.len ++] = 3409 (value >> 0) & 0xff; 3410 } 3411 if (s->tx_req < 4) 3412 omap_mcbsp_tx_done(s); 3413 } else 3414 printf("%s: Tx FIFO overrun\n", __FUNCTION__); 3415 return; 3416 } 3417 3418 omap_badwidth_write16(opaque, addr, value); 3419 } 3420 3421 static void omap_mcbsp_write(void *opaque, hwaddr addr, 3422 uint64_t value, unsigned size) 3423 { 3424 switch (size) { 3425 case 2: 3426 omap_mcbsp_writeh(opaque, addr, value); 3427 break; 3428 case 4: 3429 omap_mcbsp_writew(opaque, addr, value); 3430 break; 3431 default: 3432 omap_badwidth_write16(opaque, addr, value); 3433 } 3434 } 3435 3436 static const MemoryRegionOps omap_mcbsp_ops = { 3437 .read = omap_mcbsp_read, 3438 .write = omap_mcbsp_write, 3439 .endianness = DEVICE_NATIVE_ENDIAN, 3440 }; 3441 3442 static void omap_mcbsp_reset(struct omap_mcbsp_s *s) 3443 { 3444 memset(&s->spcr, 0, sizeof(s->spcr)); 3445 memset(&s->rcr, 0, sizeof(s->rcr)); 3446 memset(&s->xcr, 0, sizeof(s->xcr)); 3447 s->srgr[0] = 0x0001; 3448 s->srgr[1] = 0x2000; 3449 memset(&s->mcr, 0, sizeof(s->mcr)); 3450 memset(&s->pcr, 0, sizeof(s->pcr)); 3451 memset(&s->rcer, 0, sizeof(s->rcer)); 3452 memset(&s->xcer, 0, sizeof(s->xcer)); 3453 s->tx_req = 0; 3454 s->rx_req = 0; 3455 s->tx_rate = 0; 3456 s->rx_rate = 0; 3457 timer_del(s->source_timer); 3458 timer_del(s->sink_timer); 3459 } 3460 3461 static struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory, 3462 hwaddr base, 3463 qemu_irq txirq, qemu_irq rxirq, 3464 qemu_irq *dma, omap_clk clk) 3465 { 3466 struct omap_mcbsp_s *s = g_new0(struct omap_mcbsp_s, 1); 3467 3468 s->txirq = txirq; 3469 s->rxirq = rxirq; 3470 s->txdrq = dma[0]; 3471 s->rxdrq = dma[1]; 3472 s->sink_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_mcbsp_sink_tick, s); 3473 s->source_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_mcbsp_source_tick, s); 3474 omap_mcbsp_reset(s); 3475 3476 memory_region_init_io(&s->iomem, NULL, &omap_mcbsp_ops, s, "omap-mcbsp", 0x800); 3477 memory_region_add_subregion(system_memory, base, &s->iomem); 3478 3479 return s; 3480 } 3481 3482 static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level) 3483 { 3484 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3485 3486 if (s->rx_rate) { 3487 s->rx_req = s->codec->in.len; 3488 omap_mcbsp_rx_newdata(s); 3489 } 3490 } 3491 3492 static void omap_mcbsp_i2s_start(void *opaque, int line, int level) 3493 { 3494 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3495 3496 if (s->tx_rate) { 3497 s->tx_req = s->codec->out.size; 3498 omap_mcbsp_tx_newdata(s); 3499 } 3500 } 3501 3502 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave) 3503 { 3504 s->codec = slave; 3505 slave->rx_swallow = qemu_allocate_irq(omap_mcbsp_i2s_swallow, s, 0); 3506 slave->tx_start = qemu_allocate_irq(omap_mcbsp_i2s_start, s, 0); 3507 } 3508 3509 /* LED Pulse Generators */ 3510 struct omap_lpg_s { 3511 MemoryRegion iomem; 3512 QEMUTimer *tm; 3513 3514 uint8_t control; 3515 uint8_t power; 3516 int64_t on; 3517 int64_t period; 3518 int clk; 3519 int cycle; 3520 }; 3521 3522 static void omap_lpg_tick(void *opaque) 3523 { 3524 struct omap_lpg_s *s = opaque; 3525 3526 if (s->cycle) 3527 timer_mod(s->tm, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->period - s->on); 3528 else 3529 timer_mod(s->tm, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->on); 3530 3531 s->cycle = !s->cycle; 3532 printf("%s: LED is %s\n", __FUNCTION__, s->cycle ? "on" : "off"); 3533 } 3534 3535 static void omap_lpg_update(struct omap_lpg_s *s) 3536 { 3537 int64_t on, period = 1, ticks = 1000; 3538 static const int per[8] = { 1, 2, 4, 8, 12, 16, 20, 24 }; 3539 3540 if (~s->control & (1 << 6)) /* LPGRES */ 3541 on = 0; 3542 else if (s->control & (1 << 7)) /* PERM_ON */ 3543 on = period; 3544 else { 3545 period = muldiv64(ticks, per[s->control & 7], /* PERCTRL */ 3546 256 / 32); 3547 on = (s->clk && s->power) ? muldiv64(ticks, 3548 per[(s->control >> 3) & 7], 256) : 0; /* ONCTRL */ 3549 } 3550 3551 timer_del(s->tm); 3552 if (on == period && s->on < s->period) 3553 printf("%s: LED is on\n", __FUNCTION__); 3554 else if (on == 0 && s->on) 3555 printf("%s: LED is off\n", __FUNCTION__); 3556 else if (on && (on != s->on || period != s->period)) { 3557 s->cycle = 0; 3558 s->on = on; 3559 s->period = period; 3560 omap_lpg_tick(s); 3561 return; 3562 } 3563 3564 s->on = on; 3565 s->period = period; 3566 } 3567 3568 static void omap_lpg_reset(struct omap_lpg_s *s) 3569 { 3570 s->control = 0x00; 3571 s->power = 0x00; 3572 s->clk = 1; 3573 omap_lpg_update(s); 3574 } 3575 3576 static uint64_t omap_lpg_read(void *opaque, hwaddr addr, 3577 unsigned size) 3578 { 3579 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; 3580 int offset = addr & OMAP_MPUI_REG_MASK; 3581 3582 if (size != 1) { 3583 return omap_badwidth_read8(opaque, addr); 3584 } 3585 3586 switch (offset) { 3587 case 0x00: /* LCR */ 3588 return s->control; 3589 3590 case 0x04: /* PMR */ 3591 return s->power; 3592 } 3593 3594 OMAP_BAD_REG(addr); 3595 return 0; 3596 } 3597 3598 static void omap_lpg_write(void *opaque, hwaddr addr, 3599 uint64_t value, unsigned size) 3600 { 3601 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; 3602 int offset = addr & OMAP_MPUI_REG_MASK; 3603 3604 if (size != 1) { 3605 omap_badwidth_write8(opaque, addr, value); 3606 return; 3607 } 3608 3609 switch (offset) { 3610 case 0x00: /* LCR */ 3611 if (~value & (1 << 6)) /* LPGRES */ 3612 omap_lpg_reset(s); 3613 s->control = value & 0xff; 3614 omap_lpg_update(s); 3615 return; 3616 3617 case 0x04: /* PMR */ 3618 s->power = value & 0x01; 3619 omap_lpg_update(s); 3620 return; 3621 3622 default: 3623 OMAP_BAD_REG(addr); 3624 return; 3625 } 3626 } 3627 3628 static const MemoryRegionOps omap_lpg_ops = { 3629 .read = omap_lpg_read, 3630 .write = omap_lpg_write, 3631 .endianness = DEVICE_NATIVE_ENDIAN, 3632 }; 3633 3634 static void omap_lpg_clk_update(void *opaque, int line, int on) 3635 { 3636 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; 3637 3638 s->clk = on; 3639 omap_lpg_update(s); 3640 } 3641 3642 static struct omap_lpg_s *omap_lpg_init(MemoryRegion *system_memory, 3643 hwaddr base, omap_clk clk) 3644 { 3645 struct omap_lpg_s *s = g_new0(struct omap_lpg_s, 1); 3646 3647 s->tm = timer_new_ms(QEMU_CLOCK_VIRTUAL, omap_lpg_tick, s); 3648 3649 omap_lpg_reset(s); 3650 3651 memory_region_init_io(&s->iomem, NULL, &omap_lpg_ops, s, "omap-lpg", 0x800); 3652 memory_region_add_subregion(system_memory, base, &s->iomem); 3653 3654 omap_clk_adduser(clk, qemu_allocate_irq(omap_lpg_clk_update, s, 0)); 3655 3656 return s; 3657 } 3658 3659 /* MPUI Peripheral Bridge configuration */ 3660 static uint64_t omap_mpui_io_read(void *opaque, hwaddr addr, 3661 unsigned size) 3662 { 3663 if (size != 2) { 3664 return omap_badwidth_read16(opaque, addr); 3665 } 3666 3667 if (addr == OMAP_MPUI_BASE) /* CMR */ 3668 return 0xfe4d; 3669 3670 OMAP_BAD_REG(addr); 3671 return 0; 3672 } 3673 3674 static void omap_mpui_io_write(void *opaque, hwaddr addr, 3675 uint64_t value, unsigned size) 3676 { 3677 /* FIXME: infinite loop */ 3678 omap_badwidth_write16(opaque, addr, value); 3679 } 3680 3681 static const MemoryRegionOps omap_mpui_io_ops = { 3682 .read = omap_mpui_io_read, 3683 .write = omap_mpui_io_write, 3684 .endianness = DEVICE_NATIVE_ENDIAN, 3685 }; 3686 3687 static void omap_setup_mpui_io(MemoryRegion *system_memory, 3688 struct omap_mpu_state_s *mpu) 3689 { 3690 memory_region_init_io(&mpu->mpui_io_iomem, NULL, &omap_mpui_io_ops, mpu, 3691 "omap-mpui-io", 0x7fff); 3692 memory_region_add_subregion(system_memory, OMAP_MPUI_BASE, 3693 &mpu->mpui_io_iomem); 3694 } 3695 3696 /* General chip reset */ 3697 static void omap1_mpu_reset(void *opaque) 3698 { 3699 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; 3700 3701 omap_dma_reset(mpu->dma); 3702 omap_mpu_timer_reset(mpu->timer[0]); 3703 omap_mpu_timer_reset(mpu->timer[1]); 3704 omap_mpu_timer_reset(mpu->timer[2]); 3705 omap_wd_timer_reset(mpu->wdt); 3706 omap_os_timer_reset(mpu->os_timer); 3707 omap_lcdc_reset(mpu->lcd); 3708 omap_ulpd_pm_reset(mpu); 3709 omap_pin_cfg_reset(mpu); 3710 omap_mpui_reset(mpu); 3711 omap_tipb_bridge_reset(mpu->private_tipb); 3712 omap_tipb_bridge_reset(mpu->public_tipb); 3713 omap_dpll_reset(mpu->dpll[0]); 3714 omap_dpll_reset(mpu->dpll[1]); 3715 omap_dpll_reset(mpu->dpll[2]); 3716 omap_uart_reset(mpu->uart[0]); 3717 omap_uart_reset(mpu->uart[1]); 3718 omap_uart_reset(mpu->uart[2]); 3719 omap_mmc_reset(mpu->mmc); 3720 omap_mpuio_reset(mpu->mpuio); 3721 omap_uwire_reset(mpu->microwire); 3722 omap_pwl_reset(mpu->pwl); 3723 omap_pwt_reset(mpu->pwt); 3724 omap_rtc_reset(mpu->rtc); 3725 omap_mcbsp_reset(mpu->mcbsp1); 3726 omap_mcbsp_reset(mpu->mcbsp2); 3727 omap_mcbsp_reset(mpu->mcbsp3); 3728 omap_lpg_reset(mpu->led[0]); 3729 omap_lpg_reset(mpu->led[1]); 3730 omap_clkm_reset(mpu); 3731 cpu_reset(CPU(mpu->cpu)); 3732 } 3733 3734 static const struct omap_map_s { 3735 hwaddr phys_dsp; 3736 hwaddr phys_mpu; 3737 uint32_t size; 3738 const char *name; 3739 } omap15xx_dsp_mm[] = { 3740 /* Strobe 0 */ 3741 { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */ 3742 { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */ 3743 { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */ 3744 { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */ 3745 { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */ 3746 { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */ 3747 { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */ 3748 { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */ 3749 { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */ 3750 { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */ 3751 { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */ 3752 { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */ 3753 { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */ 3754 { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */ 3755 { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */ 3756 { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */ 3757 { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */ 3758 /* Strobe 1 */ 3759 { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */ 3760 3761 { 0 } 3762 }; 3763 3764 static void omap_setup_dsp_mapping(MemoryRegion *system_memory, 3765 const struct omap_map_s *map) 3766 { 3767 MemoryRegion *io; 3768 3769 for (; map->phys_dsp; map ++) { 3770 io = g_new(MemoryRegion, 1); 3771 memory_region_init_alias(io, NULL, map->name, 3772 system_memory, map->phys_mpu, map->size); 3773 memory_region_add_subregion(system_memory, map->phys_dsp, io); 3774 } 3775 } 3776 3777 void omap_mpu_wakeup(void *opaque, int irq, int req) 3778 { 3779 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; 3780 CPUState *cpu = CPU(mpu->cpu); 3781 3782 if (cpu->halted) { 3783 cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB); 3784 } 3785 } 3786 3787 static const struct dma_irq_map omap1_dma_irq_map[] = { 3788 { 0, OMAP_INT_DMA_CH0_6 }, 3789 { 0, OMAP_INT_DMA_CH1_7 }, 3790 { 0, OMAP_INT_DMA_CH2_8 }, 3791 { 0, OMAP_INT_DMA_CH3 }, 3792 { 0, OMAP_INT_DMA_CH4 }, 3793 { 0, OMAP_INT_DMA_CH5 }, 3794 { 1, OMAP_INT_1610_DMA_CH6 }, 3795 { 1, OMAP_INT_1610_DMA_CH7 }, 3796 { 1, OMAP_INT_1610_DMA_CH8 }, 3797 { 1, OMAP_INT_1610_DMA_CH9 }, 3798 { 1, OMAP_INT_1610_DMA_CH10 }, 3799 { 1, OMAP_INT_1610_DMA_CH11 }, 3800 { 1, OMAP_INT_1610_DMA_CH12 }, 3801 { 1, OMAP_INT_1610_DMA_CH13 }, 3802 { 1, OMAP_INT_1610_DMA_CH14 }, 3803 { 1, OMAP_INT_1610_DMA_CH15 } 3804 }; 3805 3806 /* DMA ports for OMAP1 */ 3807 static int omap_validate_emiff_addr(struct omap_mpu_state_s *s, 3808 hwaddr addr) 3809 { 3810 return range_covers_byte(OMAP_EMIFF_BASE, s->sdram_size, addr); 3811 } 3812 3813 static int omap_validate_emifs_addr(struct omap_mpu_state_s *s, 3814 hwaddr addr) 3815 { 3816 return range_covers_byte(OMAP_EMIFS_BASE, OMAP_EMIFF_BASE - OMAP_EMIFS_BASE, 3817 addr); 3818 } 3819 3820 static int omap_validate_imif_addr(struct omap_mpu_state_s *s, 3821 hwaddr addr) 3822 { 3823 return range_covers_byte(OMAP_IMIF_BASE, s->sram_size, addr); 3824 } 3825 3826 static int omap_validate_tipb_addr(struct omap_mpu_state_s *s, 3827 hwaddr addr) 3828 { 3829 return range_covers_byte(0xfffb0000, 0xffff0000 - 0xfffb0000, addr); 3830 } 3831 3832 static int omap_validate_local_addr(struct omap_mpu_state_s *s, 3833 hwaddr addr) 3834 { 3835 return range_covers_byte(OMAP_LOCALBUS_BASE, 0x1000000, addr); 3836 } 3837 3838 static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s, 3839 hwaddr addr) 3840 { 3841 return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr); 3842 } 3843 3844 struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory, 3845 unsigned long sdram_size, 3846 const char *core) 3847 { 3848 int i; 3849 struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1); 3850 qemu_irq dma_irqs[6]; 3851 DriveInfo *dinfo; 3852 SysBusDevice *busdev; 3853 3854 if (!core) 3855 core = "ti925t"; 3856 3857 /* Core */ 3858 s->mpu_model = omap310; 3859 s->cpu = cpu_arm_init(core); 3860 if (s->cpu == NULL) { 3861 fprintf(stderr, "Unable to find CPU definition\n"); 3862 exit(1); 3863 } 3864 s->sdram_size = sdram_size; 3865 s->sram_size = OMAP15XX_SRAM_SIZE; 3866 3867 s->wakeup = qemu_allocate_irq(omap_mpu_wakeup, s, 0); 3868 3869 /* Clocks */ 3870 omap_clk_init(s); 3871 3872 /* Memory-mapped stuff */ 3873 memory_region_allocate_system_memory(&s->emiff_ram, NULL, "omap1.dram", 3874 s->sdram_size); 3875 memory_region_add_subregion(system_memory, OMAP_EMIFF_BASE, &s->emiff_ram); 3876 memory_region_init_ram(&s->imif_ram, NULL, "omap1.sram", s->sram_size, 3877 &error_fatal); 3878 vmstate_register_ram_global(&s->imif_ram); 3879 memory_region_add_subregion(system_memory, OMAP_IMIF_BASE, &s->imif_ram); 3880 3881 omap_clkm_init(system_memory, 0xfffece00, 0xe1008000, s); 3882 3883 s->ih[0] = qdev_create(NULL, "omap-intc"); 3884 qdev_prop_set_uint32(s->ih[0], "size", 0x100); 3885 qdev_prop_set_ptr(s->ih[0], "clk", omap_findclk(s, "arminth_ck")); 3886 qdev_init_nofail(s->ih[0]); 3887 busdev = SYS_BUS_DEVICE(s->ih[0]); 3888 sysbus_connect_irq(busdev, 0, 3889 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ)); 3890 sysbus_connect_irq(busdev, 1, 3891 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ)); 3892 sysbus_mmio_map(busdev, 0, 0xfffecb00); 3893 s->ih[1] = qdev_create(NULL, "omap-intc"); 3894 qdev_prop_set_uint32(s->ih[1], "size", 0x800); 3895 qdev_prop_set_ptr(s->ih[1], "clk", omap_findclk(s, "arminth_ck")); 3896 qdev_init_nofail(s->ih[1]); 3897 busdev = SYS_BUS_DEVICE(s->ih[1]); 3898 sysbus_connect_irq(busdev, 0, 3899 qdev_get_gpio_in(s->ih[0], OMAP_INT_15XX_IH2_IRQ)); 3900 /* The second interrupt controller's FIQ output is not wired up */ 3901 sysbus_mmio_map(busdev, 0, 0xfffe0000); 3902 3903 for (i = 0; i < 6; i++) { 3904 dma_irqs[i] = qdev_get_gpio_in(s->ih[omap1_dma_irq_map[i].ih], 3905 omap1_dma_irq_map[i].intr); 3906 } 3907 s->dma = omap_dma_init(0xfffed800, dma_irqs, system_memory, 3908 qdev_get_gpio_in(s->ih[0], OMAP_INT_DMA_LCD), 3909 s, omap_findclk(s, "dma_ck"), omap_dma_3_1); 3910 3911 s->port[emiff ].addr_valid = omap_validate_emiff_addr; 3912 s->port[emifs ].addr_valid = omap_validate_emifs_addr; 3913 s->port[imif ].addr_valid = omap_validate_imif_addr; 3914 s->port[tipb ].addr_valid = omap_validate_tipb_addr; 3915 s->port[local ].addr_valid = omap_validate_local_addr; 3916 s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr; 3917 3918 /* Register SDRAM and SRAM DMA ports for fast transfers. */ 3919 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->emiff_ram), 3920 OMAP_EMIFF_BASE, s->sdram_size); 3921 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->imif_ram), 3922 OMAP_IMIF_BASE, s->sram_size); 3923 3924 s->timer[0] = omap_mpu_timer_init(system_memory, 0xfffec500, 3925 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER1), 3926 omap_findclk(s, "mputim_ck")); 3927 s->timer[1] = omap_mpu_timer_init(system_memory, 0xfffec600, 3928 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER2), 3929 omap_findclk(s, "mputim_ck")); 3930 s->timer[2] = omap_mpu_timer_init(system_memory, 0xfffec700, 3931 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER3), 3932 omap_findclk(s, "mputim_ck")); 3933 3934 s->wdt = omap_wd_timer_init(system_memory, 0xfffec800, 3935 qdev_get_gpio_in(s->ih[0], OMAP_INT_WD_TIMER), 3936 omap_findclk(s, "armwdt_ck")); 3937 3938 s->os_timer = omap_os_timer_init(system_memory, 0xfffb9000, 3939 qdev_get_gpio_in(s->ih[1], OMAP_INT_OS_TIMER), 3940 omap_findclk(s, "clk32-kHz")); 3941 3942 s->lcd = omap_lcdc_init(system_memory, 0xfffec000, 3943 qdev_get_gpio_in(s->ih[0], OMAP_INT_LCD_CTRL), 3944 omap_dma_get_lcdch(s->dma), 3945 omap_findclk(s, "lcd_ck")); 3946 3947 omap_ulpd_pm_init(system_memory, 0xfffe0800, s); 3948 omap_pin_cfg_init(system_memory, 0xfffe1000, s); 3949 omap_id_init(system_memory, s); 3950 3951 omap_mpui_init(system_memory, 0xfffec900, s); 3952 3953 s->private_tipb = omap_tipb_bridge_init(system_memory, 0xfffeca00, 3954 qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PRIV), 3955 omap_findclk(s, "tipb_ck")); 3956 s->public_tipb = omap_tipb_bridge_init(system_memory, 0xfffed300, 3957 qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PUB), 3958 omap_findclk(s, "tipb_ck")); 3959 3960 omap_tcmi_init(system_memory, 0xfffecc00, s); 3961 3962 s->uart[0] = omap_uart_init(0xfffb0000, 3963 qdev_get_gpio_in(s->ih[1], OMAP_INT_UART1), 3964 omap_findclk(s, "uart1_ck"), 3965 omap_findclk(s, "uart1_ck"), 3966 s->drq[OMAP_DMA_UART1_TX], s->drq[OMAP_DMA_UART1_RX], 3967 "uart1", 3968 serial_hds[0]); 3969 s->uart[1] = omap_uart_init(0xfffb0800, 3970 qdev_get_gpio_in(s->ih[1], OMAP_INT_UART2), 3971 omap_findclk(s, "uart2_ck"), 3972 omap_findclk(s, "uart2_ck"), 3973 s->drq[OMAP_DMA_UART2_TX], s->drq[OMAP_DMA_UART2_RX], 3974 "uart2", 3975 serial_hds[0] ? serial_hds[1] : NULL); 3976 s->uart[2] = omap_uart_init(0xfffb9800, 3977 qdev_get_gpio_in(s->ih[0], OMAP_INT_UART3), 3978 omap_findclk(s, "uart3_ck"), 3979 omap_findclk(s, "uart3_ck"), 3980 s->drq[OMAP_DMA_UART3_TX], s->drq[OMAP_DMA_UART3_RX], 3981 "uart3", 3982 serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL); 3983 3984 s->dpll[0] = omap_dpll_init(system_memory, 0xfffecf00, 3985 omap_findclk(s, "dpll1")); 3986 s->dpll[1] = omap_dpll_init(system_memory, 0xfffed000, 3987 omap_findclk(s, "dpll2")); 3988 s->dpll[2] = omap_dpll_init(system_memory, 0xfffed100, 3989 omap_findclk(s, "dpll3")); 3990 3991 dinfo = drive_get(IF_SD, 0, 0); 3992 if (!dinfo) { 3993 fprintf(stderr, "qemu: missing SecureDigital device\n"); 3994 exit(1); 3995 } 3996 s->mmc = omap_mmc_init(0xfffb7800, system_memory, 3997 blk_by_legacy_dinfo(dinfo), 3998 qdev_get_gpio_in(s->ih[1], OMAP_INT_OQN), 3999 &s->drq[OMAP_DMA_MMC_TX], 4000 omap_findclk(s, "mmc_ck")); 4001 4002 s->mpuio = omap_mpuio_init(system_memory, 0xfffb5000, 4003 qdev_get_gpio_in(s->ih[1], OMAP_INT_KEYBOARD), 4004 qdev_get_gpio_in(s->ih[1], OMAP_INT_MPUIO), 4005 s->wakeup, omap_findclk(s, "clk32-kHz")); 4006 4007 s->gpio = qdev_create(NULL, "omap-gpio"); 4008 qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model); 4009 qdev_prop_set_ptr(s->gpio, "clk", omap_findclk(s, "arm_gpio_ck")); 4010 qdev_init_nofail(s->gpio); 4011 sysbus_connect_irq(SYS_BUS_DEVICE(s->gpio), 0, 4012 qdev_get_gpio_in(s->ih[0], OMAP_INT_GPIO_BANK1)); 4013 sysbus_mmio_map(SYS_BUS_DEVICE(s->gpio), 0, 0xfffce000); 4014 4015 s->microwire = omap_uwire_init(system_memory, 0xfffb3000, 4016 qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireTX), 4017 qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireRX), 4018 s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck")); 4019 4020 s->pwl = omap_pwl_init(system_memory, 0xfffb5800, 4021 omap_findclk(s, "armxor_ck")); 4022 s->pwt = omap_pwt_init(system_memory, 0xfffb6000, 4023 omap_findclk(s, "armxor_ck")); 4024 4025 s->i2c[0] = qdev_create(NULL, "omap_i2c"); 4026 qdev_prop_set_uint8(s->i2c[0], "revision", 0x11); 4027 qdev_prop_set_ptr(s->i2c[0], "fclk", omap_findclk(s, "mpuper_ck")); 4028 qdev_init_nofail(s->i2c[0]); 4029 busdev = SYS_BUS_DEVICE(s->i2c[0]); 4030 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C)); 4031 sysbus_connect_irq(busdev, 1, s->drq[OMAP_DMA_I2C_TX]); 4032 sysbus_connect_irq(busdev, 2, s->drq[OMAP_DMA_I2C_RX]); 4033 sysbus_mmio_map(busdev, 0, 0xfffb3800); 4034 4035 s->rtc = omap_rtc_init(system_memory, 0xfffb4800, 4036 qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_TIMER), 4037 qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_ALARM), 4038 omap_findclk(s, "clk32-kHz")); 4039 4040 s->mcbsp1 = omap_mcbsp_init(system_memory, 0xfffb1800, 4041 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1TX), 4042 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1RX), 4043 &s->drq[OMAP_DMA_MCBSP1_TX], omap_findclk(s, "dspxor_ck")); 4044 s->mcbsp2 = omap_mcbsp_init(system_memory, 0xfffb1000, 4045 qdev_get_gpio_in(s->ih[0], 4046 OMAP_INT_310_McBSP2_TX), 4047 qdev_get_gpio_in(s->ih[0], 4048 OMAP_INT_310_McBSP2_RX), 4049 &s->drq[OMAP_DMA_MCBSP2_TX], omap_findclk(s, "mpuper_ck")); 4050 s->mcbsp3 = omap_mcbsp_init(system_memory, 0xfffb7000, 4051 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3TX), 4052 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3RX), 4053 &s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck")); 4054 4055 s->led[0] = omap_lpg_init(system_memory, 4056 0xfffbd000, omap_findclk(s, "clk32-kHz")); 4057 s->led[1] = omap_lpg_init(system_memory, 4058 0xfffbd800, omap_findclk(s, "clk32-kHz")); 4059 4060 /* Register mappings not currenlty implemented: 4061 * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310) 4062 * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310) 4063 * USB W2FC fffb4000 - fffb47ff 4064 * Camera Interface fffb6800 - fffb6fff 4065 * USB Host fffba000 - fffba7ff 4066 * FAC fffba800 - fffbafff 4067 * HDQ/1-Wire fffbc000 - fffbc7ff 4068 * TIPB switches fffbc800 - fffbcfff 4069 * Mailbox fffcf000 - fffcf7ff 4070 * Local bus IF fffec100 - fffec1ff 4071 * Local bus MMU fffec200 - fffec2ff 4072 * DSP MMU fffed200 - fffed2ff 4073 */ 4074 4075 omap_setup_dsp_mapping(system_memory, omap15xx_dsp_mm); 4076 omap_setup_mpui_io(system_memory, s); 4077 4078 qemu_register_reset(omap1_mpu_reset, s); 4079 4080 return s; 4081 } 4082