1 /* 2 * Nokia N-series internet tablets. 3 * 4 * Copyright (C) 2007 Nokia Corporation 5 * Written by Andrzej Zaborowski <andrew@openedhand.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 or 10 * (at your option) version 3 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "cpu.h" 24 #include "qemu/cutils.h" 25 #include "qemu/bswap.h" 26 #include "sysemu/reset.h" 27 #include "sysemu/runstate.h" 28 #include "sysemu/sysemu.h" 29 #include "hw/arm/omap.h" 30 #include "hw/arm/boot.h" 31 #include "hw/irq.h" 32 #include "ui/console.h" 33 #include "hw/boards.h" 34 #include "hw/i2c/i2c.h" 35 #include "hw/display/blizzard.h" 36 #include "hw/input/tsc2xxx.h" 37 #include "hw/misc/cbus.h" 38 #include "hw/misc/tmp105.h" 39 #include "hw/qdev-properties.h" 40 #include "hw/block/flash.h" 41 #include "hw/hw.h" 42 #include "hw/bt.h" 43 #include "hw/loader.h" 44 #include "hw/sysbus.h" 45 #include "qemu/log.h" 46 #include "exec/address-spaces.h" 47 48 /* Nokia N8x0 support */ 49 struct n800_s { 50 struct omap_mpu_state_s *mpu; 51 52 struct rfbi_chip_s blizzard; 53 struct { 54 void *opaque; 55 uint32_t (*txrx)(void *opaque, uint32_t value, int len); 56 uWireSlave *chip; 57 } ts; 58 59 int keymap[0x80]; 60 DeviceState *kbd; 61 62 DeviceState *usb; 63 void *retu; 64 void *tahvo; 65 DeviceState *nand; 66 }; 67 68 /* GPIO pins */ 69 #define N8X0_TUSB_ENABLE_GPIO 0 70 #define N800_MMC2_WP_GPIO 8 71 #define N800_UNKNOWN_GPIO0 9 /* out */ 72 #define N810_MMC2_VIOSD_GPIO 9 73 #define N810_HEADSET_AMP_GPIO 10 74 #define N800_CAM_TURN_GPIO 12 75 #define N810_GPS_RESET_GPIO 12 76 #define N800_BLIZZARD_POWERDOWN_GPIO 15 77 #define N800_MMC1_WP_GPIO 23 78 #define N810_MMC2_VSD_GPIO 23 79 #define N8X0_ONENAND_GPIO 26 80 #define N810_BLIZZARD_RESET_GPIO 30 81 #define N800_UNKNOWN_GPIO2 53 /* out */ 82 #define N8X0_TUSB_INT_GPIO 58 83 #define N8X0_BT_WKUP_GPIO 61 84 #define N8X0_STI_GPIO 62 85 #define N8X0_CBUS_SEL_GPIO 64 86 #define N8X0_CBUS_DAT_GPIO 65 87 #define N8X0_CBUS_CLK_GPIO 66 88 #define N8X0_WLAN_IRQ_GPIO 87 89 #define N8X0_BT_RESET_GPIO 92 90 #define N8X0_TEA5761_CS_GPIO 93 91 #define N800_UNKNOWN_GPIO 94 92 #define N810_TSC_RESET_GPIO 94 93 #define N800_CAM_ACT_GPIO 95 94 #define N810_GPS_WAKEUP_GPIO 95 95 #define N8X0_MMC_CS_GPIO 96 96 #define N8X0_WLAN_PWR_GPIO 97 97 #define N8X0_BT_HOST_WKUP_GPIO 98 98 #define N810_SPEAKER_AMP_GPIO 101 99 #define N810_KB_LOCK_GPIO 102 100 #define N800_TSC_TS_GPIO 103 101 #define N810_TSC_TS_GPIO 106 102 #define N8X0_HEADPHONE_GPIO 107 103 #define N8X0_RETU_GPIO 108 104 #define N800_TSC_KP_IRQ_GPIO 109 105 #define N810_KEYBOARD_GPIO 109 106 #define N800_BAT_COVER_GPIO 110 107 #define N810_SLIDE_GPIO 110 108 #define N8X0_TAHVO_GPIO 111 109 #define N800_UNKNOWN_GPIO4 112 /* out */ 110 #define N810_SLEEPX_LED_GPIO 112 111 #define N800_TSC_RESET_GPIO 118 /* ? */ 112 #define N810_AIC33_RESET_GPIO 118 113 #define N800_TSC_UNKNOWN_GPIO 119 /* out */ 114 #define N8X0_TMP105_GPIO 125 115 116 /* Config */ 117 #define BT_UART 0 118 #define XLDR_LL_UART 1 119 120 /* Addresses on the I2C bus 0 */ 121 #define N810_TLV320AIC33_ADDR 0x18 /* Audio CODEC */ 122 #define N8X0_TCM825x_ADDR 0x29 /* Camera */ 123 #define N810_LP5521_ADDR 0x32 /* LEDs */ 124 #define N810_TSL2563_ADDR 0x3d /* Light sensor */ 125 #define N810_LM8323_ADDR 0x45 /* Keyboard */ 126 /* Addresses on the I2C bus 1 */ 127 #define N8X0_TMP105_ADDR 0x48 /* Temperature sensor */ 128 #define N8X0_MENELAUS_ADDR 0x72 /* Power management */ 129 130 /* Chipselects on GPMC NOR interface */ 131 #define N8X0_ONENAND_CS 0 132 #define N8X0_USB_ASYNC_CS 1 133 #define N8X0_USB_SYNC_CS 4 134 135 #define N8X0_BD_ADDR 0x00, 0x1a, 0x89, 0x9e, 0x3e, 0x81 136 137 static void n800_mmc_cs_cb(void *opaque, int line, int level) 138 { 139 /* TODO: this seems to actually be connected to the menelaus, to 140 * which also both MMC slots connect. */ 141 omap_mmc_enable((struct omap_mmc_s *) opaque, !level); 142 } 143 144 static void n8x0_gpio_setup(struct n800_s *s) 145 { 146 qdev_connect_gpio_out(s->mpu->gpio, N8X0_MMC_CS_GPIO, 147 qemu_allocate_irq(n800_mmc_cs_cb, s->mpu->mmc, 0)); 148 qemu_irq_lower(qdev_get_gpio_in(s->mpu->gpio, N800_BAT_COVER_GPIO)); 149 } 150 151 #define MAEMO_CAL_HEADER(...) \ 152 'C', 'o', 'n', 'F', 0x02, 0x00, 0x04, 0x00, \ 153 __VA_ARGS__, \ 154 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 155 156 static const uint8_t n8x0_cal_wlan_mac[] = { 157 MAEMO_CAL_HEADER('w', 'l', 'a', 'n', '-', 'm', 'a', 'c') 158 0x1c, 0x00, 0x00, 0x00, 0x47, 0xd6, 0x69, 0xb3, 159 0x30, 0x08, 0xa0, 0x83, 0x00, 0x00, 0x00, 0x00, 160 0x00, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00, 161 0x89, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00, 0x00, 162 0x5d, 0x00, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 163 }; 164 165 static const uint8_t n8x0_cal_bt_id[] = { 166 MAEMO_CAL_HEADER('b', 't', '-', 'i', 'd', 0, 0, 0) 167 0x0a, 0x00, 0x00, 0x00, 0xa3, 0x4b, 0xf6, 0x96, 168 0xa8, 0xeb, 0xb2, 0x41, 0x00, 0x00, 0x00, 0x00, 169 N8X0_BD_ADDR, 170 }; 171 172 static void n8x0_nand_setup(struct n800_s *s) 173 { 174 char *otp_region; 175 DriveInfo *dinfo; 176 177 s->nand = qdev_create(NULL, "onenand"); 178 qdev_prop_set_uint16(s->nand, "manufacturer_id", NAND_MFR_SAMSUNG); 179 /* Either 0x40 or 0x48 are OK for the device ID */ 180 qdev_prop_set_uint16(s->nand, "device_id", 0x48); 181 qdev_prop_set_uint16(s->nand, "version_id", 0); 182 qdev_prop_set_int32(s->nand, "shift", 1); 183 dinfo = drive_get(IF_MTD, 0, 0); 184 if (dinfo) { 185 qdev_prop_set_drive(s->nand, "drive", blk_by_legacy_dinfo(dinfo), 186 &error_fatal); 187 } 188 qdev_init_nofail(s->nand); 189 sysbus_connect_irq(SYS_BUS_DEVICE(s->nand), 0, 190 qdev_get_gpio_in(s->mpu->gpio, N8X0_ONENAND_GPIO)); 191 omap_gpmc_attach(s->mpu->gpmc, N8X0_ONENAND_CS, 192 sysbus_mmio_get_region(SYS_BUS_DEVICE(s->nand), 0)); 193 otp_region = onenand_raw_otp(s->nand); 194 195 memcpy(otp_region + 0x000, n8x0_cal_wlan_mac, sizeof(n8x0_cal_wlan_mac)); 196 memcpy(otp_region + 0x800, n8x0_cal_bt_id, sizeof(n8x0_cal_bt_id)); 197 /* XXX: in theory should also update the OOB for both pages */ 198 } 199 200 static qemu_irq n8x0_system_powerdown; 201 202 static void n8x0_powerdown_req(Notifier *n, void *opaque) 203 { 204 qemu_irq_raise(n8x0_system_powerdown); 205 } 206 207 static Notifier n8x0_system_powerdown_notifier = { 208 .notify = n8x0_powerdown_req 209 }; 210 211 static void n8x0_i2c_setup(struct n800_s *s) 212 { 213 DeviceState *dev; 214 qemu_irq tmp_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_TMP105_GPIO); 215 I2CBus *i2c = omap_i2c_bus(s->mpu->i2c[0]); 216 217 /* Attach a menelaus PM chip */ 218 dev = i2c_create_slave(i2c, "twl92230", N8X0_MENELAUS_ADDR); 219 qdev_connect_gpio_out(dev, 3, 220 qdev_get_gpio_in(s->mpu->ih[0], 221 OMAP_INT_24XX_SYS_NIRQ)); 222 223 n8x0_system_powerdown = qdev_get_gpio_in(dev, 3); 224 qemu_register_powerdown_notifier(&n8x0_system_powerdown_notifier); 225 226 /* Attach a TMP105 PM chip (A0 wired to ground) */ 227 dev = i2c_create_slave(i2c, TYPE_TMP105, N8X0_TMP105_ADDR); 228 qdev_connect_gpio_out(dev, 0, tmp_irq); 229 } 230 231 /* Touchscreen and keypad controller */ 232 static MouseTransformInfo n800_pointercal = { 233 .x = 800, 234 .y = 480, 235 .a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 }, 236 }; 237 238 static MouseTransformInfo n810_pointercal = { 239 .x = 800, 240 .y = 480, 241 .a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 }, 242 }; 243 244 #define RETU_KEYCODE 61 /* F3 */ 245 246 static void n800_key_event(void *opaque, int keycode) 247 { 248 struct n800_s *s = (struct n800_s *) opaque; 249 int code = s->keymap[keycode & 0x7f]; 250 251 if (code == -1) { 252 if ((keycode & 0x7f) == RETU_KEYCODE) { 253 retu_key_event(s->retu, !(keycode & 0x80)); 254 } 255 return; 256 } 257 258 tsc210x_key_event(s->ts.chip, code, !(keycode & 0x80)); 259 } 260 261 static const int n800_keys[16] = { 262 -1, 263 72, /* Up */ 264 63, /* Home (F5) */ 265 -1, 266 75, /* Left */ 267 28, /* Enter */ 268 77, /* Right */ 269 -1, 270 1, /* Cycle (ESC) */ 271 80, /* Down */ 272 62, /* Menu (F4) */ 273 -1, 274 66, /* Zoom- (F8) */ 275 64, /* FullScreen (F6) */ 276 65, /* Zoom+ (F7) */ 277 -1, 278 }; 279 280 static void n800_tsc_kbd_setup(struct n800_s *s) 281 { 282 int i; 283 284 /* XXX: are the three pins inverted inside the chip between the 285 * tsc and the cpu (N4111)? */ 286 qemu_irq penirq = NULL; /* NC */ 287 qemu_irq kbirq = qdev_get_gpio_in(s->mpu->gpio, N800_TSC_KP_IRQ_GPIO); 288 qemu_irq dav = qdev_get_gpio_in(s->mpu->gpio, N800_TSC_TS_GPIO); 289 290 s->ts.chip = tsc2301_init(penirq, kbirq, dav); 291 s->ts.opaque = s->ts.chip->opaque; 292 s->ts.txrx = tsc210x_txrx; 293 294 for (i = 0; i < 0x80; i++) { 295 s->keymap[i] = -1; 296 } 297 for (i = 0; i < 0x10; i++) { 298 if (n800_keys[i] >= 0) { 299 s->keymap[n800_keys[i]] = i; 300 } 301 } 302 303 qemu_add_kbd_event_handler(n800_key_event, s); 304 305 tsc210x_set_transform(s->ts.chip, &n800_pointercal); 306 } 307 308 static void n810_tsc_setup(struct n800_s *s) 309 { 310 qemu_irq pintdav = qdev_get_gpio_in(s->mpu->gpio, N810_TSC_TS_GPIO); 311 312 s->ts.opaque = tsc2005_init(pintdav); 313 s->ts.txrx = tsc2005_txrx; 314 315 tsc2005_set_transform(s->ts.opaque, &n810_pointercal); 316 } 317 318 /* N810 Keyboard controller */ 319 static void n810_key_event(void *opaque, int keycode) 320 { 321 struct n800_s *s = (struct n800_s *) opaque; 322 int code = s->keymap[keycode & 0x7f]; 323 324 if (code == -1) { 325 if ((keycode & 0x7f) == RETU_KEYCODE) { 326 retu_key_event(s->retu, !(keycode & 0x80)); 327 } 328 return; 329 } 330 331 lm832x_key_event(s->kbd, code, !(keycode & 0x80)); 332 } 333 334 #define M 0 335 336 static int n810_keys[0x80] = { 337 [0x01] = 16, /* Q */ 338 [0x02] = 37, /* K */ 339 [0x03] = 24, /* O */ 340 [0x04] = 25, /* P */ 341 [0x05] = 14, /* Backspace */ 342 [0x06] = 30, /* A */ 343 [0x07] = 31, /* S */ 344 [0x08] = 32, /* D */ 345 [0x09] = 33, /* F */ 346 [0x0a] = 34, /* G */ 347 [0x0b] = 35, /* H */ 348 [0x0c] = 36, /* J */ 349 350 [0x11] = 17, /* W */ 351 [0x12] = 62, /* Menu (F4) */ 352 [0x13] = 38, /* L */ 353 [0x14] = 40, /* ' (Apostrophe) */ 354 [0x16] = 44, /* Z */ 355 [0x17] = 45, /* X */ 356 [0x18] = 46, /* C */ 357 [0x19] = 47, /* V */ 358 [0x1a] = 48, /* B */ 359 [0x1b] = 49, /* N */ 360 [0x1c] = 42, /* Shift (Left shift) */ 361 [0x1f] = 65, /* Zoom+ (F7) */ 362 363 [0x21] = 18, /* E */ 364 [0x22] = 39, /* ; (Semicolon) */ 365 [0x23] = 12, /* - (Minus) */ 366 [0x24] = 13, /* = (Equal) */ 367 [0x2b] = 56, /* Fn (Left Alt) */ 368 [0x2c] = 50, /* M */ 369 [0x2f] = 66, /* Zoom- (F8) */ 370 371 [0x31] = 19, /* R */ 372 [0x32] = 29 | M, /* Right Ctrl */ 373 [0x34] = 57, /* Space */ 374 [0x35] = 51, /* , (Comma) */ 375 [0x37] = 72 | M, /* Up */ 376 [0x3c] = 82 | M, /* Compose (Insert) */ 377 [0x3f] = 64, /* FullScreen (F6) */ 378 379 [0x41] = 20, /* T */ 380 [0x44] = 52, /* . (Dot) */ 381 [0x46] = 77 | M, /* Right */ 382 [0x4f] = 63, /* Home (F5) */ 383 [0x51] = 21, /* Y */ 384 [0x53] = 80 | M, /* Down */ 385 [0x55] = 28, /* Enter */ 386 [0x5f] = 1, /* Cycle (ESC) */ 387 388 [0x61] = 22, /* U */ 389 [0x64] = 75 | M, /* Left */ 390 391 [0x71] = 23, /* I */ 392 #if 0 393 [0x75] = 28 | M, /* KP Enter (KP Enter) */ 394 #else 395 [0x75] = 15, /* KP Enter (Tab) */ 396 #endif 397 }; 398 399 #undef M 400 401 static void n810_kbd_setup(struct n800_s *s) 402 { 403 qemu_irq kbd_irq = qdev_get_gpio_in(s->mpu->gpio, N810_KEYBOARD_GPIO); 404 int i; 405 406 for (i = 0; i < 0x80; i++) { 407 s->keymap[i] = -1; 408 } 409 for (i = 0; i < 0x80; i++) { 410 if (n810_keys[i] > 0) { 411 s->keymap[n810_keys[i]] = i; 412 } 413 } 414 415 qemu_add_kbd_event_handler(n810_key_event, s); 416 417 /* Attach the LM8322 keyboard to the I2C bus, 418 * should happen in n8x0_i2c_setup and s->kbd be initialised here. */ 419 s->kbd = i2c_create_slave(omap_i2c_bus(s->mpu->i2c[0]), 420 "lm8323", N810_LM8323_ADDR); 421 qdev_connect_gpio_out(s->kbd, 0, kbd_irq); 422 } 423 424 /* LCD MIPI DBI-C controller (URAL) */ 425 struct mipid_s { 426 int resp[4]; 427 int param[4]; 428 int p; 429 int pm; 430 int cmd; 431 432 int sleep; 433 int booster; 434 int te; 435 int selfcheck; 436 int partial; 437 int normal; 438 int vscr; 439 int invert; 440 int onoff; 441 int gamma; 442 uint32_t id; 443 }; 444 445 static void mipid_reset(struct mipid_s *s) 446 { 447 s->pm = 0; 448 s->cmd = 0; 449 450 s->sleep = 1; 451 s->booster = 0; 452 s->selfcheck = 453 (1 << 7) | /* Register loading OK. */ 454 (1 << 5) | /* The chip is attached. */ 455 (1 << 4); /* Display glass still in one piece. */ 456 s->te = 0; 457 s->partial = 0; 458 s->normal = 1; 459 s->vscr = 0; 460 s->invert = 0; 461 s->onoff = 1; 462 s->gamma = 0; 463 } 464 465 static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len) 466 { 467 struct mipid_s *s = (struct mipid_s *) opaque; 468 uint8_t ret; 469 470 if (len > 9) { 471 hw_error("%s: FIXME: bad SPI word width %i\n", __func__, len); 472 } 473 474 if (s->p >= ARRAY_SIZE(s->resp)) { 475 ret = 0; 476 } else { 477 ret = s->resp[s->p++]; 478 } 479 if (s->pm-- > 0) { 480 s->param[s->pm] = cmd; 481 } else { 482 s->cmd = cmd; 483 } 484 485 switch (s->cmd) { 486 case 0x00: /* NOP */ 487 break; 488 489 case 0x01: /* SWRESET */ 490 mipid_reset(s); 491 break; 492 493 case 0x02: /* BSTROFF */ 494 s->booster = 0; 495 break; 496 case 0x03: /* BSTRON */ 497 s->booster = 1; 498 break; 499 500 case 0x04: /* RDDID */ 501 s->p = 0; 502 s->resp[0] = (s->id >> 16) & 0xff; 503 s->resp[1] = (s->id >> 8) & 0xff; 504 s->resp[2] = (s->id >> 0) & 0xff; 505 break; 506 507 case 0x06: /* RD_RED */ 508 case 0x07: /* RD_GREEN */ 509 /* XXX the bootloader sometimes issues RD_BLUE meaning RDDID so 510 * for the bootloader one needs to change this. */ 511 case 0x08: /* RD_BLUE */ 512 s->p = 0; 513 /* TODO: return first pixel components */ 514 s->resp[0] = 0x01; 515 break; 516 517 case 0x09: /* RDDST */ 518 s->p = 0; 519 s->resp[0] = s->booster << 7; 520 s->resp[1] = (5 << 4) | (s->partial << 2) | 521 (s->sleep << 1) | s->normal; 522 s->resp[2] = (s->vscr << 7) | (s->invert << 5) | 523 (s->onoff << 2) | (s->te << 1) | (s->gamma >> 2); 524 s->resp[3] = s->gamma << 6; 525 break; 526 527 case 0x0a: /* RDDPM */ 528 s->p = 0; 529 s->resp[0] = (s->onoff << 2) | (s->normal << 3) | (s->sleep << 4) | 530 (s->partial << 5) | (s->sleep << 6) | (s->booster << 7); 531 break; 532 case 0x0b: /* RDDMADCTR */ 533 s->p = 0; 534 s->resp[0] = 0; 535 break; 536 case 0x0c: /* RDDCOLMOD */ 537 s->p = 0; 538 s->resp[0] = 5; /* 65K colours */ 539 break; 540 case 0x0d: /* RDDIM */ 541 s->p = 0; 542 s->resp[0] = (s->invert << 5) | (s->vscr << 7) | s->gamma; 543 break; 544 case 0x0e: /* RDDSM */ 545 s->p = 0; 546 s->resp[0] = s->te << 7; 547 break; 548 case 0x0f: /* RDDSDR */ 549 s->p = 0; 550 s->resp[0] = s->selfcheck; 551 break; 552 553 case 0x10: /* SLPIN */ 554 s->sleep = 1; 555 break; 556 case 0x11: /* SLPOUT */ 557 s->sleep = 0; 558 s->selfcheck ^= 1 << 6; /* POFF self-diagnosis Ok */ 559 break; 560 561 case 0x12: /* PTLON */ 562 s->partial = 1; 563 s->normal = 0; 564 s->vscr = 0; 565 break; 566 case 0x13: /* NORON */ 567 s->partial = 0; 568 s->normal = 1; 569 s->vscr = 0; 570 break; 571 572 case 0x20: /* INVOFF */ 573 s->invert = 0; 574 break; 575 case 0x21: /* INVON */ 576 s->invert = 1; 577 break; 578 579 case 0x22: /* APOFF */ 580 case 0x23: /* APON */ 581 goto bad_cmd; 582 583 case 0x25: /* WRCNTR */ 584 if (s->pm < 0) { 585 s->pm = 1; 586 } 587 goto bad_cmd; 588 589 case 0x26: /* GAMSET */ 590 if (!s->pm) { 591 s->gamma = ctz32(s->param[0] & 0xf); 592 if (s->gamma == 32) { 593 s->gamma = -1; /* XXX: should this be 0? */ 594 } 595 } else if (s->pm < 0) { 596 s->pm = 1; 597 } 598 break; 599 600 case 0x28: /* DISPOFF */ 601 s->onoff = 0; 602 break; 603 case 0x29: /* DISPON */ 604 s->onoff = 1; 605 break; 606 607 case 0x2a: /* CASET */ 608 case 0x2b: /* RASET */ 609 case 0x2c: /* RAMWR */ 610 case 0x2d: /* RGBSET */ 611 case 0x2e: /* RAMRD */ 612 case 0x30: /* PTLAR */ 613 case 0x33: /* SCRLAR */ 614 goto bad_cmd; 615 616 case 0x34: /* TEOFF */ 617 s->te = 0; 618 break; 619 case 0x35: /* TEON */ 620 if (!s->pm) { 621 s->te = 1; 622 } else if (s->pm < 0) { 623 s->pm = 1; 624 } 625 break; 626 627 case 0x36: /* MADCTR */ 628 goto bad_cmd; 629 630 case 0x37: /* VSCSAD */ 631 s->partial = 0; 632 s->normal = 0; 633 s->vscr = 1; 634 break; 635 636 case 0x38: /* IDMOFF */ 637 case 0x39: /* IDMON */ 638 case 0x3a: /* COLMOD */ 639 goto bad_cmd; 640 641 case 0xb0: /* CLKINT / DISCTL */ 642 case 0xb1: /* CLKEXT */ 643 if (s->pm < 0) { 644 s->pm = 2; 645 } 646 break; 647 648 case 0xb4: /* FRMSEL */ 649 break; 650 651 case 0xb5: /* FRM8SEL */ 652 case 0xb6: /* TMPRNG / INIESC */ 653 case 0xb7: /* TMPHIS / NOP2 */ 654 case 0xb8: /* TMPREAD / MADCTL */ 655 case 0xba: /* DISTCTR */ 656 case 0xbb: /* EPVOL */ 657 goto bad_cmd; 658 659 case 0xbd: /* Unknown */ 660 s->p = 0; 661 s->resp[0] = 0; 662 s->resp[1] = 1; 663 break; 664 665 case 0xc2: /* IFMOD */ 666 if (s->pm < 0) { 667 s->pm = 2; 668 } 669 break; 670 671 case 0xc6: /* PWRCTL */ 672 case 0xc7: /* PPWRCTL */ 673 case 0xd0: /* EPWROUT */ 674 case 0xd1: /* EPWRIN */ 675 case 0xd4: /* RDEV */ 676 case 0xd5: /* RDRR */ 677 goto bad_cmd; 678 679 case 0xda: /* RDID1 */ 680 s->p = 0; 681 s->resp[0] = (s->id >> 16) & 0xff; 682 break; 683 case 0xdb: /* RDID2 */ 684 s->p = 0; 685 s->resp[0] = (s->id >> 8) & 0xff; 686 break; 687 case 0xdc: /* RDID3 */ 688 s->p = 0; 689 s->resp[0] = (s->id >> 0) & 0xff; 690 break; 691 692 default: 693 bad_cmd: 694 qemu_log_mask(LOG_GUEST_ERROR, 695 "%s: unknown command %02x\n", __func__, s->cmd); 696 break; 697 } 698 699 return ret; 700 } 701 702 static void *mipid_init(void) 703 { 704 struct mipid_s *s = (struct mipid_s *) g_malloc0(sizeof(*s)); 705 706 s->id = 0x838f03; 707 mipid_reset(s); 708 709 return s; 710 } 711 712 static void n8x0_spi_setup(struct n800_s *s) 713 { 714 void *tsc = s->ts.opaque; 715 void *mipid = mipid_init(); 716 717 omap_mcspi_attach(s->mpu->mcspi[0], s->ts.txrx, tsc, 0); 718 omap_mcspi_attach(s->mpu->mcspi[0], mipid_txrx, mipid, 1); 719 } 720 721 /* This task is normally performed by the bootloader. If we're loading 722 * a kernel directly, we need to enable the Blizzard ourselves. */ 723 static void n800_dss_init(struct rfbi_chip_s *chip) 724 { 725 uint8_t *fb_blank; 726 727 chip->write(chip->opaque, 0, 0x2a); /* LCD Width register */ 728 chip->write(chip->opaque, 1, 0x64); 729 chip->write(chip->opaque, 0, 0x2c); /* LCD HNDP register */ 730 chip->write(chip->opaque, 1, 0x1e); 731 chip->write(chip->opaque, 0, 0x2e); /* LCD Height 0 register */ 732 chip->write(chip->opaque, 1, 0xe0); 733 chip->write(chip->opaque, 0, 0x30); /* LCD Height 1 register */ 734 chip->write(chip->opaque, 1, 0x01); 735 chip->write(chip->opaque, 0, 0x32); /* LCD VNDP register */ 736 chip->write(chip->opaque, 1, 0x06); 737 chip->write(chip->opaque, 0, 0x68); /* Display Mode register */ 738 chip->write(chip->opaque, 1, 1); /* Enable bit */ 739 740 chip->write(chip->opaque, 0, 0x6c); 741 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */ 742 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */ 743 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */ 744 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */ 745 chip->write(chip->opaque, 1, 0x1f); /* Input X End Position */ 746 chip->write(chip->opaque, 1, 0x03); /* Input X End Position */ 747 chip->write(chip->opaque, 1, 0xdf); /* Input Y End Position */ 748 chip->write(chip->opaque, 1, 0x01); /* Input Y End Position */ 749 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */ 750 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */ 751 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */ 752 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */ 753 chip->write(chip->opaque, 1, 0x1f); /* Output X End Position */ 754 chip->write(chip->opaque, 1, 0x03); /* Output X End Position */ 755 chip->write(chip->opaque, 1, 0xdf); /* Output Y End Position */ 756 chip->write(chip->opaque, 1, 0x01); /* Output Y End Position */ 757 chip->write(chip->opaque, 1, 0x01); /* Input Data Format */ 758 chip->write(chip->opaque, 1, 0x01); /* Data Source Select */ 759 760 fb_blank = memset(g_malloc(800 * 480 * 2), 0xff, 800 * 480 * 2); 761 /* Display Memory Data Port */ 762 chip->block(chip->opaque, 1, fb_blank, 800 * 480 * 2, 800); 763 g_free(fb_blank); 764 } 765 766 static void n8x0_dss_setup(struct n800_s *s) 767 { 768 s->blizzard.opaque = s1d13745_init(NULL); 769 s->blizzard.block = s1d13745_write_block; 770 s->blizzard.write = s1d13745_write; 771 s->blizzard.read = s1d13745_read; 772 773 omap_rfbi_attach(s->mpu->dss, 0, &s->blizzard); 774 } 775 776 static void n8x0_cbus_setup(struct n800_s *s) 777 { 778 qemu_irq dat_out = qdev_get_gpio_in(s->mpu->gpio, N8X0_CBUS_DAT_GPIO); 779 qemu_irq retu_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_RETU_GPIO); 780 qemu_irq tahvo_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_TAHVO_GPIO); 781 782 CBus *cbus = cbus_init(dat_out); 783 784 qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_CLK_GPIO, cbus->clk); 785 qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_DAT_GPIO, cbus->dat); 786 qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_SEL_GPIO, cbus->sel); 787 788 cbus_attach(cbus, s->retu = retu_init(retu_irq, 1)); 789 cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1)); 790 } 791 792 static void n8x0_uart_setup(struct n800_s *s) 793 { 794 Chardev *radio = uart_hci_init(); 795 796 qdev_connect_gpio_out(s->mpu->gpio, N8X0_BT_RESET_GPIO, 797 csrhci_pins_get(radio)[csrhci_pin_reset]); 798 qdev_connect_gpio_out(s->mpu->gpio, N8X0_BT_WKUP_GPIO, 799 csrhci_pins_get(radio)[csrhci_pin_wakeup]); 800 801 omap_uart_attach(s->mpu->uart[BT_UART], radio); 802 } 803 804 static void n8x0_usb_setup(struct n800_s *s) 805 { 806 SysBusDevice *dev; 807 s->usb = qdev_create(NULL, "tusb6010"); 808 dev = SYS_BUS_DEVICE(s->usb); 809 qdev_init_nofail(s->usb); 810 sysbus_connect_irq(dev, 0, 811 qdev_get_gpio_in(s->mpu->gpio, N8X0_TUSB_INT_GPIO)); 812 /* Using the NOR interface */ 813 omap_gpmc_attach(s->mpu->gpmc, N8X0_USB_ASYNC_CS, 814 sysbus_mmio_get_region(dev, 0)); 815 omap_gpmc_attach(s->mpu->gpmc, N8X0_USB_SYNC_CS, 816 sysbus_mmio_get_region(dev, 1)); 817 qdev_connect_gpio_out(s->mpu->gpio, N8X0_TUSB_ENABLE_GPIO, 818 qdev_get_gpio_in(s->usb, 0)); /* tusb_pwr */ 819 } 820 821 /* Setup done before the main bootloader starts by some early setup code 822 * - used when we want to run the main bootloader in emulation. This 823 * isn't documented. */ 824 static uint32_t n800_pinout[104] = { 825 0x080f00d8, 0x00d40808, 0x03080808, 0x080800d0, 826 0x00dc0808, 0x0b0f0f00, 0x080800b4, 0x00c00808, 827 0x08080808, 0x180800c4, 0x00b80000, 0x08080808, 828 0x080800bc, 0x00cc0808, 0x08081818, 0x18180128, 829 0x01241800, 0x18181818, 0x000000f0, 0x01300000, 830 0x00001b0b, 0x1b0f0138, 0x00e0181b, 0x1b031b0b, 831 0x180f0078, 0x00740018, 0x0f0f0f1a, 0x00000080, 832 0x007c0000, 0x00000000, 0x00000088, 0x00840000, 833 0x00000000, 0x00000094, 0x00980300, 0x0f180003, 834 0x0000008c, 0x00900f0f, 0x0f0f1b00, 0x0f00009c, 835 0x01140000, 0x1b1b0f18, 0x0818013c, 0x01400008, 836 0x00001818, 0x000b0110, 0x010c1800, 0x0b030b0f, 837 0x181800f4, 0x00f81818, 0x00000018, 0x000000fc, 838 0x00401808, 0x00000000, 0x0f1b0030, 0x003c0008, 839 0x00000000, 0x00000038, 0x00340000, 0x00000000, 840 0x1a080070, 0x00641a1a, 0x08080808, 0x08080060, 841 0x005c0808, 0x08080808, 0x08080058, 0x00540808, 842 0x08080808, 0x0808006c, 0x00680808, 0x08080808, 843 0x000000a8, 0x00b00000, 0x08080808, 0x000000a0, 844 0x00a40000, 0x00000000, 0x08ff0050, 0x004c0808, 845 0xffffffff, 0xffff0048, 0x0044ffff, 0xffffffff, 846 0x000000ac, 0x01040800, 0x08080b0f, 0x18180100, 847 0x01081818, 0x0b0b1808, 0x1a0300e4, 0x012c0b1a, 848 0x02020018, 0x0b000134, 0x011c0800, 0x0b1b1b00, 849 0x0f0000c8, 0x00ec181b, 0x000f0f02, 0x00180118, 850 0x01200000, 0x0f0b1b1b, 0x0f0200e8, 0x0000020b, 851 }; 852 853 static void n800_setup_nolo_tags(void *sram_base) 854 { 855 int i; 856 uint32_t *p = sram_base + 0x8000; 857 uint32_t *v = sram_base + 0xa000; 858 859 memset(p, 0, 0x3000); 860 861 strcpy((void *) (p + 0), "QEMU N800"); 862 863 strcpy((void *) (p + 8), "F5"); 864 865 stl_p(p + 10, 0x04f70000); 866 strcpy((void *) (p + 9), "RX-34"); 867 868 /* RAM size in MB? */ 869 stl_p(p + 12, 0x80); 870 871 /* Pointer to the list of tags */ 872 stl_p(p + 13, OMAP2_SRAM_BASE + 0x9000); 873 874 /* The NOLO tags start here */ 875 p = sram_base + 0x9000; 876 #define ADD_TAG(tag, len) \ 877 stw_p((uint16_t *) p + 0, tag); \ 878 stw_p((uint16_t *) p + 1, len); p++; \ 879 stl_p(p++, OMAP2_SRAM_BASE | (((void *) v - sram_base) & 0xffff)); 880 881 /* OMAP STI console? Pin out settings? */ 882 ADD_TAG(0x6e01, 414); 883 for (i = 0; i < ARRAY_SIZE(n800_pinout); i++) { 884 stl_p(v++, n800_pinout[i]); 885 } 886 887 /* Kernel memsize? */ 888 ADD_TAG(0x6e05, 1); 889 stl_p(v++, 2); 890 891 /* NOLO serial console */ 892 ADD_TAG(0x6e02, 4); 893 stl_p(v++, XLDR_LL_UART); /* UART number (1 - 3) */ 894 895 #if 0 896 /* CBUS settings (Retu/AVilma) */ 897 ADD_TAG(0x6e03, 6); 898 stw_p((uint16_t *) v + 0, 65); /* CBUS GPIO0 */ 899 stw_p((uint16_t *) v + 1, 66); /* CBUS GPIO1 */ 900 stw_p((uint16_t *) v + 2, 64); /* CBUS GPIO2 */ 901 v += 2; 902 #endif 903 904 /* Nokia ASIC BB5 (Retu/Tahvo) */ 905 ADD_TAG(0x6e0a, 4); 906 stw_p((uint16_t *) v + 0, 111); /* "Retu" interrupt GPIO */ 907 stw_p((uint16_t *) v + 1, 108); /* "Tahvo" interrupt GPIO */ 908 v++; 909 910 /* LCD console? */ 911 ADD_TAG(0x6e04, 4); 912 stw_p((uint16_t *) v + 0, 30); /* ??? */ 913 stw_p((uint16_t *) v + 1, 24); /* ??? */ 914 v++; 915 916 #if 0 917 /* LCD settings */ 918 ADD_TAG(0x6e06, 2); 919 stw_p((uint16_t *) (v++), 15); /* ??? */ 920 #endif 921 922 /* I^2C (Menelaus) */ 923 ADD_TAG(0x6e07, 4); 924 stl_p(v++, 0x00720000); /* ??? */ 925 926 /* Unknown */ 927 ADD_TAG(0x6e0b, 6); 928 stw_p((uint16_t *) v + 0, 94); /* ??? */ 929 stw_p((uint16_t *) v + 1, 23); /* ??? */ 930 stw_p((uint16_t *) v + 2, 0); /* ??? */ 931 v += 2; 932 933 /* OMAP gpio switch info */ 934 ADD_TAG(0x6e0c, 80); 935 strcpy((void *) v, "bat_cover"); v += 3; 936 stw_p((uint16_t *) v + 0, 110); /* GPIO num ??? */ 937 stw_p((uint16_t *) v + 1, 1); /* GPIO num ??? */ 938 v += 2; 939 strcpy((void *) v, "cam_act"); v += 3; 940 stw_p((uint16_t *) v + 0, 95); /* GPIO num ??? */ 941 stw_p((uint16_t *) v + 1, 32); /* GPIO num ??? */ 942 v += 2; 943 strcpy((void *) v, "cam_turn"); v += 3; 944 stw_p((uint16_t *) v + 0, 12); /* GPIO num ??? */ 945 stw_p((uint16_t *) v + 1, 33); /* GPIO num ??? */ 946 v += 2; 947 strcpy((void *) v, "headphone"); v += 3; 948 stw_p((uint16_t *) v + 0, 107); /* GPIO num ??? */ 949 stw_p((uint16_t *) v + 1, 17); /* GPIO num ??? */ 950 v += 2; 951 952 /* Bluetooth */ 953 ADD_TAG(0x6e0e, 12); 954 stl_p(v++, 0x5c623d01); /* ??? */ 955 stl_p(v++, 0x00000201); /* ??? */ 956 stl_p(v++, 0x00000000); /* ??? */ 957 958 /* CX3110x WLAN settings */ 959 ADD_TAG(0x6e0f, 8); 960 stl_p(v++, 0x00610025); /* ??? */ 961 stl_p(v++, 0xffff0057); /* ??? */ 962 963 /* MMC host settings */ 964 ADD_TAG(0x6e10, 12); 965 stl_p(v++, 0xffff000f); /* ??? */ 966 stl_p(v++, 0xffffffff); /* ??? */ 967 stl_p(v++, 0x00000060); /* ??? */ 968 969 /* OneNAND chip select */ 970 ADD_TAG(0x6e11, 10); 971 stl_p(v++, 0x00000401); /* ??? */ 972 stl_p(v++, 0x0002003a); /* ??? */ 973 stl_p(v++, 0x00000002); /* ??? */ 974 975 /* TEA5761 sensor settings */ 976 ADD_TAG(0x6e12, 2); 977 stl_p(v++, 93); /* GPIO num ??? */ 978 979 #if 0 980 /* Unknown tag */ 981 ADD_TAG(6e09, 0); 982 983 /* Kernel UART / console */ 984 ADD_TAG(6e12, 0); 985 #endif 986 987 /* End of the list */ 988 stl_p(p++, 0x00000000); 989 stl_p(p++, 0x00000000); 990 } 991 992 /* This task is normally performed by the bootloader. If we're loading 993 * a kernel directly, we need to set up GPMC mappings ourselves. */ 994 static void n800_gpmc_init(struct n800_s *s) 995 { 996 uint32_t config7 = 997 (0xf << 8) | /* MASKADDRESS */ 998 (1 << 6) | /* CSVALID */ 999 (4 << 0); /* BASEADDRESS */ 1000 1001 cpu_physical_memory_write(0x6800a078, /* GPMC_CONFIG7_0 */ 1002 &config7, sizeof(config7)); 1003 } 1004 1005 /* Setup sequence done by the bootloader */ 1006 static void n8x0_boot_init(void *opaque) 1007 { 1008 struct n800_s *s = (struct n800_s *) opaque; 1009 uint32_t buf; 1010 1011 /* PRCM setup */ 1012 #define omap_writel(addr, val) \ 1013 buf = (val); \ 1014 cpu_physical_memory_write(addr, &buf, sizeof(buf)) 1015 1016 omap_writel(0x48008060, 0x41); /* PRCM_CLKSRC_CTRL */ 1017 omap_writel(0x48008070, 1); /* PRCM_CLKOUT_CTRL */ 1018 omap_writel(0x48008078, 0); /* PRCM_CLKEMUL_CTRL */ 1019 omap_writel(0x48008090, 0); /* PRCM_VOLTSETUP */ 1020 omap_writel(0x48008094, 0); /* PRCM_CLKSSETUP */ 1021 omap_writel(0x48008098, 0); /* PRCM_POLCTRL */ 1022 omap_writel(0x48008140, 2); /* CM_CLKSEL_MPU */ 1023 omap_writel(0x48008148, 0); /* CM_CLKSTCTRL_MPU */ 1024 omap_writel(0x48008158, 1); /* RM_RSTST_MPU */ 1025 omap_writel(0x480081c8, 0x15); /* PM_WKDEP_MPU */ 1026 omap_writel(0x480081d4, 0x1d4); /* PM_EVGENCTRL_MPU */ 1027 omap_writel(0x480081d8, 0); /* PM_EVEGENONTIM_MPU */ 1028 omap_writel(0x480081dc, 0); /* PM_EVEGENOFFTIM_MPU */ 1029 omap_writel(0x480081e0, 0xc); /* PM_PWSTCTRL_MPU */ 1030 omap_writel(0x48008200, 0x047e7ff7); /* CM_FCLKEN1_CORE */ 1031 omap_writel(0x48008204, 0x00000004); /* CM_FCLKEN2_CORE */ 1032 omap_writel(0x48008210, 0x047e7ff1); /* CM_ICLKEN1_CORE */ 1033 omap_writel(0x48008214, 0x00000004); /* CM_ICLKEN2_CORE */ 1034 omap_writel(0x4800821c, 0x00000000); /* CM_ICLKEN4_CORE */ 1035 omap_writel(0x48008230, 0); /* CM_AUTOIDLE1_CORE */ 1036 omap_writel(0x48008234, 0); /* CM_AUTOIDLE2_CORE */ 1037 omap_writel(0x48008238, 7); /* CM_AUTOIDLE3_CORE */ 1038 omap_writel(0x4800823c, 0); /* CM_AUTOIDLE4_CORE */ 1039 omap_writel(0x48008240, 0x04360626); /* CM_CLKSEL1_CORE */ 1040 omap_writel(0x48008244, 0x00000014); /* CM_CLKSEL2_CORE */ 1041 omap_writel(0x48008248, 0); /* CM_CLKSTCTRL_CORE */ 1042 omap_writel(0x48008300, 0x00000000); /* CM_FCLKEN_GFX */ 1043 omap_writel(0x48008310, 0x00000000); /* CM_ICLKEN_GFX */ 1044 omap_writel(0x48008340, 0x00000001); /* CM_CLKSEL_GFX */ 1045 omap_writel(0x48008400, 0x00000004); /* CM_FCLKEN_WKUP */ 1046 omap_writel(0x48008410, 0x00000004); /* CM_ICLKEN_WKUP */ 1047 omap_writel(0x48008440, 0x00000000); /* CM_CLKSEL_WKUP */ 1048 omap_writel(0x48008500, 0x000000cf); /* CM_CLKEN_PLL */ 1049 omap_writel(0x48008530, 0x0000000c); /* CM_AUTOIDLE_PLL */ 1050 omap_writel(0x48008540, /* CM_CLKSEL1_PLL */ 1051 (0x78 << 12) | (6 << 8)); 1052 omap_writel(0x48008544, 2); /* CM_CLKSEL2_PLL */ 1053 1054 /* GPMC setup */ 1055 n800_gpmc_init(s); 1056 1057 /* Video setup */ 1058 n800_dss_init(&s->blizzard); 1059 1060 /* CPU setup */ 1061 s->mpu->cpu->env.GE = 0x5; 1062 1063 /* If the machine has a slided keyboard, open it */ 1064 if (s->kbd) { 1065 qemu_irq_raise(qdev_get_gpio_in(s->mpu->gpio, N810_SLIDE_GPIO)); 1066 } 1067 } 1068 1069 #define OMAP_TAG_NOKIA_BT 0x4e01 1070 #define OMAP_TAG_WLAN_CX3110X 0x4e02 1071 #define OMAP_TAG_CBUS 0x4e03 1072 #define OMAP_TAG_EM_ASIC_BB5 0x4e04 1073 1074 static struct omap_gpiosw_info_s { 1075 const char *name; 1076 int line; 1077 int type; 1078 } n800_gpiosw_info[] = { 1079 { 1080 "bat_cover", N800_BAT_COVER_GPIO, 1081 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED, 1082 }, { 1083 "cam_act", N800_CAM_ACT_GPIO, 1084 OMAP_GPIOSW_TYPE_ACTIVITY, 1085 }, { 1086 "cam_turn", N800_CAM_TURN_GPIO, 1087 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED, 1088 }, { 1089 "headphone", N8X0_HEADPHONE_GPIO, 1090 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED, 1091 }, 1092 { NULL } 1093 }, n810_gpiosw_info[] = { 1094 { 1095 "gps_reset", N810_GPS_RESET_GPIO, 1096 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT, 1097 }, { 1098 "gps_wakeup", N810_GPS_WAKEUP_GPIO, 1099 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT, 1100 }, { 1101 "headphone", N8X0_HEADPHONE_GPIO, 1102 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED, 1103 }, { 1104 "kb_lock", N810_KB_LOCK_GPIO, 1105 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED, 1106 }, { 1107 "sleepx_led", N810_SLEEPX_LED_GPIO, 1108 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED | OMAP_GPIOSW_OUTPUT, 1109 }, { 1110 "slide", N810_SLIDE_GPIO, 1111 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED, 1112 }, 1113 { NULL } 1114 }; 1115 1116 static struct omap_partition_info_s { 1117 uint32_t offset; 1118 uint32_t size; 1119 int mask; 1120 const char *name; 1121 } n800_part_info[] = { 1122 { 0x00000000, 0x00020000, 0x3, "bootloader" }, 1123 { 0x00020000, 0x00060000, 0x0, "config" }, 1124 { 0x00080000, 0x00200000, 0x0, "kernel" }, 1125 { 0x00280000, 0x00200000, 0x3, "initfs" }, 1126 { 0x00480000, 0x0fb80000, 0x3, "rootfs" }, 1127 1128 { 0, 0, 0, NULL } 1129 }, n810_part_info[] = { 1130 { 0x00000000, 0x00020000, 0x3, "bootloader" }, 1131 { 0x00020000, 0x00060000, 0x0, "config" }, 1132 { 0x00080000, 0x00220000, 0x0, "kernel" }, 1133 { 0x002a0000, 0x00400000, 0x0, "initfs" }, 1134 { 0x006a0000, 0x0f960000, 0x0, "rootfs" }, 1135 1136 { 0, 0, 0, NULL } 1137 }; 1138 1139 static bdaddr_t n8x0_bd_addr = {{ N8X0_BD_ADDR }}; 1140 1141 static int n8x0_atag_setup(void *p, int model) 1142 { 1143 uint8_t *b; 1144 uint16_t *w; 1145 uint32_t *l; 1146 struct omap_gpiosw_info_s *gpiosw; 1147 struct omap_partition_info_s *partition; 1148 const char *tag; 1149 1150 w = p; 1151 1152 stw_p(w++, OMAP_TAG_UART); /* u16 tag */ 1153 stw_p(w++, 4); /* u16 len */ 1154 stw_p(w++, (1 << 2) | (1 << 1) | (1 << 0)); /* uint enabled_uarts */ 1155 w++; 1156 1157 #if 0 1158 stw_p(w++, OMAP_TAG_SERIAL_CONSOLE); /* u16 tag */ 1159 stw_p(w++, 4); /* u16 len */ 1160 stw_p(w++, XLDR_LL_UART + 1); /* u8 console_uart */ 1161 stw_p(w++, 115200); /* u32 console_speed */ 1162 #endif 1163 1164 stw_p(w++, OMAP_TAG_LCD); /* u16 tag */ 1165 stw_p(w++, 36); /* u16 len */ 1166 strcpy((void *) w, "QEMU LCD panel"); /* char panel_name[16] */ 1167 w += 8; 1168 strcpy((void *) w, "blizzard"); /* char ctrl_name[16] */ 1169 w += 8; 1170 stw_p(w++, N810_BLIZZARD_RESET_GPIO); /* TODO: n800 s16 nreset_gpio */ 1171 stw_p(w++, 24); /* u8 data_lines */ 1172 1173 stw_p(w++, OMAP_TAG_CBUS); /* u16 tag */ 1174 stw_p(w++, 8); /* u16 len */ 1175 stw_p(w++, N8X0_CBUS_CLK_GPIO); /* s16 clk_gpio */ 1176 stw_p(w++, N8X0_CBUS_DAT_GPIO); /* s16 dat_gpio */ 1177 stw_p(w++, N8X0_CBUS_SEL_GPIO); /* s16 sel_gpio */ 1178 w++; 1179 1180 stw_p(w++, OMAP_TAG_EM_ASIC_BB5); /* u16 tag */ 1181 stw_p(w++, 4); /* u16 len */ 1182 stw_p(w++, N8X0_RETU_GPIO); /* s16 retu_irq_gpio */ 1183 stw_p(w++, N8X0_TAHVO_GPIO); /* s16 tahvo_irq_gpio */ 1184 1185 gpiosw = (model == 810) ? n810_gpiosw_info : n800_gpiosw_info; 1186 for (; gpiosw->name; gpiosw++) { 1187 stw_p(w++, OMAP_TAG_GPIO_SWITCH); /* u16 tag */ 1188 stw_p(w++, 20); /* u16 len */ 1189 strcpy((void *) w, gpiosw->name); /* char name[12] */ 1190 w += 6; 1191 stw_p(w++, gpiosw->line); /* u16 gpio */ 1192 stw_p(w++, gpiosw->type); 1193 stw_p(w++, 0); 1194 stw_p(w++, 0); 1195 } 1196 1197 stw_p(w++, OMAP_TAG_NOKIA_BT); /* u16 tag */ 1198 stw_p(w++, 12); /* u16 len */ 1199 b = (void *) w; 1200 stb_p(b++, 0x01); /* u8 chip_type (CSR) */ 1201 stb_p(b++, N8X0_BT_WKUP_GPIO); /* u8 bt_wakeup_gpio */ 1202 stb_p(b++, N8X0_BT_HOST_WKUP_GPIO); /* u8 host_wakeup_gpio */ 1203 stb_p(b++, N8X0_BT_RESET_GPIO); /* u8 reset_gpio */ 1204 stb_p(b++, BT_UART + 1); /* u8 bt_uart */ 1205 memcpy(b, &n8x0_bd_addr, 6); /* u8 bd_addr[6] */ 1206 b += 6; 1207 stb_p(b++, 0x02); /* u8 bt_sysclk (38.4) */ 1208 w = (void *) b; 1209 1210 stw_p(w++, OMAP_TAG_WLAN_CX3110X); /* u16 tag */ 1211 stw_p(w++, 8); /* u16 len */ 1212 stw_p(w++, 0x25); /* u8 chip_type */ 1213 stw_p(w++, N8X0_WLAN_PWR_GPIO); /* s16 power_gpio */ 1214 stw_p(w++, N8X0_WLAN_IRQ_GPIO); /* s16 irq_gpio */ 1215 stw_p(w++, -1); /* s16 spi_cs_gpio */ 1216 1217 stw_p(w++, OMAP_TAG_MMC); /* u16 tag */ 1218 stw_p(w++, 16); /* u16 len */ 1219 if (model == 810) { 1220 stw_p(w++, 0x23f); /* unsigned flags */ 1221 stw_p(w++, -1); /* s16 power_pin */ 1222 stw_p(w++, -1); /* s16 switch_pin */ 1223 stw_p(w++, -1); /* s16 wp_pin */ 1224 stw_p(w++, 0x240); /* unsigned flags */ 1225 stw_p(w++, 0xc000); /* s16 power_pin */ 1226 stw_p(w++, 0x0248); /* s16 switch_pin */ 1227 stw_p(w++, 0xc000); /* s16 wp_pin */ 1228 } else { 1229 stw_p(w++, 0xf); /* unsigned flags */ 1230 stw_p(w++, -1); /* s16 power_pin */ 1231 stw_p(w++, -1); /* s16 switch_pin */ 1232 stw_p(w++, -1); /* s16 wp_pin */ 1233 stw_p(w++, 0); /* unsigned flags */ 1234 stw_p(w++, 0); /* s16 power_pin */ 1235 stw_p(w++, 0); /* s16 switch_pin */ 1236 stw_p(w++, 0); /* s16 wp_pin */ 1237 } 1238 1239 stw_p(w++, OMAP_TAG_TEA5761); /* u16 tag */ 1240 stw_p(w++, 4); /* u16 len */ 1241 stw_p(w++, N8X0_TEA5761_CS_GPIO); /* u16 enable_gpio */ 1242 w++; 1243 1244 partition = (model == 810) ? n810_part_info : n800_part_info; 1245 for (; partition->name; partition++) { 1246 stw_p(w++, OMAP_TAG_PARTITION); /* u16 tag */ 1247 stw_p(w++, 28); /* u16 len */ 1248 strcpy((void *) w, partition->name); /* char name[16] */ 1249 l = (void *) (w + 8); 1250 stl_p(l++, partition->size); /* unsigned int size */ 1251 stl_p(l++, partition->offset); /* unsigned int offset */ 1252 stl_p(l++, partition->mask); /* unsigned int mask_flags */ 1253 w = (void *) l; 1254 } 1255 1256 stw_p(w++, OMAP_TAG_BOOT_REASON); /* u16 tag */ 1257 stw_p(w++, 12); /* u16 len */ 1258 #if 0 1259 strcpy((void *) w, "por"); /* char reason_str[12] */ 1260 strcpy((void *) w, "charger"); /* char reason_str[12] */ 1261 strcpy((void *) w, "32wd_to"); /* char reason_str[12] */ 1262 strcpy((void *) w, "sw_rst"); /* char reason_str[12] */ 1263 strcpy((void *) w, "mbus"); /* char reason_str[12] */ 1264 strcpy((void *) w, "unknown"); /* char reason_str[12] */ 1265 strcpy((void *) w, "swdg_to"); /* char reason_str[12] */ 1266 strcpy((void *) w, "sec_vio"); /* char reason_str[12] */ 1267 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */ 1268 strcpy((void *) w, "rtc_alarm"); /* char reason_str[12] */ 1269 #else 1270 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */ 1271 #endif 1272 w += 6; 1273 1274 tag = (model == 810) ? "RX-44" : "RX-34"; 1275 stw_p(w++, OMAP_TAG_VERSION_STR); /* u16 tag */ 1276 stw_p(w++, 24); /* u16 len */ 1277 strcpy((void *) w, "product"); /* char component[12] */ 1278 w += 6; 1279 strcpy((void *) w, tag); /* char version[12] */ 1280 w += 6; 1281 1282 stw_p(w++, OMAP_TAG_VERSION_STR); /* u16 tag */ 1283 stw_p(w++, 24); /* u16 len */ 1284 strcpy((void *) w, "hw-build"); /* char component[12] */ 1285 w += 6; 1286 strcpy((void *) w, "QEMU "); 1287 pstrcat((void *) w, 12, qemu_hw_version()); /* char version[12] */ 1288 w += 6; 1289 1290 tag = (model == 810) ? "1.1.10-qemu" : "1.1.6-qemu"; 1291 stw_p(w++, OMAP_TAG_VERSION_STR); /* u16 tag */ 1292 stw_p(w++, 24); /* u16 len */ 1293 strcpy((void *) w, "nolo"); /* char component[12] */ 1294 w += 6; 1295 strcpy((void *) w, tag); /* char version[12] */ 1296 w += 6; 1297 1298 return (void *) w - p; 1299 } 1300 1301 static int n800_atag_setup(const struct arm_boot_info *info, void *p) 1302 { 1303 return n8x0_atag_setup(p, 800); 1304 } 1305 1306 static int n810_atag_setup(const struct arm_boot_info *info, void *p) 1307 { 1308 return n8x0_atag_setup(p, 810); 1309 } 1310 1311 static void n8x0_init(MachineState *machine, 1312 struct arm_boot_info *binfo, int model) 1313 { 1314 MemoryRegion *sysmem = get_system_memory(); 1315 struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s)); 1316 int sdram_size = binfo->ram_size; 1317 1318 s->mpu = omap2420_mpu_init(sysmem, sdram_size, machine->cpu_type); 1319 1320 /* Setup peripherals 1321 * 1322 * Believed external peripherals layout in the N810: 1323 * (spi bus 1) 1324 * tsc2005 1325 * lcd_mipid 1326 * (spi bus 2) 1327 * Conexant cx3110x (WLAN) 1328 * optional: pc2400m (WiMAX) 1329 * (i2c bus 0) 1330 * TLV320AIC33 (audio codec) 1331 * TCM825x (camera by Toshiba) 1332 * lp5521 (clever LEDs) 1333 * tsl2563 (light sensor, hwmon, model 7, rev. 0) 1334 * lm8323 (keypad, manf 00, rev 04) 1335 * (i2c bus 1) 1336 * tmp105 (temperature sensor, hwmon) 1337 * menelaus (pm) 1338 * (somewhere on i2c - maybe N800-only) 1339 * tea5761 (FM tuner) 1340 * (serial 0) 1341 * GPS 1342 * (some serial port) 1343 * csr41814 (Bluetooth) 1344 */ 1345 n8x0_gpio_setup(s); 1346 n8x0_nand_setup(s); 1347 n8x0_i2c_setup(s); 1348 if (model == 800) { 1349 n800_tsc_kbd_setup(s); 1350 } else if (model == 810) { 1351 n810_tsc_setup(s); 1352 n810_kbd_setup(s); 1353 } 1354 n8x0_spi_setup(s); 1355 n8x0_dss_setup(s); 1356 n8x0_cbus_setup(s); 1357 n8x0_uart_setup(s); 1358 if (machine_usb(machine)) { 1359 n8x0_usb_setup(s); 1360 } 1361 1362 if (machine->kernel_filename) { 1363 /* Or at the linux loader. */ 1364 arm_load_kernel(s->mpu->cpu, machine, binfo); 1365 1366 qemu_register_reset(n8x0_boot_init, s); 1367 } 1368 1369 if (option_rom[0].name && 1370 (machine->boot_order[0] == 'n' || !machine->kernel_filename)) { 1371 uint8_t *nolo_tags = g_new(uint8_t, 0x10000); 1372 /* No, wait, better start at the ROM. */ 1373 s->mpu->cpu->env.regs[15] = OMAP2_Q2_BASE + 0x400000; 1374 1375 /* This is intended for loading the `secondary.bin' program from 1376 * Nokia images (the NOLO bootloader). The entry point seems 1377 * to be at OMAP2_Q2_BASE + 0x400000. 1378 * 1379 * The `2nd.bin' files contain some kind of earlier boot code and 1380 * for them the entry point needs to be set to OMAP2_SRAM_BASE. 1381 * 1382 * The code above is for loading the `zImage' file from Nokia 1383 * images. */ 1384 load_image_targphys(option_rom[0].name, 1385 OMAP2_Q2_BASE + 0x400000, 1386 sdram_size - 0x400000); 1387 1388 n800_setup_nolo_tags(nolo_tags); 1389 cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000); 1390 g_free(nolo_tags); 1391 } 1392 } 1393 1394 static struct arm_boot_info n800_binfo = { 1395 .loader_start = OMAP2_Q2_BASE, 1396 /* Actually two chips of 0x4000000 bytes each */ 1397 .ram_size = 0x08000000, 1398 .board_id = 0x4f7, 1399 .atag_board = n800_atag_setup, 1400 }; 1401 1402 static struct arm_boot_info n810_binfo = { 1403 .loader_start = OMAP2_Q2_BASE, 1404 /* Actually two chips of 0x4000000 bytes each */ 1405 .ram_size = 0x08000000, 1406 /* 0x60c and 0x6bf (WiMAX Edition) have been assigned but are not 1407 * used by some older versions of the bootloader and 5555 is used 1408 * instead (including versions that shipped with many devices). */ 1409 .board_id = 0x60c, 1410 .atag_board = n810_atag_setup, 1411 }; 1412 1413 static void n800_init(MachineState *machine) 1414 { 1415 n8x0_init(machine, &n800_binfo, 800); 1416 } 1417 1418 static void n810_init(MachineState *machine) 1419 { 1420 n8x0_init(machine, &n810_binfo, 810); 1421 } 1422 1423 static void n800_class_init(ObjectClass *oc, void *data) 1424 { 1425 MachineClass *mc = MACHINE_CLASS(oc); 1426 1427 mc->desc = "Nokia N800 tablet aka. RX-34 (OMAP2420)"; 1428 mc->init = n800_init; 1429 mc->default_boot_order = ""; 1430 mc->ignore_memory_transaction_failures = true; 1431 mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm1136-r2"); 1432 } 1433 1434 static const TypeInfo n800_type = { 1435 .name = MACHINE_TYPE_NAME("n800"), 1436 .parent = TYPE_MACHINE, 1437 .class_init = n800_class_init, 1438 }; 1439 1440 static void n810_class_init(ObjectClass *oc, void *data) 1441 { 1442 MachineClass *mc = MACHINE_CLASS(oc); 1443 1444 mc->desc = "Nokia N810 tablet aka. RX-44 (OMAP2420)"; 1445 mc->init = n810_init; 1446 mc->default_boot_order = ""; 1447 mc->ignore_memory_transaction_failures = true; 1448 mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm1136-r2"); 1449 } 1450 1451 static const TypeInfo n810_type = { 1452 .name = MACHINE_TYPE_NAME("n810"), 1453 .parent = TYPE_MACHINE, 1454 .class_init = n810_class_init, 1455 }; 1456 1457 static void nseries_machine_init(void) 1458 { 1459 type_register_static(&n800_type); 1460 type_register_static(&n810_type); 1461 } 1462 1463 type_init(nseries_machine_init) 1464