1 /* 2 * Nokia N-series internet tablets. 3 * 4 * Copyright (C) 2007 Nokia Corporation 5 * Written by Andrzej Zaborowski <andrew@openedhand.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 or 10 * (at your option) version 3 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "cpu.h" 24 #include "qemu/cutils.h" 25 #include "qemu/bswap.h" 26 #include "sysemu/reset.h" 27 #include "sysemu/sysemu.h" 28 #include "hw/arm/omap.h" 29 #include "hw/arm/boot.h" 30 #include "hw/irq.h" 31 #include "ui/console.h" 32 #include "hw/boards.h" 33 #include "hw/i2c/i2c.h" 34 #include "hw/display/blizzard.h" 35 #include "hw/input/tsc2xxx.h" 36 #include "hw/misc/cbus.h" 37 #include "hw/misc/tmp105.h" 38 #include "hw/block/flash.h" 39 #include "hw/hw.h" 40 #include "hw/bt.h" 41 #include "hw/loader.h" 42 #include "hw/sysbus.h" 43 #include "qemu/log.h" 44 #include "exec/address-spaces.h" 45 46 /* Nokia N8x0 support */ 47 struct n800_s { 48 struct omap_mpu_state_s *mpu; 49 50 struct rfbi_chip_s blizzard; 51 struct { 52 void *opaque; 53 uint32_t (*txrx)(void *opaque, uint32_t value, int len); 54 uWireSlave *chip; 55 } ts; 56 57 int keymap[0x80]; 58 DeviceState *kbd; 59 60 DeviceState *usb; 61 void *retu; 62 void *tahvo; 63 DeviceState *nand; 64 }; 65 66 /* GPIO pins */ 67 #define N8X0_TUSB_ENABLE_GPIO 0 68 #define N800_MMC2_WP_GPIO 8 69 #define N800_UNKNOWN_GPIO0 9 /* out */ 70 #define N810_MMC2_VIOSD_GPIO 9 71 #define N810_HEADSET_AMP_GPIO 10 72 #define N800_CAM_TURN_GPIO 12 73 #define N810_GPS_RESET_GPIO 12 74 #define N800_BLIZZARD_POWERDOWN_GPIO 15 75 #define N800_MMC1_WP_GPIO 23 76 #define N810_MMC2_VSD_GPIO 23 77 #define N8X0_ONENAND_GPIO 26 78 #define N810_BLIZZARD_RESET_GPIO 30 79 #define N800_UNKNOWN_GPIO2 53 /* out */ 80 #define N8X0_TUSB_INT_GPIO 58 81 #define N8X0_BT_WKUP_GPIO 61 82 #define N8X0_STI_GPIO 62 83 #define N8X0_CBUS_SEL_GPIO 64 84 #define N8X0_CBUS_DAT_GPIO 65 85 #define N8X0_CBUS_CLK_GPIO 66 86 #define N8X0_WLAN_IRQ_GPIO 87 87 #define N8X0_BT_RESET_GPIO 92 88 #define N8X0_TEA5761_CS_GPIO 93 89 #define N800_UNKNOWN_GPIO 94 90 #define N810_TSC_RESET_GPIO 94 91 #define N800_CAM_ACT_GPIO 95 92 #define N810_GPS_WAKEUP_GPIO 95 93 #define N8X0_MMC_CS_GPIO 96 94 #define N8X0_WLAN_PWR_GPIO 97 95 #define N8X0_BT_HOST_WKUP_GPIO 98 96 #define N810_SPEAKER_AMP_GPIO 101 97 #define N810_KB_LOCK_GPIO 102 98 #define N800_TSC_TS_GPIO 103 99 #define N810_TSC_TS_GPIO 106 100 #define N8X0_HEADPHONE_GPIO 107 101 #define N8X0_RETU_GPIO 108 102 #define N800_TSC_KP_IRQ_GPIO 109 103 #define N810_KEYBOARD_GPIO 109 104 #define N800_BAT_COVER_GPIO 110 105 #define N810_SLIDE_GPIO 110 106 #define N8X0_TAHVO_GPIO 111 107 #define N800_UNKNOWN_GPIO4 112 /* out */ 108 #define N810_SLEEPX_LED_GPIO 112 109 #define N800_TSC_RESET_GPIO 118 /* ? */ 110 #define N810_AIC33_RESET_GPIO 118 111 #define N800_TSC_UNKNOWN_GPIO 119 /* out */ 112 #define N8X0_TMP105_GPIO 125 113 114 /* Config */ 115 #define BT_UART 0 116 #define XLDR_LL_UART 1 117 118 /* Addresses on the I2C bus 0 */ 119 #define N810_TLV320AIC33_ADDR 0x18 /* Audio CODEC */ 120 #define N8X0_TCM825x_ADDR 0x29 /* Camera */ 121 #define N810_LP5521_ADDR 0x32 /* LEDs */ 122 #define N810_TSL2563_ADDR 0x3d /* Light sensor */ 123 #define N810_LM8323_ADDR 0x45 /* Keyboard */ 124 /* Addresses on the I2C bus 1 */ 125 #define N8X0_TMP105_ADDR 0x48 /* Temperature sensor */ 126 #define N8X0_MENELAUS_ADDR 0x72 /* Power management */ 127 128 /* Chipselects on GPMC NOR interface */ 129 #define N8X0_ONENAND_CS 0 130 #define N8X0_USB_ASYNC_CS 1 131 #define N8X0_USB_SYNC_CS 4 132 133 #define N8X0_BD_ADDR 0x00, 0x1a, 0x89, 0x9e, 0x3e, 0x81 134 135 static void n800_mmc_cs_cb(void *opaque, int line, int level) 136 { 137 /* TODO: this seems to actually be connected to the menelaus, to 138 * which also both MMC slots connect. */ 139 omap_mmc_enable((struct omap_mmc_s *) opaque, !level); 140 } 141 142 static void n8x0_gpio_setup(struct n800_s *s) 143 { 144 qdev_connect_gpio_out(s->mpu->gpio, N8X0_MMC_CS_GPIO, 145 qemu_allocate_irq(n800_mmc_cs_cb, s->mpu->mmc, 0)); 146 qemu_irq_lower(qdev_get_gpio_in(s->mpu->gpio, N800_BAT_COVER_GPIO)); 147 } 148 149 #define MAEMO_CAL_HEADER(...) \ 150 'C', 'o', 'n', 'F', 0x02, 0x00, 0x04, 0x00, \ 151 __VA_ARGS__, \ 152 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 153 154 static const uint8_t n8x0_cal_wlan_mac[] = { 155 MAEMO_CAL_HEADER('w', 'l', 'a', 'n', '-', 'm', 'a', 'c') 156 0x1c, 0x00, 0x00, 0x00, 0x47, 0xd6, 0x69, 0xb3, 157 0x30, 0x08, 0xa0, 0x83, 0x00, 0x00, 0x00, 0x00, 158 0x00, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00, 159 0x89, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00, 0x00, 160 0x5d, 0x00, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 161 }; 162 163 static const uint8_t n8x0_cal_bt_id[] = { 164 MAEMO_CAL_HEADER('b', 't', '-', 'i', 'd', 0, 0, 0) 165 0x0a, 0x00, 0x00, 0x00, 0xa3, 0x4b, 0xf6, 0x96, 166 0xa8, 0xeb, 0xb2, 0x41, 0x00, 0x00, 0x00, 0x00, 167 N8X0_BD_ADDR, 168 }; 169 170 static void n8x0_nand_setup(struct n800_s *s) 171 { 172 char *otp_region; 173 DriveInfo *dinfo; 174 175 s->nand = qdev_create(NULL, "onenand"); 176 qdev_prop_set_uint16(s->nand, "manufacturer_id", NAND_MFR_SAMSUNG); 177 /* Either 0x40 or 0x48 are OK for the device ID */ 178 qdev_prop_set_uint16(s->nand, "device_id", 0x48); 179 qdev_prop_set_uint16(s->nand, "version_id", 0); 180 qdev_prop_set_int32(s->nand, "shift", 1); 181 dinfo = drive_get(IF_MTD, 0, 0); 182 if (dinfo) { 183 qdev_prop_set_drive(s->nand, "drive", blk_by_legacy_dinfo(dinfo), 184 &error_fatal); 185 } 186 qdev_init_nofail(s->nand); 187 sysbus_connect_irq(SYS_BUS_DEVICE(s->nand), 0, 188 qdev_get_gpio_in(s->mpu->gpio, N8X0_ONENAND_GPIO)); 189 omap_gpmc_attach(s->mpu->gpmc, N8X0_ONENAND_CS, 190 sysbus_mmio_get_region(SYS_BUS_DEVICE(s->nand), 0)); 191 otp_region = onenand_raw_otp(s->nand); 192 193 memcpy(otp_region + 0x000, n8x0_cal_wlan_mac, sizeof(n8x0_cal_wlan_mac)); 194 memcpy(otp_region + 0x800, n8x0_cal_bt_id, sizeof(n8x0_cal_bt_id)); 195 /* XXX: in theory should also update the OOB for both pages */ 196 } 197 198 static qemu_irq n8x0_system_powerdown; 199 200 static void n8x0_powerdown_req(Notifier *n, void *opaque) 201 { 202 qemu_irq_raise(n8x0_system_powerdown); 203 } 204 205 static Notifier n8x0_system_powerdown_notifier = { 206 .notify = n8x0_powerdown_req 207 }; 208 209 static void n8x0_i2c_setup(struct n800_s *s) 210 { 211 DeviceState *dev; 212 qemu_irq tmp_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_TMP105_GPIO); 213 I2CBus *i2c = omap_i2c_bus(s->mpu->i2c[0]); 214 215 /* Attach a menelaus PM chip */ 216 dev = i2c_create_slave(i2c, "twl92230", N8X0_MENELAUS_ADDR); 217 qdev_connect_gpio_out(dev, 3, 218 qdev_get_gpio_in(s->mpu->ih[0], 219 OMAP_INT_24XX_SYS_NIRQ)); 220 221 n8x0_system_powerdown = qdev_get_gpio_in(dev, 3); 222 qemu_register_powerdown_notifier(&n8x0_system_powerdown_notifier); 223 224 /* Attach a TMP105 PM chip (A0 wired to ground) */ 225 dev = i2c_create_slave(i2c, TYPE_TMP105, N8X0_TMP105_ADDR); 226 qdev_connect_gpio_out(dev, 0, tmp_irq); 227 } 228 229 /* Touchscreen and keypad controller */ 230 static MouseTransformInfo n800_pointercal = { 231 .x = 800, 232 .y = 480, 233 .a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 }, 234 }; 235 236 static MouseTransformInfo n810_pointercal = { 237 .x = 800, 238 .y = 480, 239 .a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 }, 240 }; 241 242 #define RETU_KEYCODE 61 /* F3 */ 243 244 static void n800_key_event(void *opaque, int keycode) 245 { 246 struct n800_s *s = (struct n800_s *) opaque; 247 int code = s->keymap[keycode & 0x7f]; 248 249 if (code == -1) { 250 if ((keycode & 0x7f) == RETU_KEYCODE) { 251 retu_key_event(s->retu, !(keycode & 0x80)); 252 } 253 return; 254 } 255 256 tsc210x_key_event(s->ts.chip, code, !(keycode & 0x80)); 257 } 258 259 static const int n800_keys[16] = { 260 -1, 261 72, /* Up */ 262 63, /* Home (F5) */ 263 -1, 264 75, /* Left */ 265 28, /* Enter */ 266 77, /* Right */ 267 -1, 268 1, /* Cycle (ESC) */ 269 80, /* Down */ 270 62, /* Menu (F4) */ 271 -1, 272 66, /* Zoom- (F8) */ 273 64, /* FullScreen (F6) */ 274 65, /* Zoom+ (F7) */ 275 -1, 276 }; 277 278 static void n800_tsc_kbd_setup(struct n800_s *s) 279 { 280 int i; 281 282 /* XXX: are the three pins inverted inside the chip between the 283 * tsc and the cpu (N4111)? */ 284 qemu_irq penirq = NULL; /* NC */ 285 qemu_irq kbirq = qdev_get_gpio_in(s->mpu->gpio, N800_TSC_KP_IRQ_GPIO); 286 qemu_irq dav = qdev_get_gpio_in(s->mpu->gpio, N800_TSC_TS_GPIO); 287 288 s->ts.chip = tsc2301_init(penirq, kbirq, dav); 289 s->ts.opaque = s->ts.chip->opaque; 290 s->ts.txrx = tsc210x_txrx; 291 292 for (i = 0; i < 0x80; i++) { 293 s->keymap[i] = -1; 294 } 295 for (i = 0; i < 0x10; i++) { 296 if (n800_keys[i] >= 0) { 297 s->keymap[n800_keys[i]] = i; 298 } 299 } 300 301 qemu_add_kbd_event_handler(n800_key_event, s); 302 303 tsc210x_set_transform(s->ts.chip, &n800_pointercal); 304 } 305 306 static void n810_tsc_setup(struct n800_s *s) 307 { 308 qemu_irq pintdav = qdev_get_gpio_in(s->mpu->gpio, N810_TSC_TS_GPIO); 309 310 s->ts.opaque = tsc2005_init(pintdav); 311 s->ts.txrx = tsc2005_txrx; 312 313 tsc2005_set_transform(s->ts.opaque, &n810_pointercal); 314 } 315 316 /* N810 Keyboard controller */ 317 static void n810_key_event(void *opaque, int keycode) 318 { 319 struct n800_s *s = (struct n800_s *) opaque; 320 int code = s->keymap[keycode & 0x7f]; 321 322 if (code == -1) { 323 if ((keycode & 0x7f) == RETU_KEYCODE) { 324 retu_key_event(s->retu, !(keycode & 0x80)); 325 } 326 return; 327 } 328 329 lm832x_key_event(s->kbd, code, !(keycode & 0x80)); 330 } 331 332 #define M 0 333 334 static int n810_keys[0x80] = { 335 [0x01] = 16, /* Q */ 336 [0x02] = 37, /* K */ 337 [0x03] = 24, /* O */ 338 [0x04] = 25, /* P */ 339 [0x05] = 14, /* Backspace */ 340 [0x06] = 30, /* A */ 341 [0x07] = 31, /* S */ 342 [0x08] = 32, /* D */ 343 [0x09] = 33, /* F */ 344 [0x0a] = 34, /* G */ 345 [0x0b] = 35, /* H */ 346 [0x0c] = 36, /* J */ 347 348 [0x11] = 17, /* W */ 349 [0x12] = 62, /* Menu (F4) */ 350 [0x13] = 38, /* L */ 351 [0x14] = 40, /* ' (Apostrophe) */ 352 [0x16] = 44, /* Z */ 353 [0x17] = 45, /* X */ 354 [0x18] = 46, /* C */ 355 [0x19] = 47, /* V */ 356 [0x1a] = 48, /* B */ 357 [0x1b] = 49, /* N */ 358 [0x1c] = 42, /* Shift (Left shift) */ 359 [0x1f] = 65, /* Zoom+ (F7) */ 360 361 [0x21] = 18, /* E */ 362 [0x22] = 39, /* ; (Semicolon) */ 363 [0x23] = 12, /* - (Minus) */ 364 [0x24] = 13, /* = (Equal) */ 365 [0x2b] = 56, /* Fn (Left Alt) */ 366 [0x2c] = 50, /* M */ 367 [0x2f] = 66, /* Zoom- (F8) */ 368 369 [0x31] = 19, /* R */ 370 [0x32] = 29 | M, /* Right Ctrl */ 371 [0x34] = 57, /* Space */ 372 [0x35] = 51, /* , (Comma) */ 373 [0x37] = 72 | M, /* Up */ 374 [0x3c] = 82 | M, /* Compose (Insert) */ 375 [0x3f] = 64, /* FullScreen (F6) */ 376 377 [0x41] = 20, /* T */ 378 [0x44] = 52, /* . (Dot) */ 379 [0x46] = 77 | M, /* Right */ 380 [0x4f] = 63, /* Home (F5) */ 381 [0x51] = 21, /* Y */ 382 [0x53] = 80 | M, /* Down */ 383 [0x55] = 28, /* Enter */ 384 [0x5f] = 1, /* Cycle (ESC) */ 385 386 [0x61] = 22, /* U */ 387 [0x64] = 75 | M, /* Left */ 388 389 [0x71] = 23, /* I */ 390 #if 0 391 [0x75] = 28 | M, /* KP Enter (KP Enter) */ 392 #else 393 [0x75] = 15, /* KP Enter (Tab) */ 394 #endif 395 }; 396 397 #undef M 398 399 static void n810_kbd_setup(struct n800_s *s) 400 { 401 qemu_irq kbd_irq = qdev_get_gpio_in(s->mpu->gpio, N810_KEYBOARD_GPIO); 402 int i; 403 404 for (i = 0; i < 0x80; i++) { 405 s->keymap[i] = -1; 406 } 407 for (i = 0; i < 0x80; i++) { 408 if (n810_keys[i] > 0) { 409 s->keymap[n810_keys[i]] = i; 410 } 411 } 412 413 qemu_add_kbd_event_handler(n810_key_event, s); 414 415 /* Attach the LM8322 keyboard to the I2C bus, 416 * should happen in n8x0_i2c_setup and s->kbd be initialised here. */ 417 s->kbd = i2c_create_slave(omap_i2c_bus(s->mpu->i2c[0]), 418 "lm8323", N810_LM8323_ADDR); 419 qdev_connect_gpio_out(s->kbd, 0, kbd_irq); 420 } 421 422 /* LCD MIPI DBI-C controller (URAL) */ 423 struct mipid_s { 424 int resp[4]; 425 int param[4]; 426 int p; 427 int pm; 428 int cmd; 429 430 int sleep; 431 int booster; 432 int te; 433 int selfcheck; 434 int partial; 435 int normal; 436 int vscr; 437 int invert; 438 int onoff; 439 int gamma; 440 uint32_t id; 441 }; 442 443 static void mipid_reset(struct mipid_s *s) 444 { 445 s->pm = 0; 446 s->cmd = 0; 447 448 s->sleep = 1; 449 s->booster = 0; 450 s->selfcheck = 451 (1 << 7) | /* Register loading OK. */ 452 (1 << 5) | /* The chip is attached. */ 453 (1 << 4); /* Display glass still in one piece. */ 454 s->te = 0; 455 s->partial = 0; 456 s->normal = 1; 457 s->vscr = 0; 458 s->invert = 0; 459 s->onoff = 1; 460 s->gamma = 0; 461 } 462 463 static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len) 464 { 465 struct mipid_s *s = (struct mipid_s *) opaque; 466 uint8_t ret; 467 468 if (len > 9) { 469 hw_error("%s: FIXME: bad SPI word width %i\n", __func__, len); 470 } 471 472 if (s->p >= ARRAY_SIZE(s->resp)) { 473 ret = 0; 474 } else { 475 ret = s->resp[s->p++]; 476 } 477 if (s->pm-- > 0) { 478 s->param[s->pm] = cmd; 479 } else { 480 s->cmd = cmd; 481 } 482 483 switch (s->cmd) { 484 case 0x00: /* NOP */ 485 break; 486 487 case 0x01: /* SWRESET */ 488 mipid_reset(s); 489 break; 490 491 case 0x02: /* BSTROFF */ 492 s->booster = 0; 493 break; 494 case 0x03: /* BSTRON */ 495 s->booster = 1; 496 break; 497 498 case 0x04: /* RDDID */ 499 s->p = 0; 500 s->resp[0] = (s->id >> 16) & 0xff; 501 s->resp[1] = (s->id >> 8) & 0xff; 502 s->resp[2] = (s->id >> 0) & 0xff; 503 break; 504 505 case 0x06: /* RD_RED */ 506 case 0x07: /* RD_GREEN */ 507 /* XXX the bootloader sometimes issues RD_BLUE meaning RDDID so 508 * for the bootloader one needs to change this. */ 509 case 0x08: /* RD_BLUE */ 510 s->p = 0; 511 /* TODO: return first pixel components */ 512 s->resp[0] = 0x01; 513 break; 514 515 case 0x09: /* RDDST */ 516 s->p = 0; 517 s->resp[0] = s->booster << 7; 518 s->resp[1] = (5 << 4) | (s->partial << 2) | 519 (s->sleep << 1) | s->normal; 520 s->resp[2] = (s->vscr << 7) | (s->invert << 5) | 521 (s->onoff << 2) | (s->te << 1) | (s->gamma >> 2); 522 s->resp[3] = s->gamma << 6; 523 break; 524 525 case 0x0a: /* RDDPM */ 526 s->p = 0; 527 s->resp[0] = (s->onoff << 2) | (s->normal << 3) | (s->sleep << 4) | 528 (s->partial << 5) | (s->sleep << 6) | (s->booster << 7); 529 break; 530 case 0x0b: /* RDDMADCTR */ 531 s->p = 0; 532 s->resp[0] = 0; 533 break; 534 case 0x0c: /* RDDCOLMOD */ 535 s->p = 0; 536 s->resp[0] = 5; /* 65K colours */ 537 break; 538 case 0x0d: /* RDDIM */ 539 s->p = 0; 540 s->resp[0] = (s->invert << 5) | (s->vscr << 7) | s->gamma; 541 break; 542 case 0x0e: /* RDDSM */ 543 s->p = 0; 544 s->resp[0] = s->te << 7; 545 break; 546 case 0x0f: /* RDDSDR */ 547 s->p = 0; 548 s->resp[0] = s->selfcheck; 549 break; 550 551 case 0x10: /* SLPIN */ 552 s->sleep = 1; 553 break; 554 case 0x11: /* SLPOUT */ 555 s->sleep = 0; 556 s->selfcheck ^= 1 << 6; /* POFF self-diagnosis Ok */ 557 break; 558 559 case 0x12: /* PTLON */ 560 s->partial = 1; 561 s->normal = 0; 562 s->vscr = 0; 563 break; 564 case 0x13: /* NORON */ 565 s->partial = 0; 566 s->normal = 1; 567 s->vscr = 0; 568 break; 569 570 case 0x20: /* INVOFF */ 571 s->invert = 0; 572 break; 573 case 0x21: /* INVON */ 574 s->invert = 1; 575 break; 576 577 case 0x22: /* APOFF */ 578 case 0x23: /* APON */ 579 goto bad_cmd; 580 581 case 0x25: /* WRCNTR */ 582 if (s->pm < 0) { 583 s->pm = 1; 584 } 585 goto bad_cmd; 586 587 case 0x26: /* GAMSET */ 588 if (!s->pm) { 589 s->gamma = ctz32(s->param[0] & 0xf); 590 if (s->gamma == 32) { 591 s->gamma = -1; /* XXX: should this be 0? */ 592 } 593 } else if (s->pm < 0) { 594 s->pm = 1; 595 } 596 break; 597 598 case 0x28: /* DISPOFF */ 599 s->onoff = 0; 600 break; 601 case 0x29: /* DISPON */ 602 s->onoff = 1; 603 break; 604 605 case 0x2a: /* CASET */ 606 case 0x2b: /* RASET */ 607 case 0x2c: /* RAMWR */ 608 case 0x2d: /* RGBSET */ 609 case 0x2e: /* RAMRD */ 610 case 0x30: /* PTLAR */ 611 case 0x33: /* SCRLAR */ 612 goto bad_cmd; 613 614 case 0x34: /* TEOFF */ 615 s->te = 0; 616 break; 617 case 0x35: /* TEON */ 618 if (!s->pm) { 619 s->te = 1; 620 } else if (s->pm < 0) { 621 s->pm = 1; 622 } 623 break; 624 625 case 0x36: /* MADCTR */ 626 goto bad_cmd; 627 628 case 0x37: /* VSCSAD */ 629 s->partial = 0; 630 s->normal = 0; 631 s->vscr = 1; 632 break; 633 634 case 0x38: /* IDMOFF */ 635 case 0x39: /* IDMON */ 636 case 0x3a: /* COLMOD */ 637 goto bad_cmd; 638 639 case 0xb0: /* CLKINT / DISCTL */ 640 case 0xb1: /* CLKEXT */ 641 if (s->pm < 0) { 642 s->pm = 2; 643 } 644 break; 645 646 case 0xb4: /* FRMSEL */ 647 break; 648 649 case 0xb5: /* FRM8SEL */ 650 case 0xb6: /* TMPRNG / INIESC */ 651 case 0xb7: /* TMPHIS / NOP2 */ 652 case 0xb8: /* TMPREAD / MADCTL */ 653 case 0xba: /* DISTCTR */ 654 case 0xbb: /* EPVOL */ 655 goto bad_cmd; 656 657 case 0xbd: /* Unknown */ 658 s->p = 0; 659 s->resp[0] = 0; 660 s->resp[1] = 1; 661 break; 662 663 case 0xc2: /* IFMOD */ 664 if (s->pm < 0) { 665 s->pm = 2; 666 } 667 break; 668 669 case 0xc6: /* PWRCTL */ 670 case 0xc7: /* PPWRCTL */ 671 case 0xd0: /* EPWROUT */ 672 case 0xd1: /* EPWRIN */ 673 case 0xd4: /* RDEV */ 674 case 0xd5: /* RDRR */ 675 goto bad_cmd; 676 677 case 0xda: /* RDID1 */ 678 s->p = 0; 679 s->resp[0] = (s->id >> 16) & 0xff; 680 break; 681 case 0xdb: /* RDID2 */ 682 s->p = 0; 683 s->resp[0] = (s->id >> 8) & 0xff; 684 break; 685 case 0xdc: /* RDID3 */ 686 s->p = 0; 687 s->resp[0] = (s->id >> 0) & 0xff; 688 break; 689 690 default: 691 bad_cmd: 692 qemu_log_mask(LOG_GUEST_ERROR, 693 "%s: unknown command %02x\n", __func__, s->cmd); 694 break; 695 } 696 697 return ret; 698 } 699 700 static void *mipid_init(void) 701 { 702 struct mipid_s *s = (struct mipid_s *) g_malloc0(sizeof(*s)); 703 704 s->id = 0x838f03; 705 mipid_reset(s); 706 707 return s; 708 } 709 710 static void n8x0_spi_setup(struct n800_s *s) 711 { 712 void *tsc = s->ts.opaque; 713 void *mipid = mipid_init(); 714 715 omap_mcspi_attach(s->mpu->mcspi[0], s->ts.txrx, tsc, 0); 716 omap_mcspi_attach(s->mpu->mcspi[0], mipid_txrx, mipid, 1); 717 } 718 719 /* This task is normally performed by the bootloader. If we're loading 720 * a kernel directly, we need to enable the Blizzard ourselves. */ 721 static void n800_dss_init(struct rfbi_chip_s *chip) 722 { 723 uint8_t *fb_blank; 724 725 chip->write(chip->opaque, 0, 0x2a); /* LCD Width register */ 726 chip->write(chip->opaque, 1, 0x64); 727 chip->write(chip->opaque, 0, 0x2c); /* LCD HNDP register */ 728 chip->write(chip->opaque, 1, 0x1e); 729 chip->write(chip->opaque, 0, 0x2e); /* LCD Height 0 register */ 730 chip->write(chip->opaque, 1, 0xe0); 731 chip->write(chip->opaque, 0, 0x30); /* LCD Height 1 register */ 732 chip->write(chip->opaque, 1, 0x01); 733 chip->write(chip->opaque, 0, 0x32); /* LCD VNDP register */ 734 chip->write(chip->opaque, 1, 0x06); 735 chip->write(chip->opaque, 0, 0x68); /* Display Mode register */ 736 chip->write(chip->opaque, 1, 1); /* Enable bit */ 737 738 chip->write(chip->opaque, 0, 0x6c); 739 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */ 740 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */ 741 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */ 742 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */ 743 chip->write(chip->opaque, 1, 0x1f); /* Input X End Position */ 744 chip->write(chip->opaque, 1, 0x03); /* Input X End Position */ 745 chip->write(chip->opaque, 1, 0xdf); /* Input Y End Position */ 746 chip->write(chip->opaque, 1, 0x01); /* Input Y End Position */ 747 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */ 748 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */ 749 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */ 750 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */ 751 chip->write(chip->opaque, 1, 0x1f); /* Output X End Position */ 752 chip->write(chip->opaque, 1, 0x03); /* Output X End Position */ 753 chip->write(chip->opaque, 1, 0xdf); /* Output Y End Position */ 754 chip->write(chip->opaque, 1, 0x01); /* Output Y End Position */ 755 chip->write(chip->opaque, 1, 0x01); /* Input Data Format */ 756 chip->write(chip->opaque, 1, 0x01); /* Data Source Select */ 757 758 fb_blank = memset(g_malloc(800 * 480 * 2), 0xff, 800 * 480 * 2); 759 /* Display Memory Data Port */ 760 chip->block(chip->opaque, 1, fb_blank, 800 * 480 * 2, 800); 761 g_free(fb_blank); 762 } 763 764 static void n8x0_dss_setup(struct n800_s *s) 765 { 766 s->blizzard.opaque = s1d13745_init(NULL); 767 s->blizzard.block = s1d13745_write_block; 768 s->blizzard.write = s1d13745_write; 769 s->blizzard.read = s1d13745_read; 770 771 omap_rfbi_attach(s->mpu->dss, 0, &s->blizzard); 772 } 773 774 static void n8x0_cbus_setup(struct n800_s *s) 775 { 776 qemu_irq dat_out = qdev_get_gpio_in(s->mpu->gpio, N8X0_CBUS_DAT_GPIO); 777 qemu_irq retu_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_RETU_GPIO); 778 qemu_irq tahvo_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_TAHVO_GPIO); 779 780 CBus *cbus = cbus_init(dat_out); 781 782 qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_CLK_GPIO, cbus->clk); 783 qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_DAT_GPIO, cbus->dat); 784 qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_SEL_GPIO, cbus->sel); 785 786 cbus_attach(cbus, s->retu = retu_init(retu_irq, 1)); 787 cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1)); 788 } 789 790 static void n8x0_uart_setup(struct n800_s *s) 791 { 792 Chardev *radio = uart_hci_init(); 793 794 qdev_connect_gpio_out(s->mpu->gpio, N8X0_BT_RESET_GPIO, 795 csrhci_pins_get(radio)[csrhci_pin_reset]); 796 qdev_connect_gpio_out(s->mpu->gpio, N8X0_BT_WKUP_GPIO, 797 csrhci_pins_get(radio)[csrhci_pin_wakeup]); 798 799 omap_uart_attach(s->mpu->uart[BT_UART], radio); 800 } 801 802 static void n8x0_usb_setup(struct n800_s *s) 803 { 804 SysBusDevice *dev; 805 s->usb = qdev_create(NULL, "tusb6010"); 806 dev = SYS_BUS_DEVICE(s->usb); 807 qdev_init_nofail(s->usb); 808 sysbus_connect_irq(dev, 0, 809 qdev_get_gpio_in(s->mpu->gpio, N8X0_TUSB_INT_GPIO)); 810 /* Using the NOR interface */ 811 omap_gpmc_attach(s->mpu->gpmc, N8X0_USB_ASYNC_CS, 812 sysbus_mmio_get_region(dev, 0)); 813 omap_gpmc_attach(s->mpu->gpmc, N8X0_USB_SYNC_CS, 814 sysbus_mmio_get_region(dev, 1)); 815 qdev_connect_gpio_out(s->mpu->gpio, N8X0_TUSB_ENABLE_GPIO, 816 qdev_get_gpio_in(s->usb, 0)); /* tusb_pwr */ 817 } 818 819 /* Setup done before the main bootloader starts by some early setup code 820 * - used when we want to run the main bootloader in emulation. This 821 * isn't documented. */ 822 static uint32_t n800_pinout[104] = { 823 0x080f00d8, 0x00d40808, 0x03080808, 0x080800d0, 824 0x00dc0808, 0x0b0f0f00, 0x080800b4, 0x00c00808, 825 0x08080808, 0x180800c4, 0x00b80000, 0x08080808, 826 0x080800bc, 0x00cc0808, 0x08081818, 0x18180128, 827 0x01241800, 0x18181818, 0x000000f0, 0x01300000, 828 0x00001b0b, 0x1b0f0138, 0x00e0181b, 0x1b031b0b, 829 0x180f0078, 0x00740018, 0x0f0f0f1a, 0x00000080, 830 0x007c0000, 0x00000000, 0x00000088, 0x00840000, 831 0x00000000, 0x00000094, 0x00980300, 0x0f180003, 832 0x0000008c, 0x00900f0f, 0x0f0f1b00, 0x0f00009c, 833 0x01140000, 0x1b1b0f18, 0x0818013c, 0x01400008, 834 0x00001818, 0x000b0110, 0x010c1800, 0x0b030b0f, 835 0x181800f4, 0x00f81818, 0x00000018, 0x000000fc, 836 0x00401808, 0x00000000, 0x0f1b0030, 0x003c0008, 837 0x00000000, 0x00000038, 0x00340000, 0x00000000, 838 0x1a080070, 0x00641a1a, 0x08080808, 0x08080060, 839 0x005c0808, 0x08080808, 0x08080058, 0x00540808, 840 0x08080808, 0x0808006c, 0x00680808, 0x08080808, 841 0x000000a8, 0x00b00000, 0x08080808, 0x000000a0, 842 0x00a40000, 0x00000000, 0x08ff0050, 0x004c0808, 843 0xffffffff, 0xffff0048, 0x0044ffff, 0xffffffff, 844 0x000000ac, 0x01040800, 0x08080b0f, 0x18180100, 845 0x01081818, 0x0b0b1808, 0x1a0300e4, 0x012c0b1a, 846 0x02020018, 0x0b000134, 0x011c0800, 0x0b1b1b00, 847 0x0f0000c8, 0x00ec181b, 0x000f0f02, 0x00180118, 848 0x01200000, 0x0f0b1b1b, 0x0f0200e8, 0x0000020b, 849 }; 850 851 static void n800_setup_nolo_tags(void *sram_base) 852 { 853 int i; 854 uint32_t *p = sram_base + 0x8000; 855 uint32_t *v = sram_base + 0xa000; 856 857 memset(p, 0, 0x3000); 858 859 strcpy((void *) (p + 0), "QEMU N800"); 860 861 strcpy((void *) (p + 8), "F5"); 862 863 stl_p(p + 10, 0x04f70000); 864 strcpy((void *) (p + 9), "RX-34"); 865 866 /* RAM size in MB? */ 867 stl_p(p + 12, 0x80); 868 869 /* Pointer to the list of tags */ 870 stl_p(p + 13, OMAP2_SRAM_BASE + 0x9000); 871 872 /* The NOLO tags start here */ 873 p = sram_base + 0x9000; 874 #define ADD_TAG(tag, len) \ 875 stw_p((uint16_t *) p + 0, tag); \ 876 stw_p((uint16_t *) p + 1, len); p++; \ 877 stl_p(p++, OMAP2_SRAM_BASE | (((void *) v - sram_base) & 0xffff)); 878 879 /* OMAP STI console? Pin out settings? */ 880 ADD_TAG(0x6e01, 414); 881 for (i = 0; i < ARRAY_SIZE(n800_pinout); i++) { 882 stl_p(v++, n800_pinout[i]); 883 } 884 885 /* Kernel memsize? */ 886 ADD_TAG(0x6e05, 1); 887 stl_p(v++, 2); 888 889 /* NOLO serial console */ 890 ADD_TAG(0x6e02, 4); 891 stl_p(v++, XLDR_LL_UART); /* UART number (1 - 3) */ 892 893 #if 0 894 /* CBUS settings (Retu/AVilma) */ 895 ADD_TAG(0x6e03, 6); 896 stw_p((uint16_t *) v + 0, 65); /* CBUS GPIO0 */ 897 stw_p((uint16_t *) v + 1, 66); /* CBUS GPIO1 */ 898 stw_p((uint16_t *) v + 2, 64); /* CBUS GPIO2 */ 899 v += 2; 900 #endif 901 902 /* Nokia ASIC BB5 (Retu/Tahvo) */ 903 ADD_TAG(0x6e0a, 4); 904 stw_p((uint16_t *) v + 0, 111); /* "Retu" interrupt GPIO */ 905 stw_p((uint16_t *) v + 1, 108); /* "Tahvo" interrupt GPIO */ 906 v++; 907 908 /* LCD console? */ 909 ADD_TAG(0x6e04, 4); 910 stw_p((uint16_t *) v + 0, 30); /* ??? */ 911 stw_p((uint16_t *) v + 1, 24); /* ??? */ 912 v++; 913 914 #if 0 915 /* LCD settings */ 916 ADD_TAG(0x6e06, 2); 917 stw_p((uint16_t *) (v++), 15); /* ??? */ 918 #endif 919 920 /* I^2C (Menelaus) */ 921 ADD_TAG(0x6e07, 4); 922 stl_p(v++, 0x00720000); /* ??? */ 923 924 /* Unknown */ 925 ADD_TAG(0x6e0b, 6); 926 stw_p((uint16_t *) v + 0, 94); /* ??? */ 927 stw_p((uint16_t *) v + 1, 23); /* ??? */ 928 stw_p((uint16_t *) v + 2, 0); /* ??? */ 929 v += 2; 930 931 /* OMAP gpio switch info */ 932 ADD_TAG(0x6e0c, 80); 933 strcpy((void *) v, "bat_cover"); v += 3; 934 stw_p((uint16_t *) v + 0, 110); /* GPIO num ??? */ 935 stw_p((uint16_t *) v + 1, 1); /* GPIO num ??? */ 936 v += 2; 937 strcpy((void *) v, "cam_act"); v += 3; 938 stw_p((uint16_t *) v + 0, 95); /* GPIO num ??? */ 939 stw_p((uint16_t *) v + 1, 32); /* GPIO num ??? */ 940 v += 2; 941 strcpy((void *) v, "cam_turn"); v += 3; 942 stw_p((uint16_t *) v + 0, 12); /* GPIO num ??? */ 943 stw_p((uint16_t *) v + 1, 33); /* GPIO num ??? */ 944 v += 2; 945 strcpy((void *) v, "headphone"); v += 3; 946 stw_p((uint16_t *) v + 0, 107); /* GPIO num ??? */ 947 stw_p((uint16_t *) v + 1, 17); /* GPIO num ??? */ 948 v += 2; 949 950 /* Bluetooth */ 951 ADD_TAG(0x6e0e, 12); 952 stl_p(v++, 0x5c623d01); /* ??? */ 953 stl_p(v++, 0x00000201); /* ??? */ 954 stl_p(v++, 0x00000000); /* ??? */ 955 956 /* CX3110x WLAN settings */ 957 ADD_TAG(0x6e0f, 8); 958 stl_p(v++, 0x00610025); /* ??? */ 959 stl_p(v++, 0xffff0057); /* ??? */ 960 961 /* MMC host settings */ 962 ADD_TAG(0x6e10, 12); 963 stl_p(v++, 0xffff000f); /* ??? */ 964 stl_p(v++, 0xffffffff); /* ??? */ 965 stl_p(v++, 0x00000060); /* ??? */ 966 967 /* OneNAND chip select */ 968 ADD_TAG(0x6e11, 10); 969 stl_p(v++, 0x00000401); /* ??? */ 970 stl_p(v++, 0x0002003a); /* ??? */ 971 stl_p(v++, 0x00000002); /* ??? */ 972 973 /* TEA5761 sensor settings */ 974 ADD_TAG(0x6e12, 2); 975 stl_p(v++, 93); /* GPIO num ??? */ 976 977 #if 0 978 /* Unknown tag */ 979 ADD_TAG(6e09, 0); 980 981 /* Kernel UART / console */ 982 ADD_TAG(6e12, 0); 983 #endif 984 985 /* End of the list */ 986 stl_p(p++, 0x00000000); 987 stl_p(p++, 0x00000000); 988 } 989 990 /* This task is normally performed by the bootloader. If we're loading 991 * a kernel directly, we need to set up GPMC mappings ourselves. */ 992 static void n800_gpmc_init(struct n800_s *s) 993 { 994 uint32_t config7 = 995 (0xf << 8) | /* MASKADDRESS */ 996 (1 << 6) | /* CSVALID */ 997 (4 << 0); /* BASEADDRESS */ 998 999 cpu_physical_memory_write(0x6800a078, /* GPMC_CONFIG7_0 */ 1000 &config7, sizeof(config7)); 1001 } 1002 1003 /* Setup sequence done by the bootloader */ 1004 static void n8x0_boot_init(void *opaque) 1005 { 1006 struct n800_s *s = (struct n800_s *) opaque; 1007 uint32_t buf; 1008 1009 /* PRCM setup */ 1010 #define omap_writel(addr, val) \ 1011 buf = (val); \ 1012 cpu_physical_memory_write(addr, &buf, sizeof(buf)) 1013 1014 omap_writel(0x48008060, 0x41); /* PRCM_CLKSRC_CTRL */ 1015 omap_writel(0x48008070, 1); /* PRCM_CLKOUT_CTRL */ 1016 omap_writel(0x48008078, 0); /* PRCM_CLKEMUL_CTRL */ 1017 omap_writel(0x48008090, 0); /* PRCM_VOLTSETUP */ 1018 omap_writel(0x48008094, 0); /* PRCM_CLKSSETUP */ 1019 omap_writel(0x48008098, 0); /* PRCM_POLCTRL */ 1020 omap_writel(0x48008140, 2); /* CM_CLKSEL_MPU */ 1021 omap_writel(0x48008148, 0); /* CM_CLKSTCTRL_MPU */ 1022 omap_writel(0x48008158, 1); /* RM_RSTST_MPU */ 1023 omap_writel(0x480081c8, 0x15); /* PM_WKDEP_MPU */ 1024 omap_writel(0x480081d4, 0x1d4); /* PM_EVGENCTRL_MPU */ 1025 omap_writel(0x480081d8, 0); /* PM_EVEGENONTIM_MPU */ 1026 omap_writel(0x480081dc, 0); /* PM_EVEGENOFFTIM_MPU */ 1027 omap_writel(0x480081e0, 0xc); /* PM_PWSTCTRL_MPU */ 1028 omap_writel(0x48008200, 0x047e7ff7); /* CM_FCLKEN1_CORE */ 1029 omap_writel(0x48008204, 0x00000004); /* CM_FCLKEN2_CORE */ 1030 omap_writel(0x48008210, 0x047e7ff1); /* CM_ICLKEN1_CORE */ 1031 omap_writel(0x48008214, 0x00000004); /* CM_ICLKEN2_CORE */ 1032 omap_writel(0x4800821c, 0x00000000); /* CM_ICLKEN4_CORE */ 1033 omap_writel(0x48008230, 0); /* CM_AUTOIDLE1_CORE */ 1034 omap_writel(0x48008234, 0); /* CM_AUTOIDLE2_CORE */ 1035 omap_writel(0x48008238, 7); /* CM_AUTOIDLE3_CORE */ 1036 omap_writel(0x4800823c, 0); /* CM_AUTOIDLE4_CORE */ 1037 omap_writel(0x48008240, 0x04360626); /* CM_CLKSEL1_CORE */ 1038 omap_writel(0x48008244, 0x00000014); /* CM_CLKSEL2_CORE */ 1039 omap_writel(0x48008248, 0); /* CM_CLKSTCTRL_CORE */ 1040 omap_writel(0x48008300, 0x00000000); /* CM_FCLKEN_GFX */ 1041 omap_writel(0x48008310, 0x00000000); /* CM_ICLKEN_GFX */ 1042 omap_writel(0x48008340, 0x00000001); /* CM_CLKSEL_GFX */ 1043 omap_writel(0x48008400, 0x00000004); /* CM_FCLKEN_WKUP */ 1044 omap_writel(0x48008410, 0x00000004); /* CM_ICLKEN_WKUP */ 1045 omap_writel(0x48008440, 0x00000000); /* CM_CLKSEL_WKUP */ 1046 omap_writel(0x48008500, 0x000000cf); /* CM_CLKEN_PLL */ 1047 omap_writel(0x48008530, 0x0000000c); /* CM_AUTOIDLE_PLL */ 1048 omap_writel(0x48008540, /* CM_CLKSEL1_PLL */ 1049 (0x78 << 12) | (6 << 8)); 1050 omap_writel(0x48008544, 2); /* CM_CLKSEL2_PLL */ 1051 1052 /* GPMC setup */ 1053 n800_gpmc_init(s); 1054 1055 /* Video setup */ 1056 n800_dss_init(&s->blizzard); 1057 1058 /* CPU setup */ 1059 s->mpu->cpu->env.GE = 0x5; 1060 1061 /* If the machine has a slided keyboard, open it */ 1062 if (s->kbd) { 1063 qemu_irq_raise(qdev_get_gpio_in(s->mpu->gpio, N810_SLIDE_GPIO)); 1064 } 1065 } 1066 1067 #define OMAP_TAG_NOKIA_BT 0x4e01 1068 #define OMAP_TAG_WLAN_CX3110X 0x4e02 1069 #define OMAP_TAG_CBUS 0x4e03 1070 #define OMAP_TAG_EM_ASIC_BB5 0x4e04 1071 1072 static struct omap_gpiosw_info_s { 1073 const char *name; 1074 int line; 1075 int type; 1076 } n800_gpiosw_info[] = { 1077 { 1078 "bat_cover", N800_BAT_COVER_GPIO, 1079 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED, 1080 }, { 1081 "cam_act", N800_CAM_ACT_GPIO, 1082 OMAP_GPIOSW_TYPE_ACTIVITY, 1083 }, { 1084 "cam_turn", N800_CAM_TURN_GPIO, 1085 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED, 1086 }, { 1087 "headphone", N8X0_HEADPHONE_GPIO, 1088 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED, 1089 }, 1090 { NULL } 1091 }, n810_gpiosw_info[] = { 1092 { 1093 "gps_reset", N810_GPS_RESET_GPIO, 1094 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT, 1095 }, { 1096 "gps_wakeup", N810_GPS_WAKEUP_GPIO, 1097 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT, 1098 }, { 1099 "headphone", N8X0_HEADPHONE_GPIO, 1100 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED, 1101 }, { 1102 "kb_lock", N810_KB_LOCK_GPIO, 1103 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED, 1104 }, { 1105 "sleepx_led", N810_SLEEPX_LED_GPIO, 1106 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED | OMAP_GPIOSW_OUTPUT, 1107 }, { 1108 "slide", N810_SLIDE_GPIO, 1109 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED, 1110 }, 1111 { NULL } 1112 }; 1113 1114 static struct omap_partition_info_s { 1115 uint32_t offset; 1116 uint32_t size; 1117 int mask; 1118 const char *name; 1119 } n800_part_info[] = { 1120 { 0x00000000, 0x00020000, 0x3, "bootloader" }, 1121 { 0x00020000, 0x00060000, 0x0, "config" }, 1122 { 0x00080000, 0x00200000, 0x0, "kernel" }, 1123 { 0x00280000, 0x00200000, 0x3, "initfs" }, 1124 { 0x00480000, 0x0fb80000, 0x3, "rootfs" }, 1125 1126 { 0, 0, 0, NULL } 1127 }, n810_part_info[] = { 1128 { 0x00000000, 0x00020000, 0x3, "bootloader" }, 1129 { 0x00020000, 0x00060000, 0x0, "config" }, 1130 { 0x00080000, 0x00220000, 0x0, "kernel" }, 1131 { 0x002a0000, 0x00400000, 0x0, "initfs" }, 1132 { 0x006a0000, 0x0f960000, 0x0, "rootfs" }, 1133 1134 { 0, 0, 0, NULL } 1135 }; 1136 1137 static bdaddr_t n8x0_bd_addr = {{ N8X0_BD_ADDR }}; 1138 1139 static int n8x0_atag_setup(void *p, int model) 1140 { 1141 uint8_t *b; 1142 uint16_t *w; 1143 uint32_t *l; 1144 struct omap_gpiosw_info_s *gpiosw; 1145 struct omap_partition_info_s *partition; 1146 const char *tag; 1147 1148 w = p; 1149 1150 stw_p(w++, OMAP_TAG_UART); /* u16 tag */ 1151 stw_p(w++, 4); /* u16 len */ 1152 stw_p(w++, (1 << 2) | (1 << 1) | (1 << 0)); /* uint enabled_uarts */ 1153 w++; 1154 1155 #if 0 1156 stw_p(w++, OMAP_TAG_SERIAL_CONSOLE); /* u16 tag */ 1157 stw_p(w++, 4); /* u16 len */ 1158 stw_p(w++, XLDR_LL_UART + 1); /* u8 console_uart */ 1159 stw_p(w++, 115200); /* u32 console_speed */ 1160 #endif 1161 1162 stw_p(w++, OMAP_TAG_LCD); /* u16 tag */ 1163 stw_p(w++, 36); /* u16 len */ 1164 strcpy((void *) w, "QEMU LCD panel"); /* char panel_name[16] */ 1165 w += 8; 1166 strcpy((void *) w, "blizzard"); /* char ctrl_name[16] */ 1167 w += 8; 1168 stw_p(w++, N810_BLIZZARD_RESET_GPIO); /* TODO: n800 s16 nreset_gpio */ 1169 stw_p(w++, 24); /* u8 data_lines */ 1170 1171 stw_p(w++, OMAP_TAG_CBUS); /* u16 tag */ 1172 stw_p(w++, 8); /* u16 len */ 1173 stw_p(w++, N8X0_CBUS_CLK_GPIO); /* s16 clk_gpio */ 1174 stw_p(w++, N8X0_CBUS_DAT_GPIO); /* s16 dat_gpio */ 1175 stw_p(w++, N8X0_CBUS_SEL_GPIO); /* s16 sel_gpio */ 1176 w++; 1177 1178 stw_p(w++, OMAP_TAG_EM_ASIC_BB5); /* u16 tag */ 1179 stw_p(w++, 4); /* u16 len */ 1180 stw_p(w++, N8X0_RETU_GPIO); /* s16 retu_irq_gpio */ 1181 stw_p(w++, N8X0_TAHVO_GPIO); /* s16 tahvo_irq_gpio */ 1182 1183 gpiosw = (model == 810) ? n810_gpiosw_info : n800_gpiosw_info; 1184 for (; gpiosw->name; gpiosw++) { 1185 stw_p(w++, OMAP_TAG_GPIO_SWITCH); /* u16 tag */ 1186 stw_p(w++, 20); /* u16 len */ 1187 strcpy((void *) w, gpiosw->name); /* char name[12] */ 1188 w += 6; 1189 stw_p(w++, gpiosw->line); /* u16 gpio */ 1190 stw_p(w++, gpiosw->type); 1191 stw_p(w++, 0); 1192 stw_p(w++, 0); 1193 } 1194 1195 stw_p(w++, OMAP_TAG_NOKIA_BT); /* u16 tag */ 1196 stw_p(w++, 12); /* u16 len */ 1197 b = (void *) w; 1198 stb_p(b++, 0x01); /* u8 chip_type (CSR) */ 1199 stb_p(b++, N8X0_BT_WKUP_GPIO); /* u8 bt_wakeup_gpio */ 1200 stb_p(b++, N8X0_BT_HOST_WKUP_GPIO); /* u8 host_wakeup_gpio */ 1201 stb_p(b++, N8X0_BT_RESET_GPIO); /* u8 reset_gpio */ 1202 stb_p(b++, BT_UART + 1); /* u8 bt_uart */ 1203 memcpy(b, &n8x0_bd_addr, 6); /* u8 bd_addr[6] */ 1204 b += 6; 1205 stb_p(b++, 0x02); /* u8 bt_sysclk (38.4) */ 1206 w = (void *) b; 1207 1208 stw_p(w++, OMAP_TAG_WLAN_CX3110X); /* u16 tag */ 1209 stw_p(w++, 8); /* u16 len */ 1210 stw_p(w++, 0x25); /* u8 chip_type */ 1211 stw_p(w++, N8X0_WLAN_PWR_GPIO); /* s16 power_gpio */ 1212 stw_p(w++, N8X0_WLAN_IRQ_GPIO); /* s16 irq_gpio */ 1213 stw_p(w++, -1); /* s16 spi_cs_gpio */ 1214 1215 stw_p(w++, OMAP_TAG_MMC); /* u16 tag */ 1216 stw_p(w++, 16); /* u16 len */ 1217 if (model == 810) { 1218 stw_p(w++, 0x23f); /* unsigned flags */ 1219 stw_p(w++, -1); /* s16 power_pin */ 1220 stw_p(w++, -1); /* s16 switch_pin */ 1221 stw_p(w++, -1); /* s16 wp_pin */ 1222 stw_p(w++, 0x240); /* unsigned flags */ 1223 stw_p(w++, 0xc000); /* s16 power_pin */ 1224 stw_p(w++, 0x0248); /* s16 switch_pin */ 1225 stw_p(w++, 0xc000); /* s16 wp_pin */ 1226 } else { 1227 stw_p(w++, 0xf); /* unsigned flags */ 1228 stw_p(w++, -1); /* s16 power_pin */ 1229 stw_p(w++, -1); /* s16 switch_pin */ 1230 stw_p(w++, -1); /* s16 wp_pin */ 1231 stw_p(w++, 0); /* unsigned flags */ 1232 stw_p(w++, 0); /* s16 power_pin */ 1233 stw_p(w++, 0); /* s16 switch_pin */ 1234 stw_p(w++, 0); /* s16 wp_pin */ 1235 } 1236 1237 stw_p(w++, OMAP_TAG_TEA5761); /* u16 tag */ 1238 stw_p(w++, 4); /* u16 len */ 1239 stw_p(w++, N8X0_TEA5761_CS_GPIO); /* u16 enable_gpio */ 1240 w++; 1241 1242 partition = (model == 810) ? n810_part_info : n800_part_info; 1243 for (; partition->name; partition++) { 1244 stw_p(w++, OMAP_TAG_PARTITION); /* u16 tag */ 1245 stw_p(w++, 28); /* u16 len */ 1246 strcpy((void *) w, partition->name); /* char name[16] */ 1247 l = (void *) (w + 8); 1248 stl_p(l++, partition->size); /* unsigned int size */ 1249 stl_p(l++, partition->offset); /* unsigned int offset */ 1250 stl_p(l++, partition->mask); /* unsigned int mask_flags */ 1251 w = (void *) l; 1252 } 1253 1254 stw_p(w++, OMAP_TAG_BOOT_REASON); /* u16 tag */ 1255 stw_p(w++, 12); /* u16 len */ 1256 #if 0 1257 strcpy((void *) w, "por"); /* char reason_str[12] */ 1258 strcpy((void *) w, "charger"); /* char reason_str[12] */ 1259 strcpy((void *) w, "32wd_to"); /* char reason_str[12] */ 1260 strcpy((void *) w, "sw_rst"); /* char reason_str[12] */ 1261 strcpy((void *) w, "mbus"); /* char reason_str[12] */ 1262 strcpy((void *) w, "unknown"); /* char reason_str[12] */ 1263 strcpy((void *) w, "swdg_to"); /* char reason_str[12] */ 1264 strcpy((void *) w, "sec_vio"); /* char reason_str[12] */ 1265 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */ 1266 strcpy((void *) w, "rtc_alarm"); /* char reason_str[12] */ 1267 #else 1268 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */ 1269 #endif 1270 w += 6; 1271 1272 tag = (model == 810) ? "RX-44" : "RX-34"; 1273 stw_p(w++, OMAP_TAG_VERSION_STR); /* u16 tag */ 1274 stw_p(w++, 24); /* u16 len */ 1275 strcpy((void *) w, "product"); /* char component[12] */ 1276 w += 6; 1277 strcpy((void *) w, tag); /* char version[12] */ 1278 w += 6; 1279 1280 stw_p(w++, OMAP_TAG_VERSION_STR); /* u16 tag */ 1281 stw_p(w++, 24); /* u16 len */ 1282 strcpy((void *) w, "hw-build"); /* char component[12] */ 1283 w += 6; 1284 strcpy((void *) w, "QEMU "); 1285 pstrcat((void *) w, 12, qemu_hw_version()); /* char version[12] */ 1286 w += 6; 1287 1288 tag = (model == 810) ? "1.1.10-qemu" : "1.1.6-qemu"; 1289 stw_p(w++, OMAP_TAG_VERSION_STR); /* u16 tag */ 1290 stw_p(w++, 24); /* u16 len */ 1291 strcpy((void *) w, "nolo"); /* char component[12] */ 1292 w += 6; 1293 strcpy((void *) w, tag); /* char version[12] */ 1294 w += 6; 1295 1296 return (void *) w - p; 1297 } 1298 1299 static int n800_atag_setup(const struct arm_boot_info *info, void *p) 1300 { 1301 return n8x0_atag_setup(p, 800); 1302 } 1303 1304 static int n810_atag_setup(const struct arm_boot_info *info, void *p) 1305 { 1306 return n8x0_atag_setup(p, 810); 1307 } 1308 1309 static void n8x0_init(MachineState *machine, 1310 struct arm_boot_info *binfo, int model) 1311 { 1312 MemoryRegion *sysmem = get_system_memory(); 1313 struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s)); 1314 int sdram_size = binfo->ram_size; 1315 1316 s->mpu = omap2420_mpu_init(sysmem, sdram_size, machine->cpu_type); 1317 1318 /* Setup peripherals 1319 * 1320 * Believed external peripherals layout in the N810: 1321 * (spi bus 1) 1322 * tsc2005 1323 * lcd_mipid 1324 * (spi bus 2) 1325 * Conexant cx3110x (WLAN) 1326 * optional: pc2400m (WiMAX) 1327 * (i2c bus 0) 1328 * TLV320AIC33 (audio codec) 1329 * TCM825x (camera by Toshiba) 1330 * lp5521 (clever LEDs) 1331 * tsl2563 (light sensor, hwmon, model 7, rev. 0) 1332 * lm8323 (keypad, manf 00, rev 04) 1333 * (i2c bus 1) 1334 * tmp105 (temperature sensor, hwmon) 1335 * menelaus (pm) 1336 * (somewhere on i2c - maybe N800-only) 1337 * tea5761 (FM tuner) 1338 * (serial 0) 1339 * GPS 1340 * (some serial port) 1341 * csr41814 (Bluetooth) 1342 */ 1343 n8x0_gpio_setup(s); 1344 n8x0_nand_setup(s); 1345 n8x0_i2c_setup(s); 1346 if (model == 800) { 1347 n800_tsc_kbd_setup(s); 1348 } else if (model == 810) { 1349 n810_tsc_setup(s); 1350 n810_kbd_setup(s); 1351 } 1352 n8x0_spi_setup(s); 1353 n8x0_dss_setup(s); 1354 n8x0_cbus_setup(s); 1355 n8x0_uart_setup(s); 1356 if (machine_usb(machine)) { 1357 n8x0_usb_setup(s); 1358 } 1359 1360 if (machine->kernel_filename) { 1361 /* Or at the linux loader. */ 1362 binfo->kernel_filename = machine->kernel_filename; 1363 binfo->kernel_cmdline = machine->kernel_cmdline; 1364 binfo->initrd_filename = machine->initrd_filename; 1365 arm_load_kernel(s->mpu->cpu, binfo); 1366 1367 qemu_register_reset(n8x0_boot_init, s); 1368 } 1369 1370 if (option_rom[0].name && 1371 (machine->boot_order[0] == 'n' || !machine->kernel_filename)) { 1372 uint8_t *nolo_tags = g_new(uint8_t, 0x10000); 1373 /* No, wait, better start at the ROM. */ 1374 s->mpu->cpu->env.regs[15] = OMAP2_Q2_BASE + 0x400000; 1375 1376 /* This is intended for loading the `secondary.bin' program from 1377 * Nokia images (the NOLO bootloader). The entry point seems 1378 * to be at OMAP2_Q2_BASE + 0x400000. 1379 * 1380 * The `2nd.bin' files contain some kind of earlier boot code and 1381 * for them the entry point needs to be set to OMAP2_SRAM_BASE. 1382 * 1383 * The code above is for loading the `zImage' file from Nokia 1384 * images. */ 1385 load_image_targphys(option_rom[0].name, 1386 OMAP2_Q2_BASE + 0x400000, 1387 sdram_size - 0x400000); 1388 1389 n800_setup_nolo_tags(nolo_tags); 1390 cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000); 1391 g_free(nolo_tags); 1392 } 1393 } 1394 1395 static struct arm_boot_info n800_binfo = { 1396 .loader_start = OMAP2_Q2_BASE, 1397 /* Actually two chips of 0x4000000 bytes each */ 1398 .ram_size = 0x08000000, 1399 .board_id = 0x4f7, 1400 .atag_board = n800_atag_setup, 1401 }; 1402 1403 static struct arm_boot_info n810_binfo = { 1404 .loader_start = OMAP2_Q2_BASE, 1405 /* Actually two chips of 0x4000000 bytes each */ 1406 .ram_size = 0x08000000, 1407 /* 0x60c and 0x6bf (WiMAX Edition) have been assigned but are not 1408 * used by some older versions of the bootloader and 5555 is used 1409 * instead (including versions that shipped with many devices). */ 1410 .board_id = 0x60c, 1411 .atag_board = n810_atag_setup, 1412 }; 1413 1414 static void n800_init(MachineState *machine) 1415 { 1416 n8x0_init(machine, &n800_binfo, 800); 1417 } 1418 1419 static void n810_init(MachineState *machine) 1420 { 1421 n8x0_init(machine, &n810_binfo, 810); 1422 } 1423 1424 static void n800_class_init(ObjectClass *oc, void *data) 1425 { 1426 MachineClass *mc = MACHINE_CLASS(oc); 1427 1428 mc->desc = "Nokia N800 tablet aka. RX-34 (OMAP2420)"; 1429 mc->init = n800_init; 1430 mc->default_boot_order = ""; 1431 mc->ignore_memory_transaction_failures = true; 1432 mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm1136-r2"); 1433 } 1434 1435 static const TypeInfo n800_type = { 1436 .name = MACHINE_TYPE_NAME("n800"), 1437 .parent = TYPE_MACHINE, 1438 .class_init = n800_class_init, 1439 }; 1440 1441 static void n810_class_init(ObjectClass *oc, void *data) 1442 { 1443 MachineClass *mc = MACHINE_CLASS(oc); 1444 1445 mc->desc = "Nokia N810 tablet aka. RX-44 (OMAP2420)"; 1446 mc->init = n810_init; 1447 mc->default_boot_order = ""; 1448 mc->ignore_memory_transaction_failures = true; 1449 mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm1136-r2"); 1450 } 1451 1452 static const TypeInfo n810_type = { 1453 .name = MACHINE_TYPE_NAME("n810"), 1454 .parent = TYPE_MACHINE, 1455 .class_init = n810_class_init, 1456 }; 1457 1458 static void nseries_machine_init(void) 1459 { 1460 type_register_static(&n800_type); 1461 type_register_static(&n810_type); 1462 } 1463 1464 type_init(nseries_machine_init) 1465