1 /* 2 * Nordic Semiconductor nRF51 SoC 3 * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf 4 * 5 * Copyright 2018 Joel Stanley <joel@jms.id.au> 6 * 7 * This code is licensed under the GPL version 2 or later. See 8 * the COPYING file in the top-level directory. 9 */ 10 11 #include "qemu/osdep.h" 12 #include "qapi/error.h" 13 #include "hw/arm/boot.h" 14 #include "hw/sysbus.h" 15 #include "hw/misc/unimp.h" 16 #include "qemu/log.h" 17 18 #include "hw/arm/nrf51.h" 19 #include "hw/arm/nrf51_soc.h" 20 21 /* 22 * The size and base is for the NRF51822 part. If other parts 23 * are supported in the future, add a sub-class of NRF51SoC for 24 * the specific variants 25 */ 26 #define NRF51822_FLASH_PAGES 256 27 #define NRF51822_SRAM_PAGES 16 28 #define NRF51822_FLASH_SIZE (NRF51822_FLASH_PAGES * NRF51_PAGE_SIZE) 29 #define NRF51822_SRAM_SIZE (NRF51822_SRAM_PAGES * NRF51_PAGE_SIZE) 30 31 #define BASE_TO_IRQ(base) ((base >> 12) & 0x1F) 32 33 /* HCLK (the main CPU clock) on this SoC is always 16MHz */ 34 #define HCLK_FRQ 16000000 35 36 static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size) 37 { 38 qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n", 39 __func__, addr, size); 40 return 1; 41 } 42 43 static void clock_write(void *opaque, hwaddr addr, uint64_t data, 44 unsigned int size) 45 { 46 qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n", 47 __func__, addr, data, size); 48 } 49 50 static const MemoryRegionOps clock_ops = { 51 .read = clock_read, 52 .write = clock_write 53 }; 54 55 56 static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) 57 { 58 NRF51State *s = NRF51_SOC(dev_soc); 59 MemoryRegion *mr; 60 Error *err = NULL; 61 uint8_t i = 0; 62 hwaddr base_addr = 0; 63 64 if (!s->board_memory) { 65 error_setg(errp, "memory property was not set"); 66 return; 67 } 68 69 system_clock_scale = NANOSECONDS_PER_SECOND / HCLK_FRQ; 70 71 object_property_set_link(OBJECT(&s->cpu), "memory", OBJECT(&s->container), 72 &error_abort); 73 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu), errp)) { 74 return; 75 } 76 77 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1); 78 79 memory_region_init_ram(&s->sram, OBJECT(s), "nrf51.sram", s->sram_size, 80 &err); 81 if (err) { 82 error_propagate(errp, err); 83 return; 84 } 85 memory_region_add_subregion(&s->container, NRF51_SRAM_BASE, &s->sram); 86 87 /* UART */ 88 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) { 89 return; 90 } 91 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0); 92 memory_region_add_subregion_overlap(&s->container, NRF51_UART_BASE, mr, 0); 93 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0, 94 qdev_get_gpio_in(DEVICE(&s->cpu), 95 BASE_TO_IRQ(NRF51_UART_BASE))); 96 97 /* RNG */ 98 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rng), errp)) { 99 return; 100 } 101 102 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0); 103 memory_region_add_subregion_overlap(&s->container, NRF51_RNG_BASE, mr, 0); 104 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0, 105 qdev_get_gpio_in(DEVICE(&s->cpu), 106 BASE_TO_IRQ(NRF51_RNG_BASE))); 107 108 /* UICR, FICR, NVMC, FLASH */ 109 if (!object_property_set_uint(OBJECT(&s->nvm), "flash-size", 110 s->flash_size, errp)) { 111 return; 112 } 113 114 if (!sysbus_realize(SYS_BUS_DEVICE(&s->nvm), errp)) { 115 return; 116 } 117 118 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 0); 119 memory_region_add_subregion_overlap(&s->container, NRF51_NVMC_BASE, mr, 0); 120 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 1); 121 memory_region_add_subregion_overlap(&s->container, NRF51_FICR_BASE, mr, 0); 122 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 2); 123 memory_region_add_subregion_overlap(&s->container, NRF51_UICR_BASE, mr, 0); 124 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 3); 125 memory_region_add_subregion_overlap(&s->container, NRF51_FLASH_BASE, mr, 0); 126 127 /* GPIO */ 128 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 129 return; 130 } 131 132 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0); 133 memory_region_add_subregion_overlap(&s->container, NRF51_GPIO_BASE, mr, 0); 134 135 /* Pass all GPIOs to the SOC layer so they are available to the board */ 136 qdev_pass_gpios(DEVICE(&s->gpio), dev_soc, NULL); 137 138 /* TIMER */ 139 for (i = 0; i < NRF51_NUM_TIMERS; i++) { 140 if (!object_property_set_uint(OBJECT(&s->timer[i]), "id", i, errp)) { 141 return; 142 } 143 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), errp)) { 144 return; 145 } 146 147 base_addr = NRF51_TIMER_BASE + i * NRF51_PERIPHERAL_SIZE; 148 149 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr); 150 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0, 151 qdev_get_gpio_in(DEVICE(&s->cpu), 152 BASE_TO_IRQ(base_addr))); 153 } 154 155 /* STUB Peripherals */ 156 memory_region_init_io(&s->clock, OBJECT(dev_soc), &clock_ops, NULL, 157 "nrf51_soc.clock", NRF51_PERIPHERAL_SIZE); 158 memory_region_add_subregion_overlap(&s->container, 159 NRF51_IOMEM_BASE, &s->clock, -1); 160 161 create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE, 162 NRF51_IOMEM_SIZE); 163 create_unimplemented_device("nrf51_soc.private", 164 NRF51_PRIVATE_BASE, NRF51_PRIVATE_SIZE); 165 } 166 167 static void nrf51_soc_init(Object *obj) 168 { 169 uint8_t i = 0; 170 171 NRF51State *s = NRF51_SOC(obj); 172 173 memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX); 174 175 object_initialize_child(OBJECT(s), "armv6m", &s->cpu, TYPE_ARMV7M); 176 qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type", 177 ARM_CPU_TYPE_NAME("cortex-m0")); 178 qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32); 179 180 object_initialize_child(obj, "uart", &s->uart, TYPE_NRF51_UART); 181 object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev"); 182 183 object_initialize_child(obj, "rng", &s->rng, TYPE_NRF51_RNG); 184 185 object_initialize_child(obj, "nvm", &s->nvm, TYPE_NRF51_NVM); 186 187 object_initialize_child(obj, "gpio", &s->gpio, TYPE_NRF51_GPIO); 188 189 for (i = 0; i < NRF51_NUM_TIMERS; i++) { 190 object_initialize_child(obj, "timer[*]", &s->timer[i], 191 TYPE_NRF51_TIMER); 192 193 } 194 } 195 196 static Property nrf51_soc_properties[] = { 197 DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGION, 198 MemoryRegion *), 199 DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_SIZE), 200 DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size, 201 NRF51822_FLASH_SIZE), 202 DEFINE_PROP_END_OF_LIST(), 203 }; 204 205 static void nrf51_soc_class_init(ObjectClass *klass, void *data) 206 { 207 DeviceClass *dc = DEVICE_CLASS(klass); 208 209 dc->realize = nrf51_soc_realize; 210 device_class_set_props(dc, nrf51_soc_properties); 211 } 212 213 static const TypeInfo nrf51_soc_info = { 214 .name = TYPE_NRF51_SOC, 215 .parent = TYPE_SYS_BUS_DEVICE, 216 .instance_size = sizeof(NRF51State), 217 .instance_init = nrf51_soc_init, 218 .class_init = nrf51_soc_class_init, 219 }; 220 221 static void nrf51_soc_types(void) 222 { 223 type_register_static(&nrf51_soc_info); 224 } 225 type_init(nrf51_soc_types) 226