1 /* 2 * Nordic Semiconductor nRF51 SoC 3 * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf 4 * 5 * Copyright 2018 Joel Stanley <joel@jms.id.au> 6 * 7 * This code is licensed under the GPL version 2 or later. See 8 * the COPYING file in the top-level directory. 9 */ 10 11 #include "qemu/osdep.h" 12 #include "qapi/error.h" 13 #include "hw/arm/boot.h" 14 #include "hw/sysbus.h" 15 #include "hw/misc/unimp.h" 16 #include "exec/address-spaces.h" 17 #include "qemu/log.h" 18 #include "cpu.h" 19 20 #include "hw/arm/nrf51.h" 21 #include "hw/arm/nrf51_soc.h" 22 23 /* 24 * The size and base is for the NRF51822 part. If other parts 25 * are supported in the future, add a sub-class of NRF51SoC for 26 * the specific variants 27 */ 28 #define NRF51822_FLASH_PAGES 256 29 #define NRF51822_SRAM_PAGES 16 30 #define NRF51822_FLASH_SIZE (NRF51822_FLASH_PAGES * NRF51_PAGE_SIZE) 31 #define NRF51822_SRAM_SIZE (NRF51822_SRAM_PAGES * NRF51_PAGE_SIZE) 32 33 #define BASE_TO_IRQ(base) ((base >> 12) & 0x1F) 34 35 /* HCLK (the main CPU clock) on this SoC is always 16MHz */ 36 #define HCLK_FRQ 16000000 37 38 static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size) 39 { 40 qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n", 41 __func__, addr, size); 42 return 1; 43 } 44 45 static void clock_write(void *opaque, hwaddr addr, uint64_t data, 46 unsigned int size) 47 { 48 qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n", 49 __func__, addr, data, size); 50 } 51 52 static const MemoryRegionOps clock_ops = { 53 .read = clock_read, 54 .write = clock_write 55 }; 56 57 58 static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) 59 { 60 NRF51State *s = NRF51_SOC(dev_soc); 61 MemoryRegion *mr; 62 Error *err = NULL; 63 uint8_t i = 0; 64 hwaddr base_addr = 0; 65 66 if (!s->board_memory) { 67 error_setg(errp, "memory property was not set"); 68 return; 69 } 70 71 system_clock_scale = NANOSECONDS_PER_SECOND / HCLK_FRQ; 72 73 object_property_set_link(OBJECT(&s->cpu), "memory", OBJECT(&s->container), 74 &error_abort); 75 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu), errp)) { 76 return; 77 } 78 79 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1); 80 81 memory_region_init_ram(&s->sram, OBJECT(s), "nrf51.sram", s->sram_size, 82 &err); 83 if (err) { 84 error_propagate(errp, err); 85 return; 86 } 87 memory_region_add_subregion(&s->container, NRF51_SRAM_BASE, &s->sram); 88 89 /* UART */ 90 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) { 91 return; 92 } 93 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0); 94 memory_region_add_subregion_overlap(&s->container, NRF51_UART_BASE, mr, 0); 95 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0, 96 qdev_get_gpio_in(DEVICE(&s->cpu), 97 BASE_TO_IRQ(NRF51_UART_BASE))); 98 99 /* RNG */ 100 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rng), errp)) { 101 return; 102 } 103 104 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0); 105 memory_region_add_subregion_overlap(&s->container, NRF51_RNG_BASE, mr, 0); 106 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0, 107 qdev_get_gpio_in(DEVICE(&s->cpu), 108 BASE_TO_IRQ(NRF51_RNG_BASE))); 109 110 /* UICR, FICR, NVMC, FLASH */ 111 if (!object_property_set_uint(OBJECT(&s->nvm), "flash-size", 112 s->flash_size, errp)) { 113 return; 114 } 115 116 if (!sysbus_realize(SYS_BUS_DEVICE(&s->nvm), errp)) { 117 return; 118 } 119 120 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 0); 121 memory_region_add_subregion_overlap(&s->container, NRF51_NVMC_BASE, mr, 0); 122 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 1); 123 memory_region_add_subregion_overlap(&s->container, NRF51_FICR_BASE, mr, 0); 124 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 2); 125 memory_region_add_subregion_overlap(&s->container, NRF51_UICR_BASE, mr, 0); 126 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 3); 127 memory_region_add_subregion_overlap(&s->container, NRF51_FLASH_BASE, mr, 0); 128 129 /* GPIO */ 130 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 131 return; 132 } 133 134 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0); 135 memory_region_add_subregion_overlap(&s->container, NRF51_GPIO_BASE, mr, 0); 136 137 /* Pass all GPIOs to the SOC layer so they are available to the board */ 138 qdev_pass_gpios(DEVICE(&s->gpio), dev_soc, NULL); 139 140 /* TIMER */ 141 for (i = 0; i < NRF51_NUM_TIMERS; i++) { 142 if (!object_property_set_uint(OBJECT(&s->timer[i]), "id", i, errp)) { 143 return; 144 } 145 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), errp)) { 146 return; 147 } 148 149 base_addr = NRF51_TIMER_BASE + i * NRF51_PERIPHERAL_SIZE; 150 151 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr); 152 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0, 153 qdev_get_gpio_in(DEVICE(&s->cpu), 154 BASE_TO_IRQ(base_addr))); 155 } 156 157 /* STUB Peripherals */ 158 memory_region_init_io(&s->clock, OBJECT(dev_soc), &clock_ops, NULL, 159 "nrf51_soc.clock", NRF51_PERIPHERAL_SIZE); 160 memory_region_add_subregion_overlap(&s->container, 161 NRF51_IOMEM_BASE, &s->clock, -1); 162 163 create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE, 164 NRF51_IOMEM_SIZE); 165 create_unimplemented_device("nrf51_soc.private", 166 NRF51_PRIVATE_BASE, NRF51_PRIVATE_SIZE); 167 } 168 169 static void nrf51_soc_init(Object *obj) 170 { 171 uint8_t i = 0; 172 173 NRF51State *s = NRF51_SOC(obj); 174 175 memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX); 176 177 object_initialize_child(OBJECT(s), "armv6m", &s->cpu, TYPE_ARMV7M); 178 qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type", 179 ARM_CPU_TYPE_NAME("cortex-m0")); 180 qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32); 181 182 object_initialize_child(obj, "uart", &s->uart, TYPE_NRF51_UART); 183 object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev"); 184 185 object_initialize_child(obj, "rng", &s->rng, TYPE_NRF51_RNG); 186 187 object_initialize_child(obj, "nvm", &s->nvm, TYPE_NRF51_NVM); 188 189 object_initialize_child(obj, "gpio", &s->gpio, TYPE_NRF51_GPIO); 190 191 for (i = 0; i < NRF51_NUM_TIMERS; i++) { 192 object_initialize_child(obj, "timer[*]", &s->timer[i], 193 TYPE_NRF51_TIMER); 194 195 } 196 } 197 198 static Property nrf51_soc_properties[] = { 199 DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGION, 200 MemoryRegion *), 201 DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_SIZE), 202 DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size, 203 NRF51822_FLASH_SIZE), 204 DEFINE_PROP_END_OF_LIST(), 205 }; 206 207 static void nrf51_soc_class_init(ObjectClass *klass, void *data) 208 { 209 DeviceClass *dc = DEVICE_CLASS(klass); 210 211 dc->realize = nrf51_soc_realize; 212 device_class_set_props(dc, nrf51_soc_properties); 213 } 214 215 static const TypeInfo nrf51_soc_info = { 216 .name = TYPE_NRF51_SOC, 217 .parent = TYPE_SYS_BUS_DEVICE, 218 .instance_size = sizeof(NRF51State), 219 .instance_init = nrf51_soc_init, 220 .class_init = nrf51_soc_class_init, 221 }; 222 223 static void nrf51_soc_types(void) 224 { 225 type_register_static(&nrf51_soc_info); 226 } 227 type_init(nrf51_soc_types) 228