1 /* 2 * Nordic Semiconductor nRF51 SoC 3 * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf 4 * 5 * Copyright 2018 Joel Stanley <joel@jms.id.au> 6 * 7 * This code is licensed under the GPL version 2 or later. See 8 * the COPYING file in the top-level directory. 9 */ 10 11 #include "qemu/osdep.h" 12 #include "qapi/error.h" 13 #include "qemu-common.h" 14 #include "hw/arm/arm.h" 15 #include "hw/sysbus.h" 16 #include "hw/boards.h" 17 #include "hw/devices.h" 18 #include "hw/misc/unimp.h" 19 #include "exec/address-spaces.h" 20 #include "sysemu/sysemu.h" 21 #include "qemu/log.h" 22 #include "cpu.h" 23 24 #include "hw/arm/nrf51_soc.h" 25 26 #define IOMEM_BASE 0x40000000 27 #define IOMEM_SIZE 0x20000000 28 29 #define FICR_BASE 0x10000000 30 #define FICR_SIZE 0x000000fc 31 32 #define FLASH_BASE 0x00000000 33 #define SRAM_BASE 0x20000000 34 35 #define PRIVATE_BASE 0xF0000000 36 #define PRIVATE_SIZE 0x10000000 37 38 /* 39 * The size and base is for the NRF51822 part. If other parts 40 * are supported in the future, add a sub-class of NRF51SoC for 41 * the specific variants 42 */ 43 #define NRF51822_FLASH_SIZE (256 * 1024) 44 #define NRF51822_SRAM_SIZE (16 * 1024) 45 46 static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) 47 { 48 NRF51State *s = NRF51_SOC(dev_soc); 49 Error *err = NULL; 50 51 if (!s->board_memory) { 52 error_setg(errp, "memory property was not set"); 53 return; 54 } 55 56 object_property_set_link(OBJECT(&s->cpu), OBJECT(&s->container), "memory", 57 &err); 58 if (err) { 59 error_propagate(errp, err); 60 return; 61 } 62 object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); 63 if (err) { 64 error_propagate(errp, err); 65 return; 66 } 67 68 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1); 69 70 memory_region_init_rom(&s->flash, OBJECT(s), "nrf51.flash", s->flash_size, 71 &err); 72 if (err) { 73 error_propagate(errp, err); 74 return; 75 } 76 memory_region_add_subregion(&s->container, FLASH_BASE, &s->flash); 77 78 memory_region_init_ram(&s->sram, NULL, "nrf51.sram", s->sram_size, &err); 79 if (err) { 80 error_propagate(errp, err); 81 return; 82 } 83 memory_region_add_subregion(&s->container, SRAM_BASE, &s->sram); 84 85 create_unimplemented_device("nrf51_soc.io", IOMEM_BASE, IOMEM_SIZE); 86 create_unimplemented_device("nrf51_soc.ficr", FICR_BASE, FICR_SIZE); 87 create_unimplemented_device("nrf51_soc.private", 88 PRIVATE_BASE, PRIVATE_SIZE); 89 } 90 91 static void nrf51_soc_init(Object *obj) 92 { 93 NRF51State *s = NRF51_SOC(obj); 94 95 memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX); 96 97 sysbus_init_child_obj(OBJECT(s), "armv6m", OBJECT(&s->cpu), sizeof(s->cpu), 98 TYPE_ARMV7M); 99 qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type", 100 ARM_CPU_TYPE_NAME("cortex-m0")); 101 qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32); 102 } 103 104 static Property nrf51_soc_properties[] = { 105 DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGION, 106 MemoryRegion *), 107 DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_SIZE), 108 DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size, 109 NRF51822_FLASH_SIZE), 110 DEFINE_PROP_END_OF_LIST(), 111 }; 112 113 static void nrf51_soc_class_init(ObjectClass *klass, void *data) 114 { 115 DeviceClass *dc = DEVICE_CLASS(klass); 116 117 dc->realize = nrf51_soc_realize; 118 dc->props = nrf51_soc_properties; 119 } 120 121 static const TypeInfo nrf51_soc_info = { 122 .name = TYPE_NRF51_SOC, 123 .parent = TYPE_SYS_BUS_DEVICE, 124 .instance_size = sizeof(NRF51State), 125 .instance_init = nrf51_soc_init, 126 .class_init = nrf51_soc_class_init, 127 }; 128 129 static void nrf51_soc_types(void) 130 { 131 type_register_static(&nrf51_soc_info); 132 } 133 type_init(nrf51_soc_types) 134