1 /* 2 * Nordic Semiconductor nRF51 SoC 3 * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf 4 * 5 * Copyright 2018 Joel Stanley <joel@jms.id.au> 6 * 7 * This code is licensed under the GPL version 2 or later. See 8 * the COPYING file in the top-level directory. 9 */ 10 11 #include "qemu/osdep.h" 12 #include "qapi/error.h" 13 #include "qemu-common.h" 14 #include "hw/arm/arm.h" 15 #include "hw/sysbus.h" 16 #include "hw/boards.h" 17 #include "hw/devices.h" 18 #include "hw/misc/unimp.h" 19 #include "exec/address-spaces.h" 20 #include "sysemu/sysemu.h" 21 #include "qemu/log.h" 22 #include "cpu.h" 23 24 #include "hw/arm/nrf51.h" 25 #include "hw/arm/nrf51_soc.h" 26 27 /* 28 * The size and base is for the NRF51822 part. If other parts 29 * are supported in the future, add a sub-class of NRF51SoC for 30 * the specific variants 31 */ 32 #define NRF51822_FLASH_PAGES 256 33 #define NRF51822_SRAM_PAGES 16 34 #define NRF51822_FLASH_SIZE (NRF51822_FLASH_PAGES * NRF51_PAGE_SIZE) 35 #define NRF51822_SRAM_SIZE (NRF51822_SRAM_PAGES * NRF51_PAGE_SIZE) 36 37 #define BASE_TO_IRQ(base) ((base >> 12) & 0x1F) 38 39 static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size) 40 { 41 qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n", 42 __func__, addr, size); 43 return 1; 44 } 45 46 static void clock_write(void *opaque, hwaddr addr, uint64_t data, 47 unsigned int size) 48 { 49 qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n", 50 __func__, addr, data, size); 51 } 52 53 static const MemoryRegionOps clock_ops = { 54 .read = clock_read, 55 .write = clock_write 56 }; 57 58 59 static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) 60 { 61 NRF51State *s = NRF51_SOC(dev_soc); 62 MemoryRegion *mr; 63 Error *err = NULL; 64 uint8_t i = 0; 65 hwaddr base_addr = 0; 66 67 if (!s->board_memory) { 68 error_setg(errp, "memory property was not set"); 69 return; 70 } 71 72 object_property_set_link(OBJECT(&s->cpu), OBJECT(&s->container), "memory", 73 &err); 74 if (err) { 75 error_propagate(errp, err); 76 return; 77 } 78 object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); 79 if (err) { 80 error_propagate(errp, err); 81 return; 82 } 83 84 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1); 85 86 memory_region_init_ram(&s->sram, OBJECT(s), "nrf51.sram", s->sram_size, 87 &err); 88 if (err) { 89 error_propagate(errp, err); 90 return; 91 } 92 memory_region_add_subregion(&s->container, NRF51_SRAM_BASE, &s->sram); 93 94 /* UART */ 95 object_property_set_bool(OBJECT(&s->uart), true, "realized", &err); 96 if (err) { 97 error_propagate(errp, err); 98 return; 99 } 100 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0); 101 memory_region_add_subregion_overlap(&s->container, NRF51_UART_BASE, mr, 0); 102 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0, 103 qdev_get_gpio_in(DEVICE(&s->cpu), 104 BASE_TO_IRQ(NRF51_UART_BASE))); 105 106 /* RNG */ 107 object_property_set_bool(OBJECT(&s->rng), true, "realized", &err); 108 if (err) { 109 error_propagate(errp, err); 110 return; 111 } 112 113 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0); 114 memory_region_add_subregion_overlap(&s->container, NRF51_RNG_BASE, mr, 0); 115 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0, 116 qdev_get_gpio_in(DEVICE(&s->cpu), 117 BASE_TO_IRQ(NRF51_RNG_BASE))); 118 119 /* UICR, FICR, NVMC, FLASH */ 120 object_property_set_uint(OBJECT(&s->nvm), s->flash_size, "flash-size", 121 &err); 122 if (err) { 123 error_propagate(errp, err); 124 return; 125 } 126 127 object_property_set_bool(OBJECT(&s->nvm), true, "realized", &err); 128 if (err) { 129 error_propagate(errp, err); 130 return; 131 } 132 133 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 0); 134 memory_region_add_subregion_overlap(&s->container, NRF51_NVMC_BASE, mr, 0); 135 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 1); 136 memory_region_add_subregion_overlap(&s->container, NRF51_FICR_BASE, mr, 0); 137 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 2); 138 memory_region_add_subregion_overlap(&s->container, NRF51_UICR_BASE, mr, 0); 139 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 3); 140 memory_region_add_subregion_overlap(&s->container, NRF51_FLASH_BASE, mr, 0); 141 142 /* GPIO */ 143 object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err); 144 if (err) { 145 error_propagate(errp, err); 146 return; 147 } 148 149 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0); 150 memory_region_add_subregion_overlap(&s->container, NRF51_GPIO_BASE, mr, 0); 151 152 /* Pass all GPIOs to the SOC layer so they are available to the board */ 153 qdev_pass_gpios(DEVICE(&s->gpio), dev_soc, NULL); 154 155 /* TIMER */ 156 for (i = 0; i < NRF51_NUM_TIMERS; i++) { 157 object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err); 158 if (err) { 159 error_propagate(errp, err); 160 return; 161 } 162 163 base_addr = NRF51_TIMER_BASE + i * NRF51_TIMER_SIZE; 164 165 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr); 166 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0, 167 qdev_get_gpio_in(DEVICE(&s->cpu), 168 BASE_TO_IRQ(base_addr))); 169 } 170 171 /* STUB Peripherals */ 172 memory_region_init_io(&s->clock, NULL, &clock_ops, NULL, 173 "nrf51_soc.clock", 0x1000); 174 memory_region_add_subregion_overlap(&s->container, 175 NRF51_IOMEM_BASE, &s->clock, -1); 176 177 create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE, 178 NRF51_IOMEM_SIZE); 179 create_unimplemented_device("nrf51_soc.private", 180 NRF51_PRIVATE_BASE, NRF51_PRIVATE_SIZE); 181 } 182 183 static void nrf51_soc_init(Object *obj) 184 { 185 uint8_t i = 0; 186 187 NRF51State *s = NRF51_SOC(obj); 188 189 memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX); 190 191 sysbus_init_child_obj(OBJECT(s), "armv6m", OBJECT(&s->cpu), sizeof(s->cpu), 192 TYPE_ARMV7M); 193 qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type", 194 ARM_CPU_TYPE_NAME("cortex-m0")); 195 qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32); 196 197 sysbus_init_child_obj(obj, "uart", &s->uart, sizeof(s->uart), 198 TYPE_NRF51_UART); 199 object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev", 200 &error_abort); 201 202 sysbus_init_child_obj(obj, "rng", &s->rng, sizeof(s->rng), 203 TYPE_NRF51_RNG); 204 205 sysbus_init_child_obj(obj, "nvm", &s->nvm, sizeof(s->nvm), TYPE_NRF51_NVM); 206 207 sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio), 208 TYPE_NRF51_GPIO); 209 210 for (i = 0; i < NRF51_NUM_TIMERS; i++) { 211 sysbus_init_child_obj(obj, "timer[*]", &s->timer[i], 212 sizeof(s->timer[i]), TYPE_NRF51_TIMER); 213 214 } 215 } 216 217 static Property nrf51_soc_properties[] = { 218 DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGION, 219 MemoryRegion *), 220 DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_SIZE), 221 DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size, 222 NRF51822_FLASH_SIZE), 223 DEFINE_PROP_END_OF_LIST(), 224 }; 225 226 static void nrf51_soc_class_init(ObjectClass *klass, void *data) 227 { 228 DeviceClass *dc = DEVICE_CLASS(klass); 229 230 dc->realize = nrf51_soc_realize; 231 dc->props = nrf51_soc_properties; 232 } 233 234 static const TypeInfo nrf51_soc_info = { 235 .name = TYPE_NRF51_SOC, 236 .parent = TYPE_SYS_BUS_DEVICE, 237 .instance_size = sizeof(NRF51State), 238 .instance_init = nrf51_soc_init, 239 .class_init = nrf51_soc_class_init, 240 }; 241 242 static void nrf51_soc_types(void) 243 { 244 type_register_static(&nrf51_soc_info); 245 } 246 type_init(nrf51_soc_types) 247