1 /* 2 * Nordic Semiconductor nRF51 SoC 3 * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf 4 * 5 * Copyright 2018 Joel Stanley <joel@jms.id.au> 6 * 7 * This code is licensed under the GPL version 2 or later. See 8 * the COPYING file in the top-level directory. 9 */ 10 11 #include "qemu/osdep.h" 12 #include "qapi/error.h" 13 #include "hw/arm/boot.h" 14 #include "hw/sysbus.h" 15 #include "hw/qdev-clock.h" 16 #include "hw/misc/unimp.h" 17 #include "qemu/log.h" 18 19 #include "hw/arm/nrf51.h" 20 #include "hw/arm/nrf51_soc.h" 21 22 /* 23 * The size and base is for the NRF51822 part. If other parts 24 * are supported in the future, add a sub-class of NRF51SoC for 25 * the specific variants 26 */ 27 #define NRF51822_FLASH_PAGES 256 28 #define NRF51822_SRAM_PAGES 16 29 #define NRF51822_FLASH_SIZE (NRF51822_FLASH_PAGES * NRF51_PAGE_SIZE) 30 #define NRF51822_SRAM_SIZE (NRF51822_SRAM_PAGES * NRF51_PAGE_SIZE) 31 32 #define BASE_TO_IRQ(base) ((base >> 12) & 0x1F) 33 34 /* HCLK (the main CPU clock) on this SoC is always 16MHz */ 35 #define HCLK_FRQ 16000000 36 37 static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size) 38 { 39 qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n", 40 __func__, addr, size); 41 return 1; 42 } 43 44 static void clock_write(void *opaque, hwaddr addr, uint64_t data, 45 unsigned int size) 46 { 47 qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n", 48 __func__, addr, data, size); 49 } 50 51 static const MemoryRegionOps clock_ops = { 52 .read = clock_read, 53 .write = clock_write 54 }; 55 56 57 static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) 58 { 59 NRF51State *s = NRF51_SOC(dev_soc); 60 MemoryRegion *mr; 61 uint8_t i = 0; 62 hwaddr base_addr = 0; 63 64 if (!s->board_memory) { 65 error_setg(errp, "memory property was not set"); 66 return; 67 } 68 69 /* 70 * HCLK on this SoC is fixed, so we set up sysclk ourselves and 71 * the board shouldn't connect it. 72 */ 73 if (clock_has_source(s->sysclk)) { 74 error_setg(errp, "sysclk clock must not be wired up by the board code"); 75 return; 76 } 77 /* This clock doesn't need migration because it is fixed-frequency */ 78 clock_set_hz(s->sysclk, HCLK_FRQ); 79 qdev_connect_clock_in(DEVICE(&s->cpu), "cpuclk", s->sysclk); 80 /* 81 * This SoC has no systick device, so don't connect refclk. 82 * TODO: model the lack of systick (currently the armv7m object 83 * will always provide one). 84 */ 85 86 object_property_set_link(OBJECT(&s->cpu), "memory", OBJECT(&s->container), 87 &error_abort); 88 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu), errp)) { 89 return; 90 } 91 92 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1); 93 94 if (!memory_region_init_ram(&s->sram, OBJECT(s), "nrf51.sram", s->sram_size, 95 errp)) { 96 return; 97 } 98 memory_region_add_subregion(&s->container, NRF51_SRAM_BASE, &s->sram); 99 100 /* UART */ 101 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) { 102 return; 103 } 104 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0); 105 memory_region_add_subregion_overlap(&s->container, NRF51_UART_BASE, mr, 0); 106 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0, 107 qdev_get_gpio_in(DEVICE(&s->cpu), 108 BASE_TO_IRQ(NRF51_UART_BASE))); 109 110 /* RNG */ 111 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rng), errp)) { 112 return; 113 } 114 115 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0); 116 memory_region_add_subregion_overlap(&s->container, NRF51_RNG_BASE, mr, 0); 117 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0, 118 qdev_get_gpio_in(DEVICE(&s->cpu), 119 BASE_TO_IRQ(NRF51_RNG_BASE))); 120 121 /* UICR, FICR, NVMC, FLASH */ 122 if (!object_property_set_uint(OBJECT(&s->nvm), "flash-size", 123 s->flash_size, errp)) { 124 return; 125 } 126 127 if (!sysbus_realize(SYS_BUS_DEVICE(&s->nvm), errp)) { 128 return; 129 } 130 131 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 0); 132 memory_region_add_subregion_overlap(&s->container, NRF51_NVMC_BASE, mr, 0); 133 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 1); 134 memory_region_add_subregion_overlap(&s->container, NRF51_FICR_BASE, mr, 0); 135 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 2); 136 memory_region_add_subregion_overlap(&s->container, NRF51_UICR_BASE, mr, 0); 137 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 3); 138 memory_region_add_subregion_overlap(&s->container, NRF51_FLASH_BASE, mr, 0); 139 140 /* GPIO */ 141 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 142 return; 143 } 144 145 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0); 146 memory_region_add_subregion_overlap(&s->container, NRF51_GPIO_BASE, mr, 0); 147 148 /* Pass all GPIOs to the SOC layer so they are available to the board */ 149 qdev_pass_gpios(DEVICE(&s->gpio), dev_soc, NULL); 150 151 /* TIMER */ 152 for (i = 0; i < NRF51_NUM_TIMERS; i++) { 153 if (!object_property_set_uint(OBJECT(&s->timer[i]), "id", i, errp)) { 154 return; 155 } 156 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), errp)) { 157 return; 158 } 159 160 base_addr = NRF51_TIMER_BASE + i * NRF51_PERIPHERAL_SIZE; 161 162 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr); 163 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0, 164 qdev_get_gpio_in(DEVICE(&s->cpu), 165 BASE_TO_IRQ(base_addr))); 166 } 167 168 /* STUB Peripherals */ 169 memory_region_init_io(&s->clock, OBJECT(dev_soc), &clock_ops, NULL, 170 "nrf51_soc.clock", NRF51_PERIPHERAL_SIZE); 171 memory_region_add_subregion_overlap(&s->container, 172 NRF51_IOMEM_BASE, &s->clock, -1); 173 174 create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE, 175 NRF51_IOMEM_SIZE); 176 create_unimplemented_device("nrf51_soc.private", 177 NRF51_PRIVATE_BASE, NRF51_PRIVATE_SIZE); 178 } 179 180 static void nrf51_soc_init(Object *obj) 181 { 182 uint8_t i = 0; 183 184 NRF51State *s = NRF51_SOC(obj); 185 186 memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX); 187 188 object_initialize_child(OBJECT(s), "armv6m", &s->cpu, TYPE_ARMV7M); 189 qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type", 190 ARM_CPU_TYPE_NAME("cortex-m0")); 191 qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32); 192 193 object_initialize_child(obj, "uart", &s->uart, TYPE_NRF51_UART); 194 object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev"); 195 196 object_initialize_child(obj, "rng", &s->rng, TYPE_NRF51_RNG); 197 198 object_initialize_child(obj, "nvm", &s->nvm, TYPE_NRF51_NVM); 199 200 object_initialize_child(obj, "gpio", &s->gpio, TYPE_NRF51_GPIO); 201 202 for (i = 0; i < NRF51_NUM_TIMERS; i++) { 203 object_initialize_child(obj, "timer[*]", &s->timer[i], 204 TYPE_NRF51_TIMER); 205 206 } 207 208 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); 209 } 210 211 static Property nrf51_soc_properties[] = { 212 DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGION, 213 MemoryRegion *), 214 DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_SIZE), 215 DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size, 216 NRF51822_FLASH_SIZE), 217 DEFINE_PROP_END_OF_LIST(), 218 }; 219 220 static void nrf51_soc_class_init(ObjectClass *klass, void *data) 221 { 222 DeviceClass *dc = DEVICE_CLASS(klass); 223 224 dc->realize = nrf51_soc_realize; 225 device_class_set_props(dc, nrf51_soc_properties); 226 } 227 228 static const TypeInfo nrf51_soc_info = { 229 .name = TYPE_NRF51_SOC, 230 .parent = TYPE_SYS_BUS_DEVICE, 231 .instance_size = sizeof(NRF51State), 232 .instance_init = nrf51_soc_init, 233 .class_init = nrf51_soc_class_init, 234 }; 235 236 static void nrf51_soc_types(void) 237 { 238 type_register_static(&nrf51_soc_info); 239 } 240 type_init(nrf51_soc_types) 241