1 /* 2 * Nordic Semiconductor nRF51 SoC 3 * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf 4 * 5 * Copyright 2018 Joel Stanley <joel@jms.id.au> 6 * 7 * This code is licensed under the GPL version 2 or later. See 8 * the COPYING file in the top-level directory. 9 */ 10 11 #include "qemu/osdep.h" 12 #include "qapi/error.h" 13 #include "qemu-common.h" 14 #include "hw/arm/arm.h" 15 #include "hw/sysbus.h" 16 #include "hw/boards.h" 17 #include "hw/misc/unimp.h" 18 #include "exec/address-spaces.h" 19 #include "sysemu/sysemu.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 23 #include "hw/arm/nrf51.h" 24 #include "hw/arm/nrf51_soc.h" 25 26 /* 27 * The size and base is for the NRF51822 part. If other parts 28 * are supported in the future, add a sub-class of NRF51SoC for 29 * the specific variants 30 */ 31 #define NRF51822_FLASH_PAGES 256 32 #define NRF51822_SRAM_PAGES 16 33 #define NRF51822_FLASH_SIZE (NRF51822_FLASH_PAGES * NRF51_PAGE_SIZE) 34 #define NRF51822_SRAM_SIZE (NRF51822_SRAM_PAGES * NRF51_PAGE_SIZE) 35 36 #define BASE_TO_IRQ(base) ((base >> 12) & 0x1F) 37 38 static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size) 39 { 40 qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n", 41 __func__, addr, size); 42 return 1; 43 } 44 45 static void clock_write(void *opaque, hwaddr addr, uint64_t data, 46 unsigned int size) 47 { 48 qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n", 49 __func__, addr, data, size); 50 } 51 52 static const MemoryRegionOps clock_ops = { 53 .read = clock_read, 54 .write = clock_write 55 }; 56 57 58 static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) 59 { 60 NRF51State *s = NRF51_SOC(dev_soc); 61 MemoryRegion *mr; 62 Error *err = NULL; 63 uint8_t i = 0; 64 hwaddr base_addr = 0; 65 66 if (!s->board_memory) { 67 error_setg(errp, "memory property was not set"); 68 return; 69 } 70 71 object_property_set_link(OBJECT(&s->cpu), OBJECT(&s->container), "memory", 72 &err); 73 if (err) { 74 error_propagate(errp, err); 75 return; 76 } 77 object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); 78 if (err) { 79 error_propagate(errp, err); 80 return; 81 } 82 83 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1); 84 85 memory_region_init_ram(&s->sram, OBJECT(s), "nrf51.sram", s->sram_size, 86 &err); 87 if (err) { 88 error_propagate(errp, err); 89 return; 90 } 91 memory_region_add_subregion(&s->container, NRF51_SRAM_BASE, &s->sram); 92 93 /* UART */ 94 object_property_set_bool(OBJECT(&s->uart), true, "realized", &err); 95 if (err) { 96 error_propagate(errp, err); 97 return; 98 } 99 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0); 100 memory_region_add_subregion_overlap(&s->container, NRF51_UART_BASE, mr, 0); 101 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0, 102 qdev_get_gpio_in(DEVICE(&s->cpu), 103 BASE_TO_IRQ(NRF51_UART_BASE))); 104 105 /* RNG */ 106 object_property_set_bool(OBJECT(&s->rng), true, "realized", &err); 107 if (err) { 108 error_propagate(errp, err); 109 return; 110 } 111 112 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0); 113 memory_region_add_subregion_overlap(&s->container, NRF51_RNG_BASE, mr, 0); 114 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0, 115 qdev_get_gpio_in(DEVICE(&s->cpu), 116 BASE_TO_IRQ(NRF51_RNG_BASE))); 117 118 /* UICR, FICR, NVMC, FLASH */ 119 object_property_set_uint(OBJECT(&s->nvm), s->flash_size, "flash-size", 120 &err); 121 if (err) { 122 error_propagate(errp, err); 123 return; 124 } 125 126 object_property_set_bool(OBJECT(&s->nvm), true, "realized", &err); 127 if (err) { 128 error_propagate(errp, err); 129 return; 130 } 131 132 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 0); 133 memory_region_add_subregion_overlap(&s->container, NRF51_NVMC_BASE, mr, 0); 134 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 1); 135 memory_region_add_subregion_overlap(&s->container, NRF51_FICR_BASE, mr, 0); 136 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 2); 137 memory_region_add_subregion_overlap(&s->container, NRF51_UICR_BASE, mr, 0); 138 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 3); 139 memory_region_add_subregion_overlap(&s->container, NRF51_FLASH_BASE, mr, 0); 140 141 /* GPIO */ 142 object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err); 143 if (err) { 144 error_propagate(errp, err); 145 return; 146 } 147 148 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0); 149 memory_region_add_subregion_overlap(&s->container, NRF51_GPIO_BASE, mr, 0); 150 151 /* Pass all GPIOs to the SOC layer so they are available to the board */ 152 qdev_pass_gpios(DEVICE(&s->gpio), dev_soc, NULL); 153 154 /* TIMER */ 155 for (i = 0; i < NRF51_NUM_TIMERS; i++) { 156 object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err); 157 if (err) { 158 error_propagate(errp, err); 159 return; 160 } 161 162 base_addr = NRF51_TIMER_BASE + i * NRF51_TIMER_SIZE; 163 164 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr); 165 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0, 166 qdev_get_gpio_in(DEVICE(&s->cpu), 167 BASE_TO_IRQ(base_addr))); 168 } 169 170 /* STUB Peripherals */ 171 memory_region_init_io(&s->clock, NULL, &clock_ops, NULL, 172 "nrf51_soc.clock", 0x1000); 173 memory_region_add_subregion_overlap(&s->container, 174 NRF51_IOMEM_BASE, &s->clock, -1); 175 176 create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE, 177 NRF51_IOMEM_SIZE); 178 create_unimplemented_device("nrf51_soc.private", 179 NRF51_PRIVATE_BASE, NRF51_PRIVATE_SIZE); 180 } 181 182 static void nrf51_soc_init(Object *obj) 183 { 184 uint8_t i = 0; 185 186 NRF51State *s = NRF51_SOC(obj); 187 188 memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX); 189 190 sysbus_init_child_obj(OBJECT(s), "armv6m", OBJECT(&s->cpu), sizeof(s->cpu), 191 TYPE_ARMV7M); 192 qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type", 193 ARM_CPU_TYPE_NAME("cortex-m0")); 194 qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32); 195 196 sysbus_init_child_obj(obj, "uart", &s->uart, sizeof(s->uart), 197 TYPE_NRF51_UART); 198 object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev", 199 &error_abort); 200 201 sysbus_init_child_obj(obj, "rng", &s->rng, sizeof(s->rng), 202 TYPE_NRF51_RNG); 203 204 sysbus_init_child_obj(obj, "nvm", &s->nvm, sizeof(s->nvm), TYPE_NRF51_NVM); 205 206 sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio), 207 TYPE_NRF51_GPIO); 208 209 for (i = 0; i < NRF51_NUM_TIMERS; i++) { 210 sysbus_init_child_obj(obj, "timer[*]", &s->timer[i], 211 sizeof(s->timer[i]), TYPE_NRF51_TIMER); 212 213 } 214 } 215 216 static Property nrf51_soc_properties[] = { 217 DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGION, 218 MemoryRegion *), 219 DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_SIZE), 220 DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size, 221 NRF51822_FLASH_SIZE), 222 DEFINE_PROP_END_OF_LIST(), 223 }; 224 225 static void nrf51_soc_class_init(ObjectClass *klass, void *data) 226 { 227 DeviceClass *dc = DEVICE_CLASS(klass); 228 229 dc->realize = nrf51_soc_realize; 230 dc->props = nrf51_soc_properties; 231 } 232 233 static const TypeInfo nrf51_soc_info = { 234 .name = TYPE_NRF51_SOC, 235 .parent = TYPE_SYS_BUS_DEVICE, 236 .instance_size = sizeof(NRF51State), 237 .instance_init = nrf51_soc_init, 238 .class_init = nrf51_soc_class_init, 239 }; 240 241 static void nrf51_soc_types(void) 242 { 243 type_register_static(&nrf51_soc_info); 244 } 245 type_init(nrf51_soc_types) 246