1 /* 2 * Nordic Semiconductor nRF51 SoC 3 * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf 4 * 5 * Copyright 2018 Joel Stanley <joel@jms.id.au> 6 * 7 * This code is licensed under the GPL version 2 or later. See 8 * the COPYING file in the top-level directory. 9 */ 10 11 #include "qemu/osdep.h" 12 #include "qapi/error.h" 13 #include "qemu-common.h" 14 #include "hw/arm/arm.h" 15 #include "hw/sysbus.h" 16 #include "hw/boards.h" 17 #include "hw/devices.h" 18 #include "hw/misc/unimp.h" 19 #include "exec/address-spaces.h" 20 #include "sysemu/sysemu.h" 21 #include "qemu/log.h" 22 #include "cpu.h" 23 24 #include "hw/arm/nrf51.h" 25 #include "hw/arm/nrf51_soc.h" 26 27 /* 28 * The size and base is for the NRF51822 part. If other parts 29 * are supported in the future, add a sub-class of NRF51SoC for 30 * the specific variants 31 */ 32 #define NRF51822_FLASH_SIZE (256 * NRF51_PAGE_SIZE) 33 #define NRF51822_SRAM_SIZE (16 * NRF51_PAGE_SIZE) 34 35 #define BASE_TO_IRQ(base) ((base >> 12) & 0x1F) 36 37 static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size) 38 { 39 qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n", 40 __func__, addr, size); 41 return 1; 42 } 43 44 static void clock_write(void *opaque, hwaddr addr, uint64_t data, 45 unsigned int size) 46 { 47 qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n", 48 __func__, addr, data, size); 49 } 50 51 static const MemoryRegionOps clock_ops = { 52 .read = clock_read, 53 .write = clock_write 54 }; 55 56 57 static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) 58 { 59 NRF51State *s = NRF51_SOC(dev_soc); 60 MemoryRegion *mr; 61 Error *err = NULL; 62 uint8_t i = 0; 63 hwaddr base_addr = 0; 64 65 if (!s->board_memory) { 66 error_setg(errp, "memory property was not set"); 67 return; 68 } 69 70 object_property_set_link(OBJECT(&s->cpu), OBJECT(&s->container), "memory", 71 &err); 72 if (err) { 73 error_propagate(errp, err); 74 return; 75 } 76 object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); 77 if (err) { 78 error_propagate(errp, err); 79 return; 80 } 81 82 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1); 83 84 memory_region_init_rom(&s->flash, OBJECT(s), "nrf51.flash", s->flash_size, 85 &err); 86 if (err) { 87 error_propagate(errp, err); 88 return; 89 } 90 memory_region_add_subregion(&s->container, NRF51_FLASH_BASE, &s->flash); 91 92 memory_region_init_ram(&s->sram, NULL, "nrf51.sram", s->sram_size, &err); 93 if (err) { 94 error_propagate(errp, err); 95 return; 96 } 97 memory_region_add_subregion(&s->container, NRF51_SRAM_BASE, &s->sram); 98 99 /* UART */ 100 object_property_set_bool(OBJECT(&s->uart), true, "realized", &err); 101 if (err) { 102 error_propagate(errp, err); 103 return; 104 } 105 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0); 106 memory_region_add_subregion_overlap(&s->container, NRF51_UART_BASE, mr, 0); 107 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0, 108 qdev_get_gpio_in(DEVICE(&s->cpu), 109 BASE_TO_IRQ(NRF51_UART_BASE))); 110 111 /* RNG */ 112 object_property_set_bool(OBJECT(&s->rng), true, "realized", &err); 113 if (err) { 114 error_propagate(errp, err); 115 return; 116 } 117 118 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0); 119 memory_region_add_subregion_overlap(&s->container, NRF51_RNG_BASE, mr, 0); 120 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0, 121 qdev_get_gpio_in(DEVICE(&s->cpu), 122 BASE_TO_IRQ(NRF51_RNG_BASE))); 123 124 /* GPIO */ 125 object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err); 126 if (err) { 127 error_propagate(errp, err); 128 return; 129 } 130 131 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0); 132 memory_region_add_subregion_overlap(&s->container, NRF51_GPIO_BASE, mr, 0); 133 134 /* Pass all GPIOs to the SOC layer so they are available to the board */ 135 qdev_pass_gpios(DEVICE(&s->gpio), dev_soc, NULL); 136 137 /* TIMER */ 138 for (i = 0; i < NRF51_NUM_TIMERS; i++) { 139 object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err); 140 if (err) { 141 error_propagate(errp, err); 142 return; 143 } 144 145 base_addr = NRF51_TIMER_BASE + i * NRF51_TIMER_SIZE; 146 147 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr); 148 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0, 149 qdev_get_gpio_in(DEVICE(&s->cpu), 150 BASE_TO_IRQ(base_addr))); 151 } 152 153 /* STUB Peripherals */ 154 memory_region_init_io(&s->clock, NULL, &clock_ops, NULL, 155 "nrf51_soc.clock", 0x1000); 156 memory_region_add_subregion_overlap(&s->container, 157 NRF51_IOMEM_BASE, &s->clock, -1); 158 159 create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE, 160 NRF51_IOMEM_SIZE); 161 create_unimplemented_device("nrf51_soc.ficr", NRF51_FICR_BASE, 162 NRF51_FICR_SIZE); 163 create_unimplemented_device("nrf51_soc.private", 164 NRF51_PRIVATE_BASE, NRF51_PRIVATE_SIZE); 165 } 166 167 static void nrf51_soc_init(Object *obj) 168 { 169 uint8_t i = 0; 170 171 NRF51State *s = NRF51_SOC(obj); 172 173 memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX); 174 175 sysbus_init_child_obj(OBJECT(s), "armv6m", OBJECT(&s->cpu), sizeof(s->cpu), 176 TYPE_ARMV7M); 177 qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type", 178 ARM_CPU_TYPE_NAME("cortex-m0")); 179 qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32); 180 181 sysbus_init_child_obj(obj, "uart", &s->uart, sizeof(s->uart), 182 TYPE_NRF51_UART); 183 object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev", 184 &error_abort); 185 186 sysbus_init_child_obj(obj, "rng", &s->rng, sizeof(s->rng), 187 TYPE_NRF51_RNG); 188 189 sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio), 190 TYPE_NRF51_GPIO); 191 192 for (i = 0; i < NRF51_NUM_TIMERS; i++) { 193 sysbus_init_child_obj(obj, "timer[*]", &s->timer[i], 194 sizeof(s->timer[i]), TYPE_NRF51_TIMER); 195 196 } 197 } 198 199 static Property nrf51_soc_properties[] = { 200 DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGION, 201 MemoryRegion *), 202 DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_SIZE), 203 DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size, 204 NRF51822_FLASH_SIZE), 205 DEFINE_PROP_END_OF_LIST(), 206 }; 207 208 static void nrf51_soc_class_init(ObjectClass *klass, void *data) 209 { 210 DeviceClass *dc = DEVICE_CLASS(klass); 211 212 dc->realize = nrf51_soc_realize; 213 dc->props = nrf51_soc_properties; 214 } 215 216 static const TypeInfo nrf51_soc_info = { 217 .name = TYPE_NRF51_SOC, 218 .parent = TYPE_SYS_BUS_DEVICE, 219 .instance_size = sizeof(NRF51State), 220 .instance_init = nrf51_soc_init, 221 .class_init = nrf51_soc_class_init, 222 }; 223 224 static void nrf51_soc_types(void) 225 { 226 type_register_static(&nrf51_soc_info); 227 } 228 type_init(nrf51_soc_types) 229