1 /* 2 * Machine definitions for boards featuring an NPCM7xx SoC. 3 * 4 * Copyright 2020 Google LLC 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 */ 16 17 #include "qemu/osdep.h" 18 19 #include "hw/arm/npcm7xx.h" 20 #include "hw/core/cpu.h" 21 #include "hw/i2c/smbus_eeprom.h" 22 #include "hw/loader.h" 23 #include "hw/qdev-core.h" 24 #include "hw/qdev-properties.h" 25 #include "qapi/error.h" 26 #include "qemu-common.h" 27 #include "qemu/datadir.h" 28 #include "qemu/units.h" 29 30 #define NPCM750_EVB_POWER_ON_STRAPS 0x00001ff7 31 #define QUANTA_GSJ_POWER_ON_STRAPS 0x00001fff 32 #define QUANTA_GBS_POWER_ON_STRAPS 0x000017ff 33 34 static const char npcm7xx_default_bootrom[] = "npcm7xx_bootrom.bin"; 35 36 static void npcm7xx_load_bootrom(MachineState *machine, NPCM7xxState *soc) 37 { 38 const char *bios_name = machine->firmware ?: npcm7xx_default_bootrom; 39 g_autofree char *filename = NULL; 40 int ret; 41 42 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 43 if (!filename) { 44 error_report("Could not find ROM image '%s'", bios_name); 45 if (!machine->kernel_filename) { 46 /* We can't boot without a bootrom or a kernel image. */ 47 exit(1); 48 } 49 return; 50 } 51 ret = load_image_mr(filename, &soc->irom); 52 if (ret < 0) { 53 error_report("Failed to load ROM image '%s'", filename); 54 exit(1); 55 } 56 } 57 58 static void npcm7xx_connect_flash(NPCM7xxFIUState *fiu, int cs_no, 59 const char *flash_type, DriveInfo *dinfo) 60 { 61 DeviceState *flash; 62 qemu_irq flash_cs; 63 64 flash = qdev_new(flash_type); 65 if (dinfo) { 66 qdev_prop_set_drive(flash, "drive", blk_by_legacy_dinfo(dinfo)); 67 } 68 qdev_realize_and_unref(flash, BUS(fiu->spi), &error_fatal); 69 70 flash_cs = qdev_get_gpio_in_named(flash, SSI_GPIO_CS, 0); 71 qdev_connect_gpio_out_named(DEVICE(fiu), "cs", cs_no, flash_cs); 72 } 73 74 static void npcm7xx_connect_dram(NPCM7xxState *soc, MemoryRegion *dram) 75 { 76 memory_region_add_subregion(get_system_memory(), NPCM7XX_DRAM_BA, dram); 77 78 object_property_set_link(OBJECT(soc), "dram-mr", OBJECT(dram), 79 &error_abort); 80 } 81 82 static NPCM7xxState *npcm7xx_create_soc(MachineState *machine, 83 uint32_t hw_straps) 84 { 85 NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_GET_CLASS(machine); 86 MachineClass *mc = MACHINE_CLASS(nmc); 87 Object *obj; 88 89 if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { 90 error_report("This board can only be used with %s", 91 mc->default_cpu_type); 92 exit(1); 93 } 94 95 obj = object_new_with_props(nmc->soc_type, OBJECT(machine), "soc", 96 &error_abort, NULL); 97 object_property_set_uint(obj, "power-on-straps", hw_straps, &error_abort); 98 99 return NPCM7XX(obj); 100 } 101 102 static I2CBus *npcm7xx_i2c_get_bus(NPCM7xxState *soc, uint32_t num) 103 { 104 g_assert(num < ARRAY_SIZE(soc->smbus)); 105 return I2C_BUS(qdev_get_child_bus(DEVICE(&soc->smbus[num]), "i2c-bus")); 106 } 107 108 static void at24c_eeprom_init(NPCM7xxState *soc, int bus, uint8_t addr, 109 uint32_t rsize) 110 { 111 I2CBus *i2c_bus = npcm7xx_i2c_get_bus(soc, bus); 112 I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr); 113 DeviceState *dev = DEVICE(i2c_dev); 114 115 qdev_prop_set_uint32(dev, "rom-size", rsize); 116 i2c_slave_realize_and_unref(i2c_dev, i2c_bus, &error_abort); 117 } 118 119 static void npcm7xx_init_pwm_splitter(NPCM7xxMachine *machine, 120 NPCM7xxState *soc, const int *fan_counts) 121 { 122 SplitIRQ *splitters = machine->fan_splitter; 123 124 /* 125 * PWM 0~3 belong to module 0 output 0~3. 126 * PWM 4~7 belong to module 1 output 0~3. 127 */ 128 for (int i = 0; i < NPCM7XX_NR_PWM_MODULES; ++i) { 129 for (int j = 0; j < NPCM7XX_PWM_PER_MODULE; ++j) { 130 int splitter_no = i * NPCM7XX_PWM_PER_MODULE + j; 131 DeviceState *splitter; 132 133 if (fan_counts[splitter_no] < 1) { 134 continue; 135 } 136 object_initialize_child(OBJECT(machine), "fan-splitter[*]", 137 &splitters[splitter_no], TYPE_SPLIT_IRQ); 138 splitter = DEVICE(&splitters[splitter_no]); 139 qdev_prop_set_uint16(splitter, "num-lines", 140 fan_counts[splitter_no]); 141 qdev_realize(splitter, NULL, &error_abort); 142 qdev_connect_gpio_out_named(DEVICE(&soc->pwm[i]), "duty-gpio-out", 143 j, qdev_get_gpio_in(splitter, 0)); 144 } 145 } 146 } 147 148 static void npcm7xx_connect_pwm_fan(NPCM7xxState *soc, SplitIRQ *splitter, 149 int fan_no, int output_no) 150 { 151 DeviceState *fan; 152 int fan_input; 153 qemu_irq fan_duty_gpio; 154 155 g_assert(fan_no >= 0 && fan_no <= NPCM7XX_MFT_MAX_FAN_INPUT); 156 /* 157 * Fan 0~1 belong to module 0 input 0~1. 158 * Fan 2~3 belong to module 1 input 0~1. 159 * ... 160 * Fan 14~15 belong to module 7 input 0~1. 161 * Fan 16~17 belong to module 0 input 2~3. 162 * Fan 18~19 belong to module 1 input 2~3. 163 */ 164 if (fan_no < 16) { 165 fan = DEVICE(&soc->mft[fan_no / 2]); 166 fan_input = fan_no % 2; 167 } else { 168 fan = DEVICE(&soc->mft[(fan_no - 16) / 2]); 169 fan_input = fan_no % 2 + 2; 170 } 171 172 /* Connect the Fan to PWM module */ 173 fan_duty_gpio = qdev_get_gpio_in_named(fan, "duty", fan_input); 174 qdev_connect_gpio_out(DEVICE(splitter), output_no, fan_duty_gpio); 175 } 176 177 static void npcm750_evb_i2c_init(NPCM7xxState *soc) 178 { 179 /* lm75 temperature sensor on SVB, tmp105 is compatible */ 180 i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 0), "tmp105", 0x48); 181 /* lm75 temperature sensor on EB, tmp105 is compatible */ 182 i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1), "tmp105", 0x48); 183 /* tmp100 temperature sensor on EB, tmp105 is compatible */ 184 i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 2), "tmp105", 0x48); 185 /* tmp100 temperature sensor on SVB, tmp105 is compatible */ 186 i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 6), "tmp105", 0x48); 187 } 188 189 static void npcm750_evb_fan_init(NPCM7xxMachine *machine, NPCM7xxState *soc) 190 { 191 SplitIRQ *splitter = machine->fan_splitter; 192 static const int fan_counts[] = {2, 2, 2, 2, 2, 2, 2, 2}; 193 194 npcm7xx_init_pwm_splitter(machine, soc, fan_counts); 195 npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x00, 0); 196 npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x01, 1); 197 npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x02, 0); 198 npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x03, 1); 199 npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x04, 0); 200 npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x05, 1); 201 npcm7xx_connect_pwm_fan(soc, &splitter[3], 0x06, 0); 202 npcm7xx_connect_pwm_fan(soc, &splitter[3], 0x07, 1); 203 npcm7xx_connect_pwm_fan(soc, &splitter[4], 0x08, 0); 204 npcm7xx_connect_pwm_fan(soc, &splitter[4], 0x09, 1); 205 npcm7xx_connect_pwm_fan(soc, &splitter[5], 0x0a, 0); 206 npcm7xx_connect_pwm_fan(soc, &splitter[5], 0x0b, 1); 207 npcm7xx_connect_pwm_fan(soc, &splitter[6], 0x0c, 0); 208 npcm7xx_connect_pwm_fan(soc, &splitter[6], 0x0d, 1); 209 npcm7xx_connect_pwm_fan(soc, &splitter[7], 0x0e, 0); 210 npcm7xx_connect_pwm_fan(soc, &splitter[7], 0x0f, 1); 211 } 212 213 static void quanta_gsj_i2c_init(NPCM7xxState *soc) 214 { 215 /* GSJ machine have 4 max31725 temperature sensors, tmp105 is compatible. */ 216 i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1), "tmp105", 0x5c); 217 i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 2), "tmp105", 0x5c); 218 i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 3), "tmp105", 0x5c); 219 i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 4), "tmp105", 0x5c); 220 221 at24c_eeprom_init(soc, 9, 0x55, 8192); 222 at24c_eeprom_init(soc, 10, 0x55, 8192); 223 224 /* TODO: Add additional i2c devices. */ 225 } 226 227 static void quanta_gsj_fan_init(NPCM7xxMachine *machine, NPCM7xxState *soc) 228 { 229 SplitIRQ *splitter = machine->fan_splitter; 230 static const int fan_counts[] = {2, 2, 2, 0, 0, 0, 0, 0}; 231 232 npcm7xx_init_pwm_splitter(machine, soc, fan_counts); 233 npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x00, 0); 234 npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x01, 1); 235 npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x02, 0); 236 npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x03, 1); 237 npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x04, 0); 238 npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x05, 1); 239 } 240 241 static void quanta_gbs_i2c_init(NPCM7xxState *soc) 242 { 243 /* 244 * i2c-0: 245 * pca9546@71 246 * 247 * i2c-1: 248 * pca9535@24 249 * pca9535@20 250 * pca9535@21 251 * pca9535@22 252 * pca9535@23 253 * pca9535@25 254 * pca9535@26 255 * 256 * i2c-2: 257 * sbtsi@4c 258 * 259 * i2c-5: 260 * atmel,24c64@50 mb_fru 261 * pca9546@71 262 * - channel 0: max31725@54 263 * - channel 1: max31725@55 264 * - channel 2: max31725@5d 265 * atmel,24c64@51 fan_fru 266 * - channel 3: atmel,24c64@52 hsbp_fru 267 * 268 * i2c-6: 269 * pca9545@73 270 * 271 * i2c-7: 272 * pca9545@72 273 * 274 * i2c-8: 275 * adi,adm1272@10 276 * 277 * i2c-9: 278 * pca9546@71 279 * - channel 0: isil,isl68137@60 280 * - channel 1: isil,isl68137@61 281 * - channel 2: isil,isl68137@63 282 * - channel 3: isil,isl68137@45 283 * 284 * i2c-10: 285 * pca9545@71 286 * 287 * i2c-11: 288 * pca9545@76 289 * 290 * i2c-12: 291 * maxim,max34451@4e 292 * isil,isl68137@5d 293 * isil,isl68137@5e 294 * 295 * i2c-14: 296 * pca9545@70 297 */ 298 } 299 300 static void npcm750_evb_init(MachineState *machine) 301 { 302 NPCM7xxState *soc; 303 304 soc = npcm7xx_create_soc(machine, NPCM750_EVB_POWER_ON_STRAPS); 305 npcm7xx_connect_dram(soc, machine->ram); 306 qdev_realize(DEVICE(soc), NULL, &error_fatal); 307 308 npcm7xx_load_bootrom(machine, soc); 309 npcm7xx_connect_flash(&soc->fiu[0], 0, "w25q256", drive_get(IF_MTD, 0, 0)); 310 npcm750_evb_i2c_init(soc); 311 npcm750_evb_fan_init(NPCM7XX_MACHINE(machine), soc); 312 npcm7xx_load_kernel(machine, soc); 313 } 314 315 static void quanta_gsj_init(MachineState *machine) 316 { 317 NPCM7xxState *soc; 318 319 soc = npcm7xx_create_soc(machine, QUANTA_GSJ_POWER_ON_STRAPS); 320 npcm7xx_connect_dram(soc, machine->ram); 321 qdev_realize(DEVICE(soc), NULL, &error_fatal); 322 323 npcm7xx_load_bootrom(machine, soc); 324 npcm7xx_connect_flash(&soc->fiu[0], 0, "mx25l25635e", 325 drive_get(IF_MTD, 0, 0)); 326 quanta_gsj_i2c_init(soc); 327 quanta_gsj_fan_init(NPCM7XX_MACHINE(machine), soc); 328 npcm7xx_load_kernel(machine, soc); 329 } 330 331 static void quanta_gbs_init(MachineState *machine) 332 { 333 NPCM7xxState *soc; 334 335 soc = npcm7xx_create_soc(machine, QUANTA_GBS_POWER_ON_STRAPS); 336 npcm7xx_connect_dram(soc, machine->ram); 337 qdev_realize(DEVICE(soc), NULL, &error_fatal); 338 339 npcm7xx_load_bootrom(machine, soc); 340 341 npcm7xx_connect_flash(&soc->fiu[0], 0, "mx66u51235f", 342 drive_get(IF_MTD, 0, 0)); 343 344 quanta_gbs_i2c_init(soc); 345 npcm7xx_load_kernel(machine, soc); 346 } 347 348 static void npcm7xx_set_soc_type(NPCM7xxMachineClass *nmc, const char *type) 349 { 350 NPCM7xxClass *sc = NPCM7XX_CLASS(object_class_by_name(type)); 351 MachineClass *mc = MACHINE_CLASS(nmc); 352 353 nmc->soc_type = type; 354 mc->default_cpus = mc->min_cpus = mc->max_cpus = sc->num_cpus; 355 } 356 357 static void npcm7xx_machine_class_init(ObjectClass *oc, void *data) 358 { 359 MachineClass *mc = MACHINE_CLASS(oc); 360 361 mc->no_floppy = 1; 362 mc->no_cdrom = 1; 363 mc->no_parallel = 1; 364 mc->default_ram_id = "ram"; 365 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); 366 } 367 368 /* 369 * Schematics: 370 * https://github.com/Nuvoton-Israel/nuvoton-info/blob/master/npcm7xx-poleg/evaluation-board/board_deliverables/NPCM750x_EB_ver.A1.1_COMPLETE.pdf 371 */ 372 static void npcm750_evb_machine_class_init(ObjectClass *oc, void *data) 373 { 374 NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc); 375 MachineClass *mc = MACHINE_CLASS(oc); 376 377 npcm7xx_set_soc_type(nmc, TYPE_NPCM750); 378 379 mc->desc = "Nuvoton NPCM750 Evaluation Board (Cortex-A9)"; 380 mc->init = npcm750_evb_init; 381 mc->default_ram_size = 512 * MiB; 382 }; 383 384 static void gsj_machine_class_init(ObjectClass *oc, void *data) 385 { 386 NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc); 387 MachineClass *mc = MACHINE_CLASS(oc); 388 389 npcm7xx_set_soc_type(nmc, TYPE_NPCM730); 390 391 mc->desc = "Quanta GSJ (Cortex-A9)"; 392 mc->init = quanta_gsj_init; 393 mc->default_ram_size = 512 * MiB; 394 }; 395 396 static void gbs_bmc_machine_class_init(ObjectClass *oc, void *data) 397 { 398 NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc); 399 MachineClass *mc = MACHINE_CLASS(oc); 400 401 npcm7xx_set_soc_type(nmc, TYPE_NPCM730); 402 403 mc->desc = "Quanta GBS (Cortex-A9)"; 404 mc->init = quanta_gbs_init; 405 mc->default_ram_size = 1 * GiB; 406 } 407 408 static const TypeInfo npcm7xx_machine_types[] = { 409 { 410 .name = TYPE_NPCM7XX_MACHINE, 411 .parent = TYPE_MACHINE, 412 .instance_size = sizeof(NPCM7xxMachine), 413 .class_size = sizeof(NPCM7xxMachineClass), 414 .class_init = npcm7xx_machine_class_init, 415 .abstract = true, 416 }, { 417 .name = MACHINE_TYPE_NAME("npcm750-evb"), 418 .parent = TYPE_NPCM7XX_MACHINE, 419 .class_init = npcm750_evb_machine_class_init, 420 }, { 421 .name = MACHINE_TYPE_NAME("quanta-gsj"), 422 .parent = TYPE_NPCM7XX_MACHINE, 423 .class_init = gsj_machine_class_init, 424 }, { 425 .name = MACHINE_TYPE_NAME("quanta-gbs-bmc"), 426 .parent = TYPE_NPCM7XX_MACHINE, 427 .class_init = gbs_bmc_machine_class_init, 428 }, 429 }; 430 431 DEFINE_TYPES(npcm7xx_machine_types) 432