1 /* 2 * Machine definitions for boards featuring an NPCM7xx SoC. 3 * 4 * Copyright 2020 Google LLC 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 */ 16 17 #include "qemu/osdep.h" 18 19 #include "hw/arm/npcm7xx.h" 20 #include "hw/core/cpu.h" 21 #include "hw/i2c/i2c_mux_pca954x.h" 22 #include "hw/i2c/smbus_eeprom.h" 23 #include "hw/loader.h" 24 #include "hw/nvram/eeprom_at24c.h" 25 #include "hw/qdev-core.h" 26 #include "hw/qdev-properties.h" 27 #include "qapi/error.h" 28 #include "qemu/datadir.h" 29 #include "qemu/units.h" 30 #include "sysemu/blockdev.h" 31 #include "sysemu/sysemu.h" 32 #include "sysemu/block-backend.h" 33 34 #define NPCM7XX_POWER_ON_STRAPS_DEFAULT ( \ 35 NPCM7XX_PWRON_STRAP_SPI0F18 | \ 36 NPCM7XX_PWRON_STRAP_SFAB | \ 37 NPCM7XX_PWRON_STRAP_BSPA | \ 38 NPCM7XX_PWRON_STRAP_FUP(FUP_NORM_UART2) | \ 39 NPCM7XX_PWRON_STRAP_SECEN | \ 40 NPCM7XX_PWRON_STRAP_HIZ | \ 41 NPCM7XX_PWRON_STRAP_ECC | \ 42 NPCM7XX_PWRON_STRAP_RESERVE1 | \ 43 NPCM7XX_PWRON_STRAP_J2EN | \ 44 NPCM7XX_PWRON_STRAP_CKFRQ(CKFRQ_DEFAULT)) 45 46 #define NPCM750_EVB_POWER_ON_STRAPS ( \ 47 NPCM7XX_POWER_ON_STRAPS_DEFAULT & ~NPCM7XX_PWRON_STRAP_J2EN) 48 #define QUANTA_GSJ_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT 49 #define QUANTA_GBS_POWER_ON_STRAPS ( \ 50 NPCM7XX_POWER_ON_STRAPS_DEFAULT & ~NPCM7XX_PWRON_STRAP_SFAB) 51 #define KUDO_BMC_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT 52 #define MORI_BMC_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT 53 54 static const char npcm7xx_default_bootrom[] = "npcm7xx_bootrom.bin"; 55 56 static void npcm7xx_load_bootrom(MachineState *machine, NPCM7xxState *soc) 57 { 58 const char *bios_name = machine->firmware ?: npcm7xx_default_bootrom; 59 g_autofree char *filename = NULL; 60 int ret; 61 62 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 63 if (!filename) { 64 error_report("Could not find ROM image '%s'", bios_name); 65 if (!machine->kernel_filename) { 66 /* We can't boot without a bootrom or a kernel image. */ 67 exit(1); 68 } 69 return; 70 } 71 ret = load_image_mr(filename, &soc->irom); 72 if (ret < 0) { 73 error_report("Failed to load ROM image '%s'", filename); 74 exit(1); 75 } 76 } 77 78 static void npcm7xx_connect_flash(NPCM7xxFIUState *fiu, int cs_no, 79 const char *flash_type, DriveInfo *dinfo) 80 { 81 DeviceState *flash; 82 qemu_irq flash_cs; 83 84 flash = qdev_new(flash_type); 85 if (dinfo) { 86 qdev_prop_set_drive(flash, "drive", blk_by_legacy_dinfo(dinfo)); 87 } 88 qdev_realize_and_unref(flash, BUS(fiu->spi), &error_fatal); 89 90 flash_cs = qdev_get_gpio_in_named(flash, SSI_GPIO_CS, 0); 91 qdev_connect_gpio_out_named(DEVICE(fiu), "cs", cs_no, flash_cs); 92 } 93 94 static void npcm7xx_connect_dram(NPCM7xxState *soc, MemoryRegion *dram) 95 { 96 memory_region_add_subregion(get_system_memory(), NPCM7XX_DRAM_BA, dram); 97 98 object_property_set_link(OBJECT(soc), "dram-mr", OBJECT(dram), 99 &error_abort); 100 } 101 102 static void sdhci_attach_drive(SDHCIState *sdhci, int unit) 103 { 104 DriveInfo *di = drive_get(IF_SD, 0, unit); 105 BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL; 106 107 BusState *bus = qdev_get_child_bus(DEVICE(sdhci), "sd-bus"); 108 if (bus == NULL) { 109 error_report("No SD bus found in SOC object"); 110 exit(1); 111 } 112 113 DeviceState *carddev = qdev_new(TYPE_SD_CARD); 114 qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal); 115 qdev_realize_and_unref(carddev, bus, &error_fatal); 116 } 117 118 static NPCM7xxState *npcm7xx_create_soc(MachineState *machine, 119 uint32_t hw_straps) 120 { 121 NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_GET_CLASS(machine); 122 MachineClass *mc = MACHINE_CLASS(nmc); 123 Object *obj; 124 125 if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { 126 error_report("This board can only be used with %s", 127 mc->default_cpu_type); 128 exit(1); 129 } 130 131 obj = object_new_with_props(nmc->soc_type, OBJECT(machine), "soc", 132 &error_abort, NULL); 133 object_property_set_uint(obj, "power-on-straps", hw_straps, &error_abort); 134 135 return NPCM7XX(obj); 136 } 137 138 static I2CBus *npcm7xx_i2c_get_bus(NPCM7xxState *soc, uint32_t num) 139 { 140 g_assert(num < ARRAY_SIZE(soc->smbus)); 141 return I2C_BUS(qdev_get_child_bus(DEVICE(&soc->smbus[num]), "i2c-bus")); 142 } 143 144 static void npcm7xx_init_pwm_splitter(NPCM7xxMachine *machine, 145 NPCM7xxState *soc, const int *fan_counts) 146 { 147 SplitIRQ *splitters = machine->fan_splitter; 148 149 /* 150 * PWM 0~3 belong to module 0 output 0~3. 151 * PWM 4~7 belong to module 1 output 0~3. 152 */ 153 for (int i = 0; i < NPCM7XX_NR_PWM_MODULES; ++i) { 154 for (int j = 0; j < NPCM7XX_PWM_PER_MODULE; ++j) { 155 int splitter_no = i * NPCM7XX_PWM_PER_MODULE + j; 156 DeviceState *splitter; 157 158 if (fan_counts[splitter_no] < 1) { 159 continue; 160 } 161 object_initialize_child(OBJECT(machine), "fan-splitter[*]", 162 &splitters[splitter_no], TYPE_SPLIT_IRQ); 163 splitter = DEVICE(&splitters[splitter_no]); 164 qdev_prop_set_uint16(splitter, "num-lines", 165 fan_counts[splitter_no]); 166 qdev_realize(splitter, NULL, &error_abort); 167 qdev_connect_gpio_out_named(DEVICE(&soc->pwm[i]), "duty-gpio-out", 168 j, qdev_get_gpio_in(splitter, 0)); 169 } 170 } 171 } 172 173 static void npcm7xx_connect_pwm_fan(NPCM7xxState *soc, SplitIRQ *splitter, 174 int fan_no, int output_no) 175 { 176 DeviceState *fan; 177 int fan_input; 178 qemu_irq fan_duty_gpio; 179 180 g_assert(fan_no >= 0 && fan_no <= NPCM7XX_MFT_MAX_FAN_INPUT); 181 /* 182 * Fan 0~1 belong to module 0 input 0~1. 183 * Fan 2~3 belong to module 1 input 0~1. 184 * ... 185 * Fan 14~15 belong to module 7 input 0~1. 186 * Fan 16~17 belong to module 0 input 2~3. 187 * Fan 18~19 belong to module 1 input 2~3. 188 */ 189 if (fan_no < 16) { 190 fan = DEVICE(&soc->mft[fan_no / 2]); 191 fan_input = fan_no % 2; 192 } else { 193 fan = DEVICE(&soc->mft[(fan_no - 16) / 2]); 194 fan_input = fan_no % 2 + 2; 195 } 196 197 /* Connect the Fan to PWM module */ 198 fan_duty_gpio = qdev_get_gpio_in_named(fan, "duty", fan_input); 199 qdev_connect_gpio_out(DEVICE(splitter), output_no, fan_duty_gpio); 200 } 201 202 static void npcm750_evb_i2c_init(NPCM7xxState *soc) 203 { 204 /* lm75 temperature sensor on SVB, tmp105 is compatible */ 205 i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 0), "tmp105", 0x48); 206 /* lm75 temperature sensor on EB, tmp105 is compatible */ 207 i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1), "tmp105", 0x48); 208 /* tmp100 temperature sensor on EB, tmp105 is compatible */ 209 i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 2), "tmp105", 0x48); 210 /* tmp100 temperature sensor on SVB, tmp105 is compatible */ 211 i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 6), "tmp105", 0x48); 212 } 213 214 static void npcm750_evb_fan_init(NPCM7xxMachine *machine, NPCM7xxState *soc) 215 { 216 SplitIRQ *splitter = machine->fan_splitter; 217 static const int fan_counts[] = {2, 2, 2, 2, 2, 2, 2, 2}; 218 219 npcm7xx_init_pwm_splitter(machine, soc, fan_counts); 220 npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x00, 0); 221 npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x01, 1); 222 npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x02, 0); 223 npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x03, 1); 224 npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x04, 0); 225 npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x05, 1); 226 npcm7xx_connect_pwm_fan(soc, &splitter[3], 0x06, 0); 227 npcm7xx_connect_pwm_fan(soc, &splitter[3], 0x07, 1); 228 npcm7xx_connect_pwm_fan(soc, &splitter[4], 0x08, 0); 229 npcm7xx_connect_pwm_fan(soc, &splitter[4], 0x09, 1); 230 npcm7xx_connect_pwm_fan(soc, &splitter[5], 0x0a, 0); 231 npcm7xx_connect_pwm_fan(soc, &splitter[5], 0x0b, 1); 232 npcm7xx_connect_pwm_fan(soc, &splitter[6], 0x0c, 0); 233 npcm7xx_connect_pwm_fan(soc, &splitter[6], 0x0d, 1); 234 npcm7xx_connect_pwm_fan(soc, &splitter[7], 0x0e, 0); 235 npcm7xx_connect_pwm_fan(soc, &splitter[7], 0x0f, 1); 236 } 237 238 static void quanta_gsj_i2c_init(NPCM7xxState *soc) 239 { 240 /* GSJ machine have 4 max31725 temperature sensors, tmp105 is compatible. */ 241 i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1), "tmp105", 0x5c); 242 i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 2), "tmp105", 0x5c); 243 i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 3), "tmp105", 0x5c); 244 i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 4), "tmp105", 0x5c); 245 246 at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 9), 0x55, 8192); 247 at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 10), 0x55, 8192); 248 249 /* 250 * i2c-11: 251 * - power-brick@36: delta,dps800 252 * - hotswap@15: ti,lm5066i 253 */ 254 255 /* 256 * i2c-12: 257 * - ucd90160@6b 258 */ 259 260 i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 15), "pca9548", 0x75); 261 } 262 263 static void quanta_gsj_fan_init(NPCM7xxMachine *machine, NPCM7xxState *soc) 264 { 265 SplitIRQ *splitter = machine->fan_splitter; 266 static const int fan_counts[] = {2, 2, 2, 0, 0, 0, 0, 0}; 267 268 npcm7xx_init_pwm_splitter(machine, soc, fan_counts); 269 npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x00, 0); 270 npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x01, 1); 271 npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x02, 0); 272 npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x03, 1); 273 npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x04, 0); 274 npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x05, 1); 275 } 276 277 static void quanta_gbs_i2c_init(NPCM7xxState *soc) 278 { 279 /* 280 * i2c-0: 281 * pca9546@71 282 * 283 * i2c-1: 284 * pca9535@24 285 * pca9535@20 286 * pca9535@21 287 * pca9535@22 288 * pca9535@23 289 * pca9535@25 290 * pca9535@26 291 * 292 * i2c-2: 293 * sbtsi@4c 294 * 295 * i2c-5: 296 * atmel,24c64@50 mb_fru 297 * pca9546@71 298 * - channel 0: max31725@54 299 * - channel 1: max31725@55 300 * - channel 2: max31725@5d 301 * atmel,24c64@51 fan_fru 302 * - channel 3: atmel,24c64@52 hsbp_fru 303 * 304 * i2c-6: 305 * pca9545@73 306 * 307 * i2c-7: 308 * pca9545@72 309 * 310 * i2c-8: 311 * adi,adm1272@10 312 * 313 * i2c-9: 314 * pca9546@71 315 * - channel 0: isil,isl68137@60 316 * - channel 1: isil,isl68137@61 317 * - channel 2: isil,isl68137@63 318 * - channel 3: isil,isl68137@45 319 * 320 * i2c-10: 321 * pca9545@71 322 * 323 * i2c-11: 324 * pca9545@76 325 * 326 * i2c-12: 327 * maxim,max34451@4e 328 * isil,isl68137@5d 329 * isil,isl68137@5e 330 * 331 * i2c-14: 332 * pca9545@70 333 */ 334 } 335 336 static void kudo_bmc_i2c_init(NPCM7xxState *soc) 337 { 338 I2CSlave *i2c_mux; 339 340 i2c_mux = i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1), 341 TYPE_PCA9548, 0x75); 342 343 /* tmp105 is compatible with the lm75 */ 344 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 4), "tmp105", 0x5c); 345 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 5), "tmp105", 0x5c); 346 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 6), "tmp105", 0x5c); 347 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 7), "tmp105", 0x5c); 348 349 i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1), TYPE_PCA9548, 0x77); 350 351 i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 4), TYPE_PCA9548, 0x77); 352 353 at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 4), 0x50, 8192); /* mbfru */ 354 355 i2c_mux = i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 13), 356 TYPE_PCA9548, 0x77); 357 358 /* tmp105 is compatible with the lm75 */ 359 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 2), "tmp105", 0x48); 360 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 3), "tmp105", 0x49); 361 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 4), "tmp105", 0x48); 362 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 5), "tmp105", 0x49); 363 364 at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 14), 0x55, 8192); /* bmcfru */ 365 366 /* TODO: Add remaining i2c devices. */ 367 } 368 369 static void npcm750_evb_init(MachineState *machine) 370 { 371 NPCM7xxState *soc; 372 373 soc = npcm7xx_create_soc(machine, NPCM750_EVB_POWER_ON_STRAPS); 374 npcm7xx_connect_dram(soc, machine->ram); 375 qdev_realize(DEVICE(soc), NULL, &error_fatal); 376 377 npcm7xx_load_bootrom(machine, soc); 378 npcm7xx_connect_flash(&soc->fiu[0], 0, "w25q256", drive_get(IF_MTD, 0, 0)); 379 npcm750_evb_i2c_init(soc); 380 npcm750_evb_fan_init(NPCM7XX_MACHINE(machine), soc); 381 npcm7xx_load_kernel(machine, soc); 382 } 383 384 static void quanta_gsj_init(MachineState *machine) 385 { 386 NPCM7xxState *soc; 387 388 soc = npcm7xx_create_soc(machine, QUANTA_GSJ_POWER_ON_STRAPS); 389 npcm7xx_connect_dram(soc, machine->ram); 390 qdev_realize(DEVICE(soc), NULL, &error_fatal); 391 392 npcm7xx_load_bootrom(machine, soc); 393 npcm7xx_connect_flash(&soc->fiu[0], 0, "mx25l25635e", 394 drive_get(IF_MTD, 0, 0)); 395 quanta_gsj_i2c_init(soc); 396 quanta_gsj_fan_init(NPCM7XX_MACHINE(machine), soc); 397 npcm7xx_load_kernel(machine, soc); 398 } 399 400 static void quanta_gbs_init(MachineState *machine) 401 { 402 NPCM7xxState *soc; 403 404 soc = npcm7xx_create_soc(machine, QUANTA_GBS_POWER_ON_STRAPS); 405 npcm7xx_connect_dram(soc, machine->ram); 406 qdev_realize(DEVICE(soc), NULL, &error_fatal); 407 408 npcm7xx_load_bootrom(machine, soc); 409 410 npcm7xx_connect_flash(&soc->fiu[0], 0, "mx66u51235f", 411 drive_get(IF_MTD, 0, 0)); 412 413 quanta_gbs_i2c_init(soc); 414 sdhci_attach_drive(&soc->mmc.sdhci, 0); 415 npcm7xx_load_kernel(machine, soc); 416 } 417 418 static void kudo_bmc_init(MachineState *machine) 419 { 420 NPCM7xxState *soc; 421 422 soc = npcm7xx_create_soc(machine, KUDO_BMC_POWER_ON_STRAPS); 423 npcm7xx_connect_dram(soc, machine->ram); 424 qdev_realize(DEVICE(soc), NULL, &error_fatal); 425 426 npcm7xx_load_bootrom(machine, soc); 427 npcm7xx_connect_flash(&soc->fiu[0], 0, "mx66u51235f", 428 drive_get(IF_MTD, 0, 0)); 429 npcm7xx_connect_flash(&soc->fiu[1], 0, "mx66u51235f", 430 drive_get(IF_MTD, 3, 0)); 431 432 kudo_bmc_i2c_init(soc); 433 sdhci_attach_drive(&soc->mmc.sdhci, 0); 434 npcm7xx_load_kernel(machine, soc); 435 } 436 437 static void mori_bmc_init(MachineState *machine) 438 { 439 NPCM7xxState *soc; 440 441 soc = npcm7xx_create_soc(machine, MORI_BMC_POWER_ON_STRAPS); 442 npcm7xx_connect_dram(soc, machine->ram); 443 qdev_realize(DEVICE(soc), NULL, &error_fatal); 444 445 npcm7xx_load_bootrom(machine, soc); 446 npcm7xx_connect_flash(&soc->fiu[1], 0, "mx66u51235f", 447 drive_get(IF_MTD, 3, 0)); 448 449 npcm7xx_load_kernel(machine, soc); 450 } 451 452 static void npcm7xx_set_soc_type(NPCM7xxMachineClass *nmc, const char *type) 453 { 454 NPCM7xxClass *sc = NPCM7XX_CLASS(object_class_by_name(type)); 455 MachineClass *mc = MACHINE_CLASS(nmc); 456 457 nmc->soc_type = type; 458 mc->default_cpus = mc->min_cpus = mc->max_cpus = sc->num_cpus; 459 } 460 461 static void npcm7xx_machine_class_init(ObjectClass *oc, void *data) 462 { 463 MachineClass *mc = MACHINE_CLASS(oc); 464 465 mc->no_floppy = 1; 466 mc->no_cdrom = 1; 467 mc->no_parallel = 1; 468 mc->default_ram_id = "ram"; 469 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); 470 } 471 472 /* 473 * Schematics: 474 * https://github.com/Nuvoton-Israel/nuvoton-info/blob/master/npcm7xx-poleg/evaluation-board/board_deliverables/NPCM750x_EB_ver.A1.1_COMPLETE.pdf 475 */ 476 static void npcm750_evb_machine_class_init(ObjectClass *oc, void *data) 477 { 478 NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc); 479 MachineClass *mc = MACHINE_CLASS(oc); 480 481 npcm7xx_set_soc_type(nmc, TYPE_NPCM750); 482 483 mc->desc = "Nuvoton NPCM750 Evaluation Board (Cortex-A9)"; 484 mc->init = npcm750_evb_init; 485 mc->default_ram_size = 512 * MiB; 486 }; 487 488 static void gsj_machine_class_init(ObjectClass *oc, void *data) 489 { 490 NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc); 491 MachineClass *mc = MACHINE_CLASS(oc); 492 493 npcm7xx_set_soc_type(nmc, TYPE_NPCM730); 494 495 mc->desc = "Quanta GSJ (Cortex-A9)"; 496 mc->init = quanta_gsj_init; 497 mc->default_ram_size = 512 * MiB; 498 }; 499 500 static void gbs_bmc_machine_class_init(ObjectClass *oc, void *data) 501 { 502 NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc); 503 MachineClass *mc = MACHINE_CLASS(oc); 504 505 npcm7xx_set_soc_type(nmc, TYPE_NPCM730); 506 507 mc->desc = "Quanta GBS (Cortex-A9)"; 508 mc->init = quanta_gbs_init; 509 mc->default_ram_size = 1 * GiB; 510 } 511 512 static void kudo_bmc_machine_class_init(ObjectClass *oc, void *data) 513 { 514 NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc); 515 MachineClass *mc = MACHINE_CLASS(oc); 516 517 npcm7xx_set_soc_type(nmc, TYPE_NPCM730); 518 519 mc->desc = "Kudo BMC (Cortex-A9)"; 520 mc->init = kudo_bmc_init; 521 mc->default_ram_size = 1 * GiB; 522 }; 523 524 static void mori_bmc_machine_class_init(ObjectClass *oc, void *data) 525 { 526 NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc); 527 MachineClass *mc = MACHINE_CLASS(oc); 528 529 npcm7xx_set_soc_type(nmc, TYPE_NPCM730); 530 531 mc->desc = "Mori BMC (Cortex-A9)"; 532 mc->init = mori_bmc_init; 533 mc->default_ram_size = 1 * GiB; 534 } 535 536 static const TypeInfo npcm7xx_machine_types[] = { 537 { 538 .name = TYPE_NPCM7XX_MACHINE, 539 .parent = TYPE_MACHINE, 540 .instance_size = sizeof(NPCM7xxMachine), 541 .class_size = sizeof(NPCM7xxMachineClass), 542 .class_init = npcm7xx_machine_class_init, 543 .abstract = true, 544 }, { 545 .name = MACHINE_TYPE_NAME("npcm750-evb"), 546 .parent = TYPE_NPCM7XX_MACHINE, 547 .class_init = npcm750_evb_machine_class_init, 548 }, { 549 .name = MACHINE_TYPE_NAME("quanta-gsj"), 550 .parent = TYPE_NPCM7XX_MACHINE, 551 .class_init = gsj_machine_class_init, 552 }, { 553 .name = MACHINE_TYPE_NAME("quanta-gbs-bmc"), 554 .parent = TYPE_NPCM7XX_MACHINE, 555 .class_init = gbs_bmc_machine_class_init, 556 }, { 557 .name = MACHINE_TYPE_NAME("kudo-bmc"), 558 .parent = TYPE_NPCM7XX_MACHINE, 559 .class_init = kudo_bmc_machine_class_init, 560 }, { 561 .name = MACHINE_TYPE_NAME("mori-bmc"), 562 .parent = TYPE_NPCM7XX_MACHINE, 563 .class_init = mori_bmc_machine_class_init, 564 }, 565 }; 566 567 DEFINE_TYPES(npcm7xx_machine_types) 568