1 /* 2 * Nuvoton NPCM7xx SoC family. 3 * 4 * Copyright 2020 Google LLC 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 */ 16 17 #include "qemu/osdep.h" 18 19 #include "exec/address-spaces.h" 20 #include "hw/arm/boot.h" 21 #include "hw/arm/npcm7xx.h" 22 #include "hw/char/serial.h" 23 #include "hw/loader.h" 24 #include "hw/misc/unimp.h" 25 #include "hw/qdev-properties.h" 26 #include "qapi/error.h" 27 #include "qemu/units.h" 28 #include "sysemu/sysemu.h" 29 30 /* 31 * This covers the whole MMIO space. We'll use this to catch any MMIO accesses 32 * that aren't handled by any device. 33 */ 34 #define NPCM7XX_MMIO_BA (0x80000000) 35 #define NPCM7XX_MMIO_SZ (0x7ffd0000) 36 37 /* OTP key storage and fuse strap array */ 38 #define NPCM7XX_OTP1_BA (0xf0189000) 39 #define NPCM7XX_OTP2_BA (0xf018a000) 40 41 /* Core system modules. */ 42 #define NPCM7XX_L2C_BA (0xf03fc000) 43 #define NPCM7XX_CPUP_BA (0xf03fe000) 44 #define NPCM7XX_GCR_BA (0xf0800000) 45 #define NPCM7XX_CLK_BA (0xf0801000) 46 #define NPCM7XX_MC_BA (0xf0824000) 47 #define NPCM7XX_RNG_BA (0xf000b000) 48 49 /* USB Host modules */ 50 #define NPCM7XX_EHCI_BA (0xf0806000) 51 #define NPCM7XX_OHCI_BA (0xf0807000) 52 53 /* Internal AHB SRAM */ 54 #define NPCM7XX_RAM3_BA (0xc0008000) 55 #define NPCM7XX_RAM3_SZ (4 * KiB) 56 57 /* Memory blocks at the end of the address space */ 58 #define NPCM7XX_RAM2_BA (0xfffd0000) 59 #define NPCM7XX_RAM2_SZ (128 * KiB) 60 #define NPCM7XX_ROM_BA (0xffff0000) 61 #define NPCM7XX_ROM_SZ (64 * KiB) 62 63 /* Clock configuration values to be fixed up when bypassing bootloader */ 64 65 /* Run PLL1 at 1600 MHz */ 66 #define NPCM7XX_PLLCON1_FIXUP_VAL (0x00402101) 67 /* Run the CPU from PLL1 and UART from PLL2 */ 68 #define NPCM7XX_CLKSEL_FIXUP_VAL (0x004aaba9) 69 70 /* 71 * Interrupt lines going into the GIC. This does not include internal Cortex-A9 72 * interrupts. 73 */ 74 enum NPCM7xxInterrupt { 75 NPCM7XX_UART0_IRQ = 2, 76 NPCM7XX_UART1_IRQ, 77 NPCM7XX_UART2_IRQ, 78 NPCM7XX_UART3_IRQ, 79 NPCM7XX_TIMER0_IRQ = 32, /* Timer Module 0 */ 80 NPCM7XX_TIMER1_IRQ, 81 NPCM7XX_TIMER2_IRQ, 82 NPCM7XX_TIMER3_IRQ, 83 NPCM7XX_TIMER4_IRQ, 84 NPCM7XX_TIMER5_IRQ, /* Timer Module 1 */ 85 NPCM7XX_TIMER6_IRQ, 86 NPCM7XX_TIMER7_IRQ, 87 NPCM7XX_TIMER8_IRQ, 88 NPCM7XX_TIMER9_IRQ, 89 NPCM7XX_TIMER10_IRQ, /* Timer Module 2 */ 90 NPCM7XX_TIMER11_IRQ, 91 NPCM7XX_TIMER12_IRQ, 92 NPCM7XX_TIMER13_IRQ, 93 NPCM7XX_TIMER14_IRQ, 94 NPCM7XX_WDG0_IRQ = 47, /* Timer Module 0 Watchdog */ 95 NPCM7XX_WDG1_IRQ, /* Timer Module 1 Watchdog */ 96 NPCM7XX_WDG2_IRQ, /* Timer Module 2 Watchdog */ 97 NPCM7XX_EHCI_IRQ = 61, 98 NPCM7XX_OHCI_IRQ = 62, 99 }; 100 101 /* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */ 102 #define NPCM7XX_NUM_IRQ (160) 103 104 /* Register base address for each Timer Module */ 105 static const hwaddr npcm7xx_tim_addr[] = { 106 0xf0008000, 107 0xf0009000, 108 0xf000a000, 109 }; 110 111 /* Register base address for each 16550 UART */ 112 static const hwaddr npcm7xx_uart_addr[] = { 113 0xf0001000, 114 0xf0002000, 115 0xf0003000, 116 0xf0004000, 117 }; 118 119 /* Direct memory-mapped access to SPI0 CS0-1. */ 120 static const hwaddr npcm7xx_fiu0_flash_addr[] = { 121 0x80000000, /* CS0 */ 122 0x88000000, /* CS1 */ 123 }; 124 125 /* Direct memory-mapped access to SPI3 CS0-3. */ 126 static const hwaddr npcm7xx_fiu3_flash_addr[] = { 127 0xa0000000, /* CS0 */ 128 0xa8000000, /* CS1 */ 129 0xb0000000, /* CS2 */ 130 0xb8000000, /* CS3 */ 131 }; 132 133 static const struct { 134 const char *name; 135 hwaddr regs_addr; 136 int cs_count; 137 const hwaddr *flash_addr; 138 } npcm7xx_fiu[] = { 139 { 140 .name = "fiu0", 141 .regs_addr = 0xfb000000, 142 .cs_count = ARRAY_SIZE(npcm7xx_fiu0_flash_addr), 143 .flash_addr = npcm7xx_fiu0_flash_addr, 144 }, { 145 .name = "fiu3", 146 .regs_addr = 0xc0000000, 147 .cs_count = ARRAY_SIZE(npcm7xx_fiu3_flash_addr), 148 .flash_addr = npcm7xx_fiu3_flash_addr, 149 }, 150 }; 151 152 static void npcm7xx_write_board_setup(ARMCPU *cpu, 153 const struct arm_boot_info *info) 154 { 155 uint32_t board_setup[] = { 156 0xe59f0010, /* ldr r0, clk_base_addr */ 157 0xe59f1010, /* ldr r1, pllcon1_value */ 158 0xe5801010, /* str r1, [r0, #16] */ 159 0xe59f100c, /* ldr r1, clksel_value */ 160 0xe5801004, /* str r1, [r0, #4] */ 161 0xe12fff1e, /* bx lr */ 162 NPCM7XX_CLK_BA, 163 NPCM7XX_PLLCON1_FIXUP_VAL, 164 NPCM7XX_CLKSEL_FIXUP_VAL, 165 }; 166 int i; 167 168 for (i = 0; i < ARRAY_SIZE(board_setup); i++) { 169 board_setup[i] = tswap32(board_setup[i]); 170 } 171 rom_add_blob_fixed("board-setup", board_setup, sizeof(board_setup), 172 info->board_setup_addr); 173 } 174 175 static void npcm7xx_write_secondary_boot(ARMCPU *cpu, 176 const struct arm_boot_info *info) 177 { 178 /* 179 * The default smpboot stub halts the secondary CPU with a 'wfi' 180 * instruction, but the arch/arm/mach-npcm/platsmp.c in the Linux kernel 181 * does not send an IPI to wake it up, so the second CPU fails to boot. So 182 * we need to provide our own smpboot stub that can not use 'wfi', it has 183 * to spin the secondary CPU until the first CPU writes to the SCRPAD reg. 184 */ 185 uint32_t smpboot[] = { 186 0xe59f2018, /* ldr r2, bootreg_addr */ 187 0xe3a00000, /* mov r0, #0 */ 188 0xe5820000, /* str r0, [r2] */ 189 0xe320f002, /* wfe */ 190 0xe5921000, /* ldr r1, [r2] */ 191 0xe1110001, /* tst r1, r1 */ 192 0x0afffffb, /* beq <wfe> */ 193 0xe12fff11, /* bx r1 */ 194 NPCM7XX_SMP_BOOTREG_ADDR, 195 }; 196 int i; 197 198 for (i = 0; i < ARRAY_SIZE(smpboot); i++) { 199 smpboot[i] = tswap32(smpboot[i]); 200 } 201 202 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), 203 NPCM7XX_SMP_LOADER_START); 204 } 205 206 static struct arm_boot_info npcm7xx_binfo = { 207 .loader_start = NPCM7XX_LOADER_START, 208 .smp_loader_start = NPCM7XX_SMP_LOADER_START, 209 .smp_bootreg_addr = NPCM7XX_SMP_BOOTREG_ADDR, 210 .gic_cpu_if_addr = NPCM7XX_GIC_CPU_IF_ADDR, 211 .write_secondary_boot = npcm7xx_write_secondary_boot, 212 .board_id = -1, 213 .board_setup_addr = NPCM7XX_BOARD_SETUP_ADDR, 214 .write_board_setup = npcm7xx_write_board_setup, 215 }; 216 217 void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc) 218 { 219 NPCM7xxClass *sc = NPCM7XX_GET_CLASS(soc); 220 221 npcm7xx_binfo.ram_size = machine->ram_size; 222 npcm7xx_binfo.nb_cpus = sc->num_cpus; 223 224 arm_load_kernel(&soc->cpu[0], machine, &npcm7xx_binfo); 225 } 226 227 static void npcm7xx_init_fuses(NPCM7xxState *s) 228 { 229 NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s); 230 uint32_t value; 231 232 /* 233 * The initial mask of disabled modules indicates the chip derivative (e.g. 234 * NPCM750 or NPCM730). 235 */ 236 value = tswap32(nc->disabled_modules); 237 npcm7xx_otp_array_write(&s->fuse_array, &value, NPCM7XX_FUSE_DERIVATIVE, 238 sizeof(value)); 239 } 240 241 static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n) 242 { 243 return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n); 244 } 245 246 static void npcm7xx_init(Object *obj) 247 { 248 NPCM7xxState *s = NPCM7XX(obj); 249 int i; 250 251 for (i = 0; i < NPCM7XX_MAX_NUM_CPUS; i++) { 252 object_initialize_child(obj, "cpu[*]", &s->cpu[i], 253 ARM_CPU_TYPE_NAME("cortex-a9")); 254 } 255 256 object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); 257 object_initialize_child(obj, "gcr", &s->gcr, TYPE_NPCM7XX_GCR); 258 object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr), 259 "power-on-straps"); 260 object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM7XX_CLK); 261 object_initialize_child(obj, "otp1", &s->key_storage, 262 TYPE_NPCM7XX_KEY_STORAGE); 263 object_initialize_child(obj, "otp2", &s->fuse_array, 264 TYPE_NPCM7XX_FUSE_ARRAY); 265 object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC); 266 object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG); 267 268 for (i = 0; i < ARRAY_SIZE(s->tim); i++) { 269 object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER); 270 } 271 272 object_initialize_child(obj, "ehci", &s->ehci, TYPE_NPCM7XX_EHCI); 273 object_initialize_child(obj, "ohci", &s->ohci, TYPE_SYSBUS_OHCI); 274 275 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu)); 276 for (i = 0; i < ARRAY_SIZE(s->fiu); i++) { 277 object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i], 278 TYPE_NPCM7XX_FIU); 279 } 280 } 281 282 static void npcm7xx_realize(DeviceState *dev, Error **errp) 283 { 284 NPCM7xxState *s = NPCM7XX(dev); 285 NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s); 286 int i; 287 288 if (memory_region_size(s->dram) > NPCM7XX_DRAM_SZ) { 289 error_setg(errp, "%s: NPCM7xx cannot address more than %" PRIu64 290 " MiB of DRAM", __func__, NPCM7XX_DRAM_SZ / MiB); 291 return; 292 } 293 294 /* CPUs */ 295 for (i = 0; i < nc->num_cpus; i++) { 296 object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity", 297 arm_cpu_mp_affinity(i, NPCM7XX_MAX_NUM_CPUS), 298 &error_abort); 299 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", 300 NPCM7XX_GIC_CPU_IF_ADDR, &error_abort); 301 object_property_set_bool(OBJECT(&s->cpu[i]), "reset-hivecs", true, 302 &error_abort); 303 304 /* Disable security extensions. */ 305 object_property_set_bool(OBJECT(&s->cpu[i]), "has_el3", false, 306 &error_abort); 307 308 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { 309 return; 310 } 311 } 312 313 /* A9MPCORE peripherals. Can only fail if we pass bad parameters here. */ 314 object_property_set_int(OBJECT(&s->a9mpcore), "num-cpu", nc->num_cpus, 315 &error_abort); 316 object_property_set_int(OBJECT(&s->a9mpcore), "num-irq", NPCM7XX_NUM_IRQ, 317 &error_abort); 318 sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), &error_abort); 319 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, NPCM7XX_CPUP_BA); 320 321 for (i = 0; i < nc->num_cpus; i++) { 322 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i, 323 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ)); 324 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + nc->num_cpus, 325 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ)); 326 } 327 328 /* L2 cache controller */ 329 sysbus_create_simple("l2x0", NPCM7XX_L2C_BA, NULL); 330 331 /* System Global Control Registers (GCR). Can fail due to user input. */ 332 object_property_set_int(OBJECT(&s->gcr), "disabled-modules", 333 nc->disabled_modules, &error_abort); 334 object_property_add_const_link(OBJECT(&s->gcr), "dram-mr", OBJECT(s->dram)); 335 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) { 336 return; 337 } 338 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gcr), 0, NPCM7XX_GCR_BA); 339 340 /* Clock Control Registers (CLK). Cannot fail. */ 341 sysbus_realize(SYS_BUS_DEVICE(&s->clk), &error_abort); 342 sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0, NPCM7XX_CLK_BA); 343 344 /* OTP key storage and fuse strap array. Cannot fail. */ 345 sysbus_realize(SYS_BUS_DEVICE(&s->key_storage), &error_abort); 346 sysbus_mmio_map(SYS_BUS_DEVICE(&s->key_storage), 0, NPCM7XX_OTP1_BA); 347 sysbus_realize(SYS_BUS_DEVICE(&s->fuse_array), &error_abort); 348 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fuse_array), 0, NPCM7XX_OTP2_BA); 349 npcm7xx_init_fuses(s); 350 351 /* Fake Memory Controller (MC). Cannot fail. */ 352 sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort); 353 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA); 354 355 /* Timer Modules (TIM). Cannot fail. */ 356 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim)); 357 for (i = 0; i < ARRAY_SIZE(s->tim); i++) { 358 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->tim[i]); 359 int first_irq; 360 int j; 361 362 sysbus_realize(sbd, &error_abort); 363 sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]); 364 365 first_irq = NPCM7XX_TIMER0_IRQ + i * NPCM7XX_TIMERS_PER_CTRL; 366 for (j = 0; j < NPCM7XX_TIMERS_PER_CTRL; j++) { 367 qemu_irq irq = npcm7xx_irq(s, first_irq + j); 368 sysbus_connect_irq(sbd, j, irq); 369 } 370 371 /* IRQ for watchdogs */ 372 sysbus_connect_irq(sbd, NPCM7XX_TIMERS_PER_CTRL, 373 npcm7xx_irq(s, NPCM7XX_WDG0_IRQ + i)); 374 /* GPIO that connects clk module with watchdog */ 375 qdev_connect_gpio_out_named(DEVICE(&s->tim[i]), 376 NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 0, 377 qdev_get_gpio_in_named(DEVICE(&s->clk), 378 NPCM7XX_WATCHDOG_RESET_GPIO_IN, i)); 379 } 380 381 /* UART0..3 (16550 compatible) */ 382 for (i = 0; i < ARRAY_SIZE(npcm7xx_uart_addr); i++) { 383 serial_mm_init(get_system_memory(), npcm7xx_uart_addr[i], 2, 384 npcm7xx_irq(s, NPCM7XX_UART0_IRQ + i), 115200, 385 serial_hd(i), DEVICE_LITTLE_ENDIAN); 386 } 387 388 /* Random Number Generator. Cannot fail. */ 389 sysbus_realize(SYS_BUS_DEVICE(&s->rng), &error_abort); 390 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rng), 0, NPCM7XX_RNG_BA); 391 392 /* USB Host */ 393 object_property_set_bool(OBJECT(&s->ehci), "companion-enable", true, 394 &error_abort); 395 sysbus_realize(SYS_BUS_DEVICE(&s->ehci), &error_abort); 396 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci), 0, NPCM7XX_EHCI_BA); 397 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci), 0, 398 npcm7xx_irq(s, NPCM7XX_EHCI_IRQ)); 399 400 object_property_set_str(OBJECT(&s->ohci), "masterbus", "usb-bus.0", 401 &error_abort); 402 object_property_set_uint(OBJECT(&s->ohci), "num-ports", 1, &error_abort); 403 sysbus_realize(SYS_BUS_DEVICE(&s->ohci), &error_abort); 404 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci), 0, NPCM7XX_OHCI_BA); 405 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci), 0, 406 npcm7xx_irq(s, NPCM7XX_OHCI_IRQ)); 407 408 /* 409 * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects 410 * specified, but this is a programming error. 411 */ 412 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu)); 413 for (i = 0; i < ARRAY_SIZE(s->fiu); i++) { 414 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->fiu[i]); 415 int j; 416 417 object_property_set_int(OBJECT(sbd), "cs-count", 418 npcm7xx_fiu[i].cs_count, &error_abort); 419 sysbus_realize(sbd, &error_abort); 420 421 sysbus_mmio_map(sbd, 0, npcm7xx_fiu[i].regs_addr); 422 for (j = 0; j < npcm7xx_fiu[i].cs_count; j++) { 423 sysbus_mmio_map(sbd, j + 1, npcm7xx_fiu[i].flash_addr[j]); 424 } 425 } 426 427 /* RAM2 (SRAM) */ 428 memory_region_init_ram(&s->sram, OBJECT(dev), "ram2", 429 NPCM7XX_RAM2_SZ, &error_abort); 430 memory_region_add_subregion(get_system_memory(), NPCM7XX_RAM2_BA, &s->sram); 431 432 /* RAM3 (SRAM) */ 433 memory_region_init_ram(&s->ram3, OBJECT(dev), "ram3", 434 NPCM7XX_RAM3_SZ, &error_abort); 435 memory_region_add_subregion(get_system_memory(), NPCM7XX_RAM3_BA, &s->ram3); 436 437 /* Internal ROM */ 438 memory_region_init_rom(&s->irom, OBJECT(dev), "irom", NPCM7XX_ROM_SZ, 439 &error_abort); 440 memory_region_add_subregion(get_system_memory(), NPCM7XX_ROM_BA, &s->irom); 441 442 create_unimplemented_device("npcm7xx.shm", 0xc0001000, 4 * KiB); 443 create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB); 444 create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB); 445 create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB); 446 create_unimplemented_device("npcm7xx.adc", 0xf000c000, 4 * KiB); 447 create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB); 448 create_unimplemented_device("npcm7xx.gpio[0]", 0xf0010000, 4 * KiB); 449 create_unimplemented_device("npcm7xx.gpio[1]", 0xf0011000, 4 * KiB); 450 create_unimplemented_device("npcm7xx.gpio[2]", 0xf0012000, 4 * KiB); 451 create_unimplemented_device("npcm7xx.gpio[3]", 0xf0013000, 4 * KiB); 452 create_unimplemented_device("npcm7xx.gpio[4]", 0xf0014000, 4 * KiB); 453 create_unimplemented_device("npcm7xx.gpio[5]", 0xf0015000, 4 * KiB); 454 create_unimplemented_device("npcm7xx.gpio[6]", 0xf0016000, 4 * KiB); 455 create_unimplemented_device("npcm7xx.gpio[7]", 0xf0017000, 4 * KiB); 456 create_unimplemented_device("npcm7xx.smbus[0]", 0xf0080000, 4 * KiB); 457 create_unimplemented_device("npcm7xx.smbus[1]", 0xf0081000, 4 * KiB); 458 create_unimplemented_device("npcm7xx.smbus[2]", 0xf0082000, 4 * KiB); 459 create_unimplemented_device("npcm7xx.smbus[3]", 0xf0083000, 4 * KiB); 460 create_unimplemented_device("npcm7xx.smbus[4]", 0xf0084000, 4 * KiB); 461 create_unimplemented_device("npcm7xx.smbus[5]", 0xf0085000, 4 * KiB); 462 create_unimplemented_device("npcm7xx.smbus[6]", 0xf0086000, 4 * KiB); 463 create_unimplemented_device("npcm7xx.smbus[7]", 0xf0087000, 4 * KiB); 464 create_unimplemented_device("npcm7xx.smbus[8]", 0xf0088000, 4 * KiB); 465 create_unimplemented_device("npcm7xx.smbus[9]", 0xf0089000, 4 * KiB); 466 create_unimplemented_device("npcm7xx.smbus[10]", 0xf008a000, 4 * KiB); 467 create_unimplemented_device("npcm7xx.smbus[11]", 0xf008b000, 4 * KiB); 468 create_unimplemented_device("npcm7xx.smbus[12]", 0xf008c000, 4 * KiB); 469 create_unimplemented_device("npcm7xx.smbus[13]", 0xf008d000, 4 * KiB); 470 create_unimplemented_device("npcm7xx.smbus[14]", 0xf008e000, 4 * KiB); 471 create_unimplemented_device("npcm7xx.smbus[15]", 0xf008f000, 4 * KiB); 472 create_unimplemented_device("npcm7xx.espi", 0xf009f000, 4 * KiB); 473 create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB); 474 create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB); 475 create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB); 476 create_unimplemented_device("npcm7xx.pwm[0]", 0xf0103000, 4 * KiB); 477 create_unimplemented_device("npcm7xx.pwm[1]", 0xf0104000, 4 * KiB); 478 create_unimplemented_device("npcm7xx.mft[0]", 0xf0180000, 4 * KiB); 479 create_unimplemented_device("npcm7xx.mft[1]", 0xf0181000, 4 * KiB); 480 create_unimplemented_device("npcm7xx.mft[2]", 0xf0182000, 4 * KiB); 481 create_unimplemented_device("npcm7xx.mft[3]", 0xf0183000, 4 * KiB); 482 create_unimplemented_device("npcm7xx.mft[4]", 0xf0184000, 4 * KiB); 483 create_unimplemented_device("npcm7xx.mft[5]", 0xf0185000, 4 * KiB); 484 create_unimplemented_device("npcm7xx.mft[6]", 0xf0186000, 4 * KiB); 485 create_unimplemented_device("npcm7xx.mft[7]", 0xf0187000, 4 * KiB); 486 create_unimplemented_device("npcm7xx.pspi1", 0xf0200000, 4 * KiB); 487 create_unimplemented_device("npcm7xx.pspi2", 0xf0201000, 4 * KiB); 488 create_unimplemented_device("npcm7xx.ahbpci", 0xf0400000, 1 * MiB); 489 create_unimplemented_device("npcm7xx.mcphy", 0xf05f0000, 64 * KiB); 490 create_unimplemented_device("npcm7xx.gmac1", 0xf0802000, 8 * KiB); 491 create_unimplemented_device("npcm7xx.gmac2", 0xf0804000, 8 * KiB); 492 create_unimplemented_device("npcm7xx.vcd", 0xf0810000, 64 * KiB); 493 create_unimplemented_device("npcm7xx.ece", 0xf0820000, 8 * KiB); 494 create_unimplemented_device("npcm7xx.vdma", 0xf0822000, 8 * KiB); 495 create_unimplemented_device("npcm7xx.emc1", 0xf0825000, 4 * KiB); 496 create_unimplemented_device("npcm7xx.emc2", 0xf0826000, 4 * KiB); 497 create_unimplemented_device("npcm7xx.usbd[0]", 0xf0830000, 4 * KiB); 498 create_unimplemented_device("npcm7xx.usbd[1]", 0xf0831000, 4 * KiB); 499 create_unimplemented_device("npcm7xx.usbd[2]", 0xf0832000, 4 * KiB); 500 create_unimplemented_device("npcm7xx.usbd[3]", 0xf0833000, 4 * KiB); 501 create_unimplemented_device("npcm7xx.usbd[4]", 0xf0834000, 4 * KiB); 502 create_unimplemented_device("npcm7xx.usbd[5]", 0xf0835000, 4 * KiB); 503 create_unimplemented_device("npcm7xx.usbd[6]", 0xf0836000, 4 * KiB); 504 create_unimplemented_device("npcm7xx.usbd[7]", 0xf0837000, 4 * KiB); 505 create_unimplemented_device("npcm7xx.usbd[8]", 0xf0838000, 4 * KiB); 506 create_unimplemented_device("npcm7xx.usbd[9]", 0xf0839000, 4 * KiB); 507 create_unimplemented_device("npcm7xx.sd", 0xf0840000, 8 * KiB); 508 create_unimplemented_device("npcm7xx.mmc", 0xf0842000, 8 * KiB); 509 create_unimplemented_device("npcm7xx.pcimbx", 0xf0848000, 512 * KiB); 510 create_unimplemented_device("npcm7xx.aes", 0xf0858000, 4 * KiB); 511 create_unimplemented_device("npcm7xx.des", 0xf0859000, 4 * KiB); 512 create_unimplemented_device("npcm7xx.sha", 0xf085a000, 4 * KiB); 513 create_unimplemented_device("npcm7xx.secacc", 0xf085b000, 4 * KiB); 514 create_unimplemented_device("npcm7xx.spixcs0", 0xf8000000, 16 * MiB); 515 create_unimplemented_device("npcm7xx.spixcs1", 0xf9000000, 16 * MiB); 516 create_unimplemented_device("npcm7xx.spix", 0xfb001000, 4 * KiB); 517 } 518 519 static Property npcm7xx_properties[] = { 520 DEFINE_PROP_LINK("dram-mr", NPCM7xxState, dram, TYPE_MEMORY_REGION, 521 MemoryRegion *), 522 DEFINE_PROP_END_OF_LIST(), 523 }; 524 525 static void npcm7xx_class_init(ObjectClass *oc, void *data) 526 { 527 DeviceClass *dc = DEVICE_CLASS(oc); 528 529 dc->realize = npcm7xx_realize; 530 dc->user_creatable = false; 531 device_class_set_props(dc, npcm7xx_properties); 532 } 533 534 static void npcm730_class_init(ObjectClass *oc, void *data) 535 { 536 NPCM7xxClass *nc = NPCM7XX_CLASS(oc); 537 538 /* NPCM730 is optimized for data center use, so no graphics, etc. */ 539 nc->disabled_modules = 0x00300395; 540 nc->num_cpus = 2; 541 } 542 543 static void npcm750_class_init(ObjectClass *oc, void *data) 544 { 545 NPCM7xxClass *nc = NPCM7XX_CLASS(oc); 546 547 /* NPCM750 has 2 cores and a full set of peripherals */ 548 nc->disabled_modules = 0x00000000; 549 nc->num_cpus = 2; 550 } 551 552 static const TypeInfo npcm7xx_soc_types[] = { 553 { 554 .name = TYPE_NPCM7XX, 555 .parent = TYPE_DEVICE, 556 .instance_size = sizeof(NPCM7xxState), 557 .instance_init = npcm7xx_init, 558 .class_size = sizeof(NPCM7xxClass), 559 .class_init = npcm7xx_class_init, 560 .abstract = true, 561 }, { 562 .name = TYPE_NPCM730, 563 .parent = TYPE_NPCM7XX, 564 .class_init = npcm730_class_init, 565 }, { 566 .name = TYPE_NPCM750, 567 .parent = TYPE_NPCM7XX, 568 .class_init = npcm750_class_init, 569 }, 570 }; 571 572 DEFINE_TYPES(npcm7xx_soc_types); 573