1 /* 2 * Nuvoton NPCM7xx SoC family. 3 * 4 * Copyright 2020 Google LLC 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 */ 16 17 #include "qemu/osdep.h" 18 19 #include "hw/arm/boot.h" 20 #include "hw/arm/npcm7xx.h" 21 #include "hw/char/serial.h" 22 #include "hw/loader.h" 23 #include "hw/misc/unimp.h" 24 #include "hw/qdev-clock.h" 25 #include "hw/qdev-properties.h" 26 #include "qapi/error.h" 27 #include "qemu/units.h" 28 #include "sysemu/sysemu.h" 29 #include "target/arm/cpu-qom.h" 30 31 /* 32 * This covers the whole MMIO space. We'll use this to catch any MMIO accesses 33 * that aren't handled by any device. 34 */ 35 #define NPCM7XX_MMIO_BA (0x80000000) 36 #define NPCM7XX_MMIO_SZ (0x7ffd0000) 37 38 /* OTP key storage and fuse strap array */ 39 #define NPCM7XX_OTP1_BA (0xf0189000) 40 #define NPCM7XX_OTP2_BA (0xf018a000) 41 42 /* Core system modules. */ 43 #define NPCM7XX_L2C_BA (0xf03fc000) 44 #define NPCM7XX_CPUP_BA (0xf03fe000) 45 #define NPCM7XX_GCR_BA (0xf0800000) 46 #define NPCM7XX_CLK_BA (0xf0801000) 47 #define NPCM7XX_MC_BA (0xf0824000) 48 #define NPCM7XX_RNG_BA (0xf000b000) 49 50 /* USB Host modules */ 51 #define NPCM7XX_EHCI_BA (0xf0806000) 52 #define NPCM7XX_OHCI_BA (0xf0807000) 53 54 /* ADC Module */ 55 #define NPCM7XX_ADC_BA (0xf000c000) 56 57 /* Internal AHB SRAM */ 58 #define NPCM7XX_RAM3_BA (0xc0008000) 59 #define NPCM7XX_RAM3_SZ (4 * KiB) 60 61 /* Memory blocks at the end of the address space */ 62 #define NPCM7XX_RAM2_BA (0xfffd0000) 63 #define NPCM7XX_RAM2_SZ (128 * KiB) 64 #define NPCM7XX_ROM_BA (0xffff0000) 65 #define NPCM7XX_ROM_SZ (64 * KiB) 66 67 /* SDHCI Modules */ 68 #define NPCM7XX_MMC_BA (0xf0842000) 69 70 /* Clock configuration values to be fixed up when bypassing bootloader */ 71 72 /* Run PLL1 at 1600 MHz */ 73 #define NPCM7XX_PLLCON1_FIXUP_VAL (0x00402101) 74 /* Run the CPU from PLL1 and UART from PLL2 */ 75 #define NPCM7XX_CLKSEL_FIXUP_VAL (0x004aaba9) 76 77 /* 78 * Interrupt lines going into the GIC. This does not include internal Cortex-A9 79 * interrupts. 80 */ 81 enum NPCM7xxInterrupt { 82 NPCM7XX_ADC_IRQ = 0, 83 NPCM7XX_UART0_IRQ = 2, 84 NPCM7XX_UART1_IRQ, 85 NPCM7XX_UART2_IRQ, 86 NPCM7XX_UART3_IRQ, 87 NPCM7XX_EMC1RX_IRQ = 15, 88 NPCM7XX_EMC1TX_IRQ, 89 NPCM7XX_MMC_IRQ = 26, 90 NPCM7XX_PSPI2_IRQ = 28, 91 NPCM7XX_PSPI1_IRQ = 31, 92 NPCM7XX_TIMER0_IRQ = 32, /* Timer Module 0 */ 93 NPCM7XX_TIMER1_IRQ, 94 NPCM7XX_TIMER2_IRQ, 95 NPCM7XX_TIMER3_IRQ, 96 NPCM7XX_TIMER4_IRQ, 97 NPCM7XX_TIMER5_IRQ, /* Timer Module 1 */ 98 NPCM7XX_TIMER6_IRQ, 99 NPCM7XX_TIMER7_IRQ, 100 NPCM7XX_TIMER8_IRQ, 101 NPCM7XX_TIMER9_IRQ, 102 NPCM7XX_TIMER10_IRQ, /* Timer Module 2 */ 103 NPCM7XX_TIMER11_IRQ, 104 NPCM7XX_TIMER12_IRQ, 105 NPCM7XX_TIMER13_IRQ, 106 NPCM7XX_TIMER14_IRQ, 107 NPCM7XX_WDG0_IRQ = 47, /* Timer Module 0 Watchdog */ 108 NPCM7XX_WDG1_IRQ, /* Timer Module 1 Watchdog */ 109 NPCM7XX_WDG2_IRQ, /* Timer Module 2 Watchdog */ 110 NPCM7XX_EHCI_IRQ = 61, 111 NPCM7XX_OHCI_IRQ = 62, 112 NPCM7XX_SMBUS0_IRQ = 64, 113 NPCM7XX_SMBUS1_IRQ, 114 NPCM7XX_SMBUS2_IRQ, 115 NPCM7XX_SMBUS3_IRQ, 116 NPCM7XX_SMBUS4_IRQ, 117 NPCM7XX_SMBUS5_IRQ, 118 NPCM7XX_SMBUS6_IRQ, 119 NPCM7XX_SMBUS7_IRQ, 120 NPCM7XX_SMBUS8_IRQ, 121 NPCM7XX_SMBUS9_IRQ, 122 NPCM7XX_SMBUS10_IRQ, 123 NPCM7XX_SMBUS11_IRQ, 124 NPCM7XX_SMBUS12_IRQ, 125 NPCM7XX_SMBUS13_IRQ, 126 NPCM7XX_SMBUS14_IRQ, 127 NPCM7XX_SMBUS15_IRQ, 128 NPCM7XX_PWM0_IRQ = 93, /* PWM module 0 */ 129 NPCM7XX_PWM1_IRQ, /* PWM module 1 */ 130 NPCM7XX_MFT0_IRQ = 96, /* MFT module 0 */ 131 NPCM7XX_MFT1_IRQ, /* MFT module 1 */ 132 NPCM7XX_MFT2_IRQ, /* MFT module 2 */ 133 NPCM7XX_MFT3_IRQ, /* MFT module 3 */ 134 NPCM7XX_MFT4_IRQ, /* MFT module 4 */ 135 NPCM7XX_MFT5_IRQ, /* MFT module 5 */ 136 NPCM7XX_MFT6_IRQ, /* MFT module 6 */ 137 NPCM7XX_MFT7_IRQ, /* MFT module 7 */ 138 NPCM7XX_EMC2RX_IRQ = 114, 139 NPCM7XX_EMC2TX_IRQ, 140 NPCM7XX_GPIO0_IRQ = 116, 141 NPCM7XX_GPIO1_IRQ, 142 NPCM7XX_GPIO2_IRQ, 143 NPCM7XX_GPIO3_IRQ, 144 NPCM7XX_GPIO4_IRQ, 145 NPCM7XX_GPIO5_IRQ, 146 NPCM7XX_GPIO6_IRQ, 147 NPCM7XX_GPIO7_IRQ, 148 }; 149 150 /* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */ 151 #define NPCM7XX_NUM_IRQ (160) 152 153 /* Register base address for each Timer Module */ 154 static const hwaddr npcm7xx_tim_addr[] = { 155 0xf0008000, 156 0xf0009000, 157 0xf000a000, 158 }; 159 160 /* Register base address for each 16550 UART */ 161 static const hwaddr npcm7xx_uart_addr[] = { 162 0xf0001000, 163 0xf0002000, 164 0xf0003000, 165 0xf0004000, 166 }; 167 168 /* Direct memory-mapped access to SPI0 CS0-1. */ 169 static const hwaddr npcm7xx_fiu0_flash_addr[] = { 170 0x80000000, /* CS0 */ 171 0x88000000, /* CS1 */ 172 }; 173 174 /* Direct memory-mapped access to SPI3 CS0-3. */ 175 static const hwaddr npcm7xx_fiu3_flash_addr[] = { 176 0xa0000000, /* CS0 */ 177 0xa8000000, /* CS1 */ 178 0xb0000000, /* CS2 */ 179 0xb8000000, /* CS3 */ 180 }; 181 182 /* Register base address for each PWM Module */ 183 static const hwaddr npcm7xx_pwm_addr[] = { 184 0xf0103000, 185 0xf0104000, 186 }; 187 188 /* Register base address for each MFT Module */ 189 static const hwaddr npcm7xx_mft_addr[] = { 190 0xf0180000, 191 0xf0181000, 192 0xf0182000, 193 0xf0183000, 194 0xf0184000, 195 0xf0185000, 196 0xf0186000, 197 0xf0187000, 198 }; 199 200 /* Direct memory-mapped access to each SMBus Module. */ 201 static const hwaddr npcm7xx_smbus_addr[] = { 202 0xf0080000, 203 0xf0081000, 204 0xf0082000, 205 0xf0083000, 206 0xf0084000, 207 0xf0085000, 208 0xf0086000, 209 0xf0087000, 210 0xf0088000, 211 0xf0089000, 212 0xf008a000, 213 0xf008b000, 214 0xf008c000, 215 0xf008d000, 216 0xf008e000, 217 0xf008f000, 218 }; 219 220 /* Register base address for each EMC Module */ 221 static const hwaddr npcm7xx_emc_addr[] = { 222 0xf0825000, 223 0xf0826000, 224 }; 225 226 /* Register base address for each PSPI Module */ 227 static const hwaddr npcm7xx_pspi_addr[] = { 228 0xf0200000, 229 0xf0201000, 230 }; 231 232 static const struct { 233 hwaddr regs_addr; 234 uint32_t unconnected_pins; 235 uint32_t reset_pu; 236 uint32_t reset_pd; 237 uint32_t reset_osrc; 238 uint32_t reset_odsc; 239 } npcm7xx_gpio[] = { 240 { 241 .regs_addr = 0xf0010000, 242 .reset_pu = 0xff03ffff, 243 .reset_pd = 0x00fc0000, 244 }, { 245 .regs_addr = 0xf0011000, 246 .unconnected_pins = 0x0000001e, 247 .reset_pu = 0xfefffe07, 248 .reset_pd = 0x010001e0, 249 }, { 250 .regs_addr = 0xf0012000, 251 .reset_pu = 0x780fffff, 252 .reset_pd = 0x07f00000, 253 .reset_odsc = 0x00700000, 254 }, { 255 .regs_addr = 0xf0013000, 256 .reset_pu = 0x00fc0000, 257 .reset_pd = 0xff000000, 258 }, { 259 .regs_addr = 0xf0014000, 260 .reset_pu = 0xffffffff, 261 }, { 262 .regs_addr = 0xf0015000, 263 .reset_pu = 0xbf83f801, 264 .reset_pd = 0x007c0000, 265 .reset_osrc = 0x000000f1, 266 .reset_odsc = 0x3f9f80f1, 267 }, { 268 .regs_addr = 0xf0016000, 269 .reset_pu = 0xfc00f801, 270 .reset_pd = 0x000007fe, 271 .reset_odsc = 0x00000800, 272 }, { 273 .regs_addr = 0xf0017000, 274 .unconnected_pins = 0xffffff00, 275 .reset_pu = 0x0000007f, 276 .reset_osrc = 0x0000007f, 277 .reset_odsc = 0x0000007f, 278 }, 279 }; 280 281 static const struct { 282 const char *name; 283 hwaddr regs_addr; 284 int cs_count; 285 const hwaddr *flash_addr; 286 } npcm7xx_fiu[] = { 287 { 288 .name = "fiu0", 289 .regs_addr = 0xfb000000, 290 .cs_count = ARRAY_SIZE(npcm7xx_fiu0_flash_addr), 291 .flash_addr = npcm7xx_fiu0_flash_addr, 292 }, { 293 .name = "fiu3", 294 .regs_addr = 0xc0000000, 295 .cs_count = ARRAY_SIZE(npcm7xx_fiu3_flash_addr), 296 .flash_addr = npcm7xx_fiu3_flash_addr, 297 }, 298 }; 299 300 static void npcm7xx_write_board_setup(ARMCPU *cpu, 301 const struct arm_boot_info *info) 302 { 303 uint32_t board_setup[] = { 304 0xe59f0010, /* ldr r0, clk_base_addr */ 305 0xe59f1010, /* ldr r1, pllcon1_value */ 306 0xe5801010, /* str r1, [r0, #16] */ 307 0xe59f100c, /* ldr r1, clksel_value */ 308 0xe5801004, /* str r1, [r0, #4] */ 309 0xe12fff1e, /* bx lr */ 310 NPCM7XX_CLK_BA, 311 NPCM7XX_PLLCON1_FIXUP_VAL, 312 NPCM7XX_CLKSEL_FIXUP_VAL, 313 }; 314 int i; 315 316 for (i = 0; i < ARRAY_SIZE(board_setup); i++) { 317 board_setup[i] = tswap32(board_setup[i]); 318 } 319 rom_add_blob_fixed("board-setup", board_setup, sizeof(board_setup), 320 info->board_setup_addr); 321 } 322 323 static void npcm7xx_write_secondary_boot(ARMCPU *cpu, 324 const struct arm_boot_info *info) 325 { 326 /* 327 * The default smpboot stub halts the secondary CPU with a 'wfi' 328 * instruction, but the arch/arm/mach-npcm/platsmp.c in the Linux kernel 329 * does not send an IPI to wake it up, so the second CPU fails to boot. So 330 * we need to provide our own smpboot stub that can not use 'wfi', it has 331 * to spin the secondary CPU until the first CPU writes to the SCRPAD reg. 332 */ 333 uint32_t smpboot[] = { 334 0xe59f2018, /* ldr r2, bootreg_addr */ 335 0xe3a00000, /* mov r0, #0 */ 336 0xe5820000, /* str r0, [r2] */ 337 0xe320f002, /* wfe */ 338 0xe5921000, /* ldr r1, [r2] */ 339 0xe1110001, /* tst r1, r1 */ 340 0x0afffffb, /* beq <wfe> */ 341 0xe12fff11, /* bx r1 */ 342 NPCM7XX_SMP_BOOTREG_ADDR, 343 }; 344 int i; 345 346 for (i = 0; i < ARRAY_SIZE(smpboot); i++) { 347 smpboot[i] = tswap32(smpboot[i]); 348 } 349 350 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), 351 NPCM7XX_SMP_LOADER_START); 352 } 353 354 static struct arm_boot_info npcm7xx_binfo = { 355 .loader_start = NPCM7XX_LOADER_START, 356 .smp_loader_start = NPCM7XX_SMP_LOADER_START, 357 .smp_bootreg_addr = NPCM7XX_SMP_BOOTREG_ADDR, 358 .gic_cpu_if_addr = NPCM7XX_GIC_CPU_IF_ADDR, 359 .write_secondary_boot = npcm7xx_write_secondary_boot, 360 .board_id = -1, 361 .board_setup_addr = NPCM7XX_BOARD_SETUP_ADDR, 362 .write_board_setup = npcm7xx_write_board_setup, 363 }; 364 365 void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc) 366 { 367 npcm7xx_binfo.ram_size = machine->ram_size; 368 369 arm_load_kernel(&soc->cpu[0], machine, &npcm7xx_binfo); 370 } 371 372 static void npcm7xx_init_fuses(NPCM7xxState *s) 373 { 374 NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s); 375 uint32_t value; 376 377 /* 378 * The initial mask of disabled modules indicates the chip derivative (e.g. 379 * NPCM750 or NPCM730). 380 */ 381 value = tswap32(nc->disabled_modules); 382 npcm7xx_otp_array_write(&s->fuse_array, &value, NPCM7XX_FUSE_DERIVATIVE, 383 sizeof(value)); 384 } 385 386 static void npcm7xx_write_adc_calibration(NPCM7xxState *s) 387 { 388 /* Both ADC and the fuse array must have realized. */ 389 QEMU_BUILD_BUG_ON(sizeof(s->adc.calibration_r_values) != 4); 390 npcm7xx_otp_array_write(&s->fuse_array, s->adc.calibration_r_values, 391 NPCM7XX_FUSE_ADC_CALIB, sizeof(s->adc.calibration_r_values)); 392 } 393 394 static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n) 395 { 396 return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n); 397 } 398 399 static void npcm7xx_init(Object *obj) 400 { 401 NPCM7xxState *s = NPCM7XX(obj); 402 int i; 403 404 for (i = 0; i < NPCM7XX_MAX_NUM_CPUS; i++) { 405 object_initialize_child(obj, "cpu[*]", &s->cpu[i], 406 ARM_CPU_TYPE_NAME("cortex-a9")); 407 } 408 409 object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); 410 object_initialize_child(obj, "gcr", &s->gcr, TYPE_NPCM7XX_GCR); 411 object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr), 412 "power-on-straps"); 413 object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM7XX_CLK); 414 object_initialize_child(obj, "otp1", &s->key_storage, 415 TYPE_NPCM7XX_KEY_STORAGE); 416 object_initialize_child(obj, "otp2", &s->fuse_array, 417 TYPE_NPCM7XX_FUSE_ARRAY); 418 object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC); 419 object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG); 420 object_initialize_child(obj, "adc", &s->adc, TYPE_NPCM7XX_ADC); 421 422 for (i = 0; i < ARRAY_SIZE(s->tim); i++) { 423 object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER); 424 } 425 426 for (i = 0; i < ARRAY_SIZE(s->gpio); i++) { 427 object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_NPCM7XX_GPIO); 428 } 429 430 for (i = 0; i < ARRAY_SIZE(s->smbus); i++) { 431 object_initialize_child(obj, "smbus[*]", &s->smbus[i], 432 TYPE_NPCM7XX_SMBUS); 433 } 434 435 object_initialize_child(obj, "ehci", &s->ehci, TYPE_NPCM7XX_EHCI); 436 object_initialize_child(obj, "ohci", &s->ohci, TYPE_SYSBUS_OHCI); 437 438 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu)); 439 for (i = 0; i < ARRAY_SIZE(s->fiu); i++) { 440 object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i], 441 TYPE_NPCM7XX_FIU); 442 } 443 444 for (i = 0; i < ARRAY_SIZE(s->pwm); i++) { 445 object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PWM); 446 } 447 448 for (i = 0; i < ARRAY_SIZE(s->mft); i++) { 449 object_initialize_child(obj, "mft[*]", &s->mft[i], TYPE_NPCM7XX_MFT); 450 } 451 452 for (i = 0; i < ARRAY_SIZE(s->emc); i++) { 453 object_initialize_child(obj, "emc[*]", &s->emc[i], TYPE_NPCM7XX_EMC); 454 } 455 456 for (i = 0; i < ARRAY_SIZE(s->pspi); i++) { 457 object_initialize_child(obj, "pspi[*]", &s->pspi[i], TYPE_NPCM_PSPI); 458 } 459 460 object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI); 461 } 462 463 static void npcm7xx_realize(DeviceState *dev, Error **errp) 464 { 465 NPCM7xxState *s = NPCM7XX(dev); 466 NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s); 467 int i; 468 469 if (memory_region_size(s->dram) > NPCM7XX_DRAM_SZ) { 470 error_setg(errp, "%s: NPCM7xx cannot address more than %" PRIu64 471 " MiB of DRAM", __func__, NPCM7XX_DRAM_SZ / MiB); 472 return; 473 } 474 475 /* CPUs */ 476 for (i = 0; i < nc->num_cpus; i++) { 477 object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity", 478 arm_build_mp_affinity(i, NPCM7XX_MAX_NUM_CPUS), 479 &error_abort); 480 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", 481 NPCM7XX_GIC_CPU_IF_ADDR, &error_abort); 482 object_property_set_bool(OBJECT(&s->cpu[i]), "reset-hivecs", true, 483 &error_abort); 484 485 /* Disable security extensions. */ 486 object_property_set_bool(OBJECT(&s->cpu[i]), "has_el3", false, 487 &error_abort); 488 489 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { 490 return; 491 } 492 } 493 494 /* A9MPCORE peripherals. Can only fail if we pass bad parameters here. */ 495 object_property_set_int(OBJECT(&s->a9mpcore), "num-cpu", nc->num_cpus, 496 &error_abort); 497 object_property_set_int(OBJECT(&s->a9mpcore), "num-irq", NPCM7XX_NUM_IRQ, 498 &error_abort); 499 sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), &error_abort); 500 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, NPCM7XX_CPUP_BA); 501 502 for (i = 0; i < nc->num_cpus; i++) { 503 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i, 504 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ)); 505 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + nc->num_cpus, 506 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ)); 507 } 508 509 /* L2 cache controller */ 510 sysbus_create_simple("l2x0", NPCM7XX_L2C_BA, NULL); 511 512 /* System Global Control Registers (GCR). Can fail due to user input. */ 513 object_property_set_int(OBJECT(&s->gcr), "disabled-modules", 514 nc->disabled_modules, &error_abort); 515 object_property_add_const_link(OBJECT(&s->gcr), "dram-mr", OBJECT(s->dram)); 516 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) { 517 return; 518 } 519 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gcr), 0, NPCM7XX_GCR_BA); 520 521 /* Clock Control Registers (CLK). Cannot fail. */ 522 sysbus_realize(SYS_BUS_DEVICE(&s->clk), &error_abort); 523 sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0, NPCM7XX_CLK_BA); 524 525 /* OTP key storage and fuse strap array. Cannot fail. */ 526 sysbus_realize(SYS_BUS_DEVICE(&s->key_storage), &error_abort); 527 sysbus_mmio_map(SYS_BUS_DEVICE(&s->key_storage), 0, NPCM7XX_OTP1_BA); 528 sysbus_realize(SYS_BUS_DEVICE(&s->fuse_array), &error_abort); 529 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fuse_array), 0, NPCM7XX_OTP2_BA); 530 npcm7xx_init_fuses(s); 531 532 /* Fake Memory Controller (MC). Cannot fail. */ 533 sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort); 534 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA); 535 536 /* ADC Modules. Cannot fail. */ 537 qdev_connect_clock_in(DEVICE(&s->adc), "clock", qdev_get_clock_out( 538 DEVICE(&s->clk), "adc-clock")); 539 sysbus_realize(SYS_BUS_DEVICE(&s->adc), &error_abort); 540 sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, NPCM7XX_ADC_BA); 541 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 542 npcm7xx_irq(s, NPCM7XX_ADC_IRQ)); 543 npcm7xx_write_adc_calibration(s); 544 545 /* Timer Modules (TIM). Cannot fail. */ 546 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim)); 547 for (i = 0; i < ARRAY_SIZE(s->tim); i++) { 548 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->tim[i]); 549 int first_irq; 550 int j; 551 552 /* Connect the timer clock. */ 553 qdev_connect_clock_in(DEVICE(&s->tim[i]), "clock", qdev_get_clock_out( 554 DEVICE(&s->clk), "timer-clock")); 555 556 sysbus_realize(sbd, &error_abort); 557 sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]); 558 559 first_irq = NPCM7XX_TIMER0_IRQ + i * NPCM7XX_TIMERS_PER_CTRL; 560 for (j = 0; j < NPCM7XX_TIMERS_PER_CTRL; j++) { 561 qemu_irq irq = npcm7xx_irq(s, first_irq + j); 562 sysbus_connect_irq(sbd, j, irq); 563 } 564 565 /* IRQ for watchdogs */ 566 sysbus_connect_irq(sbd, NPCM7XX_TIMERS_PER_CTRL, 567 npcm7xx_irq(s, NPCM7XX_WDG0_IRQ + i)); 568 /* GPIO that connects clk module with watchdog */ 569 qdev_connect_gpio_out_named(DEVICE(&s->tim[i]), 570 NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 0, 571 qdev_get_gpio_in_named(DEVICE(&s->clk), 572 NPCM7XX_WATCHDOG_RESET_GPIO_IN, i)); 573 } 574 575 /* UART0..3 (16550 compatible) */ 576 for (i = 0; i < ARRAY_SIZE(npcm7xx_uart_addr); i++) { 577 serial_mm_init(get_system_memory(), npcm7xx_uart_addr[i], 2, 578 npcm7xx_irq(s, NPCM7XX_UART0_IRQ + i), 115200, 579 serial_hd(i), DEVICE_LITTLE_ENDIAN); 580 } 581 582 /* Random Number Generator. Cannot fail. */ 583 sysbus_realize(SYS_BUS_DEVICE(&s->rng), &error_abort); 584 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rng), 0, NPCM7XX_RNG_BA); 585 586 /* GPIO modules. Cannot fail. */ 587 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_gpio) != ARRAY_SIZE(s->gpio)); 588 for (i = 0; i < ARRAY_SIZE(s->gpio); i++) { 589 Object *obj = OBJECT(&s->gpio[i]); 590 591 object_property_set_uint(obj, "reset-pullup", 592 npcm7xx_gpio[i].reset_pu, &error_abort); 593 object_property_set_uint(obj, "reset-pulldown", 594 npcm7xx_gpio[i].reset_pd, &error_abort); 595 object_property_set_uint(obj, "reset-osrc", 596 npcm7xx_gpio[i].reset_osrc, &error_abort); 597 object_property_set_uint(obj, "reset-odsc", 598 npcm7xx_gpio[i].reset_odsc, &error_abort); 599 sysbus_realize(SYS_BUS_DEVICE(obj), &error_abort); 600 sysbus_mmio_map(SYS_BUS_DEVICE(obj), 0, npcm7xx_gpio[i].regs_addr); 601 sysbus_connect_irq(SYS_BUS_DEVICE(obj), 0, 602 npcm7xx_irq(s, NPCM7XX_GPIO0_IRQ + i)); 603 } 604 605 /* SMBus modules. Cannot fail. */ 606 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_smbus_addr) != ARRAY_SIZE(s->smbus)); 607 for (i = 0; i < ARRAY_SIZE(s->smbus); i++) { 608 Object *obj = OBJECT(&s->smbus[i]); 609 610 sysbus_realize(SYS_BUS_DEVICE(obj), &error_abort); 611 sysbus_mmio_map(SYS_BUS_DEVICE(obj), 0, npcm7xx_smbus_addr[i]); 612 sysbus_connect_irq(SYS_BUS_DEVICE(obj), 0, 613 npcm7xx_irq(s, NPCM7XX_SMBUS0_IRQ + i)); 614 } 615 616 /* USB Host */ 617 object_property_set_bool(OBJECT(&s->ehci), "companion-enable", true, 618 &error_abort); 619 sysbus_realize(SYS_BUS_DEVICE(&s->ehci), &error_abort); 620 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci), 0, NPCM7XX_EHCI_BA); 621 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci), 0, 622 npcm7xx_irq(s, NPCM7XX_EHCI_IRQ)); 623 624 object_property_set_str(OBJECT(&s->ohci), "masterbus", "usb-bus.0", 625 &error_abort); 626 object_property_set_uint(OBJECT(&s->ohci), "num-ports", 1, &error_abort); 627 sysbus_realize(SYS_BUS_DEVICE(&s->ohci), &error_abort); 628 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci), 0, NPCM7XX_OHCI_BA); 629 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci), 0, 630 npcm7xx_irq(s, NPCM7XX_OHCI_IRQ)); 631 632 /* PWM Modules. Cannot fail. */ 633 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pwm_addr) != ARRAY_SIZE(s->pwm)); 634 for (i = 0; i < ARRAY_SIZE(s->pwm); i++) { 635 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pwm[i]); 636 637 qdev_connect_clock_in(DEVICE(&s->pwm[i]), "clock", qdev_get_clock_out( 638 DEVICE(&s->clk), "apb3-clock")); 639 sysbus_realize(sbd, &error_abort); 640 sysbus_mmio_map(sbd, 0, npcm7xx_pwm_addr[i]); 641 sysbus_connect_irq(sbd, i, npcm7xx_irq(s, NPCM7XX_PWM0_IRQ + i)); 642 } 643 644 /* MFT Modules. Cannot fail. */ 645 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_mft_addr) != ARRAY_SIZE(s->mft)); 646 for (i = 0; i < ARRAY_SIZE(s->mft); i++) { 647 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->mft[i]); 648 649 qdev_connect_clock_in(DEVICE(&s->mft[i]), "clock-in", 650 qdev_get_clock_out(DEVICE(&s->clk), 651 "apb4-clock")); 652 sysbus_realize(sbd, &error_abort); 653 sysbus_mmio_map(sbd, 0, npcm7xx_mft_addr[i]); 654 sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, NPCM7XX_MFT0_IRQ + i)); 655 } 656 657 /* 658 * EMC Modules. Cannot fail. 659 * The mapping of the device to its netdev backend works as follows: 660 * emc[i] = nd_table[i] 661 * This works around the inability to specify the netdev property for the 662 * emc device: it's not pluggable and thus the -device option can't be 663 * used. 664 */ 665 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_emc_addr) != ARRAY_SIZE(s->emc)); 666 QEMU_BUILD_BUG_ON(ARRAY_SIZE(s->emc) != 2); 667 for (i = 0; i < ARRAY_SIZE(s->emc); i++) { 668 s->emc[i].emc_num = i; 669 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->emc[i]); 670 if (nd_table[i].used) { 671 qemu_check_nic_model(&nd_table[i], TYPE_NPCM7XX_EMC); 672 qdev_set_nic_properties(DEVICE(sbd), &nd_table[i]); 673 } 674 /* 675 * The device exists regardless of whether it's connected to a QEMU 676 * netdev backend. So always instantiate it even if there is no 677 * backend. 678 */ 679 sysbus_realize(sbd, &error_abort); 680 sysbus_mmio_map(sbd, 0, npcm7xx_emc_addr[i]); 681 int tx_irq = i == 0 ? NPCM7XX_EMC1TX_IRQ : NPCM7XX_EMC2TX_IRQ; 682 int rx_irq = i == 0 ? NPCM7XX_EMC1RX_IRQ : NPCM7XX_EMC2RX_IRQ; 683 /* 684 * N.B. The values for the second argument sysbus_connect_irq are 685 * chosen to match the registration order in npcm7xx_emc_realize. 686 */ 687 sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, tx_irq)); 688 sysbus_connect_irq(sbd, 1, npcm7xx_irq(s, rx_irq)); 689 } 690 691 /* 692 * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects 693 * specified, but this is a programming error. 694 */ 695 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu)); 696 for (i = 0; i < ARRAY_SIZE(s->fiu); i++) { 697 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->fiu[i]); 698 int j; 699 700 object_property_set_int(OBJECT(sbd), "cs-count", 701 npcm7xx_fiu[i].cs_count, &error_abort); 702 sysbus_realize(sbd, &error_abort); 703 704 sysbus_mmio_map(sbd, 0, npcm7xx_fiu[i].regs_addr); 705 for (j = 0; j < npcm7xx_fiu[i].cs_count; j++) { 706 sysbus_mmio_map(sbd, j + 1, npcm7xx_fiu[i].flash_addr[j]); 707 } 708 } 709 710 /* RAM2 (SRAM) */ 711 memory_region_init_ram(&s->sram, OBJECT(dev), "ram2", 712 NPCM7XX_RAM2_SZ, &error_abort); 713 memory_region_add_subregion(get_system_memory(), NPCM7XX_RAM2_BA, &s->sram); 714 715 /* RAM3 (SRAM) */ 716 memory_region_init_ram(&s->ram3, OBJECT(dev), "ram3", 717 NPCM7XX_RAM3_SZ, &error_abort); 718 memory_region_add_subregion(get_system_memory(), NPCM7XX_RAM3_BA, &s->ram3); 719 720 /* Internal ROM */ 721 memory_region_init_rom(&s->irom, OBJECT(dev), "irom", NPCM7XX_ROM_SZ, 722 &error_abort); 723 memory_region_add_subregion(get_system_memory(), NPCM7XX_ROM_BA, &s->irom); 724 725 /* SDHCI */ 726 sysbus_realize(SYS_BUS_DEVICE(&s->mmc), &error_abort); 727 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc), 0, NPCM7XX_MMC_BA); 728 sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc), 0, 729 npcm7xx_irq(s, NPCM7XX_MMC_IRQ)); 730 731 /* PSPI */ 732 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pspi_addr) != ARRAY_SIZE(s->pspi)); 733 for (i = 0; i < ARRAY_SIZE(s->pspi); i++) { 734 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pspi[i]); 735 int irq = (i == 0) ? NPCM7XX_PSPI1_IRQ : NPCM7XX_PSPI2_IRQ; 736 737 sysbus_realize(sbd, &error_abort); 738 sysbus_mmio_map(sbd, 0, npcm7xx_pspi_addr[i]); 739 sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, irq)); 740 } 741 742 create_unimplemented_device("npcm7xx.shm", 0xc0001000, 4 * KiB); 743 create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB); 744 create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB); 745 create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB); 746 create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB); 747 create_unimplemented_device("npcm7xx.espi", 0xf009f000, 4 * KiB); 748 create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB); 749 create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB); 750 create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB); 751 create_unimplemented_device("npcm7xx.ahbpci", 0xf0400000, 1 * MiB); 752 create_unimplemented_device("npcm7xx.mcphy", 0xf05f0000, 64 * KiB); 753 create_unimplemented_device("npcm7xx.gmac1", 0xf0802000, 8 * KiB); 754 create_unimplemented_device("npcm7xx.gmac2", 0xf0804000, 8 * KiB); 755 create_unimplemented_device("npcm7xx.vcd", 0xf0810000, 64 * KiB); 756 create_unimplemented_device("npcm7xx.ece", 0xf0820000, 8 * KiB); 757 create_unimplemented_device("npcm7xx.vdma", 0xf0822000, 8 * KiB); 758 create_unimplemented_device("npcm7xx.usbd[0]", 0xf0830000, 4 * KiB); 759 create_unimplemented_device("npcm7xx.usbd[1]", 0xf0831000, 4 * KiB); 760 create_unimplemented_device("npcm7xx.usbd[2]", 0xf0832000, 4 * KiB); 761 create_unimplemented_device("npcm7xx.usbd[3]", 0xf0833000, 4 * KiB); 762 create_unimplemented_device("npcm7xx.usbd[4]", 0xf0834000, 4 * KiB); 763 create_unimplemented_device("npcm7xx.usbd[5]", 0xf0835000, 4 * KiB); 764 create_unimplemented_device("npcm7xx.usbd[6]", 0xf0836000, 4 * KiB); 765 create_unimplemented_device("npcm7xx.usbd[7]", 0xf0837000, 4 * KiB); 766 create_unimplemented_device("npcm7xx.usbd[8]", 0xf0838000, 4 * KiB); 767 create_unimplemented_device("npcm7xx.usbd[9]", 0xf0839000, 4 * KiB); 768 create_unimplemented_device("npcm7xx.sd", 0xf0840000, 8 * KiB); 769 create_unimplemented_device("npcm7xx.pcimbx", 0xf0848000, 512 * KiB); 770 create_unimplemented_device("npcm7xx.aes", 0xf0858000, 4 * KiB); 771 create_unimplemented_device("npcm7xx.des", 0xf0859000, 4 * KiB); 772 create_unimplemented_device("npcm7xx.sha", 0xf085a000, 4 * KiB); 773 create_unimplemented_device("npcm7xx.secacc", 0xf085b000, 4 * KiB); 774 create_unimplemented_device("npcm7xx.spixcs0", 0xf8000000, 16 * MiB); 775 create_unimplemented_device("npcm7xx.spixcs1", 0xf9000000, 16 * MiB); 776 create_unimplemented_device("npcm7xx.spix", 0xfb001000, 4 * KiB); 777 } 778 779 static Property npcm7xx_properties[] = { 780 DEFINE_PROP_LINK("dram-mr", NPCM7xxState, dram, TYPE_MEMORY_REGION, 781 MemoryRegion *), 782 DEFINE_PROP_END_OF_LIST(), 783 }; 784 785 static void npcm7xx_class_init(ObjectClass *oc, void *data) 786 { 787 DeviceClass *dc = DEVICE_CLASS(oc); 788 789 dc->realize = npcm7xx_realize; 790 dc->user_creatable = false; 791 device_class_set_props(dc, npcm7xx_properties); 792 } 793 794 static void npcm730_class_init(ObjectClass *oc, void *data) 795 { 796 NPCM7xxClass *nc = NPCM7XX_CLASS(oc); 797 798 /* NPCM730 is optimized for data center use, so no graphics, etc. */ 799 nc->disabled_modules = 0x00300395; 800 nc->num_cpus = 2; 801 } 802 803 static void npcm750_class_init(ObjectClass *oc, void *data) 804 { 805 NPCM7xxClass *nc = NPCM7XX_CLASS(oc); 806 807 /* NPCM750 has 2 cores and a full set of peripherals */ 808 nc->disabled_modules = 0x00000000; 809 nc->num_cpus = 2; 810 } 811 812 static const TypeInfo npcm7xx_soc_types[] = { 813 { 814 .name = TYPE_NPCM7XX, 815 .parent = TYPE_DEVICE, 816 .instance_size = sizeof(NPCM7xxState), 817 .instance_init = npcm7xx_init, 818 .class_size = sizeof(NPCM7xxClass), 819 .class_init = npcm7xx_class_init, 820 .abstract = true, 821 }, { 822 .name = TYPE_NPCM730, 823 .parent = TYPE_NPCM7XX, 824 .class_init = npcm730_class_init, 825 }, { 826 .name = TYPE_NPCM750, 827 .parent = TYPE_NPCM7XX, 828 .class_init = npcm750_class_init, 829 }, 830 }; 831 832 DEFINE_TYPES(npcm7xx_soc_types); 833