1 /* 2 * Nuvoton NPCM7xx SoC family. 3 * 4 * Copyright 2020 Google LLC 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 */ 16 17 #include "qemu/osdep.h" 18 19 #include "exec/address-spaces.h" 20 #include "hw/arm/boot.h" 21 #include "hw/arm/npcm7xx.h" 22 #include "hw/char/serial.h" 23 #include "hw/loader.h" 24 #include "hw/misc/unimp.h" 25 #include "hw/qdev-properties.h" 26 #include "qapi/error.h" 27 #include "qemu/units.h" 28 #include "sysemu/sysemu.h" 29 30 /* 31 * This covers the whole MMIO space. We'll use this to catch any MMIO accesses 32 * that aren't handled by any device. 33 */ 34 #define NPCM7XX_MMIO_BA (0x80000000) 35 #define NPCM7XX_MMIO_SZ (0x7ffd0000) 36 37 /* OTP key storage and fuse strap array */ 38 #define NPCM7XX_OTP1_BA (0xf0189000) 39 #define NPCM7XX_OTP2_BA (0xf018a000) 40 41 /* Core system modules. */ 42 #define NPCM7XX_L2C_BA (0xf03fc000) 43 #define NPCM7XX_CPUP_BA (0xf03fe000) 44 #define NPCM7XX_GCR_BA (0xf0800000) 45 #define NPCM7XX_CLK_BA (0xf0801000) 46 #define NPCM7XX_MC_BA (0xf0824000) 47 48 /* Internal AHB SRAM */ 49 #define NPCM7XX_RAM3_BA (0xc0008000) 50 #define NPCM7XX_RAM3_SZ (4 * KiB) 51 52 /* Memory blocks at the end of the address space */ 53 #define NPCM7XX_RAM2_BA (0xfffd0000) 54 #define NPCM7XX_RAM2_SZ (128 * KiB) 55 #define NPCM7XX_ROM_BA (0xffff0000) 56 #define NPCM7XX_ROM_SZ (64 * KiB) 57 58 /* 59 * Interrupt lines going into the GIC. This does not include internal Cortex-A9 60 * interrupts. 61 */ 62 enum NPCM7xxInterrupt { 63 NPCM7XX_UART0_IRQ = 2, 64 NPCM7XX_UART1_IRQ, 65 NPCM7XX_UART2_IRQ, 66 NPCM7XX_UART3_IRQ, 67 NPCM7XX_TIMER0_IRQ = 32, /* Timer Module 0 */ 68 NPCM7XX_TIMER1_IRQ, 69 NPCM7XX_TIMER2_IRQ, 70 NPCM7XX_TIMER3_IRQ, 71 NPCM7XX_TIMER4_IRQ, 72 NPCM7XX_TIMER5_IRQ, /* Timer Module 1 */ 73 NPCM7XX_TIMER6_IRQ, 74 NPCM7XX_TIMER7_IRQ, 75 NPCM7XX_TIMER8_IRQ, 76 NPCM7XX_TIMER9_IRQ, 77 NPCM7XX_TIMER10_IRQ, /* Timer Module 2 */ 78 NPCM7XX_TIMER11_IRQ, 79 NPCM7XX_TIMER12_IRQ, 80 NPCM7XX_TIMER13_IRQ, 81 NPCM7XX_TIMER14_IRQ, 82 }; 83 84 /* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */ 85 #define NPCM7XX_NUM_IRQ (160) 86 87 /* Register base address for each Timer Module */ 88 static const hwaddr npcm7xx_tim_addr[] = { 89 0xf0008000, 90 0xf0009000, 91 0xf000a000, 92 }; 93 94 /* Register base address for each 16550 UART */ 95 static const hwaddr npcm7xx_uart_addr[] = { 96 0xf0001000, 97 0xf0002000, 98 0xf0003000, 99 0xf0004000, 100 }; 101 102 /* Direct memory-mapped access to SPI0 CS0-1. */ 103 static const hwaddr npcm7xx_fiu0_flash_addr[] = { 104 0x80000000, /* CS0 */ 105 0x88000000, /* CS1 */ 106 }; 107 108 /* Direct memory-mapped access to SPI3 CS0-3. */ 109 static const hwaddr npcm7xx_fiu3_flash_addr[] = { 110 0xa0000000, /* CS0 */ 111 0xa8000000, /* CS1 */ 112 0xb0000000, /* CS2 */ 113 0xb8000000, /* CS3 */ 114 }; 115 116 static const struct { 117 const char *name; 118 hwaddr regs_addr; 119 int cs_count; 120 const hwaddr *flash_addr; 121 } npcm7xx_fiu[] = { 122 { 123 .name = "fiu0", 124 .regs_addr = 0xfb000000, 125 .cs_count = ARRAY_SIZE(npcm7xx_fiu0_flash_addr), 126 .flash_addr = npcm7xx_fiu0_flash_addr, 127 }, { 128 .name = "fiu3", 129 .regs_addr = 0xc0000000, 130 .cs_count = ARRAY_SIZE(npcm7xx_fiu3_flash_addr), 131 .flash_addr = npcm7xx_fiu3_flash_addr, 132 }, 133 }; 134 135 static void npcm7xx_write_secondary_boot(ARMCPU *cpu, 136 const struct arm_boot_info *info) 137 { 138 /* 139 * The default smpboot stub halts the secondary CPU with a 'wfi' 140 * instruction, but the arch/arm/mach-npcm/platsmp.c in the Linux kernel 141 * does not send an IPI to wake it up, so the second CPU fails to boot. So 142 * we need to provide our own smpboot stub that can not use 'wfi', it has 143 * to spin the secondary CPU until the first CPU writes to the SCRPAD reg. 144 */ 145 uint32_t smpboot[] = { 146 0xe59f2018, /* ldr r2, bootreg_addr */ 147 0xe3a00000, /* mov r0, #0 */ 148 0xe5820000, /* str r0, [r2] */ 149 0xe320f002, /* wfe */ 150 0xe5921000, /* ldr r1, [r2] */ 151 0xe1110001, /* tst r1, r1 */ 152 0x0afffffb, /* beq <wfe> */ 153 0xe12fff11, /* bx r1 */ 154 NPCM7XX_SMP_BOOTREG_ADDR, 155 }; 156 int i; 157 158 for (i = 0; i < ARRAY_SIZE(smpboot); i++) { 159 smpboot[i] = tswap32(smpboot[i]); 160 } 161 162 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), 163 NPCM7XX_SMP_LOADER_START); 164 } 165 166 static struct arm_boot_info npcm7xx_binfo = { 167 .loader_start = NPCM7XX_LOADER_START, 168 .smp_loader_start = NPCM7XX_SMP_LOADER_START, 169 .smp_bootreg_addr = NPCM7XX_SMP_BOOTREG_ADDR, 170 .gic_cpu_if_addr = NPCM7XX_GIC_CPU_IF_ADDR, 171 .write_secondary_boot = npcm7xx_write_secondary_boot, 172 .board_id = -1, 173 }; 174 175 void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc) 176 { 177 NPCM7xxClass *sc = NPCM7XX_GET_CLASS(soc); 178 179 npcm7xx_binfo.ram_size = machine->ram_size; 180 npcm7xx_binfo.nb_cpus = sc->num_cpus; 181 182 arm_load_kernel(&soc->cpu[0], machine, &npcm7xx_binfo); 183 } 184 185 static void npcm7xx_init_fuses(NPCM7xxState *s) 186 { 187 NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s); 188 uint32_t value; 189 190 /* 191 * The initial mask of disabled modules indicates the chip derivative (e.g. 192 * NPCM750 or NPCM730). 193 */ 194 value = tswap32(nc->disabled_modules); 195 npcm7xx_otp_array_write(&s->fuse_array, &value, NPCM7XX_FUSE_DERIVATIVE, 196 sizeof(value)); 197 } 198 199 static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n) 200 { 201 return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n); 202 } 203 204 static void npcm7xx_init(Object *obj) 205 { 206 NPCM7xxState *s = NPCM7XX(obj); 207 int i; 208 209 for (i = 0; i < NPCM7XX_MAX_NUM_CPUS; i++) { 210 object_initialize_child(obj, "cpu[*]", &s->cpu[i], 211 ARM_CPU_TYPE_NAME("cortex-a9")); 212 } 213 214 object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); 215 object_initialize_child(obj, "gcr", &s->gcr, TYPE_NPCM7XX_GCR); 216 object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr), 217 "power-on-straps"); 218 object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM7XX_CLK); 219 object_initialize_child(obj, "otp1", &s->key_storage, 220 TYPE_NPCM7XX_KEY_STORAGE); 221 object_initialize_child(obj, "otp2", &s->fuse_array, 222 TYPE_NPCM7XX_FUSE_ARRAY); 223 object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC); 224 225 for (i = 0; i < ARRAY_SIZE(s->tim); i++) { 226 object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER); 227 } 228 229 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu)); 230 for (i = 0; i < ARRAY_SIZE(s->fiu); i++) { 231 object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i], 232 TYPE_NPCM7XX_FIU); 233 } 234 } 235 236 static void npcm7xx_realize(DeviceState *dev, Error **errp) 237 { 238 NPCM7xxState *s = NPCM7XX(dev); 239 NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s); 240 int i; 241 242 if (memory_region_size(s->dram) > NPCM7XX_DRAM_SZ) { 243 error_setg(errp, "%s: NPCM7xx cannot address more than %" PRIu64 244 " MiB of DRAM", __func__, NPCM7XX_DRAM_SZ / MiB); 245 return; 246 } 247 248 /* CPUs */ 249 for (i = 0; i < nc->num_cpus; i++) { 250 object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity", 251 arm_cpu_mp_affinity(i, NPCM7XX_MAX_NUM_CPUS), 252 &error_abort); 253 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", 254 NPCM7XX_GIC_CPU_IF_ADDR, &error_abort); 255 object_property_set_bool(OBJECT(&s->cpu[i]), "reset-hivecs", true, 256 &error_abort); 257 258 /* Disable security extensions. */ 259 object_property_set_bool(OBJECT(&s->cpu[i]), "has_el3", false, 260 &error_abort); 261 262 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { 263 return; 264 } 265 } 266 267 /* A9MPCORE peripherals. Can only fail if we pass bad parameters here. */ 268 object_property_set_int(OBJECT(&s->a9mpcore), "num-cpu", nc->num_cpus, 269 &error_abort); 270 object_property_set_int(OBJECT(&s->a9mpcore), "num-irq", NPCM7XX_NUM_IRQ, 271 &error_abort); 272 sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), &error_abort); 273 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, NPCM7XX_CPUP_BA); 274 275 for (i = 0; i < nc->num_cpus; i++) { 276 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i, 277 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ)); 278 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + nc->num_cpus, 279 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ)); 280 } 281 282 /* L2 cache controller */ 283 sysbus_create_simple("l2x0", NPCM7XX_L2C_BA, NULL); 284 285 /* System Global Control Registers (GCR). Can fail due to user input. */ 286 object_property_set_int(OBJECT(&s->gcr), "disabled-modules", 287 nc->disabled_modules, &error_abort); 288 object_property_add_const_link(OBJECT(&s->gcr), "dram-mr", OBJECT(s->dram)); 289 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) { 290 return; 291 } 292 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gcr), 0, NPCM7XX_GCR_BA); 293 294 /* Clock Control Registers (CLK). Cannot fail. */ 295 sysbus_realize(SYS_BUS_DEVICE(&s->clk), &error_abort); 296 sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0, NPCM7XX_CLK_BA); 297 298 /* OTP key storage and fuse strap array. Cannot fail. */ 299 sysbus_realize(SYS_BUS_DEVICE(&s->key_storage), &error_abort); 300 sysbus_mmio_map(SYS_BUS_DEVICE(&s->key_storage), 0, NPCM7XX_OTP1_BA); 301 sysbus_realize(SYS_BUS_DEVICE(&s->fuse_array), &error_abort); 302 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fuse_array), 0, NPCM7XX_OTP2_BA); 303 npcm7xx_init_fuses(s); 304 305 /* Fake Memory Controller (MC). Cannot fail. */ 306 sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort); 307 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA); 308 309 /* Timer Modules (TIM). Cannot fail. */ 310 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim)); 311 for (i = 0; i < ARRAY_SIZE(s->tim); i++) { 312 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->tim[i]); 313 int first_irq; 314 int j; 315 316 sysbus_realize(sbd, &error_abort); 317 sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]); 318 319 first_irq = NPCM7XX_TIMER0_IRQ + i * NPCM7XX_TIMERS_PER_CTRL; 320 for (j = 0; j < NPCM7XX_TIMERS_PER_CTRL; j++) { 321 qemu_irq irq = npcm7xx_irq(s, first_irq + j); 322 sysbus_connect_irq(sbd, j, irq); 323 } 324 } 325 326 /* UART0..3 (16550 compatible) */ 327 for (i = 0; i < ARRAY_SIZE(npcm7xx_uart_addr); i++) { 328 serial_mm_init(get_system_memory(), npcm7xx_uart_addr[i], 2, 329 npcm7xx_irq(s, NPCM7XX_UART0_IRQ + i), 115200, 330 serial_hd(i), DEVICE_LITTLE_ENDIAN); 331 } 332 333 /* 334 * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects 335 * specified, but this is a programming error. 336 */ 337 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu)); 338 for (i = 0; i < ARRAY_SIZE(s->fiu); i++) { 339 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->fiu[i]); 340 int j; 341 342 object_property_set_int(OBJECT(sbd), "cs-count", 343 npcm7xx_fiu[i].cs_count, &error_abort); 344 sysbus_realize(sbd, &error_abort); 345 346 sysbus_mmio_map(sbd, 0, npcm7xx_fiu[i].regs_addr); 347 for (j = 0; j < npcm7xx_fiu[i].cs_count; j++) { 348 sysbus_mmio_map(sbd, j + 1, npcm7xx_fiu[i].flash_addr[j]); 349 } 350 } 351 352 /* RAM2 (SRAM) */ 353 memory_region_init_ram(&s->sram, OBJECT(dev), "ram2", 354 NPCM7XX_RAM2_SZ, &error_abort); 355 memory_region_add_subregion(get_system_memory(), NPCM7XX_RAM2_BA, &s->sram); 356 357 /* RAM3 (SRAM) */ 358 memory_region_init_ram(&s->ram3, OBJECT(dev), "ram3", 359 NPCM7XX_RAM3_SZ, &error_abort); 360 memory_region_add_subregion(get_system_memory(), NPCM7XX_RAM3_BA, &s->ram3); 361 362 /* Internal ROM */ 363 memory_region_init_rom(&s->irom, OBJECT(dev), "irom", NPCM7XX_ROM_SZ, 364 &error_abort); 365 memory_region_add_subregion(get_system_memory(), NPCM7XX_ROM_BA, &s->irom); 366 367 create_unimplemented_device("npcm7xx.shm", 0xc0001000, 4 * KiB); 368 create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB); 369 create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB); 370 create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB); 371 create_unimplemented_device("npcm7xx.rng", 0xf000b000, 4 * KiB); 372 create_unimplemented_device("npcm7xx.adc", 0xf000c000, 4 * KiB); 373 create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB); 374 create_unimplemented_device("npcm7xx.gpio[0]", 0xf0010000, 4 * KiB); 375 create_unimplemented_device("npcm7xx.gpio[1]", 0xf0011000, 4 * KiB); 376 create_unimplemented_device("npcm7xx.gpio[2]", 0xf0012000, 4 * KiB); 377 create_unimplemented_device("npcm7xx.gpio[3]", 0xf0013000, 4 * KiB); 378 create_unimplemented_device("npcm7xx.gpio[4]", 0xf0014000, 4 * KiB); 379 create_unimplemented_device("npcm7xx.gpio[5]", 0xf0015000, 4 * KiB); 380 create_unimplemented_device("npcm7xx.gpio[6]", 0xf0016000, 4 * KiB); 381 create_unimplemented_device("npcm7xx.gpio[7]", 0xf0017000, 4 * KiB); 382 create_unimplemented_device("npcm7xx.smbus[0]", 0xf0080000, 4 * KiB); 383 create_unimplemented_device("npcm7xx.smbus[1]", 0xf0081000, 4 * KiB); 384 create_unimplemented_device("npcm7xx.smbus[2]", 0xf0082000, 4 * KiB); 385 create_unimplemented_device("npcm7xx.smbus[3]", 0xf0083000, 4 * KiB); 386 create_unimplemented_device("npcm7xx.smbus[4]", 0xf0084000, 4 * KiB); 387 create_unimplemented_device("npcm7xx.smbus[5]", 0xf0085000, 4 * KiB); 388 create_unimplemented_device("npcm7xx.smbus[6]", 0xf0086000, 4 * KiB); 389 create_unimplemented_device("npcm7xx.smbus[7]", 0xf0087000, 4 * KiB); 390 create_unimplemented_device("npcm7xx.smbus[8]", 0xf0088000, 4 * KiB); 391 create_unimplemented_device("npcm7xx.smbus[9]", 0xf0089000, 4 * KiB); 392 create_unimplemented_device("npcm7xx.smbus[10]", 0xf008a000, 4 * KiB); 393 create_unimplemented_device("npcm7xx.smbus[11]", 0xf008b000, 4 * KiB); 394 create_unimplemented_device("npcm7xx.smbus[12]", 0xf008c000, 4 * KiB); 395 create_unimplemented_device("npcm7xx.smbus[13]", 0xf008d000, 4 * KiB); 396 create_unimplemented_device("npcm7xx.smbus[14]", 0xf008e000, 4 * KiB); 397 create_unimplemented_device("npcm7xx.smbus[15]", 0xf008f000, 4 * KiB); 398 create_unimplemented_device("npcm7xx.espi", 0xf009f000, 4 * KiB); 399 create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB); 400 create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB); 401 create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB); 402 create_unimplemented_device("npcm7xx.pwm[0]", 0xf0103000, 4 * KiB); 403 create_unimplemented_device("npcm7xx.pwm[1]", 0xf0104000, 4 * KiB); 404 create_unimplemented_device("npcm7xx.mft[0]", 0xf0180000, 4 * KiB); 405 create_unimplemented_device("npcm7xx.mft[1]", 0xf0181000, 4 * KiB); 406 create_unimplemented_device("npcm7xx.mft[2]", 0xf0182000, 4 * KiB); 407 create_unimplemented_device("npcm7xx.mft[3]", 0xf0183000, 4 * KiB); 408 create_unimplemented_device("npcm7xx.mft[4]", 0xf0184000, 4 * KiB); 409 create_unimplemented_device("npcm7xx.mft[5]", 0xf0185000, 4 * KiB); 410 create_unimplemented_device("npcm7xx.mft[6]", 0xf0186000, 4 * KiB); 411 create_unimplemented_device("npcm7xx.mft[7]", 0xf0187000, 4 * KiB); 412 create_unimplemented_device("npcm7xx.pspi1", 0xf0200000, 4 * KiB); 413 create_unimplemented_device("npcm7xx.pspi2", 0xf0201000, 4 * KiB); 414 create_unimplemented_device("npcm7xx.ahbpci", 0xf0400000, 1 * MiB); 415 create_unimplemented_device("npcm7xx.mcphy", 0xf05f0000, 64 * KiB); 416 create_unimplemented_device("npcm7xx.gmac1", 0xf0802000, 8 * KiB); 417 create_unimplemented_device("npcm7xx.gmac2", 0xf0804000, 8 * KiB); 418 create_unimplemented_device("npcm7xx.ehci", 0xf0806000, 4 * KiB); 419 create_unimplemented_device("npcm7xx.ohci", 0xf0807000, 4 * KiB); 420 create_unimplemented_device("npcm7xx.vcd", 0xf0810000, 64 * KiB); 421 create_unimplemented_device("npcm7xx.ece", 0xf0820000, 8 * KiB); 422 create_unimplemented_device("npcm7xx.vdma", 0xf0822000, 8 * KiB); 423 create_unimplemented_device("npcm7xx.emc1", 0xf0825000, 4 * KiB); 424 create_unimplemented_device("npcm7xx.emc2", 0xf0826000, 4 * KiB); 425 create_unimplemented_device("npcm7xx.usbd[0]", 0xf0830000, 4 * KiB); 426 create_unimplemented_device("npcm7xx.usbd[1]", 0xf0831000, 4 * KiB); 427 create_unimplemented_device("npcm7xx.usbd[2]", 0xf0832000, 4 * KiB); 428 create_unimplemented_device("npcm7xx.usbd[3]", 0xf0833000, 4 * KiB); 429 create_unimplemented_device("npcm7xx.usbd[4]", 0xf0834000, 4 * KiB); 430 create_unimplemented_device("npcm7xx.usbd[5]", 0xf0835000, 4 * KiB); 431 create_unimplemented_device("npcm7xx.usbd[6]", 0xf0836000, 4 * KiB); 432 create_unimplemented_device("npcm7xx.usbd[7]", 0xf0837000, 4 * KiB); 433 create_unimplemented_device("npcm7xx.usbd[8]", 0xf0838000, 4 * KiB); 434 create_unimplemented_device("npcm7xx.usbd[9]", 0xf0839000, 4 * KiB); 435 create_unimplemented_device("npcm7xx.sd", 0xf0840000, 8 * KiB); 436 create_unimplemented_device("npcm7xx.mmc", 0xf0842000, 8 * KiB); 437 create_unimplemented_device("npcm7xx.pcimbx", 0xf0848000, 512 * KiB); 438 create_unimplemented_device("npcm7xx.aes", 0xf0858000, 4 * KiB); 439 create_unimplemented_device("npcm7xx.des", 0xf0859000, 4 * KiB); 440 create_unimplemented_device("npcm7xx.sha", 0xf085a000, 4 * KiB); 441 create_unimplemented_device("npcm7xx.secacc", 0xf085b000, 4 * KiB); 442 create_unimplemented_device("npcm7xx.spixcs0", 0xf8000000, 16 * MiB); 443 create_unimplemented_device("npcm7xx.spixcs1", 0xf9000000, 16 * MiB); 444 create_unimplemented_device("npcm7xx.spix", 0xfb001000, 4 * KiB); 445 } 446 447 static Property npcm7xx_properties[] = { 448 DEFINE_PROP_LINK("dram-mr", NPCM7xxState, dram, TYPE_MEMORY_REGION, 449 MemoryRegion *), 450 DEFINE_PROP_END_OF_LIST(), 451 }; 452 453 static void npcm7xx_class_init(ObjectClass *oc, void *data) 454 { 455 DeviceClass *dc = DEVICE_CLASS(oc); 456 457 dc->realize = npcm7xx_realize; 458 dc->user_creatable = false; 459 device_class_set_props(dc, npcm7xx_properties); 460 } 461 462 static void npcm730_class_init(ObjectClass *oc, void *data) 463 { 464 NPCM7xxClass *nc = NPCM7XX_CLASS(oc); 465 466 /* NPCM730 is optimized for data center use, so no graphics, etc. */ 467 nc->disabled_modules = 0x00300395; 468 nc->num_cpus = 2; 469 } 470 471 static void npcm750_class_init(ObjectClass *oc, void *data) 472 { 473 NPCM7xxClass *nc = NPCM7XX_CLASS(oc); 474 475 /* NPCM750 has 2 cores and a full set of peripherals */ 476 nc->disabled_modules = 0x00000000; 477 nc->num_cpus = 2; 478 } 479 480 static const TypeInfo npcm7xx_soc_types[] = { 481 { 482 .name = TYPE_NPCM7XX, 483 .parent = TYPE_DEVICE, 484 .instance_size = sizeof(NPCM7xxState), 485 .instance_init = npcm7xx_init, 486 .class_size = sizeof(NPCM7xxClass), 487 .class_init = npcm7xx_class_init, 488 .abstract = true, 489 }, { 490 .name = TYPE_NPCM730, 491 .parent = TYPE_NPCM7XX, 492 .class_init = npcm730_class_init, 493 }, { 494 .name = TYPE_NPCM750, 495 .parent = TYPE_NPCM7XX, 496 .class_init = npcm750_class_init, 497 }, 498 }; 499 500 DEFINE_TYPES(npcm7xx_soc_types); 501