1 /* 2 * Nuvoton NPCM7xx SoC family. 3 * 4 * Copyright 2020 Google LLC 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 */ 16 17 #include "qemu/osdep.h" 18 19 #include "exec/address-spaces.h" 20 #include "hw/arm/boot.h" 21 #include "hw/arm/npcm7xx.h" 22 #include "hw/char/serial.h" 23 #include "hw/loader.h" 24 #include "hw/misc/unimp.h" 25 #include "hw/qdev-properties.h" 26 #include "qapi/error.h" 27 #include "qemu/units.h" 28 #include "sysemu/sysemu.h" 29 30 /* 31 * This covers the whole MMIO space. We'll use this to catch any MMIO accesses 32 * that aren't handled by any device. 33 */ 34 #define NPCM7XX_MMIO_BA (0x80000000) 35 #define NPCM7XX_MMIO_SZ (0x7ffd0000) 36 37 /* OTP key storage and fuse strap array */ 38 #define NPCM7XX_OTP1_BA (0xf0189000) 39 #define NPCM7XX_OTP2_BA (0xf018a000) 40 41 /* Core system modules. */ 42 #define NPCM7XX_L2C_BA (0xf03fc000) 43 #define NPCM7XX_CPUP_BA (0xf03fe000) 44 #define NPCM7XX_GCR_BA (0xf0800000) 45 #define NPCM7XX_CLK_BA (0xf0801000) 46 #define NPCM7XX_MC_BA (0xf0824000) 47 48 /* Internal AHB SRAM */ 49 #define NPCM7XX_RAM3_BA (0xc0008000) 50 #define NPCM7XX_RAM3_SZ (4 * KiB) 51 52 /* Memory blocks at the end of the address space */ 53 #define NPCM7XX_RAM2_BA (0xfffd0000) 54 #define NPCM7XX_RAM2_SZ (128 * KiB) 55 #define NPCM7XX_ROM_BA (0xffff0000) 56 #define NPCM7XX_ROM_SZ (64 * KiB) 57 58 /* Clock configuration values to be fixed up when bypassing bootloader */ 59 60 /* Run PLL1 at 1600 MHz */ 61 #define NPCM7XX_PLLCON1_FIXUP_VAL (0x00402101) 62 /* Run the CPU from PLL1 and UART from PLL2 */ 63 #define NPCM7XX_CLKSEL_FIXUP_VAL (0x004aaba9) 64 65 /* 66 * Interrupt lines going into the GIC. This does not include internal Cortex-A9 67 * interrupts. 68 */ 69 enum NPCM7xxInterrupt { 70 NPCM7XX_UART0_IRQ = 2, 71 NPCM7XX_UART1_IRQ, 72 NPCM7XX_UART2_IRQ, 73 NPCM7XX_UART3_IRQ, 74 NPCM7XX_TIMER0_IRQ = 32, /* Timer Module 0 */ 75 NPCM7XX_TIMER1_IRQ, 76 NPCM7XX_TIMER2_IRQ, 77 NPCM7XX_TIMER3_IRQ, 78 NPCM7XX_TIMER4_IRQ, 79 NPCM7XX_TIMER5_IRQ, /* Timer Module 1 */ 80 NPCM7XX_TIMER6_IRQ, 81 NPCM7XX_TIMER7_IRQ, 82 NPCM7XX_TIMER8_IRQ, 83 NPCM7XX_TIMER9_IRQ, 84 NPCM7XX_TIMER10_IRQ, /* Timer Module 2 */ 85 NPCM7XX_TIMER11_IRQ, 86 NPCM7XX_TIMER12_IRQ, 87 NPCM7XX_TIMER13_IRQ, 88 NPCM7XX_TIMER14_IRQ, 89 }; 90 91 /* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */ 92 #define NPCM7XX_NUM_IRQ (160) 93 94 /* Register base address for each Timer Module */ 95 static const hwaddr npcm7xx_tim_addr[] = { 96 0xf0008000, 97 0xf0009000, 98 0xf000a000, 99 }; 100 101 /* Register base address for each 16550 UART */ 102 static const hwaddr npcm7xx_uart_addr[] = { 103 0xf0001000, 104 0xf0002000, 105 0xf0003000, 106 0xf0004000, 107 }; 108 109 /* Direct memory-mapped access to SPI0 CS0-1. */ 110 static const hwaddr npcm7xx_fiu0_flash_addr[] = { 111 0x80000000, /* CS0 */ 112 0x88000000, /* CS1 */ 113 }; 114 115 /* Direct memory-mapped access to SPI3 CS0-3. */ 116 static const hwaddr npcm7xx_fiu3_flash_addr[] = { 117 0xa0000000, /* CS0 */ 118 0xa8000000, /* CS1 */ 119 0xb0000000, /* CS2 */ 120 0xb8000000, /* CS3 */ 121 }; 122 123 static const struct { 124 const char *name; 125 hwaddr regs_addr; 126 int cs_count; 127 const hwaddr *flash_addr; 128 } npcm7xx_fiu[] = { 129 { 130 .name = "fiu0", 131 .regs_addr = 0xfb000000, 132 .cs_count = ARRAY_SIZE(npcm7xx_fiu0_flash_addr), 133 .flash_addr = npcm7xx_fiu0_flash_addr, 134 }, { 135 .name = "fiu3", 136 .regs_addr = 0xc0000000, 137 .cs_count = ARRAY_SIZE(npcm7xx_fiu3_flash_addr), 138 .flash_addr = npcm7xx_fiu3_flash_addr, 139 }, 140 }; 141 142 static void npcm7xx_write_board_setup(ARMCPU *cpu, 143 const struct arm_boot_info *info) 144 { 145 uint32_t board_setup[] = { 146 0xe59f0010, /* ldr r0, clk_base_addr */ 147 0xe59f1010, /* ldr r1, pllcon1_value */ 148 0xe5801010, /* str r1, [r0, #16] */ 149 0xe59f100c, /* ldr r1, clksel_value */ 150 0xe5801004, /* str r1, [r0, #4] */ 151 0xe12fff1e, /* bx lr */ 152 NPCM7XX_CLK_BA, 153 NPCM7XX_PLLCON1_FIXUP_VAL, 154 NPCM7XX_CLKSEL_FIXUP_VAL, 155 }; 156 int i; 157 158 for (i = 0; i < ARRAY_SIZE(board_setup); i++) { 159 board_setup[i] = tswap32(board_setup[i]); 160 } 161 rom_add_blob_fixed("board-setup", board_setup, sizeof(board_setup), 162 info->board_setup_addr); 163 } 164 165 static void npcm7xx_write_secondary_boot(ARMCPU *cpu, 166 const struct arm_boot_info *info) 167 { 168 /* 169 * The default smpboot stub halts the secondary CPU with a 'wfi' 170 * instruction, but the arch/arm/mach-npcm/platsmp.c in the Linux kernel 171 * does not send an IPI to wake it up, so the second CPU fails to boot. So 172 * we need to provide our own smpboot stub that can not use 'wfi', it has 173 * to spin the secondary CPU until the first CPU writes to the SCRPAD reg. 174 */ 175 uint32_t smpboot[] = { 176 0xe59f2018, /* ldr r2, bootreg_addr */ 177 0xe3a00000, /* mov r0, #0 */ 178 0xe5820000, /* str r0, [r2] */ 179 0xe320f002, /* wfe */ 180 0xe5921000, /* ldr r1, [r2] */ 181 0xe1110001, /* tst r1, r1 */ 182 0x0afffffb, /* beq <wfe> */ 183 0xe12fff11, /* bx r1 */ 184 NPCM7XX_SMP_BOOTREG_ADDR, 185 }; 186 int i; 187 188 for (i = 0; i < ARRAY_SIZE(smpboot); i++) { 189 smpboot[i] = tswap32(smpboot[i]); 190 } 191 192 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), 193 NPCM7XX_SMP_LOADER_START); 194 } 195 196 static struct arm_boot_info npcm7xx_binfo = { 197 .loader_start = NPCM7XX_LOADER_START, 198 .smp_loader_start = NPCM7XX_SMP_LOADER_START, 199 .smp_bootreg_addr = NPCM7XX_SMP_BOOTREG_ADDR, 200 .gic_cpu_if_addr = NPCM7XX_GIC_CPU_IF_ADDR, 201 .write_secondary_boot = npcm7xx_write_secondary_boot, 202 .board_id = -1, 203 .board_setup_addr = NPCM7XX_BOARD_SETUP_ADDR, 204 .write_board_setup = npcm7xx_write_board_setup, 205 }; 206 207 void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc) 208 { 209 NPCM7xxClass *sc = NPCM7XX_GET_CLASS(soc); 210 211 npcm7xx_binfo.ram_size = machine->ram_size; 212 npcm7xx_binfo.nb_cpus = sc->num_cpus; 213 214 arm_load_kernel(&soc->cpu[0], machine, &npcm7xx_binfo); 215 } 216 217 static void npcm7xx_init_fuses(NPCM7xxState *s) 218 { 219 NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s); 220 uint32_t value; 221 222 /* 223 * The initial mask of disabled modules indicates the chip derivative (e.g. 224 * NPCM750 or NPCM730). 225 */ 226 value = tswap32(nc->disabled_modules); 227 npcm7xx_otp_array_write(&s->fuse_array, &value, NPCM7XX_FUSE_DERIVATIVE, 228 sizeof(value)); 229 } 230 231 static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n) 232 { 233 return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n); 234 } 235 236 static void npcm7xx_init(Object *obj) 237 { 238 NPCM7xxState *s = NPCM7XX(obj); 239 int i; 240 241 for (i = 0; i < NPCM7XX_MAX_NUM_CPUS; i++) { 242 object_initialize_child(obj, "cpu[*]", &s->cpu[i], 243 ARM_CPU_TYPE_NAME("cortex-a9")); 244 } 245 246 object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); 247 object_initialize_child(obj, "gcr", &s->gcr, TYPE_NPCM7XX_GCR); 248 object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr), 249 "power-on-straps"); 250 object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM7XX_CLK); 251 object_initialize_child(obj, "otp1", &s->key_storage, 252 TYPE_NPCM7XX_KEY_STORAGE); 253 object_initialize_child(obj, "otp2", &s->fuse_array, 254 TYPE_NPCM7XX_FUSE_ARRAY); 255 object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC); 256 257 for (i = 0; i < ARRAY_SIZE(s->tim); i++) { 258 object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER); 259 } 260 261 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu)); 262 for (i = 0; i < ARRAY_SIZE(s->fiu); i++) { 263 object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i], 264 TYPE_NPCM7XX_FIU); 265 } 266 } 267 268 static void npcm7xx_realize(DeviceState *dev, Error **errp) 269 { 270 NPCM7xxState *s = NPCM7XX(dev); 271 NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s); 272 int i; 273 274 if (memory_region_size(s->dram) > NPCM7XX_DRAM_SZ) { 275 error_setg(errp, "%s: NPCM7xx cannot address more than %" PRIu64 276 " MiB of DRAM", __func__, NPCM7XX_DRAM_SZ / MiB); 277 return; 278 } 279 280 /* CPUs */ 281 for (i = 0; i < nc->num_cpus; i++) { 282 object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity", 283 arm_cpu_mp_affinity(i, NPCM7XX_MAX_NUM_CPUS), 284 &error_abort); 285 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", 286 NPCM7XX_GIC_CPU_IF_ADDR, &error_abort); 287 object_property_set_bool(OBJECT(&s->cpu[i]), "reset-hivecs", true, 288 &error_abort); 289 290 /* Disable security extensions. */ 291 object_property_set_bool(OBJECT(&s->cpu[i]), "has_el3", false, 292 &error_abort); 293 294 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { 295 return; 296 } 297 } 298 299 /* A9MPCORE peripherals. Can only fail if we pass bad parameters here. */ 300 object_property_set_int(OBJECT(&s->a9mpcore), "num-cpu", nc->num_cpus, 301 &error_abort); 302 object_property_set_int(OBJECT(&s->a9mpcore), "num-irq", NPCM7XX_NUM_IRQ, 303 &error_abort); 304 sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), &error_abort); 305 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, NPCM7XX_CPUP_BA); 306 307 for (i = 0; i < nc->num_cpus; i++) { 308 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i, 309 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ)); 310 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + nc->num_cpus, 311 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ)); 312 } 313 314 /* L2 cache controller */ 315 sysbus_create_simple("l2x0", NPCM7XX_L2C_BA, NULL); 316 317 /* System Global Control Registers (GCR). Can fail due to user input. */ 318 object_property_set_int(OBJECT(&s->gcr), "disabled-modules", 319 nc->disabled_modules, &error_abort); 320 object_property_add_const_link(OBJECT(&s->gcr), "dram-mr", OBJECT(s->dram)); 321 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) { 322 return; 323 } 324 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gcr), 0, NPCM7XX_GCR_BA); 325 326 /* Clock Control Registers (CLK). Cannot fail. */ 327 sysbus_realize(SYS_BUS_DEVICE(&s->clk), &error_abort); 328 sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0, NPCM7XX_CLK_BA); 329 330 /* OTP key storage and fuse strap array. Cannot fail. */ 331 sysbus_realize(SYS_BUS_DEVICE(&s->key_storage), &error_abort); 332 sysbus_mmio_map(SYS_BUS_DEVICE(&s->key_storage), 0, NPCM7XX_OTP1_BA); 333 sysbus_realize(SYS_BUS_DEVICE(&s->fuse_array), &error_abort); 334 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fuse_array), 0, NPCM7XX_OTP2_BA); 335 npcm7xx_init_fuses(s); 336 337 /* Fake Memory Controller (MC). Cannot fail. */ 338 sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort); 339 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA); 340 341 /* Timer Modules (TIM). Cannot fail. */ 342 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim)); 343 for (i = 0; i < ARRAY_SIZE(s->tim); i++) { 344 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->tim[i]); 345 int first_irq; 346 int j; 347 348 sysbus_realize(sbd, &error_abort); 349 sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]); 350 351 first_irq = NPCM7XX_TIMER0_IRQ + i * NPCM7XX_TIMERS_PER_CTRL; 352 for (j = 0; j < NPCM7XX_TIMERS_PER_CTRL; j++) { 353 qemu_irq irq = npcm7xx_irq(s, first_irq + j); 354 sysbus_connect_irq(sbd, j, irq); 355 } 356 } 357 358 /* UART0..3 (16550 compatible) */ 359 for (i = 0; i < ARRAY_SIZE(npcm7xx_uart_addr); i++) { 360 serial_mm_init(get_system_memory(), npcm7xx_uart_addr[i], 2, 361 npcm7xx_irq(s, NPCM7XX_UART0_IRQ + i), 115200, 362 serial_hd(i), DEVICE_LITTLE_ENDIAN); 363 } 364 365 /* 366 * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects 367 * specified, but this is a programming error. 368 */ 369 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu)); 370 for (i = 0; i < ARRAY_SIZE(s->fiu); i++) { 371 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->fiu[i]); 372 int j; 373 374 object_property_set_int(OBJECT(sbd), "cs-count", 375 npcm7xx_fiu[i].cs_count, &error_abort); 376 sysbus_realize(sbd, &error_abort); 377 378 sysbus_mmio_map(sbd, 0, npcm7xx_fiu[i].regs_addr); 379 for (j = 0; j < npcm7xx_fiu[i].cs_count; j++) { 380 sysbus_mmio_map(sbd, j + 1, npcm7xx_fiu[i].flash_addr[j]); 381 } 382 } 383 384 /* RAM2 (SRAM) */ 385 memory_region_init_ram(&s->sram, OBJECT(dev), "ram2", 386 NPCM7XX_RAM2_SZ, &error_abort); 387 memory_region_add_subregion(get_system_memory(), NPCM7XX_RAM2_BA, &s->sram); 388 389 /* RAM3 (SRAM) */ 390 memory_region_init_ram(&s->ram3, OBJECT(dev), "ram3", 391 NPCM7XX_RAM3_SZ, &error_abort); 392 memory_region_add_subregion(get_system_memory(), NPCM7XX_RAM3_BA, &s->ram3); 393 394 /* Internal ROM */ 395 memory_region_init_rom(&s->irom, OBJECT(dev), "irom", NPCM7XX_ROM_SZ, 396 &error_abort); 397 memory_region_add_subregion(get_system_memory(), NPCM7XX_ROM_BA, &s->irom); 398 399 create_unimplemented_device("npcm7xx.shm", 0xc0001000, 4 * KiB); 400 create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB); 401 create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB); 402 create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB); 403 create_unimplemented_device("npcm7xx.rng", 0xf000b000, 4 * KiB); 404 create_unimplemented_device("npcm7xx.adc", 0xf000c000, 4 * KiB); 405 create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB); 406 create_unimplemented_device("npcm7xx.gpio[0]", 0xf0010000, 4 * KiB); 407 create_unimplemented_device("npcm7xx.gpio[1]", 0xf0011000, 4 * KiB); 408 create_unimplemented_device("npcm7xx.gpio[2]", 0xf0012000, 4 * KiB); 409 create_unimplemented_device("npcm7xx.gpio[3]", 0xf0013000, 4 * KiB); 410 create_unimplemented_device("npcm7xx.gpio[4]", 0xf0014000, 4 * KiB); 411 create_unimplemented_device("npcm7xx.gpio[5]", 0xf0015000, 4 * KiB); 412 create_unimplemented_device("npcm7xx.gpio[6]", 0xf0016000, 4 * KiB); 413 create_unimplemented_device("npcm7xx.gpio[7]", 0xf0017000, 4 * KiB); 414 create_unimplemented_device("npcm7xx.smbus[0]", 0xf0080000, 4 * KiB); 415 create_unimplemented_device("npcm7xx.smbus[1]", 0xf0081000, 4 * KiB); 416 create_unimplemented_device("npcm7xx.smbus[2]", 0xf0082000, 4 * KiB); 417 create_unimplemented_device("npcm7xx.smbus[3]", 0xf0083000, 4 * KiB); 418 create_unimplemented_device("npcm7xx.smbus[4]", 0xf0084000, 4 * KiB); 419 create_unimplemented_device("npcm7xx.smbus[5]", 0xf0085000, 4 * KiB); 420 create_unimplemented_device("npcm7xx.smbus[6]", 0xf0086000, 4 * KiB); 421 create_unimplemented_device("npcm7xx.smbus[7]", 0xf0087000, 4 * KiB); 422 create_unimplemented_device("npcm7xx.smbus[8]", 0xf0088000, 4 * KiB); 423 create_unimplemented_device("npcm7xx.smbus[9]", 0xf0089000, 4 * KiB); 424 create_unimplemented_device("npcm7xx.smbus[10]", 0xf008a000, 4 * KiB); 425 create_unimplemented_device("npcm7xx.smbus[11]", 0xf008b000, 4 * KiB); 426 create_unimplemented_device("npcm7xx.smbus[12]", 0xf008c000, 4 * KiB); 427 create_unimplemented_device("npcm7xx.smbus[13]", 0xf008d000, 4 * KiB); 428 create_unimplemented_device("npcm7xx.smbus[14]", 0xf008e000, 4 * KiB); 429 create_unimplemented_device("npcm7xx.smbus[15]", 0xf008f000, 4 * KiB); 430 create_unimplemented_device("npcm7xx.espi", 0xf009f000, 4 * KiB); 431 create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB); 432 create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB); 433 create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB); 434 create_unimplemented_device("npcm7xx.pwm[0]", 0xf0103000, 4 * KiB); 435 create_unimplemented_device("npcm7xx.pwm[1]", 0xf0104000, 4 * KiB); 436 create_unimplemented_device("npcm7xx.mft[0]", 0xf0180000, 4 * KiB); 437 create_unimplemented_device("npcm7xx.mft[1]", 0xf0181000, 4 * KiB); 438 create_unimplemented_device("npcm7xx.mft[2]", 0xf0182000, 4 * KiB); 439 create_unimplemented_device("npcm7xx.mft[3]", 0xf0183000, 4 * KiB); 440 create_unimplemented_device("npcm7xx.mft[4]", 0xf0184000, 4 * KiB); 441 create_unimplemented_device("npcm7xx.mft[5]", 0xf0185000, 4 * KiB); 442 create_unimplemented_device("npcm7xx.mft[6]", 0xf0186000, 4 * KiB); 443 create_unimplemented_device("npcm7xx.mft[7]", 0xf0187000, 4 * KiB); 444 create_unimplemented_device("npcm7xx.pspi1", 0xf0200000, 4 * KiB); 445 create_unimplemented_device("npcm7xx.pspi2", 0xf0201000, 4 * KiB); 446 create_unimplemented_device("npcm7xx.ahbpci", 0xf0400000, 1 * MiB); 447 create_unimplemented_device("npcm7xx.mcphy", 0xf05f0000, 64 * KiB); 448 create_unimplemented_device("npcm7xx.gmac1", 0xf0802000, 8 * KiB); 449 create_unimplemented_device("npcm7xx.gmac2", 0xf0804000, 8 * KiB); 450 create_unimplemented_device("npcm7xx.ehci", 0xf0806000, 4 * KiB); 451 create_unimplemented_device("npcm7xx.ohci", 0xf0807000, 4 * KiB); 452 create_unimplemented_device("npcm7xx.vcd", 0xf0810000, 64 * KiB); 453 create_unimplemented_device("npcm7xx.ece", 0xf0820000, 8 * KiB); 454 create_unimplemented_device("npcm7xx.vdma", 0xf0822000, 8 * KiB); 455 create_unimplemented_device("npcm7xx.emc1", 0xf0825000, 4 * KiB); 456 create_unimplemented_device("npcm7xx.emc2", 0xf0826000, 4 * KiB); 457 create_unimplemented_device("npcm7xx.usbd[0]", 0xf0830000, 4 * KiB); 458 create_unimplemented_device("npcm7xx.usbd[1]", 0xf0831000, 4 * KiB); 459 create_unimplemented_device("npcm7xx.usbd[2]", 0xf0832000, 4 * KiB); 460 create_unimplemented_device("npcm7xx.usbd[3]", 0xf0833000, 4 * KiB); 461 create_unimplemented_device("npcm7xx.usbd[4]", 0xf0834000, 4 * KiB); 462 create_unimplemented_device("npcm7xx.usbd[5]", 0xf0835000, 4 * KiB); 463 create_unimplemented_device("npcm7xx.usbd[6]", 0xf0836000, 4 * KiB); 464 create_unimplemented_device("npcm7xx.usbd[7]", 0xf0837000, 4 * KiB); 465 create_unimplemented_device("npcm7xx.usbd[8]", 0xf0838000, 4 * KiB); 466 create_unimplemented_device("npcm7xx.usbd[9]", 0xf0839000, 4 * KiB); 467 create_unimplemented_device("npcm7xx.sd", 0xf0840000, 8 * KiB); 468 create_unimplemented_device("npcm7xx.mmc", 0xf0842000, 8 * KiB); 469 create_unimplemented_device("npcm7xx.pcimbx", 0xf0848000, 512 * KiB); 470 create_unimplemented_device("npcm7xx.aes", 0xf0858000, 4 * KiB); 471 create_unimplemented_device("npcm7xx.des", 0xf0859000, 4 * KiB); 472 create_unimplemented_device("npcm7xx.sha", 0xf085a000, 4 * KiB); 473 create_unimplemented_device("npcm7xx.secacc", 0xf085b000, 4 * KiB); 474 create_unimplemented_device("npcm7xx.spixcs0", 0xf8000000, 16 * MiB); 475 create_unimplemented_device("npcm7xx.spixcs1", 0xf9000000, 16 * MiB); 476 create_unimplemented_device("npcm7xx.spix", 0xfb001000, 4 * KiB); 477 } 478 479 static Property npcm7xx_properties[] = { 480 DEFINE_PROP_LINK("dram-mr", NPCM7xxState, dram, TYPE_MEMORY_REGION, 481 MemoryRegion *), 482 DEFINE_PROP_END_OF_LIST(), 483 }; 484 485 static void npcm7xx_class_init(ObjectClass *oc, void *data) 486 { 487 DeviceClass *dc = DEVICE_CLASS(oc); 488 489 dc->realize = npcm7xx_realize; 490 dc->user_creatable = false; 491 device_class_set_props(dc, npcm7xx_properties); 492 } 493 494 static void npcm730_class_init(ObjectClass *oc, void *data) 495 { 496 NPCM7xxClass *nc = NPCM7XX_CLASS(oc); 497 498 /* NPCM730 is optimized for data center use, so no graphics, etc. */ 499 nc->disabled_modules = 0x00300395; 500 nc->num_cpus = 2; 501 } 502 503 static void npcm750_class_init(ObjectClass *oc, void *data) 504 { 505 NPCM7xxClass *nc = NPCM7XX_CLASS(oc); 506 507 /* NPCM750 has 2 cores and a full set of peripherals */ 508 nc->disabled_modules = 0x00000000; 509 nc->num_cpus = 2; 510 } 511 512 static const TypeInfo npcm7xx_soc_types[] = { 513 { 514 .name = TYPE_NPCM7XX, 515 .parent = TYPE_DEVICE, 516 .instance_size = sizeof(NPCM7xxState), 517 .instance_init = npcm7xx_init, 518 .class_size = sizeof(NPCM7xxClass), 519 .class_init = npcm7xx_class_init, 520 .abstract = true, 521 }, { 522 .name = TYPE_NPCM730, 523 .parent = TYPE_NPCM7XX, 524 .class_init = npcm730_class_init, 525 }, { 526 .name = TYPE_NPCM750, 527 .parent = TYPE_NPCM7XX, 528 .class_init = npcm750_class_init, 529 }, 530 }; 531 532 DEFINE_TYPES(npcm7xx_soc_types); 533