1 /* 2 * Nuvoton NPCM7xx SoC family. 3 * 4 * Copyright 2020 Google LLC 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 */ 16 17 #include "qemu/osdep.h" 18 19 #include "exec/address-spaces.h" 20 #include "hw/arm/boot.h" 21 #include "hw/arm/npcm7xx.h" 22 #include "hw/char/serial.h" 23 #include "hw/loader.h" 24 #include "hw/misc/unimp.h" 25 #include "hw/qdev-clock.h" 26 #include "hw/qdev-properties.h" 27 #include "qapi/error.h" 28 #include "qemu/units.h" 29 #include "sysemu/sysemu.h" 30 31 /* 32 * This covers the whole MMIO space. We'll use this to catch any MMIO accesses 33 * that aren't handled by any device. 34 */ 35 #define NPCM7XX_MMIO_BA (0x80000000) 36 #define NPCM7XX_MMIO_SZ (0x7ffd0000) 37 38 /* OTP key storage and fuse strap array */ 39 #define NPCM7XX_OTP1_BA (0xf0189000) 40 #define NPCM7XX_OTP2_BA (0xf018a000) 41 42 /* Core system modules. */ 43 #define NPCM7XX_L2C_BA (0xf03fc000) 44 #define NPCM7XX_CPUP_BA (0xf03fe000) 45 #define NPCM7XX_GCR_BA (0xf0800000) 46 #define NPCM7XX_CLK_BA (0xf0801000) 47 #define NPCM7XX_MC_BA (0xf0824000) 48 #define NPCM7XX_RNG_BA (0xf000b000) 49 50 /* USB Host modules */ 51 #define NPCM7XX_EHCI_BA (0xf0806000) 52 #define NPCM7XX_OHCI_BA (0xf0807000) 53 54 /* Internal AHB SRAM */ 55 #define NPCM7XX_RAM3_BA (0xc0008000) 56 #define NPCM7XX_RAM3_SZ (4 * KiB) 57 58 /* Memory blocks at the end of the address space */ 59 #define NPCM7XX_RAM2_BA (0xfffd0000) 60 #define NPCM7XX_RAM2_SZ (128 * KiB) 61 #define NPCM7XX_ROM_BA (0xffff0000) 62 #define NPCM7XX_ROM_SZ (64 * KiB) 63 64 /* Clock configuration values to be fixed up when bypassing bootloader */ 65 66 /* Run PLL1 at 1600 MHz */ 67 #define NPCM7XX_PLLCON1_FIXUP_VAL (0x00402101) 68 /* Run the CPU from PLL1 and UART from PLL2 */ 69 #define NPCM7XX_CLKSEL_FIXUP_VAL (0x004aaba9) 70 71 /* 72 * Interrupt lines going into the GIC. This does not include internal Cortex-A9 73 * interrupts. 74 */ 75 enum NPCM7xxInterrupt { 76 NPCM7XX_UART0_IRQ = 2, 77 NPCM7XX_UART1_IRQ, 78 NPCM7XX_UART2_IRQ, 79 NPCM7XX_UART3_IRQ, 80 NPCM7XX_TIMER0_IRQ = 32, /* Timer Module 0 */ 81 NPCM7XX_TIMER1_IRQ, 82 NPCM7XX_TIMER2_IRQ, 83 NPCM7XX_TIMER3_IRQ, 84 NPCM7XX_TIMER4_IRQ, 85 NPCM7XX_TIMER5_IRQ, /* Timer Module 1 */ 86 NPCM7XX_TIMER6_IRQ, 87 NPCM7XX_TIMER7_IRQ, 88 NPCM7XX_TIMER8_IRQ, 89 NPCM7XX_TIMER9_IRQ, 90 NPCM7XX_TIMER10_IRQ, /* Timer Module 2 */ 91 NPCM7XX_TIMER11_IRQ, 92 NPCM7XX_TIMER12_IRQ, 93 NPCM7XX_TIMER13_IRQ, 94 NPCM7XX_TIMER14_IRQ, 95 NPCM7XX_WDG0_IRQ = 47, /* Timer Module 0 Watchdog */ 96 NPCM7XX_WDG1_IRQ, /* Timer Module 1 Watchdog */ 97 NPCM7XX_WDG2_IRQ, /* Timer Module 2 Watchdog */ 98 NPCM7XX_EHCI_IRQ = 61, 99 NPCM7XX_OHCI_IRQ = 62, 100 NPCM7XX_GPIO0_IRQ = 116, 101 NPCM7XX_GPIO1_IRQ, 102 NPCM7XX_GPIO2_IRQ, 103 NPCM7XX_GPIO3_IRQ, 104 NPCM7XX_GPIO4_IRQ, 105 NPCM7XX_GPIO5_IRQ, 106 NPCM7XX_GPIO6_IRQ, 107 NPCM7XX_GPIO7_IRQ, 108 }; 109 110 /* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */ 111 #define NPCM7XX_NUM_IRQ (160) 112 113 /* Register base address for each Timer Module */ 114 static const hwaddr npcm7xx_tim_addr[] = { 115 0xf0008000, 116 0xf0009000, 117 0xf000a000, 118 }; 119 120 /* Register base address for each 16550 UART */ 121 static const hwaddr npcm7xx_uart_addr[] = { 122 0xf0001000, 123 0xf0002000, 124 0xf0003000, 125 0xf0004000, 126 }; 127 128 /* Direct memory-mapped access to SPI0 CS0-1. */ 129 static const hwaddr npcm7xx_fiu0_flash_addr[] = { 130 0x80000000, /* CS0 */ 131 0x88000000, /* CS1 */ 132 }; 133 134 /* Direct memory-mapped access to SPI3 CS0-3. */ 135 static const hwaddr npcm7xx_fiu3_flash_addr[] = { 136 0xa0000000, /* CS0 */ 137 0xa8000000, /* CS1 */ 138 0xb0000000, /* CS2 */ 139 0xb8000000, /* CS3 */ 140 }; 141 142 static const struct { 143 hwaddr regs_addr; 144 uint32_t unconnected_pins; 145 uint32_t reset_pu; 146 uint32_t reset_pd; 147 uint32_t reset_osrc; 148 uint32_t reset_odsc; 149 } npcm7xx_gpio[] = { 150 { 151 .regs_addr = 0xf0010000, 152 .reset_pu = 0xff03ffff, 153 .reset_pd = 0x00fc0000, 154 }, { 155 .regs_addr = 0xf0011000, 156 .unconnected_pins = 0x0000001e, 157 .reset_pu = 0xfefffe07, 158 .reset_pd = 0x010001e0, 159 }, { 160 .regs_addr = 0xf0012000, 161 .reset_pu = 0x780fffff, 162 .reset_pd = 0x07f00000, 163 .reset_odsc = 0x00700000, 164 }, { 165 .regs_addr = 0xf0013000, 166 .reset_pu = 0x00fc0000, 167 .reset_pd = 0xff000000, 168 }, { 169 .regs_addr = 0xf0014000, 170 .reset_pu = 0xffffffff, 171 }, { 172 .regs_addr = 0xf0015000, 173 .reset_pu = 0xbf83f801, 174 .reset_pd = 0x007c0000, 175 .reset_osrc = 0x000000f1, 176 .reset_odsc = 0x3f9f80f1, 177 }, { 178 .regs_addr = 0xf0016000, 179 .reset_pu = 0xfc00f801, 180 .reset_pd = 0x000007fe, 181 .reset_odsc = 0x00000800, 182 }, { 183 .regs_addr = 0xf0017000, 184 .unconnected_pins = 0xffffff00, 185 .reset_pu = 0x0000007f, 186 .reset_osrc = 0x0000007f, 187 .reset_odsc = 0x0000007f, 188 }, 189 }; 190 191 static const struct { 192 const char *name; 193 hwaddr regs_addr; 194 int cs_count; 195 const hwaddr *flash_addr; 196 } npcm7xx_fiu[] = { 197 { 198 .name = "fiu0", 199 .regs_addr = 0xfb000000, 200 .cs_count = ARRAY_SIZE(npcm7xx_fiu0_flash_addr), 201 .flash_addr = npcm7xx_fiu0_flash_addr, 202 }, { 203 .name = "fiu3", 204 .regs_addr = 0xc0000000, 205 .cs_count = ARRAY_SIZE(npcm7xx_fiu3_flash_addr), 206 .flash_addr = npcm7xx_fiu3_flash_addr, 207 }, 208 }; 209 210 static void npcm7xx_write_board_setup(ARMCPU *cpu, 211 const struct arm_boot_info *info) 212 { 213 uint32_t board_setup[] = { 214 0xe59f0010, /* ldr r0, clk_base_addr */ 215 0xe59f1010, /* ldr r1, pllcon1_value */ 216 0xe5801010, /* str r1, [r0, #16] */ 217 0xe59f100c, /* ldr r1, clksel_value */ 218 0xe5801004, /* str r1, [r0, #4] */ 219 0xe12fff1e, /* bx lr */ 220 NPCM7XX_CLK_BA, 221 NPCM7XX_PLLCON1_FIXUP_VAL, 222 NPCM7XX_CLKSEL_FIXUP_VAL, 223 }; 224 int i; 225 226 for (i = 0; i < ARRAY_SIZE(board_setup); i++) { 227 board_setup[i] = tswap32(board_setup[i]); 228 } 229 rom_add_blob_fixed("board-setup", board_setup, sizeof(board_setup), 230 info->board_setup_addr); 231 } 232 233 static void npcm7xx_write_secondary_boot(ARMCPU *cpu, 234 const struct arm_boot_info *info) 235 { 236 /* 237 * The default smpboot stub halts the secondary CPU with a 'wfi' 238 * instruction, but the arch/arm/mach-npcm/platsmp.c in the Linux kernel 239 * does not send an IPI to wake it up, so the second CPU fails to boot. So 240 * we need to provide our own smpboot stub that can not use 'wfi', it has 241 * to spin the secondary CPU until the first CPU writes to the SCRPAD reg. 242 */ 243 uint32_t smpboot[] = { 244 0xe59f2018, /* ldr r2, bootreg_addr */ 245 0xe3a00000, /* mov r0, #0 */ 246 0xe5820000, /* str r0, [r2] */ 247 0xe320f002, /* wfe */ 248 0xe5921000, /* ldr r1, [r2] */ 249 0xe1110001, /* tst r1, r1 */ 250 0x0afffffb, /* beq <wfe> */ 251 0xe12fff11, /* bx r1 */ 252 NPCM7XX_SMP_BOOTREG_ADDR, 253 }; 254 int i; 255 256 for (i = 0; i < ARRAY_SIZE(smpboot); i++) { 257 smpboot[i] = tswap32(smpboot[i]); 258 } 259 260 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), 261 NPCM7XX_SMP_LOADER_START); 262 } 263 264 static struct arm_boot_info npcm7xx_binfo = { 265 .loader_start = NPCM7XX_LOADER_START, 266 .smp_loader_start = NPCM7XX_SMP_LOADER_START, 267 .smp_bootreg_addr = NPCM7XX_SMP_BOOTREG_ADDR, 268 .gic_cpu_if_addr = NPCM7XX_GIC_CPU_IF_ADDR, 269 .write_secondary_boot = npcm7xx_write_secondary_boot, 270 .board_id = -1, 271 .board_setup_addr = NPCM7XX_BOARD_SETUP_ADDR, 272 .write_board_setup = npcm7xx_write_board_setup, 273 }; 274 275 void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc) 276 { 277 NPCM7xxClass *sc = NPCM7XX_GET_CLASS(soc); 278 279 npcm7xx_binfo.ram_size = machine->ram_size; 280 npcm7xx_binfo.nb_cpus = sc->num_cpus; 281 282 arm_load_kernel(&soc->cpu[0], machine, &npcm7xx_binfo); 283 } 284 285 static void npcm7xx_init_fuses(NPCM7xxState *s) 286 { 287 NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s); 288 uint32_t value; 289 290 /* 291 * The initial mask of disabled modules indicates the chip derivative (e.g. 292 * NPCM750 or NPCM730). 293 */ 294 value = tswap32(nc->disabled_modules); 295 npcm7xx_otp_array_write(&s->fuse_array, &value, NPCM7XX_FUSE_DERIVATIVE, 296 sizeof(value)); 297 } 298 299 static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n) 300 { 301 return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n); 302 } 303 304 static void npcm7xx_init(Object *obj) 305 { 306 NPCM7xxState *s = NPCM7XX(obj); 307 int i; 308 309 for (i = 0; i < NPCM7XX_MAX_NUM_CPUS; i++) { 310 object_initialize_child(obj, "cpu[*]", &s->cpu[i], 311 ARM_CPU_TYPE_NAME("cortex-a9")); 312 } 313 314 object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); 315 object_initialize_child(obj, "gcr", &s->gcr, TYPE_NPCM7XX_GCR); 316 object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr), 317 "power-on-straps"); 318 object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM7XX_CLK); 319 object_initialize_child(obj, "otp1", &s->key_storage, 320 TYPE_NPCM7XX_KEY_STORAGE); 321 object_initialize_child(obj, "otp2", &s->fuse_array, 322 TYPE_NPCM7XX_FUSE_ARRAY); 323 object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC); 324 object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG); 325 326 for (i = 0; i < ARRAY_SIZE(s->tim); i++) { 327 object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER); 328 } 329 330 for (i = 0; i < ARRAY_SIZE(s->gpio); i++) { 331 object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_NPCM7XX_GPIO); 332 } 333 334 object_initialize_child(obj, "ehci", &s->ehci, TYPE_NPCM7XX_EHCI); 335 object_initialize_child(obj, "ohci", &s->ohci, TYPE_SYSBUS_OHCI); 336 337 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu)); 338 for (i = 0; i < ARRAY_SIZE(s->fiu); i++) { 339 object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i], 340 TYPE_NPCM7XX_FIU); 341 } 342 } 343 344 static void npcm7xx_realize(DeviceState *dev, Error **errp) 345 { 346 NPCM7xxState *s = NPCM7XX(dev); 347 NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s); 348 int i; 349 350 if (memory_region_size(s->dram) > NPCM7XX_DRAM_SZ) { 351 error_setg(errp, "%s: NPCM7xx cannot address more than %" PRIu64 352 " MiB of DRAM", __func__, NPCM7XX_DRAM_SZ / MiB); 353 return; 354 } 355 356 /* CPUs */ 357 for (i = 0; i < nc->num_cpus; i++) { 358 object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity", 359 arm_cpu_mp_affinity(i, NPCM7XX_MAX_NUM_CPUS), 360 &error_abort); 361 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", 362 NPCM7XX_GIC_CPU_IF_ADDR, &error_abort); 363 object_property_set_bool(OBJECT(&s->cpu[i]), "reset-hivecs", true, 364 &error_abort); 365 366 /* Disable security extensions. */ 367 object_property_set_bool(OBJECT(&s->cpu[i]), "has_el3", false, 368 &error_abort); 369 370 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { 371 return; 372 } 373 } 374 375 /* A9MPCORE peripherals. Can only fail if we pass bad parameters here. */ 376 object_property_set_int(OBJECT(&s->a9mpcore), "num-cpu", nc->num_cpus, 377 &error_abort); 378 object_property_set_int(OBJECT(&s->a9mpcore), "num-irq", NPCM7XX_NUM_IRQ, 379 &error_abort); 380 sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), &error_abort); 381 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, NPCM7XX_CPUP_BA); 382 383 for (i = 0; i < nc->num_cpus; i++) { 384 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i, 385 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ)); 386 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + nc->num_cpus, 387 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ)); 388 } 389 390 /* L2 cache controller */ 391 sysbus_create_simple("l2x0", NPCM7XX_L2C_BA, NULL); 392 393 /* System Global Control Registers (GCR). Can fail due to user input. */ 394 object_property_set_int(OBJECT(&s->gcr), "disabled-modules", 395 nc->disabled_modules, &error_abort); 396 object_property_add_const_link(OBJECT(&s->gcr), "dram-mr", OBJECT(s->dram)); 397 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) { 398 return; 399 } 400 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gcr), 0, NPCM7XX_GCR_BA); 401 402 /* Clock Control Registers (CLK). Cannot fail. */ 403 sysbus_realize(SYS_BUS_DEVICE(&s->clk), &error_abort); 404 sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0, NPCM7XX_CLK_BA); 405 406 /* OTP key storage and fuse strap array. Cannot fail. */ 407 sysbus_realize(SYS_BUS_DEVICE(&s->key_storage), &error_abort); 408 sysbus_mmio_map(SYS_BUS_DEVICE(&s->key_storage), 0, NPCM7XX_OTP1_BA); 409 sysbus_realize(SYS_BUS_DEVICE(&s->fuse_array), &error_abort); 410 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fuse_array), 0, NPCM7XX_OTP2_BA); 411 npcm7xx_init_fuses(s); 412 413 /* Fake Memory Controller (MC). Cannot fail. */ 414 sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort); 415 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA); 416 417 /* Timer Modules (TIM). Cannot fail. */ 418 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim)); 419 for (i = 0; i < ARRAY_SIZE(s->tim); i++) { 420 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->tim[i]); 421 int first_irq; 422 int j; 423 424 /* Connect the timer clock. */ 425 qdev_connect_clock_in(DEVICE(&s->tim[i]), "clock", qdev_get_clock_out( 426 DEVICE(&s->clk), "timer-clock")); 427 428 sysbus_realize(sbd, &error_abort); 429 sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]); 430 431 first_irq = NPCM7XX_TIMER0_IRQ + i * NPCM7XX_TIMERS_PER_CTRL; 432 for (j = 0; j < NPCM7XX_TIMERS_PER_CTRL; j++) { 433 qemu_irq irq = npcm7xx_irq(s, first_irq + j); 434 sysbus_connect_irq(sbd, j, irq); 435 } 436 437 /* IRQ for watchdogs */ 438 sysbus_connect_irq(sbd, NPCM7XX_TIMERS_PER_CTRL, 439 npcm7xx_irq(s, NPCM7XX_WDG0_IRQ + i)); 440 /* GPIO that connects clk module with watchdog */ 441 qdev_connect_gpio_out_named(DEVICE(&s->tim[i]), 442 NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 0, 443 qdev_get_gpio_in_named(DEVICE(&s->clk), 444 NPCM7XX_WATCHDOG_RESET_GPIO_IN, i)); 445 } 446 447 /* UART0..3 (16550 compatible) */ 448 for (i = 0; i < ARRAY_SIZE(npcm7xx_uart_addr); i++) { 449 serial_mm_init(get_system_memory(), npcm7xx_uart_addr[i], 2, 450 npcm7xx_irq(s, NPCM7XX_UART0_IRQ + i), 115200, 451 serial_hd(i), DEVICE_LITTLE_ENDIAN); 452 } 453 454 /* Random Number Generator. Cannot fail. */ 455 sysbus_realize(SYS_BUS_DEVICE(&s->rng), &error_abort); 456 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rng), 0, NPCM7XX_RNG_BA); 457 458 /* GPIO modules. Cannot fail. */ 459 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_gpio) != ARRAY_SIZE(s->gpio)); 460 for (i = 0; i < ARRAY_SIZE(s->gpio); i++) { 461 Object *obj = OBJECT(&s->gpio[i]); 462 463 object_property_set_uint(obj, "reset-pullup", 464 npcm7xx_gpio[i].reset_pu, &error_abort); 465 object_property_set_uint(obj, "reset-pulldown", 466 npcm7xx_gpio[i].reset_pd, &error_abort); 467 object_property_set_uint(obj, "reset-osrc", 468 npcm7xx_gpio[i].reset_osrc, &error_abort); 469 object_property_set_uint(obj, "reset-odsc", 470 npcm7xx_gpio[i].reset_odsc, &error_abort); 471 sysbus_realize(SYS_BUS_DEVICE(obj), &error_abort); 472 sysbus_mmio_map(SYS_BUS_DEVICE(obj), 0, npcm7xx_gpio[i].regs_addr); 473 sysbus_connect_irq(SYS_BUS_DEVICE(obj), 0, 474 npcm7xx_irq(s, NPCM7XX_GPIO0_IRQ + i)); 475 } 476 477 /* USB Host */ 478 object_property_set_bool(OBJECT(&s->ehci), "companion-enable", true, 479 &error_abort); 480 sysbus_realize(SYS_BUS_DEVICE(&s->ehci), &error_abort); 481 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci), 0, NPCM7XX_EHCI_BA); 482 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci), 0, 483 npcm7xx_irq(s, NPCM7XX_EHCI_IRQ)); 484 485 object_property_set_str(OBJECT(&s->ohci), "masterbus", "usb-bus.0", 486 &error_abort); 487 object_property_set_uint(OBJECT(&s->ohci), "num-ports", 1, &error_abort); 488 sysbus_realize(SYS_BUS_DEVICE(&s->ohci), &error_abort); 489 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci), 0, NPCM7XX_OHCI_BA); 490 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci), 0, 491 npcm7xx_irq(s, NPCM7XX_OHCI_IRQ)); 492 493 /* 494 * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects 495 * specified, but this is a programming error. 496 */ 497 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu)); 498 for (i = 0; i < ARRAY_SIZE(s->fiu); i++) { 499 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->fiu[i]); 500 int j; 501 502 object_property_set_int(OBJECT(sbd), "cs-count", 503 npcm7xx_fiu[i].cs_count, &error_abort); 504 sysbus_realize(sbd, &error_abort); 505 506 sysbus_mmio_map(sbd, 0, npcm7xx_fiu[i].regs_addr); 507 for (j = 0; j < npcm7xx_fiu[i].cs_count; j++) { 508 sysbus_mmio_map(sbd, j + 1, npcm7xx_fiu[i].flash_addr[j]); 509 } 510 } 511 512 /* RAM2 (SRAM) */ 513 memory_region_init_ram(&s->sram, OBJECT(dev), "ram2", 514 NPCM7XX_RAM2_SZ, &error_abort); 515 memory_region_add_subregion(get_system_memory(), NPCM7XX_RAM2_BA, &s->sram); 516 517 /* RAM3 (SRAM) */ 518 memory_region_init_ram(&s->ram3, OBJECT(dev), "ram3", 519 NPCM7XX_RAM3_SZ, &error_abort); 520 memory_region_add_subregion(get_system_memory(), NPCM7XX_RAM3_BA, &s->ram3); 521 522 /* Internal ROM */ 523 memory_region_init_rom(&s->irom, OBJECT(dev), "irom", NPCM7XX_ROM_SZ, 524 &error_abort); 525 memory_region_add_subregion(get_system_memory(), NPCM7XX_ROM_BA, &s->irom); 526 527 create_unimplemented_device("npcm7xx.shm", 0xc0001000, 4 * KiB); 528 create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB); 529 create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB); 530 create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB); 531 create_unimplemented_device("npcm7xx.adc", 0xf000c000, 4 * KiB); 532 create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB); 533 create_unimplemented_device("npcm7xx.gpio[0]", 0xf0010000, 4 * KiB); 534 create_unimplemented_device("npcm7xx.gpio[1]", 0xf0011000, 4 * KiB); 535 create_unimplemented_device("npcm7xx.gpio[2]", 0xf0012000, 4 * KiB); 536 create_unimplemented_device("npcm7xx.gpio[3]", 0xf0013000, 4 * KiB); 537 create_unimplemented_device("npcm7xx.gpio[4]", 0xf0014000, 4 * KiB); 538 create_unimplemented_device("npcm7xx.gpio[5]", 0xf0015000, 4 * KiB); 539 create_unimplemented_device("npcm7xx.gpio[6]", 0xf0016000, 4 * KiB); 540 create_unimplemented_device("npcm7xx.gpio[7]", 0xf0017000, 4 * KiB); 541 create_unimplemented_device("npcm7xx.smbus[0]", 0xf0080000, 4 * KiB); 542 create_unimplemented_device("npcm7xx.smbus[1]", 0xf0081000, 4 * KiB); 543 create_unimplemented_device("npcm7xx.smbus[2]", 0xf0082000, 4 * KiB); 544 create_unimplemented_device("npcm7xx.smbus[3]", 0xf0083000, 4 * KiB); 545 create_unimplemented_device("npcm7xx.smbus[4]", 0xf0084000, 4 * KiB); 546 create_unimplemented_device("npcm7xx.smbus[5]", 0xf0085000, 4 * KiB); 547 create_unimplemented_device("npcm7xx.smbus[6]", 0xf0086000, 4 * KiB); 548 create_unimplemented_device("npcm7xx.smbus[7]", 0xf0087000, 4 * KiB); 549 create_unimplemented_device("npcm7xx.smbus[8]", 0xf0088000, 4 * KiB); 550 create_unimplemented_device("npcm7xx.smbus[9]", 0xf0089000, 4 * KiB); 551 create_unimplemented_device("npcm7xx.smbus[10]", 0xf008a000, 4 * KiB); 552 create_unimplemented_device("npcm7xx.smbus[11]", 0xf008b000, 4 * KiB); 553 create_unimplemented_device("npcm7xx.smbus[12]", 0xf008c000, 4 * KiB); 554 create_unimplemented_device("npcm7xx.smbus[13]", 0xf008d000, 4 * KiB); 555 create_unimplemented_device("npcm7xx.smbus[14]", 0xf008e000, 4 * KiB); 556 create_unimplemented_device("npcm7xx.smbus[15]", 0xf008f000, 4 * KiB); 557 create_unimplemented_device("npcm7xx.espi", 0xf009f000, 4 * KiB); 558 create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB); 559 create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB); 560 create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB); 561 create_unimplemented_device("npcm7xx.pwm[0]", 0xf0103000, 4 * KiB); 562 create_unimplemented_device("npcm7xx.pwm[1]", 0xf0104000, 4 * KiB); 563 create_unimplemented_device("npcm7xx.mft[0]", 0xf0180000, 4 * KiB); 564 create_unimplemented_device("npcm7xx.mft[1]", 0xf0181000, 4 * KiB); 565 create_unimplemented_device("npcm7xx.mft[2]", 0xf0182000, 4 * KiB); 566 create_unimplemented_device("npcm7xx.mft[3]", 0xf0183000, 4 * KiB); 567 create_unimplemented_device("npcm7xx.mft[4]", 0xf0184000, 4 * KiB); 568 create_unimplemented_device("npcm7xx.mft[5]", 0xf0185000, 4 * KiB); 569 create_unimplemented_device("npcm7xx.mft[6]", 0xf0186000, 4 * KiB); 570 create_unimplemented_device("npcm7xx.mft[7]", 0xf0187000, 4 * KiB); 571 create_unimplemented_device("npcm7xx.pspi1", 0xf0200000, 4 * KiB); 572 create_unimplemented_device("npcm7xx.pspi2", 0xf0201000, 4 * KiB); 573 create_unimplemented_device("npcm7xx.ahbpci", 0xf0400000, 1 * MiB); 574 create_unimplemented_device("npcm7xx.mcphy", 0xf05f0000, 64 * KiB); 575 create_unimplemented_device("npcm7xx.gmac1", 0xf0802000, 8 * KiB); 576 create_unimplemented_device("npcm7xx.gmac2", 0xf0804000, 8 * KiB); 577 create_unimplemented_device("npcm7xx.vcd", 0xf0810000, 64 * KiB); 578 create_unimplemented_device("npcm7xx.ece", 0xf0820000, 8 * KiB); 579 create_unimplemented_device("npcm7xx.vdma", 0xf0822000, 8 * KiB); 580 create_unimplemented_device("npcm7xx.emc1", 0xf0825000, 4 * KiB); 581 create_unimplemented_device("npcm7xx.emc2", 0xf0826000, 4 * KiB); 582 create_unimplemented_device("npcm7xx.usbd[0]", 0xf0830000, 4 * KiB); 583 create_unimplemented_device("npcm7xx.usbd[1]", 0xf0831000, 4 * KiB); 584 create_unimplemented_device("npcm7xx.usbd[2]", 0xf0832000, 4 * KiB); 585 create_unimplemented_device("npcm7xx.usbd[3]", 0xf0833000, 4 * KiB); 586 create_unimplemented_device("npcm7xx.usbd[4]", 0xf0834000, 4 * KiB); 587 create_unimplemented_device("npcm7xx.usbd[5]", 0xf0835000, 4 * KiB); 588 create_unimplemented_device("npcm7xx.usbd[6]", 0xf0836000, 4 * KiB); 589 create_unimplemented_device("npcm7xx.usbd[7]", 0xf0837000, 4 * KiB); 590 create_unimplemented_device("npcm7xx.usbd[8]", 0xf0838000, 4 * KiB); 591 create_unimplemented_device("npcm7xx.usbd[9]", 0xf0839000, 4 * KiB); 592 create_unimplemented_device("npcm7xx.sd", 0xf0840000, 8 * KiB); 593 create_unimplemented_device("npcm7xx.mmc", 0xf0842000, 8 * KiB); 594 create_unimplemented_device("npcm7xx.pcimbx", 0xf0848000, 512 * KiB); 595 create_unimplemented_device("npcm7xx.aes", 0xf0858000, 4 * KiB); 596 create_unimplemented_device("npcm7xx.des", 0xf0859000, 4 * KiB); 597 create_unimplemented_device("npcm7xx.sha", 0xf085a000, 4 * KiB); 598 create_unimplemented_device("npcm7xx.secacc", 0xf085b000, 4 * KiB); 599 create_unimplemented_device("npcm7xx.spixcs0", 0xf8000000, 16 * MiB); 600 create_unimplemented_device("npcm7xx.spixcs1", 0xf9000000, 16 * MiB); 601 create_unimplemented_device("npcm7xx.spix", 0xfb001000, 4 * KiB); 602 } 603 604 static Property npcm7xx_properties[] = { 605 DEFINE_PROP_LINK("dram-mr", NPCM7xxState, dram, TYPE_MEMORY_REGION, 606 MemoryRegion *), 607 DEFINE_PROP_END_OF_LIST(), 608 }; 609 610 static void npcm7xx_class_init(ObjectClass *oc, void *data) 611 { 612 DeviceClass *dc = DEVICE_CLASS(oc); 613 614 dc->realize = npcm7xx_realize; 615 dc->user_creatable = false; 616 device_class_set_props(dc, npcm7xx_properties); 617 } 618 619 static void npcm730_class_init(ObjectClass *oc, void *data) 620 { 621 NPCM7xxClass *nc = NPCM7XX_CLASS(oc); 622 623 /* NPCM730 is optimized for data center use, so no graphics, etc. */ 624 nc->disabled_modules = 0x00300395; 625 nc->num_cpus = 2; 626 } 627 628 static void npcm750_class_init(ObjectClass *oc, void *data) 629 { 630 NPCM7xxClass *nc = NPCM7XX_CLASS(oc); 631 632 /* NPCM750 has 2 cores and a full set of peripherals */ 633 nc->disabled_modules = 0x00000000; 634 nc->num_cpus = 2; 635 } 636 637 static const TypeInfo npcm7xx_soc_types[] = { 638 { 639 .name = TYPE_NPCM7XX, 640 .parent = TYPE_DEVICE, 641 .instance_size = sizeof(NPCM7xxState), 642 .instance_init = npcm7xx_init, 643 .class_size = sizeof(NPCM7xxClass), 644 .class_init = npcm7xx_class_init, 645 .abstract = true, 646 }, { 647 .name = TYPE_NPCM730, 648 .parent = TYPE_NPCM7XX, 649 .class_init = npcm730_class_init, 650 }, { 651 .name = TYPE_NPCM750, 652 .parent = TYPE_NPCM7XX, 653 .class_init = npcm750_class_init, 654 }, 655 }; 656 657 DEFINE_TYPES(npcm7xx_soc_types); 658