12d8f048cSHavard Skinnemoen /* 22d8f048cSHavard Skinnemoen * Nuvoton NPCM7xx SoC family. 32d8f048cSHavard Skinnemoen * 42d8f048cSHavard Skinnemoen * Copyright 2020 Google LLC 52d8f048cSHavard Skinnemoen * 62d8f048cSHavard Skinnemoen * This program is free software; you can redistribute it and/or modify it 72d8f048cSHavard Skinnemoen * under the terms of the GNU General Public License as published by the 82d8f048cSHavard Skinnemoen * Free Software Foundation; either version 2 of the License, or 92d8f048cSHavard Skinnemoen * (at your option) any later version. 102d8f048cSHavard Skinnemoen * 112d8f048cSHavard Skinnemoen * This program is distributed in the hope that it will be useful, but WITHOUT 122d8f048cSHavard Skinnemoen * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 132d8f048cSHavard Skinnemoen * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 142d8f048cSHavard Skinnemoen * for more details. 152d8f048cSHavard Skinnemoen */ 162d8f048cSHavard Skinnemoen 172d8f048cSHavard Skinnemoen #include "qemu/osdep.h" 182d8f048cSHavard Skinnemoen 192d8f048cSHavard Skinnemoen #include "exec/address-spaces.h" 202d8f048cSHavard Skinnemoen #include "hw/arm/boot.h" 212d8f048cSHavard Skinnemoen #include "hw/arm/npcm7xx.h" 222d8f048cSHavard Skinnemoen #include "hw/char/serial.h" 232d8f048cSHavard Skinnemoen #include "hw/loader.h" 242d8f048cSHavard Skinnemoen #include "hw/misc/unimp.h" 252d8f048cSHavard Skinnemoen #include "hw/qdev-properties.h" 262d8f048cSHavard Skinnemoen #include "qapi/error.h" 272d8f048cSHavard Skinnemoen #include "qemu/units.h" 282d8f048cSHavard Skinnemoen #include "sysemu/sysemu.h" 292d8f048cSHavard Skinnemoen 302d8f048cSHavard Skinnemoen /* 312d8f048cSHavard Skinnemoen * This covers the whole MMIO space. We'll use this to catch any MMIO accesses 322d8f048cSHavard Skinnemoen * that aren't handled by any device. 332d8f048cSHavard Skinnemoen */ 342d8f048cSHavard Skinnemoen #define NPCM7XX_MMIO_BA (0x80000000) 352d8f048cSHavard Skinnemoen #define NPCM7XX_MMIO_SZ (0x7ffd0000) 362d8f048cSHavard Skinnemoen 37c752bb07SHavard Skinnemoen /* OTP key storage and fuse strap array */ 38c752bb07SHavard Skinnemoen #define NPCM7XX_OTP1_BA (0xf0189000) 39c752bb07SHavard Skinnemoen #define NPCM7XX_OTP2_BA (0xf018a000) 40c752bb07SHavard Skinnemoen 412d8f048cSHavard Skinnemoen /* Core system modules. */ 422d8f048cSHavard Skinnemoen #define NPCM7XX_L2C_BA (0xf03fc000) 432d8f048cSHavard Skinnemoen #define NPCM7XX_CPUP_BA (0xf03fe000) 442d8f048cSHavard Skinnemoen #define NPCM7XX_GCR_BA (0xf0800000) 452d8f048cSHavard Skinnemoen #define NPCM7XX_CLK_BA (0xf0801000) 46*1351f892SHavard Skinnemoen #define NPCM7XX_MC_BA (0xf0824000) 472d8f048cSHavard Skinnemoen 482d8f048cSHavard Skinnemoen /* Internal AHB SRAM */ 492d8f048cSHavard Skinnemoen #define NPCM7XX_RAM3_BA (0xc0008000) 502d8f048cSHavard Skinnemoen #define NPCM7XX_RAM3_SZ (4 * KiB) 512d8f048cSHavard Skinnemoen 522d8f048cSHavard Skinnemoen /* Memory blocks at the end of the address space */ 532d8f048cSHavard Skinnemoen #define NPCM7XX_RAM2_BA (0xfffd0000) 542d8f048cSHavard Skinnemoen #define NPCM7XX_RAM2_SZ (128 * KiB) 552d8f048cSHavard Skinnemoen #define NPCM7XX_ROM_BA (0xffff0000) 562d8f048cSHavard Skinnemoen #define NPCM7XX_ROM_SZ (64 * KiB) 572d8f048cSHavard Skinnemoen 582d8f048cSHavard Skinnemoen /* 592d8f048cSHavard Skinnemoen * Interrupt lines going into the GIC. This does not include internal Cortex-A9 602d8f048cSHavard Skinnemoen * interrupts. 612d8f048cSHavard Skinnemoen */ 622d8f048cSHavard Skinnemoen enum NPCM7xxInterrupt { 632d8f048cSHavard Skinnemoen NPCM7XX_UART0_IRQ = 2, 642d8f048cSHavard Skinnemoen NPCM7XX_UART1_IRQ, 652d8f048cSHavard Skinnemoen NPCM7XX_UART2_IRQ, 662d8f048cSHavard Skinnemoen NPCM7XX_UART3_IRQ, 672d8f048cSHavard Skinnemoen NPCM7XX_TIMER0_IRQ = 32, /* Timer Module 0 */ 682d8f048cSHavard Skinnemoen NPCM7XX_TIMER1_IRQ, 692d8f048cSHavard Skinnemoen NPCM7XX_TIMER2_IRQ, 702d8f048cSHavard Skinnemoen NPCM7XX_TIMER3_IRQ, 712d8f048cSHavard Skinnemoen NPCM7XX_TIMER4_IRQ, 722d8f048cSHavard Skinnemoen NPCM7XX_TIMER5_IRQ, /* Timer Module 1 */ 732d8f048cSHavard Skinnemoen NPCM7XX_TIMER6_IRQ, 742d8f048cSHavard Skinnemoen NPCM7XX_TIMER7_IRQ, 752d8f048cSHavard Skinnemoen NPCM7XX_TIMER8_IRQ, 762d8f048cSHavard Skinnemoen NPCM7XX_TIMER9_IRQ, 772d8f048cSHavard Skinnemoen NPCM7XX_TIMER10_IRQ, /* Timer Module 2 */ 782d8f048cSHavard Skinnemoen NPCM7XX_TIMER11_IRQ, 792d8f048cSHavard Skinnemoen NPCM7XX_TIMER12_IRQ, 802d8f048cSHavard Skinnemoen NPCM7XX_TIMER13_IRQ, 812d8f048cSHavard Skinnemoen NPCM7XX_TIMER14_IRQ, 822d8f048cSHavard Skinnemoen }; 832d8f048cSHavard Skinnemoen 842d8f048cSHavard Skinnemoen /* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */ 852d8f048cSHavard Skinnemoen #define NPCM7XX_NUM_IRQ (160) 862d8f048cSHavard Skinnemoen 872d8f048cSHavard Skinnemoen /* Register base address for each Timer Module */ 882d8f048cSHavard Skinnemoen static const hwaddr npcm7xx_tim_addr[] = { 892d8f048cSHavard Skinnemoen 0xf0008000, 902d8f048cSHavard Skinnemoen 0xf0009000, 912d8f048cSHavard Skinnemoen 0xf000a000, 922d8f048cSHavard Skinnemoen }; 932d8f048cSHavard Skinnemoen 942d8f048cSHavard Skinnemoen /* Register base address for each 16550 UART */ 952d8f048cSHavard Skinnemoen static const hwaddr npcm7xx_uart_addr[] = { 962d8f048cSHavard Skinnemoen 0xf0001000, 972d8f048cSHavard Skinnemoen 0xf0002000, 982d8f048cSHavard Skinnemoen 0xf0003000, 992d8f048cSHavard Skinnemoen 0xf0004000, 1002d8f048cSHavard Skinnemoen }; 1012d8f048cSHavard Skinnemoen 1022d8f048cSHavard Skinnemoen static void npcm7xx_write_secondary_boot(ARMCPU *cpu, 1032d8f048cSHavard Skinnemoen const struct arm_boot_info *info) 1042d8f048cSHavard Skinnemoen { 1052d8f048cSHavard Skinnemoen /* 1062d8f048cSHavard Skinnemoen * The default smpboot stub halts the secondary CPU with a 'wfi' 1072d8f048cSHavard Skinnemoen * instruction, but the arch/arm/mach-npcm/platsmp.c in the Linux kernel 1082d8f048cSHavard Skinnemoen * does not send an IPI to wake it up, so the second CPU fails to boot. So 1092d8f048cSHavard Skinnemoen * we need to provide our own smpboot stub that can not use 'wfi', it has 1102d8f048cSHavard Skinnemoen * to spin the secondary CPU until the first CPU writes to the SCRPAD reg. 1112d8f048cSHavard Skinnemoen */ 1122d8f048cSHavard Skinnemoen uint32_t smpboot[] = { 1132d8f048cSHavard Skinnemoen 0xe59f2018, /* ldr r2, bootreg_addr */ 1142d8f048cSHavard Skinnemoen 0xe3a00000, /* mov r0, #0 */ 1152d8f048cSHavard Skinnemoen 0xe5820000, /* str r0, [r2] */ 1162d8f048cSHavard Skinnemoen 0xe320f002, /* wfe */ 1172d8f048cSHavard Skinnemoen 0xe5921000, /* ldr r1, [r2] */ 1182d8f048cSHavard Skinnemoen 0xe1110001, /* tst r1, r1 */ 1192d8f048cSHavard Skinnemoen 0x0afffffb, /* beq <wfe> */ 1202d8f048cSHavard Skinnemoen 0xe12fff11, /* bx r1 */ 1212d8f048cSHavard Skinnemoen NPCM7XX_SMP_BOOTREG_ADDR, 1222d8f048cSHavard Skinnemoen }; 1232d8f048cSHavard Skinnemoen int i; 1242d8f048cSHavard Skinnemoen 1252d8f048cSHavard Skinnemoen for (i = 0; i < ARRAY_SIZE(smpboot); i++) { 1262d8f048cSHavard Skinnemoen smpboot[i] = tswap32(smpboot[i]); 1272d8f048cSHavard Skinnemoen } 1282d8f048cSHavard Skinnemoen 1292d8f048cSHavard Skinnemoen rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), 1302d8f048cSHavard Skinnemoen NPCM7XX_SMP_LOADER_START); 1312d8f048cSHavard Skinnemoen } 1322d8f048cSHavard Skinnemoen 1332d8f048cSHavard Skinnemoen static struct arm_boot_info npcm7xx_binfo = { 1342d8f048cSHavard Skinnemoen .loader_start = NPCM7XX_LOADER_START, 1352d8f048cSHavard Skinnemoen .smp_loader_start = NPCM7XX_SMP_LOADER_START, 1362d8f048cSHavard Skinnemoen .smp_bootreg_addr = NPCM7XX_SMP_BOOTREG_ADDR, 1372d8f048cSHavard Skinnemoen .gic_cpu_if_addr = NPCM7XX_GIC_CPU_IF_ADDR, 1382d8f048cSHavard Skinnemoen .write_secondary_boot = npcm7xx_write_secondary_boot, 1392d8f048cSHavard Skinnemoen .board_id = -1, 1402d8f048cSHavard Skinnemoen }; 1412d8f048cSHavard Skinnemoen 1422d8f048cSHavard Skinnemoen void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc) 1432d8f048cSHavard Skinnemoen { 1442d8f048cSHavard Skinnemoen NPCM7xxClass *sc = NPCM7XX_GET_CLASS(soc); 1452d8f048cSHavard Skinnemoen 1462d8f048cSHavard Skinnemoen npcm7xx_binfo.ram_size = machine->ram_size; 1472d8f048cSHavard Skinnemoen npcm7xx_binfo.nb_cpus = sc->num_cpus; 1482d8f048cSHavard Skinnemoen 1492d8f048cSHavard Skinnemoen arm_load_kernel(&soc->cpu[0], machine, &npcm7xx_binfo); 1502d8f048cSHavard Skinnemoen } 1512d8f048cSHavard Skinnemoen 152c752bb07SHavard Skinnemoen static void npcm7xx_init_fuses(NPCM7xxState *s) 153c752bb07SHavard Skinnemoen { 154c752bb07SHavard Skinnemoen NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s); 155c752bb07SHavard Skinnemoen uint32_t value; 156c752bb07SHavard Skinnemoen 157c752bb07SHavard Skinnemoen /* 158c752bb07SHavard Skinnemoen * The initial mask of disabled modules indicates the chip derivative (e.g. 159c752bb07SHavard Skinnemoen * NPCM750 or NPCM730). 160c752bb07SHavard Skinnemoen */ 161c752bb07SHavard Skinnemoen value = tswap32(nc->disabled_modules); 162c752bb07SHavard Skinnemoen npcm7xx_otp_array_write(&s->fuse_array, &value, NPCM7XX_FUSE_DERIVATIVE, 163c752bb07SHavard Skinnemoen sizeof(value)); 164c752bb07SHavard Skinnemoen } 165c752bb07SHavard Skinnemoen 1662d8f048cSHavard Skinnemoen static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n) 1672d8f048cSHavard Skinnemoen { 1682d8f048cSHavard Skinnemoen return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n); 1692d8f048cSHavard Skinnemoen } 1702d8f048cSHavard Skinnemoen 1712d8f048cSHavard Skinnemoen static void npcm7xx_init(Object *obj) 1722d8f048cSHavard Skinnemoen { 1732d8f048cSHavard Skinnemoen NPCM7xxState *s = NPCM7XX(obj); 1742d8f048cSHavard Skinnemoen int i; 1752d8f048cSHavard Skinnemoen 1762d8f048cSHavard Skinnemoen for (i = 0; i < NPCM7XX_MAX_NUM_CPUS; i++) { 1772d8f048cSHavard Skinnemoen object_initialize_child(obj, "cpu[*]", &s->cpu[i], 1782d8f048cSHavard Skinnemoen ARM_CPU_TYPE_NAME("cortex-a9")); 1792d8f048cSHavard Skinnemoen } 1802d8f048cSHavard Skinnemoen 1812d8f048cSHavard Skinnemoen object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); 1822d8f048cSHavard Skinnemoen object_initialize_child(obj, "gcr", &s->gcr, TYPE_NPCM7XX_GCR); 1832d8f048cSHavard Skinnemoen object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr), 1842d8f048cSHavard Skinnemoen "power-on-straps"); 1852d8f048cSHavard Skinnemoen object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM7XX_CLK); 186c752bb07SHavard Skinnemoen object_initialize_child(obj, "otp1", &s->key_storage, 187c752bb07SHavard Skinnemoen TYPE_NPCM7XX_KEY_STORAGE); 188c752bb07SHavard Skinnemoen object_initialize_child(obj, "otp2", &s->fuse_array, 189c752bb07SHavard Skinnemoen TYPE_NPCM7XX_FUSE_ARRAY); 190*1351f892SHavard Skinnemoen object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC); 1912d8f048cSHavard Skinnemoen 1922d8f048cSHavard Skinnemoen for (i = 0; i < ARRAY_SIZE(s->tim); i++) { 1932d8f048cSHavard Skinnemoen object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER); 1942d8f048cSHavard Skinnemoen } 1952d8f048cSHavard Skinnemoen } 1962d8f048cSHavard Skinnemoen 1972d8f048cSHavard Skinnemoen static void npcm7xx_realize(DeviceState *dev, Error **errp) 1982d8f048cSHavard Skinnemoen { 1992d8f048cSHavard Skinnemoen NPCM7xxState *s = NPCM7XX(dev); 2002d8f048cSHavard Skinnemoen NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s); 2012d8f048cSHavard Skinnemoen int i; 2022d8f048cSHavard Skinnemoen 2032d8f048cSHavard Skinnemoen if (memory_region_size(s->dram) > NPCM7XX_DRAM_SZ) { 2042d8f048cSHavard Skinnemoen error_setg(errp, "%s: NPCM7xx cannot address more than %" PRIu64 2052d8f048cSHavard Skinnemoen " MiB of DRAM", __func__, NPCM7XX_DRAM_SZ / MiB); 2062d8f048cSHavard Skinnemoen return; 2072d8f048cSHavard Skinnemoen } 2082d8f048cSHavard Skinnemoen 2092d8f048cSHavard Skinnemoen /* CPUs */ 2102d8f048cSHavard Skinnemoen for (i = 0; i < nc->num_cpus; i++) { 2112d8f048cSHavard Skinnemoen object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity", 2122d8f048cSHavard Skinnemoen arm_cpu_mp_affinity(i, NPCM7XX_MAX_NUM_CPUS), 2132d8f048cSHavard Skinnemoen &error_abort); 2142d8f048cSHavard Skinnemoen object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", 2152d8f048cSHavard Skinnemoen NPCM7XX_GIC_CPU_IF_ADDR, &error_abort); 2162d8f048cSHavard Skinnemoen object_property_set_bool(OBJECT(&s->cpu[i]), "reset-hivecs", true, 2172d8f048cSHavard Skinnemoen &error_abort); 2182d8f048cSHavard Skinnemoen 2192d8f048cSHavard Skinnemoen /* Disable security extensions. */ 2202d8f048cSHavard Skinnemoen object_property_set_bool(OBJECT(&s->cpu[i]), "has_el3", false, 2212d8f048cSHavard Skinnemoen &error_abort); 2222d8f048cSHavard Skinnemoen 2232d8f048cSHavard Skinnemoen if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { 2242d8f048cSHavard Skinnemoen return; 2252d8f048cSHavard Skinnemoen } 2262d8f048cSHavard Skinnemoen } 2272d8f048cSHavard Skinnemoen 2282d8f048cSHavard Skinnemoen /* A9MPCORE peripherals. Can only fail if we pass bad parameters here. */ 2292d8f048cSHavard Skinnemoen object_property_set_int(OBJECT(&s->a9mpcore), "num-cpu", nc->num_cpus, 2302d8f048cSHavard Skinnemoen &error_abort); 2312d8f048cSHavard Skinnemoen object_property_set_int(OBJECT(&s->a9mpcore), "num-irq", NPCM7XX_NUM_IRQ, 2322d8f048cSHavard Skinnemoen &error_abort); 2332d8f048cSHavard Skinnemoen sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), &error_abort); 2342d8f048cSHavard Skinnemoen sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, NPCM7XX_CPUP_BA); 2352d8f048cSHavard Skinnemoen 2362d8f048cSHavard Skinnemoen for (i = 0; i < nc->num_cpus; i++) { 2372d8f048cSHavard Skinnemoen sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i, 2382d8f048cSHavard Skinnemoen qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ)); 2392d8f048cSHavard Skinnemoen sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + nc->num_cpus, 2402d8f048cSHavard Skinnemoen qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ)); 2412d8f048cSHavard Skinnemoen } 2422d8f048cSHavard Skinnemoen 2432d8f048cSHavard Skinnemoen /* L2 cache controller */ 2442d8f048cSHavard Skinnemoen sysbus_create_simple("l2x0", NPCM7XX_L2C_BA, NULL); 2452d8f048cSHavard Skinnemoen 2462d8f048cSHavard Skinnemoen /* System Global Control Registers (GCR). Can fail due to user input. */ 2472d8f048cSHavard Skinnemoen object_property_set_int(OBJECT(&s->gcr), "disabled-modules", 2482d8f048cSHavard Skinnemoen nc->disabled_modules, &error_abort); 2492d8f048cSHavard Skinnemoen object_property_add_const_link(OBJECT(&s->gcr), "dram-mr", OBJECT(s->dram)); 2502d8f048cSHavard Skinnemoen if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) { 2512d8f048cSHavard Skinnemoen return; 2522d8f048cSHavard Skinnemoen } 2532d8f048cSHavard Skinnemoen sysbus_mmio_map(SYS_BUS_DEVICE(&s->gcr), 0, NPCM7XX_GCR_BA); 2542d8f048cSHavard Skinnemoen 2552d8f048cSHavard Skinnemoen /* Clock Control Registers (CLK). Cannot fail. */ 2562d8f048cSHavard Skinnemoen sysbus_realize(SYS_BUS_DEVICE(&s->clk), &error_abort); 2572d8f048cSHavard Skinnemoen sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0, NPCM7XX_CLK_BA); 2582d8f048cSHavard Skinnemoen 259c752bb07SHavard Skinnemoen /* OTP key storage and fuse strap array. Cannot fail. */ 260c752bb07SHavard Skinnemoen sysbus_realize(SYS_BUS_DEVICE(&s->key_storage), &error_abort); 261c752bb07SHavard Skinnemoen sysbus_mmio_map(SYS_BUS_DEVICE(&s->key_storage), 0, NPCM7XX_OTP1_BA); 262c752bb07SHavard Skinnemoen sysbus_realize(SYS_BUS_DEVICE(&s->fuse_array), &error_abort); 263c752bb07SHavard Skinnemoen sysbus_mmio_map(SYS_BUS_DEVICE(&s->fuse_array), 0, NPCM7XX_OTP2_BA); 264c752bb07SHavard Skinnemoen npcm7xx_init_fuses(s); 265c752bb07SHavard Skinnemoen 266*1351f892SHavard Skinnemoen /* Fake Memory Controller (MC). Cannot fail. */ 267*1351f892SHavard Skinnemoen sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort); 268*1351f892SHavard Skinnemoen sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA); 269*1351f892SHavard Skinnemoen 2702d8f048cSHavard Skinnemoen /* Timer Modules (TIM). Cannot fail. */ 2712d8f048cSHavard Skinnemoen QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim)); 2722d8f048cSHavard Skinnemoen for (i = 0; i < ARRAY_SIZE(s->tim); i++) { 2732d8f048cSHavard Skinnemoen SysBusDevice *sbd = SYS_BUS_DEVICE(&s->tim[i]); 2742d8f048cSHavard Skinnemoen int first_irq; 2752d8f048cSHavard Skinnemoen int j; 2762d8f048cSHavard Skinnemoen 2772d8f048cSHavard Skinnemoen sysbus_realize(sbd, &error_abort); 2782d8f048cSHavard Skinnemoen sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]); 2792d8f048cSHavard Skinnemoen 2802d8f048cSHavard Skinnemoen first_irq = NPCM7XX_TIMER0_IRQ + i * NPCM7XX_TIMERS_PER_CTRL; 2812d8f048cSHavard Skinnemoen for (j = 0; j < NPCM7XX_TIMERS_PER_CTRL; j++) { 2822d8f048cSHavard Skinnemoen qemu_irq irq = npcm7xx_irq(s, first_irq + j); 2832d8f048cSHavard Skinnemoen sysbus_connect_irq(sbd, j, irq); 2842d8f048cSHavard Skinnemoen } 2852d8f048cSHavard Skinnemoen } 2862d8f048cSHavard Skinnemoen 2872d8f048cSHavard Skinnemoen /* UART0..3 (16550 compatible) */ 2882d8f048cSHavard Skinnemoen for (i = 0; i < ARRAY_SIZE(npcm7xx_uart_addr); i++) { 2892d8f048cSHavard Skinnemoen serial_mm_init(get_system_memory(), npcm7xx_uart_addr[i], 2, 2902d8f048cSHavard Skinnemoen npcm7xx_irq(s, NPCM7XX_UART0_IRQ + i), 115200, 2912d8f048cSHavard Skinnemoen serial_hd(i), DEVICE_LITTLE_ENDIAN); 2922d8f048cSHavard Skinnemoen } 2932d8f048cSHavard Skinnemoen 2942d8f048cSHavard Skinnemoen /* RAM2 (SRAM) */ 2952d8f048cSHavard Skinnemoen memory_region_init_ram(&s->sram, OBJECT(dev), "ram2", 2962d8f048cSHavard Skinnemoen NPCM7XX_RAM2_SZ, &error_abort); 2972d8f048cSHavard Skinnemoen memory_region_add_subregion(get_system_memory(), NPCM7XX_RAM2_BA, &s->sram); 2982d8f048cSHavard Skinnemoen 2992d8f048cSHavard Skinnemoen /* RAM3 (SRAM) */ 3002d8f048cSHavard Skinnemoen memory_region_init_ram(&s->ram3, OBJECT(dev), "ram3", 3012d8f048cSHavard Skinnemoen NPCM7XX_RAM3_SZ, &error_abort); 3022d8f048cSHavard Skinnemoen memory_region_add_subregion(get_system_memory(), NPCM7XX_RAM3_BA, &s->ram3); 3032d8f048cSHavard Skinnemoen 3042d8f048cSHavard Skinnemoen /* Internal ROM */ 3052d8f048cSHavard Skinnemoen memory_region_init_rom(&s->irom, OBJECT(dev), "irom", NPCM7XX_ROM_SZ, 3062d8f048cSHavard Skinnemoen &error_abort); 3072d8f048cSHavard Skinnemoen memory_region_add_subregion(get_system_memory(), NPCM7XX_ROM_BA, &s->irom); 3082d8f048cSHavard Skinnemoen 3092d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.shm", 0xc0001000, 4 * KiB); 3102d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB); 3112d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB); 3122d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB); 3132d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.rng", 0xf000b000, 4 * KiB); 3142d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.adc", 0xf000c000, 4 * KiB); 3152d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB); 3162d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.gpio[0]", 0xf0010000, 4 * KiB); 3172d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.gpio[1]", 0xf0011000, 4 * KiB); 3182d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.gpio[2]", 0xf0012000, 4 * KiB); 3192d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.gpio[3]", 0xf0013000, 4 * KiB); 3202d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.gpio[4]", 0xf0014000, 4 * KiB); 3212d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.gpio[5]", 0xf0015000, 4 * KiB); 3222d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.gpio[6]", 0xf0016000, 4 * KiB); 3232d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.gpio[7]", 0xf0017000, 4 * KiB); 3242d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.smbus[0]", 0xf0080000, 4 * KiB); 3252d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.smbus[1]", 0xf0081000, 4 * KiB); 3262d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.smbus[2]", 0xf0082000, 4 * KiB); 3272d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.smbus[3]", 0xf0083000, 4 * KiB); 3282d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.smbus[4]", 0xf0084000, 4 * KiB); 3292d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.smbus[5]", 0xf0085000, 4 * KiB); 3302d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.smbus[6]", 0xf0086000, 4 * KiB); 3312d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.smbus[7]", 0xf0087000, 4 * KiB); 3322d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.smbus[8]", 0xf0088000, 4 * KiB); 3332d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.smbus[9]", 0xf0089000, 4 * KiB); 3342d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.smbus[10]", 0xf008a000, 4 * KiB); 3352d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.smbus[11]", 0xf008b000, 4 * KiB); 3362d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.smbus[12]", 0xf008c000, 4 * KiB); 3372d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.smbus[13]", 0xf008d000, 4 * KiB); 3382d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.smbus[14]", 0xf008e000, 4 * KiB); 3392d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.smbus[15]", 0xf008f000, 4 * KiB); 3402d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.espi", 0xf009f000, 4 * KiB); 3412d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB); 3422d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB); 3432d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB); 3442d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.pwm[0]", 0xf0103000, 4 * KiB); 3452d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.pwm[1]", 0xf0104000, 4 * KiB); 3462d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.mft[0]", 0xf0180000, 4 * KiB); 3472d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.mft[1]", 0xf0181000, 4 * KiB); 3482d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.mft[2]", 0xf0182000, 4 * KiB); 3492d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.mft[3]", 0xf0183000, 4 * KiB); 3502d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.mft[4]", 0xf0184000, 4 * KiB); 3512d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.mft[5]", 0xf0185000, 4 * KiB); 3522d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.mft[6]", 0xf0186000, 4 * KiB); 3532d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.mft[7]", 0xf0187000, 4 * KiB); 3542d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.pspi1", 0xf0200000, 4 * KiB); 3552d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.pspi2", 0xf0201000, 4 * KiB); 3562d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.ahbpci", 0xf0400000, 1 * MiB); 3572d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.mcphy", 0xf05f0000, 64 * KiB); 3582d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.gmac1", 0xf0802000, 8 * KiB); 3592d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.gmac2", 0xf0804000, 8 * KiB); 3602d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.ehci", 0xf0806000, 4 * KiB); 3612d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.ohci", 0xf0807000, 4 * KiB); 3622d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.vcd", 0xf0810000, 64 * KiB); 3632d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.ece", 0xf0820000, 8 * KiB); 3642d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.vdma", 0xf0822000, 8 * KiB); 3652d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.emc1", 0xf0825000, 4 * KiB); 3662d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.emc2", 0xf0826000, 4 * KiB); 3672d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.usbd[0]", 0xf0830000, 4 * KiB); 3682d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.usbd[1]", 0xf0831000, 4 * KiB); 3692d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.usbd[2]", 0xf0832000, 4 * KiB); 3702d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.usbd[3]", 0xf0833000, 4 * KiB); 3712d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.usbd[4]", 0xf0834000, 4 * KiB); 3722d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.usbd[5]", 0xf0835000, 4 * KiB); 3732d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.usbd[6]", 0xf0836000, 4 * KiB); 3742d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.usbd[7]", 0xf0837000, 4 * KiB); 3752d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.usbd[8]", 0xf0838000, 4 * KiB); 3762d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.usbd[9]", 0xf0839000, 4 * KiB); 3772d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.sd", 0xf0840000, 8 * KiB); 3782d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.mmc", 0xf0842000, 8 * KiB); 3792d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.pcimbx", 0xf0848000, 512 * KiB); 3802d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.aes", 0xf0858000, 4 * KiB); 3812d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.des", 0xf0859000, 4 * KiB); 3822d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.sha", 0xf085a000, 4 * KiB); 3832d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.secacc", 0xf085b000, 4 * KiB); 3842d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.spixcs0", 0xf8000000, 16 * MiB); 3852d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.spixcs1", 0xf9000000, 16 * MiB); 3862d8f048cSHavard Skinnemoen create_unimplemented_device("npcm7xx.spix", 0xfb001000, 4 * KiB); 3872d8f048cSHavard Skinnemoen } 3882d8f048cSHavard Skinnemoen 3892d8f048cSHavard Skinnemoen static Property npcm7xx_properties[] = { 3902d8f048cSHavard Skinnemoen DEFINE_PROP_LINK("dram-mr", NPCM7xxState, dram, TYPE_MEMORY_REGION, 3912d8f048cSHavard Skinnemoen MemoryRegion *), 3922d8f048cSHavard Skinnemoen DEFINE_PROP_END_OF_LIST(), 3932d8f048cSHavard Skinnemoen }; 3942d8f048cSHavard Skinnemoen 3952d8f048cSHavard Skinnemoen static void npcm7xx_class_init(ObjectClass *oc, void *data) 3962d8f048cSHavard Skinnemoen { 3972d8f048cSHavard Skinnemoen DeviceClass *dc = DEVICE_CLASS(oc); 3982d8f048cSHavard Skinnemoen 3992d8f048cSHavard Skinnemoen dc->realize = npcm7xx_realize; 4002d8f048cSHavard Skinnemoen dc->user_creatable = false; 4012d8f048cSHavard Skinnemoen device_class_set_props(dc, npcm7xx_properties); 4022d8f048cSHavard Skinnemoen } 4032d8f048cSHavard Skinnemoen 4042d8f048cSHavard Skinnemoen static void npcm730_class_init(ObjectClass *oc, void *data) 4052d8f048cSHavard Skinnemoen { 4062d8f048cSHavard Skinnemoen NPCM7xxClass *nc = NPCM7XX_CLASS(oc); 4072d8f048cSHavard Skinnemoen 4082d8f048cSHavard Skinnemoen /* NPCM730 is optimized for data center use, so no graphics, etc. */ 4092d8f048cSHavard Skinnemoen nc->disabled_modules = 0x00300395; 4102d8f048cSHavard Skinnemoen nc->num_cpus = 2; 4112d8f048cSHavard Skinnemoen } 4122d8f048cSHavard Skinnemoen 4132d8f048cSHavard Skinnemoen static void npcm750_class_init(ObjectClass *oc, void *data) 4142d8f048cSHavard Skinnemoen { 4152d8f048cSHavard Skinnemoen NPCM7xxClass *nc = NPCM7XX_CLASS(oc); 4162d8f048cSHavard Skinnemoen 4172d8f048cSHavard Skinnemoen /* NPCM750 has 2 cores and a full set of peripherals */ 4182d8f048cSHavard Skinnemoen nc->disabled_modules = 0x00000000; 4192d8f048cSHavard Skinnemoen nc->num_cpus = 2; 4202d8f048cSHavard Skinnemoen } 4212d8f048cSHavard Skinnemoen 4222d8f048cSHavard Skinnemoen static const TypeInfo npcm7xx_soc_types[] = { 4232d8f048cSHavard Skinnemoen { 4242d8f048cSHavard Skinnemoen .name = TYPE_NPCM7XX, 4252d8f048cSHavard Skinnemoen .parent = TYPE_DEVICE, 4262d8f048cSHavard Skinnemoen .instance_size = sizeof(NPCM7xxState), 4272d8f048cSHavard Skinnemoen .instance_init = npcm7xx_init, 4282d8f048cSHavard Skinnemoen .class_size = sizeof(NPCM7xxClass), 4292d8f048cSHavard Skinnemoen .class_init = npcm7xx_class_init, 4302d8f048cSHavard Skinnemoen .abstract = true, 4312d8f048cSHavard Skinnemoen }, { 4322d8f048cSHavard Skinnemoen .name = TYPE_NPCM730, 4332d8f048cSHavard Skinnemoen .parent = TYPE_NPCM7XX, 4342d8f048cSHavard Skinnemoen .class_init = npcm730_class_init, 4352d8f048cSHavard Skinnemoen }, { 4362d8f048cSHavard Skinnemoen .name = TYPE_NPCM750, 4372d8f048cSHavard Skinnemoen .parent = TYPE_NPCM7XX, 4382d8f048cSHavard Skinnemoen .class_init = npcm750_class_init, 4392d8f048cSHavard Skinnemoen }, 4402d8f048cSHavard Skinnemoen }; 4412d8f048cSHavard Skinnemoen 4422d8f048cSHavard Skinnemoen DEFINE_TYPES(npcm7xx_soc_types); 443